JPH1050862A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To independently set polysilicon impurity concentration of an upper/ lower layer part, precisely control work function to be a desired value, and realize a dual-gate electrode having no electrode depletions by a method wherein a gate electrode comprises two layers or more containing an upper layer part and a lower layer part, and nitrogen exists in the lower layer part. SOLUTION: An NMOS transistor is formed in a P-well 5 formed in a surface of a semiconductor substrate 1, and a PMOS transistor is formed in an N-well 6. The NMOS transistor contains an N-type gate electrode 9 provided via a thin film gate insulation film 2 on the P-well 5. Further, the PMOS transistor contains a P-type gate electrode 10 provided via a thin film gate insulation film 2 on the N-well 5. The N-type gate electrode 9 and P-type gate electrode 10 are a two-layer structure of an upper layer part PG2 and a lower layer part PG1. Nitrogen is implanted onto the lower layer part PG1 of the N-type gate electrode 9 and the lower layer part PG1 of the P-type gate electrode 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a complementary field effect transistor having a dual gate electrode structure. The present invention also relates to an improvement in a gate wiring structure.

[0002]

2. Description of the Related Art As the power supply voltage of a semiconductor device is reduced, in order to improve the conventional circuit performance, it is necessary to lower the threshold voltage of a transistor to increase the current drive capability, and to increase the parasitic resistance and the like. It is important to reduce the parasitic capacitance as much as possible. A so-called dual gate structure in which the work function difference between the gate electrode of each of the NMOS transistor / PMOS transistor and the substrate is reduced has been proposed as a means for realizing a low voltage in the CMOS structure. The threshold voltage can be reduced by reducing the work function difference between the gate electrode and the substrate.

FIG. 16 is a cross-sectional view of a conventional CMOSFET using a dual gate structure. Referring to FIG. 16, a P-well 5 and an N-well 6 are provided in a semiconductor substrate. The P-well 5 and the N-well 6 are separated by the isolation insulating film 3. An N-type gate electrode 9 is provided on P-well 5 with gate insulating film 2 interposed. N-type source / drain regions 7 are provided in the main surface of P-well 5 on both sides of N-type gate electrode 9. The silicide film 1 is formed on the surface of the N-type gate electrode 9 and the surface of the N-type source / drain region 7 (Self-AlignedSilicide). P-type gate electrode 10 is provided on N-well 6 with gate insulating film 2 interposed. P-type source / drain regions 8 are provided in the main surface of P-well 6 on both sides of P-type gate electrode 10. The silicide film 1 is formed on the surface of the P-type gate electrode 10 and the surface of the P-type source / drain region 8. N-type gate electrode 9 and P-type gate electrode 10
Are provided with side wall spacers 4 respectively.

Specifically, in the dual gate structure, NM
A conductive material doped with an N-type impurity is used for the gate electrode 9 of the OS transistor, and a conductive material doped with a P-type impurity is used for the gate electrode 10 of the PMOS transistor.

[0005]

In the dual gate structure, it is necessary that two different types of impurities contribute to conduction in each gate electrode (that is, activated carriers). It is important in suppressing the conversion. When the transistor is operated in a state where the gate electrode is depleted, the current driving capability is reduced in accordance with the depletion rate, so that the circuit performance is significantly reduced.

However, considering the actual manufacturing process, even if the impurity concentration in the gate electrode is sufficient, the heat treatment (temperature, time, means (FA)
In some cases, if the activation is insufficient or the heat treatment is too much, the impurities in the electrodes penetrate the thin gate insulating film toward the substrate due to diffusion, and affect the impurity concentration on the substrate. And there were control difficulties.

[0007] Turning to the gate electrode and gate wiring resistance, silicide wiring is effective for lowering the resistance. In particular, a salicide process (Self-Aligned Silic) in which the gate and source / drain regions are simultaneously silicided by self-alignment after forming the source / drain using only polysilicon as the gate material.
It is very attractive for varieties that emphasize high-speed processing (ide Process).

However, if the polysilicon surface is heavily doped with impurities or nitrogen is present as in the dual gate structure, the silicide reaction is adversely affected. In particular, miniaturization tends to increase the silicide resistance of a necessary thin line portion, and sometimes causes a failure in peeling of the silicide film.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to control (activated) impurity concentration profiles for impurities having different types of gates in a semiconductor device having a dual gate structure, to prevent electrode depletion, and to improve the work efficiency. The purpose of the present invention is to make the function a desired value and obtain a high-drive transistor as a result.

Another object of the present invention is to form a gate wiring which does not increase the resistance of a thin line portion even when a salicide process is performed.

Still another object of the present invention is to reduce a parasitic wiring capacitance between a gate and a substrate in a gate wiring structure.

[0012]

A semiconductor device according to a first aspect of the present invention comprises an NMOS transistor having an N-type gate electrode containing an N-type impurity and a PMOS transistor having a P-type gate electrode containing a P-type impurity. And a transistor. The N-type gate electrode has a structure of two or more layers including an upper layer portion and a lower layer portion. The P-type gate electrode,
It has a structure of two or more layers including an upper layer portion and a lower layer portion.
Nitrogen is implanted into at least one of the lower layer portion of the N-type gate electrode and the lower layer portion of the P-type gate electrode.

A semiconductor device according to a second aspect of the present invention is an NMO having an N-type gate electrode containing an N-type impurity.
The transistor includes an S transistor and a PMOS transistor having a P-type gate electrode containing a P-type impurity. Each of the N-type gate electrode and the P-type gate electrode has a structure of two or more layers including an upper layer portion and a lower layer portion. In each gate electrode, the impurity concentration in the lower layer portion is:
It is larger than that in the upper layer.

A semiconductor device according to a third aspect of the present invention is an NMO having an N-type gate electrode containing an N-type impurity.
The semiconductor device includes an S transistor, a PMOS transistor having a P-type gate electrode containing a P-type impurity, and a capacitor portion formed on a field oxide film. The capacitor portion includes a lower layer portion into which one of the N-type or P-type impurities is implanted, an insulating film provided on the lower layer portion,
An upper layer portion provided on the insulating film and into which the one type of impurity is implanted.

A semiconductor device according to a fourth aspect of the present invention includes an NMOS transistor having an N-type gate electrode;
A PMOS transistor having a P-type gate electrode. The N-type gate electrode and the P-type gate electrode each include an upper layer portion and a lower layer portion. The lower layer portion is non-doped.

A semiconductor device according to a fifth aspect of the present invention includes a transistor having a gate electrode. The gate electrode includes an upper layer and a lower layer. At least the upper layer is non-doped, and all or part of the upper layer in the height direction is silicided.

A semiconductor device according to a sixth aspect of the present invention includes a gate wiring and a capacitor portion formed on a field oxide film. The capacitor portion includes a lower layer portion into which impurities are implanted, an insulating film provided on the lower layer portion, and an upper layer portion provided on the insulating film. The device further includes a silicide protection film provided on the gate oxide film and formed of the same material as the insulating film.

[0018]

Embodiment 1 FIG. 1 is a sectional view of a complementary field effect transistor according to Embodiment 1 of the present invention. A P-well 5 and an N-well 6 are formed in the surface of the semiconductor substrate 1. The P-well 5 and the N-well 6 are separated by the isolation insulating film 3. An NMOS transistor is formed in the P-well 5, and a PMOS transistor is formed in the N-well 6. The NMOS transistor includes an N-type gate electrode 9 provided on the P-well 5 with the thin gate insulating film 2 interposed. N-type source / drain regions 7 are provided in the main surface of P-well 5 on both sides of N-type gate electrode 9. The surface of the N-type gate electrode 9 and N
The surface of the mold source / drain region 7 is silicided, and the silicide layer 1 is formed. The N-type gate electrode 9 has a two-layer structure including an upper layer portion NG2 and a lower layer portion NG1. Here, a two-layer structure is described as an example, but the present invention is not limited to this, and the gate electrode may have a structure of two or more layers.

The PMOS transistor includes a P-type gate electrode 10 provided on N-well 6 with thin gate insulating film 2 interposed. P-type source / drain regions 8 are provided in the main surface of N-well 6 on both sides of P-type gate electrode 10. The surface of the P-type gate electrode 10 and the surface of the P-type source / drain region 8 are silicided, and the silicide film 1 is formed. The P-type gate electrode 10 has a two-layer structure of an upper part PG2 and a lower part PG1. Table 1 shows specific examples 1-3.

[0020]

[Table 1]

In the first embodiment, nitrogen is implanted into the lower layer portion NG1 of the N-type gate electrode 9 and the lower layer portion PG1 of the P-type gate electrode 10. The upper layer portion NG2 of the N-type gate electrode 9 and the upper layer portion PG2 of the P-type gate electrode 10 do not contain nitrogen.

In the second embodiment, nitrogen is injected only into the lower layer portion PG1 of the P-type gate electrode 10, and the other portions NG1,
No nitrogen is injected into NG2 and PG2.

In the third embodiment, nitrogen is injected only into the lower layer portion NG1 of the N-type gate electrode 9, and the other portions NG2 and PG
2. No nitrogen is injected into PG1.

Next, the CMOSFET according to the first embodiment
A method of manufacturing the device will be described. Referring to FIG. 1, isolation insulating film 3, P-well 5, N-well 6, and thin-film gate insulating film 2 are formed on the main surface of a semiconductor substrate. Non-doped polysilicon corresponding to the lower layer of the gate electrode is deposited on a semiconductor substrate, and masked to form an NMOS, a PMOS.
The necessary ion implantation is performed in each of the regions. NG1 and PG1 portions are formed by this ion implantation. Examples of the impurity species used include phosphorus and arsenic in the NMOS region, and boron and BF _{2 in the} PMOS region. Further, thereafter, non-doped polysilicon corresponding to the upper layer portion of the electrode is deposited again, and masks are again applied, and ions are implanted into each of the NMOS and PMOS regions. For the second ion implantation, it is also possible to perform the source / drain implantation simultaneously.

[0025] Regarding the doping method of nitrogen, in the case of performing the doping by the ion implantation method, the doping is performed in the first ion implantation performed after depositing the polysilicon in the lower layer, and the method is performed after the polysilicon in the upper layer is deposited. In the second ion implantation, there is a method in which the range (Rp) is adjusted to the polysilicon of the lower layer portion. Example 1
In the structure (2), since nitrogen exists in both the NMOS and the PMOS, the entire surface is implanted without masking. The structures of the second and third embodiments can be realized by masking each of the NMOS and PMOS regions and implanting nitrogen ions only in necessary regions. According to this method, NM
An optimal amount can be injected into OS / PMOS.

In addition, instead of the ion implantation method, in-si
There is also a method in which an N-type or P-type impurity and further a nitrogen-containing impurity are deposited as tu-doped polysilicon, and only necessary impurity doping is performed by ion implantation.

According to the first embodiment, the following effects can be obtained. First, the polysilicon impurity concentration in the upper layer portion and the lower layer portion can be set independently. Even if the electrode thickness is the same as that of the related art, it is possible to more accurately control the impurity concentration in the vicinity of the gate insulating film by dividing into two layers. As a result, the work function can be accurately controlled to a desired value, and a dual gate electrode without electrode depletion can be realized. In addition, optimization of the NMOS and PMOS sections is possible, and the performance balance as a CMOS circuit is improved.

In the single-layer structure of polysilicon having the conventional structure, even if high concentration doping is performed by ion implantation and heat treatment acceptable in the process is performed, the vicinity of the gate insulating film, which is important for suppressing depletion, is important. Impurities that contribute to conduction, that is, carrier concentrations are often insufficient (especially in PMOS). That is, a certain thickness (for example, 3
In the electrode layer structure that requires 2,000 to 2,000 ° C.), depletion has occurred even if high-concentration doping is performed and heat treatment is applied. According to the first embodiment, such a problem can be solved.

The second effect obtained by the first embodiment is that the polysilicon film thickness of the upper layer portion and the lower layer portion and the film thickness ratio can be freely set. For example, the first effect described above can be further enhanced by reducing the thickness of the polysilicon layer in the lower layer. Further, by increasing only the thickness of the polysilicon layer in the upper layer, there is an effect that a margin can be provided for short-circuit failure between the source / drain region and the gate, which is often a problem in the salicide process.

As a third effect, the presence of nitrogen in the lower layer improves the barrier property due to the diffusion of impurities into the thin gate insulating film, and prevents penetration into the substrate.
In the conventional structure, if heat treatment is performed frequently, impurities penetrate to the substrate side through the gate insulating film, causing a problem that the threshold voltage fluctuates. According to the structure of the first embodiment, since nitrogen is implanted in the lower portion of the polysilicon film, the barrier property due to impurity diffusion into the thin film gate insulating film is improved. , The controllability of the nitrogen profile and the concentration is improved as compared with the case where the gate electrode structure is a single layer. Further, it becomes possible to inject an optimum amount into the N-channel transistor and the P-channel transistor.

As a fourth effect, the presence of nitrogen in the lower layer portion has an effect that nitrogen atoms are partially taken into the gate insulating film to form a nitride insulating film. Also, there is an effect that nitrogen atoms segregate at the gate insulating film / electrode interface or the gate insulating film / substrate interface. Due to these effects, an electrode structure which is improved in reliability of the thin gate insulating film and resistant to hot carriers can be obtained.

A fifth effect is that since nitrogen does not exist in the upper polysilicon layer, low-resistance silicide can be formed, and the margin for the peeling failure of the silicide film is improved. In the structure according to the first embodiment, since nitrogen does not exist in the upper polysilicon layer, the compatibility with the silicide process is good. In any of the structures of the first to third embodiments, a low-resistance salicide wiring with no increase in the resistance of the thin wire can be realized. In addition, the margin is increased even for the peeling failure of the silicide film.

Second Embodiment FIGS. 2 and 3 show a CM according to a second embodiment of the present invention.
FIG. 4 is a diagram showing an impurity concentration profile of a dual gate electrode structure of an OSFET. Referring to FIG. 2 and FIG. 3, the impurity concentration of the lower layer portion in the gate electrode having the two-layer structure is
It is set higher than the impurity concentration in the upper layer portion. FIG.
Indicates that the concentration profile is on a step function,
FIG. 3 shows a profile structure having two peaks. The method for manufacturing such a semiconductor device is performed according to the first embodiment.

The effects obtained by the second embodiment are as follows. That is, the depletion of the electrode can be prevented by setting the activated impurity concentration at the interface between the lower layer electrode and the gate insulating film to 4E20 / cm ³ or more. Therefore, the concentration of the other portions can be reduced to a level that does not cause an electrical problem.

Further, in the structure according to the second embodiment, since the impurity concentration in the polysilicon in the upper layer portion is kept to a necessary minimum, a low-resistance silicide having no increase in fine line resistance is formed in the silicide formation. Gate wiring can be formed. In particular, when the polysilicon layer in the upper layer is thin, this portion is not doped, and all or most of the upper layer polysilicon is converted into a metal compound by silicidation to be electrically connected to the lower layer doped polysilicon. It is also possible to have an electrically connected electrode structure.

Further, the low concentration and non-doping are effective also for the peeling of the silicide film which occurs when the impurity concentration in the polysilicon is high.

Third Embodiment FIG. 4 is a sectional view of a dual gate electrode structure of a CMOSFET according to a third embodiment. FIG. 5 shows a concentration profile in the gate electrode. This embodiment is the same as Embodiments 1 and 2 except for the following, and therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated. The difference between the structure of the gate electrode according to the third embodiment and the first and second embodiments is that
The point is that a tunnel insulating film 11 is provided between the upper layer portion and the lower layer portion of each of the mold gate electrode 9 and the P-type gate electrode 10. The gate electrode having such a structure is obtained by depositing a thin tunnel insulating film 11 before depositing the upper polysilicon layer in the first embodiment. According to the third embodiment, out-diffusion of impurities can be prevented when depositing the polysilicon in the upper layer or when performing heat treatment before that. Further, since the tunnel insulating film functions as a barrier layer for impurity diffusion with respect to any heat treatment during the process in a later step, there is an effect that the impurity concentration can be easily controlled accurately.

Fourth Embodiment A fourth embodiment is directed to an NMOS transistor and a PMOS transistor.
The present invention relates to a CMOSFET including a plurality of transistors. Then, as a dual gate electrode structure, transistors having different basic characteristics are formed by partially changing the impurity doping amount with respect to polysilicon in a lower layer portion.
Such formation of a transistor having a partially different threshold voltage can be realized by changing the impurity concentration in the polysilicon in the lower layer, which has a great effect on determining the work function.

Next, a method of manufacturing the device according to the fourth embodiment will be described. The case of forming using the ion implantation method in the manufacturing method of the first embodiment will be described. Deposit non-doped polysilicon corresponding to the electrode lower layer part,
In each of the NMOS and PMOS regions, for example, a mask is increased one by one, and ion implantation of a required concentration is performed.

According to the fourth embodiment, although the number of mask steps increases, the threshold value and the driving capability can be selected depending on the circuit, so that the present invention can be applied to low power consumption. If the lower electrode is used in a state where the concentration of the lower electrode is lowered and the lower part of the electrode is depleted, a low gate capacitance transistor can be manufactured. With the two-layer structure, the concentration control in the electrode by ion implantation is improved.

Fifth Embodiment A fifth embodiment relates to a method for manufacturing a dual gate electrode structure. As a method of manufacturing a dual gate electrode structure, a method of forming only non-doped polysilicon using ion implantation, a method of forming only using in-situ doped polysilicon, and a method of forming in-situ doped polysilicon In this case, a method of forming by performing ion implantation as necessary is possible. The formed electrode structures are all the same.

The method described above, that is, the formation method using in-situ doped polysilicon is complicated in process. That is, 1) after depositing doped polysilicon containing one type of impurity, 2) removing unnecessary portions,
3) Where necessary, an oxide film or the like having an etching selectivity with polysilicon is used as a mask. 4) Doped polysilicon containing another type of impurity is deposited again. Unnecessary portions are also removed from the film, and 6) the oxide film used as a mask thereunder is removed. 7) Then, lithography of the gate is performed. The above flow is fundamental. As an effect, the concentration profile of the impurity becomes uniform, and the controllability of the concentration in the vicinity of the gate insulating film is better than the method of forming the non-doped polysilicon using only ion implantation. Batch to batch uniformity is also improved.

In the method of performing ion implantation into in-situ doped polysilicon, a P-type electrode is formed by doping a thin N-type polysilicon with a P-type, which is the opposite type, more than that. Is the way. According to this, the degree of freedom in selection increases in terms of process. It can be said that in-situ doped polysilicon is used only in a portion that is difficult to control by ion implantation.

Embodiment 6 This embodiment relates to the dual gate electrode structure in which an insulating film is inserted between upper and lower polysilicon layers to form capacitors simultaneously. FIG.
FIG. 15 is a cross-sectional view of a transistor and a capacitor in a semiconductor device according to a sixth embodiment. P in the main surface of the semiconductor substrate
A well 5 is provided; An isolation insulating film 3 is provided on the main surface of the semiconductor substrate. An N-type gate electrode 9 is provided on the P-well 5 with the gate insulating film 2 interposed. N-type source / drain regions 7 are formed in the main surface of P-well 5 on both sides of N-type gate electrode 9. Surface of N-type source / drain region 7 and N
The silicide layer 1 is provided on the surface of the mold gate electrode 9. A capacitor is formed on the isolation insulating film 3.
The capacitor includes an N-type lower layer portion NG1, an insulating film 12 provided on the lower layer portion NG1, and an upper layer portion NG2 provided on the insulating film 12. The silicide layer 1 is formed on the upper layer portion NG2. An interlayer insulating film 20 is provided so as to cover the transistor section and the capacitor section. In the interlayer insulating film 20, a contact hole 13a for exposing a part of the surface of the N-type source / drain region 7 and a contact hole 1 for exposing a surface of an upper layer portion of the capacitor portion are provided.
3b and a contact hole 13c for exposing a part of the surface of the insulating film 12 are provided.

Next, a method for manufacturing a semiconductor device according to the sixth embodiment will be described. Referring to FIG. 7, P-well 5 and isolation insulating film 3 are formed in the main surface of the semiconductor substrate.
A thin gate insulating film 2 is formed on a semiconductor substrate. Lower polysilicon (NG1) is deposited on the semiconductor substrate with the thin gate insulating film 2 interposed therebetween, and impurities are doped by ion implantation. The portion into which the impurities are implanted serves as an electrode of the transistor and also serves as a lower electrode of the capacitor. Here, the capacitor is formed on the isolation insulating film 3. In addition, the type of the impurities contained in the portion of the capacitor which will be the electrode can be selected from N-type and P-type.

Referring to FIG. 8, an insulating film 12 necessary for forming a capacitor is formed. Examples of the material include an oxide film, a nitride film, and a combination thereof. The film thickness is an amount necessary to obtain a desired capacity. Next, photolithography of the capacitor portion is performed, and patterning is performed by RIE dry etching or the like. In this case, in addition to the area required for the capacitor, a region for taking the lower electrode of the capacitor is also secured (a circle in the figure).

Next, referring to FIG. 9, an upper layer of polysilicon NG2 is deposited and is doped with impurities by an ion implantation method. The portion into which the impurities are implanted serves as an electrode of the transistor and also serves as an upper electrode of the capacitor. The ion implantation performed here may be performed later, concurrently with the source / drain implantation.

Referring to FIG. 10, gate patterning is performed. At this time, with respect to the capacitor portion, a resist is applied only to a region necessary for forming a capacitor. Then, the polysilicon is etched to form a capacitor portion shown in FIG. Normally, since the etching selectivity between polysilicon and the insulating film is sufficient, the insulating film 12 in the circled portion does not penetrate and the polysilicon does not disappear.

Then, after LDD implantation and sidewall formation, source / drain implantation is performed. When the salicide process is performed, only the electrode portion of the transistor and the upper electrode of the capacitor are silicided. After depositing the interlayer film, go to contact. As for the lower electrode of the capacitor, the insulating film 12 is dug by etching.
It will be connected directly to the underlying polysilicon.

According to the embodiment of the present invention, although photolithography is performed once, a dual gate electrode having a polysilicon two-layer structure and a capacitor can be simultaneously formed. Since the capacitance value changes by dividing the electrode of the capacitor into N type and P type,
It is preferable to select these as appropriate.

Seventh Embodiment FIG. 12 is a sectional view of a gate wiring according to a seventh embodiment. The illustrated gate electrode is an N-type gate electrode having an N-type gate electrode.
PMOS having MOS transistor and P-type gate electrode
FIG. 3 is a cross-sectional view of an N-type gate electrode or a P-type gate electrode of a CMOSFET having a transistor. The gate electrode includes an upper layer and a lower layer, and the lower layer is non-doped.
The gate electrode having such a structure is formed by masking the gate wiring portion at the time of ion implantation into the underlying polysilicon. According to the present embodiment, the gate wiring portion where the actual current flows can be separated from the substrate, so that the wiring capacitance to the substrate is reduced. This is effective when the height of the gate electrode needs to be the same as the conventional one. For example, a gate-source /
In order to prevent a short circuit between the drains and to prevent the gate electrode from penetrating the source / drain, the present invention is effective even when the same height as the conventional gate electrode is required.

Eighth Embodiment Referring to FIG. 13, as a gate wiring structure, an insulating film used for forming a capacitor is present between polysilicon in an upper layer and polysilicon in a lower layer. The method of manufacturing such a gate electrode is basically the same as the method of manufacturing the capacitor (Embodiment 6). When the insulating film for forming the capacitor is etched, the gate wiring is etched, and the polysilicon in the upper layer is also patterned thereon. The effects of the eighth embodiment are as follows. That is, since the gate wiring portion where the current actually flows can be separated from the substrate, the capacity generated with respect to the substrate is reduced. Also,
As described in the seventh embodiment, the above effect is further enhanced by making the lower polysilicon layer non-doped.
Further, even when the lower layer polysilicon and the thin tunnel insulating film used in the third embodiment are present, the impurity in the upper layer polysilicon is less likely to diffuse into the lower layer, so that the wiring capacitance to the substrate is reduced. Decrease.

Ninth Embodiment FIG. 14 is a sectional view of a gate wiring according to a ninth embodiment. The gate electrode includes an upper layer and a lower layer. The upper layer is non-doped polysilicon. All or part of the upper layer in the height direction is silicided. According to the ninth embodiment, a low-resistance silicide film can be formed. On the other hand, there is no problem with the function as the gate wiring. By making the lower layer non-doped as in the seventh embodiment, the wiring capacitance to the substrate is further reduced.

Tenth Embodiment FIG. 15 is a sectional view of a gate wiring according to a tenth embodiment. The insulating film formed for the capacitor of the sixth embodiment is used as a silicide protection film for a gate wiring. An insulating film for a capacitor is patterned on the gate insulating film. The polysilicon deposited thereon is removed by gate etching. Since the insulating film serves as a mask when silicide is formed, an interconnect made of only polysilicon in the lower layer is formed. Regarding the contact, either a method of directly contacting the polysilicon in the lower layer or a method of contacting the contact on the gate on which the silicide is formed is possible. The process using the capacitor according to the sixth embodiment has an effect that silicide protection of a gate wiring can be performed without adding a step or a mask.

[0055]

As described above, according to the semiconductor device according to the first aspect of the present invention, since the gate electrode has a structure of two or more layers including the upper layer and the lower layer, the gate electrode has the upper layer and the lower layer. The polysilicon impurity concentration can be set independently. As a result, it is possible to control the work function to a desired value with high accuracy, and to achieve a dual gate electrode without electrode depletion. In addition, the presence of nitrogen in the lower layer improves the barrier properties due to the diffusion of impurities into the thin gate insulating film, and has the effect of preventing penetration into the substrate.

According to the semiconductor device according to the second aspect of the present invention, the gate electrode has a structure of two or more layers including an upper layer and a lower layer, and the impurity concentration in the lower layer is higher than that in the upper layer. Has been enlarged. That is, since the impurity concentration in the polysilicon in the upper layer portion is kept to a necessary minimum, there is an effect that it is possible to form a low-resistance silicide gate wiring without increasing the fine line resistance in forming silicide. .

According to the semiconductor device according to the third aspect of the present invention, there is an effect that a dual gate electrode having a polysilicon two-layer structure and a capacitor are simultaneously formed.

According to the semiconductor device according to the fourth aspect of the present invention, the gate electrode includes the upper layer and the lower layer, and the lower layer is non-doped. This has the effect of reducing the wiring capacitance to the substrate.

According to the semiconductor device according to the fifth aspect of the present invention, the gate electrode includes an upper layer portion and a lower layer portion, at least the upper layer portion is non-doped, and all or part of the upper layer portion in the height direction is formed. Because of silicidation, a low-resistance silicide film can be formed. On the other hand, there is an effect that there is no problem in the function as the gate wiring.

According to the semiconductor device according to the sixth aspect of the present invention, since the semiconductor device includes the silicide protection film formed of the same material as the insulating film, the effect that the silicide protection of the gate wiring becomes possible is achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a complementary field effect transistor according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an impurity concentration profile of a dual gate electrode of a complementary field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a diagram showing another impurity concentration profile of the dual gate electrode structure of the complementary field effect transistor according to the second embodiment of the present invention.

FIG. 4 is a sectional view of a dual gate electrode structure of a complementary field effect transistor according to a third embodiment of the present invention.

FIG. 5 is a concentration profile in a gate electrode of the complementary field effect transistor according to the third embodiment.

FIG. 6 is a cross-sectional view of a transistor and a capacitor in a semiconductor device according to a sixth embodiment;

FIG. 7 is a cross-sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a sixth embodiment.

FIG. 8 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 9 is a cross-sectional view of the semiconductor device in a third step in the order of the method of manufacturing the semiconductor device according to the sixth embodiment.

FIG. 10 is a cross-sectional view of the semiconductor device in a fourth step in the order of the method of manufacturing the semiconductor device according to the sixth embodiment.

FIG. 11 is a cross-sectional view of the semiconductor device in a fifth step in the order of the method of manufacturing the semiconductor device according to the sixth embodiment.

FIG. 12 is a sectional view of a gate wiring according to a seventh embodiment.

FIG. 13 is a sectional view of a gate wiring structure according to an eighth embodiment.

FIG. 14 is a sectional view of a gate wiring according to a ninth embodiment;

FIG. 15 is a sectional view of a gate wiring according to a tenth embodiment;

FIG. 16 is a sectional view of a conventional complementary field effect transistor.

[Explanation of symbols]

1 silicide film, 2 thin film gate insulating film, 3 isolation insulating film, 4 sidewall spacer, 5 P-well,
6 N-well, 7 N-type source / drain regions, 8
P-type source / drain region, 9 N-type gate electrode, 10
P-type gate electrode

Claims (9)

[Claims] 1. An NMOS transistor having an N-type gate electrode containing an N-type impurity, and a PMOS transistor having a P-type gate electrode containing a P-type impurity, wherein the N-type gate electrode has an upper layer portion. A P-type gate electrode having a structure of two or more layers including an upper layer portion and a lower layer portion; and a P-type gate having a lower layer portion of the N-type gate electrode. A semiconductor device, wherein at least one of the lower layer portions of the electrode contains nitrogen. 2. An NMOS transistor having an N-type gate electrode containing an N-type impurity, and a PMOS transistor having a P-type gate electrode containing a P-type impurity, wherein the N-type gate electrode and the P-type gate are provided. Each of the electrodes has a structure of two or more layers including an upper layer portion and a lower layer portion, and in each gate electrode, the impurity concentration in the lower layer portion is set higher than that in the upper layer portion. , Semiconductor devices. 3. The semiconductor device according to claim 1, wherein the N-type gate electrode and the P-type gate electrode each include a tunnel insulating film provided between the upper layer and the lower layer. . 4. The NMOS transistor and the P transistor
A plurality of MOS transistors are provided, and the impurity concentration in the lower layer portion of the N-type gate electrode of some NMOS transistors is different from that of other NMOS transistors. 4. The semiconductor device according to claim 1, wherein an impurity concentration in said lower layer portion is different from that of another PMOS transistor. 5. An NMOS transistor having an N-type gate electrode containing an N-type impurity, a PMOS transistor having a P-type gate electrode containing a P-type impurity, and a capacitor portion formed on a field oxide film. The capacitor portion includes: a lower layer portion into which one of the N-type or P-type impurities is implanted; an insulating film provided on the lower layer portion; And an upper layer portion provided with the one type of impurity. 6. An NMOS transistor having an N-type gate electrode, and a PMOS transistor having a P-type gate electrode, wherein the N-type gate electrode and the P-type gate electrode have an upper layer portion and a lower layer portion, respectively. The semiconductor device, wherein the lower layer portion is non-doped. 7. The semiconductor device according to claim 6, wherein an insulating film is provided between said upper layer portion and said lower layer portion. 8. A transistor having a gate electrode, wherein each of the gate electrodes includes an upper layer portion and a lower layer portion, and at least the upper layer portion is non-doped, and all or part of the upper layer portion in a height direction is provided. Has been silicided,
Semiconductor device. 9. A semiconductor device comprising: a gate line; and a capacitor portion formed on a field oxide film, wherein the capacitor portion includes a lower portion into which an impurity is implanted and an insulating portion provided on the lower portion. A film, and an upper layer portion provided on the insulating film, the device is further provided on the gate wiring,
A semiconductor device comprising a silicide protection film formed of the same material as the insulating film.