JPH1050777A - Semiconductor device and production thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device and a production method thereof by increasing the production yield of chip while simplifying the production process. SOLUTION: An integrated circuit 61 is formed on a semiconductor wafer using an IC fabrication process and then bonding pads 31-33 for connecting the integrated circuit 61 with an external circuit are provided thus forming a main chip part 11. Probe pads 41-43 are then provided in a region of the semiconductor wafer other than the main chip part 11 thus forming a monitor chip part 21. Prior to wafer test where probe needles 51-53 are abutted against the bonding pads 31-33 at the main chip part 11, the probe needles 51-53 are abutted against the probe pads 41-43 at the monitor chip part 21 and the abutting conditions are adjusted. While keeping the adjusted abutting conditions, the probe needles 51-53 are set to abut against the bonding pads 31-33 thus a wafer test surely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor wafer.
The present invention relates to a semiconductor device formed by performing a C manufacturing process and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor wafer has a plurality of circuits formed on an upper portion thereof and is cut into semiconductor chips by the formed circuits. Usually, semiconductor chips are rectangular, and before being cut, they are in close contact with each other without gaps.

On the other hand, semiconductor wafers are circular,
It is impossible to make the whole semiconductor wafer into a semiconductor chip. If an attempt is made to force the entire semiconductor wafer into semiconductor chips, the outermost semiconductor chip of the semiconductor wafer will not be rectangular.

In the process of forming a semiconductor chip, a peripheral portion of the semiconductor wafer near the outside comes into contact with jigs and tools of a production facility. For this reason, there is a high probability that a semiconductor chip formed in the peripheral portion becomes a defective chip.

Further, in the peripheral portion of the semiconductor wafer, the thickness of the photoresist applied in the photolithography process varies, and it is difficult to form a desired circuit with high accuracy.

[0006] For the above reasons, semiconductor chips are often not formed in the peripheral portion of the semiconductor wafer. As a technique for utilizing the peripheral portion of a semiconductor wafer, a conventional technique of forming a bad mark to be attached to a defective chip (Invention Association published technical report 94-816) is known.

Before a semiconductor wafer having a circuit formed thereon is cut, it is necessary to inspect the circuit by a wafer test. In a wafer test, a probe needle connected to a tester is brought into contact with an electrode of a circuit to check the electrical characteristics of the circuit. The place where the probe needle contacts is a bonding pad which is a part to be wire-bonded among the electrodes. Inspection of the circuit is performed for each circuit, and the probe needle is set so as to automatically contact each bonding pad of the circuit.

Further, the tip of the probe needle is set so as to abut substantially the center of each bonding pad and to penetrate to an appropriate depth of the bonding pad.

In order to inspect a single semiconductor wafer, the contact state of the probe needle is set in a circuit to be inspected first in the semiconductor wafer, and the first probe needle is set in a circuit to be inspected thereafter. The inspection is performed based on The first subtle setting relies on human vision.

Note that an initial setting deviation may occur during a wafer test, which may damage the wiring portions of the electrodes other than the bonding pads. In this case, the damaged circuits are removed one by one by a visual inspection later.

[0011]

The contact position of the probe needle and the depth of the bite are adjusted by human eyes, so that there is a great difference between individuals. In addition, when adjusting, the probe may fail to contact the bonding pad, or the probe may bite into the bonding pad too deeply, thereby damaging the circuit.

During the inspection of a plurality of circuits, the contact position of the initially set probe may be shifted during the test, and the probe needle may not contact the bonding pad. Circuits not contacted by the probe needle are not tested. In addition, the probe needle whose contact position is shifted may damage circuits other than the bonding pad.

After the completion of the wafer test, it is necessary to visually inspect all the circuits in order to check the contact state of the probe needles with the bonding pads, which is very time-consuming.

It is an object of the present invention to provide a highly reliable semiconductor device and a method for manufacturing the same by improving the yield of chips and simplifying the manufacturing process.

[0015]

SUMMARY OF THE INVENTION The present invention provides a substrate made of a semiconductor material, an integrated circuit formed on the substrate using an IC manufacturing process, and a bonding pad for connecting the integrated circuit to an external circuit. This chip section including
A semiconductor device comprising: a monitor chip portion including a probe pad to which an inspection probe can contact in a region other than the main chip portion of the substrate. According to the present invention, a wafer test for a semiconductor device is performed by bringing a probe into contact with a bonding pad of the present chip portion. Before the wafer test, the probe is brought into contact with the probe pad of the monitor chip portion, and the contact position of the probe and the bite depth are adjusted. As a result, the probe can be accurately brought into contact with the bonding pad and the inspection can be performed accurately, so that the reliability of the operation of the semiconductor device is improved. In addition, the probe can be adjusted without using this chip, and it does not damage this chip,
The yield of chips can be improved.

The present invention also provides a step of forming an integrated circuit on a substrate made of a semiconductor material by using an IC manufacturing process;
Forming a bonding pad for connecting the integrated circuit to an external circuit on the substrate to form a main chip portion; and contacting an inspection probe with a region other than the main chip portion of the substrate. Forming a monitor chip portion by forming a possible probe pad and forming a monitor chip portion. According to the present invention, the chip section includes an integrated circuit and a bonding pad, and the monitor chip section includes a probe pad. A wafer test for this semiconductor device is performed by bringing a probe into contact with a bonding pad of the present chip portion. Before the wafer test, the probe is brought into contact with the probe pad of the monitor chip portion, and the contact position of the probe and the bite depth are adjusted. As a result, the probe can be accurately brought into contact with the bonding pad and the inspection can be performed accurately, so that the reliability of the operation of the semiconductor device is improved. In addition, the probe can be adjusted without using this chip, and it does not damage this chip,
The yield of chips can be improved.

Further, according to the present invention, the relative positions of the probe pads in the monitor chip portion coincide with the relative positions of the bonding pads in the main chip portion. According to the present invention, the probe pad is formed at a position where the probe pad overlaps the bonding pad when the monitor chip portion is moved in parallel and superimposed on the main chip portion. When the contact position and the bite depth of the probe are adjusted in accordance with the probe pad, the probe can be more reliably brought into contact with the bonding pad of the present chip portion.

Further, according to the present invention, the area of the probe pad of the monitor chip portion is smaller than the area of the bonding pad of the main chip portion. According to the present invention,
A probe pad having a smaller area than the bonding pad is formed. If the probe is set to contact the smaller probe pad, it is more certain that the probe will contact the larger bonding pad.

Further, the present invention is characterized in that the method further comprises a step of marking a scale around the probe pad of the monitor chip portion. According to the present invention, the positions of the probe traces remaining on the probe pads of the monitor chip portion can be quantitatively specified by marking scales at equal intervals around the monitor chip portion, for example, in two directions, and the contact position of the probe Can be easily adjusted. In the case of a probe having a shape that becomes thinner toward the tip, the size of the probe mark can be quantitatively specified by the scale, and the depth of the probe bite can be easily adjusted.

Further, the present invention further includes a step of inspecting the operation of the integrated circuit by using a probe for inspection in a predetermined order for the plurality of main chip parts. In the monitor chip part forming step, the inspection is performed first. A monitor chip section is formed at a position adjacent to the main chip section to be tested and at a position adjacent to the main chip section to be tested last. According to the present invention, one monitor chip portion is formed at a position adjacent to the main chip portion to be tested first, and one monitor chip portion is formed at a position adjacent to the main chip portion to be tested last. The former is used to confirm the contact state of the probe before performing the wafer test, and the latter is used to confirm the contact state of the probe again after the completion of the wafer test. In this manner, in the visual inspection performed later, the contact state of the probe with the main chip portion can be known only by checking the contact state of the probe with the two monitor chip portions. The labor required for visual inspection after the test can be greatly reduced.

[0021]

1 to 3 show a first embodiment of the present invention.
FIG. 1 is a plan view of a semiconductor device 1 and FIG.
FIG. 3 is a partially enlarged view, and FIG. 3 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 1, a plurality of main chip portions 10 having circuits are formed on a semiconductor wafer 2 and are closely arranged in a matrix. This chip part 1
Numeral 1 is located at the left end of the first row from the top among a plurality of main chip units 10 arranged in a matrix. The monitor chip unit 21 is located adjacent to the left of the main chip unit 11.
Are formed. The main chip section 12 and the monitor chip section 22 at the lower right of FIG. 1 will be described later.

As shown in FIG. 2, an integrated circuit 61 is formed in the chip section 11, and bonding pads 31 and 32 are provided so as to contact the integrated circuit 61.
And a bonding pad 33 are formed. By using respective IC manufacturing processes such as oxidation, photolithography, impurity diffusion, and electrode formation, an integrated circuit 61 having predetermined electric operation characteristics is formed, and metal bonding pads 31 to 33 are formed. The bonding pads 31 to 33 are used during a wafer test performed before the semiconductor device 1 is separated for each semiconductor chip.
This is a portion where the probe needle comes into contact, and a portion that is wire-bonded after being cut. A plurality of main chip units 10 (FIG. 1) other than the main chip unit 11 are all
It is formed in the same manner as the main chip portion 11.

No integrated circuit is formed on the monitor chip section 21, but only probe pads 41 to 43 are formed. The probe pads 41 to 43 are portions for checking the contact state by contacting the probe needles, and are made of metal, similarly to the bonding pads 31 to 33, and formed by using an appropriate IC manufacturing process. A probe pad 41 is formed at a relative position of the monitor chip section 21 corresponding to the bonding pad 31 of the present chip section 11. The area of the probe pad 41 is smaller than the area of the bonding pad 31, and the center of the probe pad 41 is
1 corresponds to the relative position of the monitor chip unit 21 corresponding to the center of the monitor chip 1. Similarly, the probe pad 42 is formed at a position corresponding to the bonding pad 32, and the probe pad 43 is formed at a position corresponding to the bonding pad 33.

The size of the pad is, for example,
While the size of one bonding pad is about 100 to 150 μm square, the size of the probe pad of the monitor chip unit 21 is about 50 μm square.

As shown in FIG. 3, a bonding pad 31 is formed on the present chip portion 11 so as to be in contact with the semiconductor wafer 2 via an electric insulating film 71. The bonding pad 31 contacts a diffusion layer 72 formed by diffusing impurities into the semiconductor wafer 2. Monitor chip unit 21
Only the probe pads 43 are formed directly on the semiconductor wafer 2.

The step of forming the integrated circuit of each main chip section 10, the step of forming the bonding pads, and the step of forming the probe pads of the monitor chip section are all performed simultaneously. After these three steps are performed simultaneously and before the wafer test, the following is performed.

As shown in FIG. 2, the probe needle 51,
The probe needle 52 and the probe needle 53 are brought into contact with the probe pad 41, the probe pad 42 and the probe pad 43, respectively, and the contact positions and the bite depth of the probe needles 51 to 53 are adjusted. During the inspection of the plurality of main chip portions 10, the contact position is set to substantially the center of the probe pads 41 to 43 so that the contact position does not shift. If the depth of the probe needles 51 to 53 is too deep, the circuit will be damaged, and if it is too shallow, the inspection will not be performed.
It is necessary to keep an appropriate depth. Since the probe needles 51 to 53 have a shape that becomes thinner toward the distal end, the depth of the bites of the probe needles 51 to 53 can be adjusted by adjusting the probe needles to an appropriate size by looking at the probe needle holes.

The probe needles 51 to 53 adjusted to appropriate contact positions and bite depths automatically move in parallel and contact the bonding pads 31 to 33 of the chip portion 11 in the same contact state. When the inspection is completed, the setting is performed so that the other main chip units 10 are sequentially inspected.

In the semiconductor device 1 formed as described above, the monitor chip portion formed on the peripheral portion of the semiconductor wafer 2 without using the chip portion 10 when adjusting the contact state of the probe needles 51 to 53. Is used, the chip part 10
Will not hurt.

The areas of the probe pads 41 to 43 may be equal to the areas of the bonding pads 31 to 33, respectively. Further, a probe pad of another shape may be formed on the monitor chip section 21, for example, the probe pad may cover the entire area of the monitor chip section 21. However, by reducing the size of the probe pad as shown in FIG. 2, the probe needle can be more reliably brought into contact with the bonding pad of the present chip portion 11.

FIG. 4 shows a second embodiment of the present invention. Each probe pad 41 of the monitor chip unit 21 shown in FIG.
It is a figure showing what attached scales 81-86 to 43. Five equally spaced scales 81 are provided horizontally on the probe pad 41, and five equally spaced scales 82 are vertically provided adjacent to the left. Similarly, a scale 83 and a scale 84 are attached to the probe pad 42, and the probe pad 43
Are provided with a scale 85 and a scale 86.

The formation of the integrated circuit, the formation of the bonding pads, the formation of the probe pads, and the formation of the scales 81 to 86 are all performed simultaneously. Thereafter, and before the wafer test, the probe needles 51 to 53 are respectively brought into contact with the probe pads 41 to 43 to adjust the contact state. The contact position of the probe needle 51 is arranged substantially at the center while viewing the scales 81 and 82 formed on the probe pad 41. The bite depth of the probe needle 51 is
While watching the scales 81 and 82, adjustment is made by making the size of the appropriate needle hole. Similarly, the contact state of the probe needles 52 and 53 is adjusted.

FIG. 5 is a plan view showing the needle holes of the probe needles 51 to 53 abutting on the monitor chip part 21 of FIG.
The needle hole 91 of the probe needle 51 is located substantially at the center of the probe pad 41, and has a size of about two scales horizontally and about two scales vertically. The needle hole 92 of the probe needle 52 and the needle hole 93 of the probe needle 53 are one scale both vertically and horizontally, and are shifted downward from the center by about one scale. Assuming that the size of the appropriate needle hole is one scale in both the vertical and horizontal directions, the bite depth of the probe needle 51 may be reduced, and the contact positions of the probe needles 52 and 53 may be shifted upward by one scale.

The width of the graduation is, for example, 10 μm per graduation for a probe pad of 50 μm square. The tip of the probe needle is, for example, 10 μm.

By attaching graduations 81 to 86 to the probe pads 41 to 43 as shown in FIG. 4, the positions of the probe needle holes can be quantitatively specified as coordinates in two directions on the probe pads 41 to 43. Can be quantitatively specified as the difference between the coordinates in the two directions. by this,
The contact state of the probe needles 51 to 53 can be easily adjusted, and the probe needles 51 to 53 can be reliably brought into contact with the bonding pads during a wafer test.

Any number of monitor chip portions may be formed anywhere in the peripheral portion of the semiconductor wafer 2, and as shown in FIG.
Only one piece may be formed. In this case, the monitor chip unit 21
Is formed at a position adjacent to the main chip unit 11, and the monitor chip unit 22 is formed at a position adjacent to the main chip unit 12.

When a wafer test is performed on the semiconductor device 1 shown in FIG. 1, the main chip unit 11 is first inspected, and the main chip units 10 in the first row from the top are inspected sequentially from the left.
When the first line is completed, the process proceeds to the second line, the third line,..., And the chip units 10 in each line are inspected in order from the left. Finally, the main chip unit 12 is inspected, and the wafer test ends.

The probe needle is brought into contact with the monitor chip portion 21 adjacent to the main chip portion 11 to be inspected first before the main chip portion 11 is inspected, and the state of contact is adjusted. After the wafer test is completed, the probe needle is brought into contact with the probe pad in the monitor chip section 22 adjacent to the main chip section 12 to be tested last.

As described above, at the time of visual inspection after visual inspection, the trace of the needle remaining on the probe pad of the monitor chip section 22 is confirmed, and if an appropriate needle hole remains, the semiconductor device 1 is removed. It can be considered that the probe needle has contacted all the bonding pads of the plurality of main chip portions 10 in an appropriate contact state, and there is no need to check the plurality of main chip portions 10. If the needle mark is not appropriate, it is only necessary to confirm the tip portion 10 for the first time. By doing so, it is possible to greatly reduce the time and labor required for appearance inspection after the wafer test.

Incidentally, a bad mark to be attached to a defective chip may be formed in these monitor chip portions. In this case, the formation of the bad mark can be confirmed without damaging the present chip portion 10.

[0041]

As described above, according to the present invention, since the probe can be accurately brought into contact with the bonding pad of the present chip portion and the inspection can be performed accurately, the reliability of the operation of the semiconductor device is improved. I do. In addition, the probe can be adjusted without using this chip, and it does not damage this chip,
The yield of chips can be improved.

According to the present invention, when the probe pad is formed such that the probe pad overlaps the bonding pad when the monitor chip portion is moved in parallel to the main chip portion, the bonding pad of the main chip portion is formed. ,
More reliable contact can be achieved.

Further, according to the present invention, by forming a probe pad having a smaller area than a bonding pad,
Further, the probe can be reliably brought into contact with the bonding pad.

Further, according to the present invention, when a scale is marked around the probe pad, the position and size of the probe mark remaining on the probe pad of the monitor chip portion can be quantitatively specified, and the contact of the probe can be performed. It is easy to adjust the position and the bite depth.

Further, according to the present invention, the contact state of the probe with respect to this chip portion can be known only by checking the contact state of the probe with the two monitor chip portions. The labor of appearance inspection can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device 1 according to a first embodiment of the present invention.

FIG. 2 is a partially enlarged view of the semiconductor device 1.

FIG. 3 is a cross-sectional view taken along the line AA of FIG. 2;

FIG. 4 is a partially enlarged view of a semiconductor device 1 according to a second embodiment of the present invention.

FIG. 5 is a plan view showing needle holes 91 to 93 of probe needles 51 to 53.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor wafer 10-12 Main chip part 21,22 Monitor chip part 31-33 Bonding pad 41-43 Probe pad 51-53 Probe needle 61 Integrated circuit 71 Electric insulating film 72 Diffusion layer 81-86 Scale

Claims (6)

[Claims] A chip portion including a substrate made of a semiconductor material, an integrated circuit formed on the substrate using an IC manufacturing process, and bonding pads for connecting the integrated circuit to an external circuit; A semiconductor device, comprising: a monitor chip portion including a probe pad to which an inspection probe can contact in a region other than the main chip portion of a substrate. 2. A step of forming an integrated circuit on a substrate made of a semiconductor material by using an IC manufacturing process, and forming a bonding pad on the substrate for connecting the integrated circuit to an external circuit. Forming a monitor chip portion in a region other than the main chip portion of the substrate by forming a probe pad to which a probe for inspection can be brought into contact, and forming a monitor chip portion. Manufacturing method. 3. The method according to claim 2, wherein a relative position of a probe pad in the monitor chip portion coincides with a relative position of a bonding pad in the main chip portion. 4. The method according to claim 3, wherein an area of the probe pad in the monitor chip portion is smaller than an area of a bonding pad in the main chip portion. 5. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of marking a scale around a probe pad of said monitor chip portion. 6. A method according to claim 1, wherein the plurality of chip portions are arranged in a predetermined order.
Further comprising the step of inspecting the operation of the integrated circuit using a probe for inspection, wherein in the monitor chip part forming step, a position adjacent to the main chip part to be inspected first and adjacent to the main chip part to be inspected last 6. The method for manufacturing a semiconductor device according to claim 2, wherein a monitor chip portion is formed at a position where the monitor chip portion is formed.