JPH1050727A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a normally off type FET having a reduced parasitic resistance, low gate leakage current or improved gate withstand voltage by providing a one-conductivity type carrier feed layer and a reverse-conductivity type threshold control layer partly formed beneath a gate electrode. SOLUTION: A one-conductivity type carrier feed layer 22, channel layer 23 having a higher electron affinity than that of the layer 22 and gate barrier layer 24 having a lower electron affinity than that of the layer 23 are formed on a semi-insulative substrate 21. A reverse-conductivity type threshold control layer 25a is partly formed on the gate barrier layer 24 and gate electrode 26 is formed on the layer 25a. Source/drain regions 28a, 28b are formed at both sides of the layer 25a with spacings from the ends of this layer 25a. Source/drain electrodes 29a, 29b are formed on the regions 28a, 28b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a field effect transistor having a carrier supply layer.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a semiconductor device which operates at high speed with low power consumption. For this purpose, it is necessary to increase the gate breakdown voltage of the element and control the threshold voltage without increasing the parasitic resistance, thereby reducing the power consumption and increasing the driving current. For example, FIG. 8A shows a conventional example of an n-type field-effect transistor (n-type FET) having a structure in which a carrier supply layer is provided below a channel layer.

As shown in FIG. 8A, a semi-insulating substrate 1
An n-type conductivity type carrier supply layer 2 and a non-doped channel layer 3 having a higher electron affinity than the carrier supply layer 2 are formed thereon.
And a non-doped gate barrier layer 4 having a smaller electron affinity than the channel layer 3 are deposited in this order. Then, the gate electrode 6 is partially formed on the gate barrier layer 4, and further on both sides of the gate electrode 6 so as not to be in contact with the gate electrode 6, at an interval from the end of the gate electrode 6. Source / drain regions 5a and 5b reaching the semi-insulating substrate 1 from the four surfaces are formed. Then, source / drain electrodes 7a, 7b are formed on the source / drain regions 5a, 5b.

FIGS. 8B and 8C show FIGS. 8A and 8B, respectively.
FIG. 2 shows an energy band diagram in a section taken along line II and a section taken along line II-II. The solid line indicates the case where no gate voltage is applied (V _G), the dotted line shows the case the application of the gate voltage (V _G). In this FET, the threshold value is controlled by adjusting the n-type impurity concentration of the carrier supply layer 2.

FIG. 9A shows another conventional n-type FE.
T. As shown in FIG. 9A, the semi-insulating substrate 11
A non-doped channel layer 12, a gate barrier layer 13 having a smaller electron affinity than the channel layer 12, and a p-type or n-type conductivity type threshold control layer 14 are deposited in this order.
After partially forming the gate electrode 16, the gate electrode 16
Using the mask as a mask, the threshold control layer 14 is etched in a self-aligned manner and is left under the gate electrode 16.

Further, an n-type semiconductor which reaches the semi-insulating substrate 11 from the surface of the gate barrier layer 13 at a distance from an end of the threshold control layer 14 so as not to contact the threshold control layer 14 on both sides of the threshold control layer 14. Source / drain regions 15a, 1
5b is formed. Then, source / drain electrodes 17a, 1a are formed on the source / drain regions 15a, 15b.
7b is formed.

FIGS. 9B and 9C respectively show FIG. 9A
FIG. 2 shows an energy band diagram in a section taken along line II and a section taken along line II-II. The solid line indicates the case where no gate voltage is applied (V _G), the dotted line shows the case the application of the gate voltage (V _G). In this FET, the threshold control layer 14 has p
In the case of the type conductivity type, it becomes a normally-off type, and in the case of the n-type conductivity type, it becomes a normally-on type. Further, the threshold voltage is finely adjusted by adjusting the impurity concentration of the threshold control layer 14. Note that p
In the case of a type FET, the above is reversed.

[0008]

In order to reduce power consumption in an FET used for a complementary field effect transistor,
A normally-off type FET is required. However, in the FET shown in FIG. 8A, when the conductivity type impurity concentration is reduced in order to make the threshold voltage normally off, the channel layer 3 in the portion between the gate electrode 6 and the source / drain regions 5a and 5b is reduced. , The parasitic resistance increases, and the current that can flow through the FET decreases.

If the source / drain regions 5a and 5b are brought into contact with the gate electrode 6 so that the parasitic resistance does not increase, the gate leakage current increases and the power consumption increases. Further, in the FET shown in FIG.
In the case of the normally-off type, as in the case of FIG. 8A, unless the source / drain regions 15a and 15b are brought into contact with or overlapped with the gate electrode 16, the parasitic resistance of the FET increases, and the FET operates. No longer. vice versa,
The source / drain regions 15a, 15b are
If they are formed so as to be in contact with or overlap with each other, the gate breakdown voltage will be reduced.

Therefore, any of the cases shown in FIGS. 8A and 9A is not suitable for a normally-off type FET which requires a high-speed operation with low power consumption. The present invention has been made in view of the above-described problems of the conventional example, and provides a normally-off type FET that can reduce parasitic resistance, reduce gate leakage current, or improve gate breakdown voltage. Things.

[0011]

The first object of the present invention is to provide a carrier supply layer of one conductivity type on a semi-insulating substrate and a carrier supply layer formed on the carrier supply layer. A channel layer having a high electron affinity, a gate barrier layer formed on the channel layer and having a lower electron affinity than the channel layer, and a threshold control layer of the opposite conductivity type partially formed on the gate barrier layer. A gate electrode on the threshold control layer, on both sides of the threshold control layer, spaced from an end of the threshold control layer, and formed so as to reach the channel layer from the surface of the gate barrier layer. And a source / drain region formed on the source / drain region and a source / drain electrode formed on the source / drain region.
A channel layer on a semi-insulating substrate, a carrier supply layer of one conductivity type formed on the channel layer and having a smaller electron affinity than the channel layer, and formed on the carrier supply layer. A gate barrier layer having a smaller electron affinity than the carrier supply layer, a threshold control layer of an opposite conductivity type partially formed on the gate barrier layer, a gate electrode on the threshold control layer, and the threshold control layer. And a source / drain region formed at an interval from an end of the threshold control layer and so as to reach the channel layer from the surface of the gate barrier layer;
And a source / drain electrode formed on the drain region.
A third invention, a channel layer on a semi-insulating substrate, a carrier supply layer of one conductivity type formed on the channel layer and having a smaller electron affinity than the channel layer, and a portion on the carrier supply layer Formed, a gate barrier layer having a smaller electron affinity than the carrier supply layer, an opposite conductivity type threshold control layer formed on the gate barrier layer,
A gate electrode formed on the threshold control layer; and source / drain electrodes formed on the carrier supply layer on both sides of the gate electrode and spaced from an end of the threshold control layer. A fourth aspect of the present invention, which is solved by a semiconductor device, wherein a threshold voltage is controlled by at least one of an impurity concentration of the carrier supply layer and an impurity concentration of the threshold control layer. The problem is solved by the semiconductor device according to any one of the first to third inventions.

The semiconductor device according to the present invention has a carrier supply layer of one conductivity type and a threshold control layer of the opposite conductivity type formed partially below the gate electrode. Therefore, under the gate electrode, by the threshold control layer of the opposite conductivity type,
For an n-type channel, the energy level at the bottom of the conduction band (E _C ) is higher than the Fermi level (E _F ),
As the electrons are depleted, the energy level (E _C ) at the bottom of the conduction band becomes lower than the Fermi level (E _F ) in the channel layer around the gate electrode, and the electrons supplied from the carrier supply layer accumulate. . Also, in the case of the p-type channel, the energy level (E _V ) at the top of the valence band is the Fermi level (E _F ) as in the case of the n-type channel.
, The holes are depleted, and the energy level (E _V ) at the top of the valence band is higher than the Fermi level (E _F ) in the channel layer around the gate electrode, so that the carrier supply layer The supplied holes accumulate.

Thus, the source / drain regions according to the first and second inventions or the source / drain electrodes according to the third invention can be moved from the end of the partially formed gate electrode, threshold control layer or gate barrier layer. Even when they are separated, carriers accumulate in the channel layer in the region between them. Therefore, the parasitic resistance can be reduced, the gate leak current can be reduced, or the gate withstand voltage can be improved.

On the other hand, since carriers are depleted in the channel layer below the gate electrode, a normally-off type FET can be realized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 (a) to 1 (d), 2
(A) and (b) show F according to the first embodiment of the present invention.
It is sectional drawing shown about the manufacturing method of ET.

First, as shown in FIG.
The molecular beam epitaxy (M
A carrier supply layer 22 of about 2 nm in thickness containing about 5 × 10 ¹⁸ cm ^{−3 of} n-type impurity Si and a non-doped layer of about 10 nm in thickness having a higher electron affinity than the carrier supply layer 22 by the BE) method. In _x Ga _1-x As film (x =
0.2) and a non-doped layer having a thickness of about 20 nm and having a smaller electron affinity than the channel layer 23.
A gate barrier layer 24 made of an Al _y Ga _1-y As film (y = 0.3) and a film thickness of about 2 including 3 × 10 ¹⁸ cm ^{−3 of} p-type impurity C;
A threshold control layer 25 made of a 0 nm GaAs film is deposited in this order. Electron affinity chi _eB substrate 21 and the layers _{22~25, χ eca, χ ech,} χ eGB, the relationship between the chi _eSC shown in FIG. Here, Ec is the energy of the bottom of the conduction band, Ev is the top energy of the valence band, the E _F shows the Fermi energy.

Next, as shown in FIG. 1B, after forming a WSi film on the threshold control layer 25, it is patterned.
A gate electrode 26 is formed. Next, as shown in FIG. 1C, the threshold control layer 25 is etched using the gate electrode 26 as a mask, and the threshold control layer 25a is formed under the gate electrode 26.
Leave. Next, as shown in FIG. 1D, the resist film is patterned to form a mask 27, and a dose of 1 ×
The n-type impurity Si is ion-implanted according to the mask 27 at 10 ¹⁵ cm ^-2 and an acceleration voltage of 50 keV. Ion implantation layer 2
8a and 28b are formed on both sides of the gate electrode 26, at a distance from the end of the gate electrode 26 so as not to contact the gate electrode 26, and so as to reach at least the channel layer 23 from the surface of the gate barrier layer 24. You. In addition,
In the case of FIG. 1D, ions are implanted so as to reach the semi-insulating substrate 21.

Next, as shown in FIG.
Annealed at 0 ° C., the source / drain regions 28 a and 28 reaching the semi-insulating substrate 21 from the surface of the gate barrier layer 24.
b is formed. Next, a 50 nm-thick AuGe film and a 300 nm-thick Au film are deposited and patterned to form source / drain electrodes 29a and 29b on the source / drain regions 28a and 28b.

The FET formed as described above has a threshold voltage of about -0.5V. Fig. 4 shows the energy band diagram.
(A) and (b) show. FIG. 4A shows a cross section taken along line III-III, and FIG. 4B shows a cross section taken along line IV-IV. FIG. 4 (a),
In (b), the solid line shows the case where the gate voltage (V _G ) is not applied, and the dotted line shows the case where the gate voltage (V _G ) is applied.

[0020] In the channel layer 23 under the gate electrode 26, as shown in FIG. 4 (a), Ec is raised higher than E _F by threshold control layer 25a is interposed, the channel layer is an electron depletion Become That is, the gate voltage (V
_G ) is normally off when not applied. By applying the gate voltage (V _G ), Ec becomes lower than E _F , electrons are supplied to the channel layer 23, and current flows between the source / drain electrodes 29a and 29b.

The source / drain regions 28a, 28
Even when b is separated from the end of the gate electrode 26, electrons supplied from the carrier supply layer 22 when no gate voltage is applied exist in the channel layer 23 between them, as shown in FIG. I do. For this reason, the parasitic resistance of the FET decreases. Therefore, according to the FET of the first embodiment, the parasitic resistance can be reduced, the gate leak current can be reduced, or the gate breakdown voltage can be improved.

In the first embodiment, the channel layer 2
3 of In _x Ga _1-x As layer of the composition x of 0.2, but the composition y of Al _y Ga _1-y As layer of the gate barrier layer 24 is set to 0.3, the electron affinity chi _ech, chi _EGB It may be changed appropriately in consideration of the threshold voltage and the like. Also, in order to adjust the threshold voltage, etc.,
It is possible to appropriately change the impurity concentration of the carrier supply layer 22 and the threshold control layer 25a.

Further, in the first embodiment, the n-channel F
Although applied to ET, it is also possible to apply to p-channel FET. Carrier supply layer 22, threshold control layer 25
By reversing the conductivity types of the a and the source / drain regions 28a and 28b, the parasitic resistance can be reduced, the gate leakage current can be reduced, or the gate breakdown voltage can be improved, as in the n-channel FET. . In this case, the energy band diagrams are as shown in FIGS. FIG. 5A shows an area under the gate electrode, and FIG. 5B shows an area between the source / drain region and the gate electrode.

(Second Embodiment) FIG. 6 is a sectional view showing an FET according to a second embodiment. The FET according to the second embodiment differs from the first embodiment in that an n-type carrier supply layer 33 is interposed between a channel layer 32 and a gate barrier layer 34.

In FIG. 6, the other reference numeral 31 denotes Ga.
As a semi-insulating substrate made of As, 35 is a gate electrode 3
7 is a p-type threshold control layer partially formed underneath.
36a and 36b are formed on both sides of the gate electrode 37 so as to be spaced from the end of the gate electrode 37 so as not to contact the gate electrode 37 and to reach the semi-insulating substrate 21 from the gate barrier layer 24. These are n-type source / drain regions. 38a and 38b are source / drain electrodes formed on the source / drain regions 36a and 36b.

[0026] Also in this case, as in the first embodiment, the channel layer 32 under the gate electrode 37, Ec is raised higher than E _F by threshold control layer 35 of p-type is interposed As a result, the electrons in the channel layer 32 are depleted, so that they are normally off when the gate voltage (V _G ) is not applied. When applying the gate voltage (V _G), Ec is lower than E _F, a current flows in the channel layer 32 is an electron supply source / drain electrodes 38a, between 38b.

The source / drain regions 36a, 36
Even when b is separated from the end of the gate electrode 37, electrons supplied from the n-type carrier supply layer 33 exist in the channel layer 32 between them when no gate voltage is applied. For this reason, the parasitic resistance of the FET decreases. Therefore, according to the FET of the second embodiment, the parasitic resistance can be reduced, the gate leakage current can be reduced, or the gate withstand voltage can be improved.

(Third Embodiment) FIG. 7 is a sectional view showing an FET according to a third embodiment.

In the FET according to the third embodiment,
The difference from the second embodiment is that the gate barrier layer 4
4 is partially formed under the p-type threshold control layer 45 under the gate electrode 46. In addition, the source / drain electrodes 47a, 47a are directly formed on the n-type carrier supply layer 43.
No source / drain regions are formed because the ohmic contact is made by forming 47b. In addition,
In FIG. 7, reference numeral 41 denotes a semi-insulating substrate made of GaAs, and reference numeral 42 denotes a channel layer on the semi-insulating substrate 41.

Also in this case, the source / drain electrodes 47
Even when a and 47b are separated from the end of the gate electrode 46, carriers are accumulated in the channel layer 42 between them as in the first and second embodiments, so that the gate leakage current is reduced. Alternatively, the parasitic resistance of the FET can be reduced while improving the gate breakdown voltage. In addition,
In the second and third embodiments, the present invention is applied to an n-channel FET, but may be applied to a p-channel FET. Carrier supply layers 33 and 43, threshold control layers 35 and 45
By inverting the conductivity types of the source / drain regions 36a and 36b, the parasitic resistance can be reduced, the gate leak current can be reduced, or the gate breakdown voltage can be improved.

[0031]

As described above, the semiconductor device according to the present invention includes the carrier supply layer of one conductivity type and the threshold control layer of the opposite conductivity type partially formed under the gate electrode. I have. Accordingly, carriers are depleted in the channel layer below the gate electrode, and carriers are accumulated in the channel layer around the gate electrode.

Thus, even when the source / drain region or the source / drain electrode is separated from the end of the partially formed gate electrode, threshold control layer or gate barrier layer, the channel layer in the region between them is formed. Will accumulate carriers. Therefore, the parasitic resistance can be reduced, the gate leak current can be reduced, or the gate withstand voltage can be improved. On the other hand, carriers are depleted in the channel layer below the gate electrode, so that a normally-off FE
T can be realized.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views (part 1) illustrating a method for manufacturing an n-type FET according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views (part 2) illustrating a method for manufacturing an n-type FET according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram of an energy band showing an electron affinity of each semiconductor layer included in the n-type FET according to the first embodiment of the present invention.

FIG. 4A is an energy band diagram of a semiconductor layer below a gate electrode in the n-type FET according to the first embodiment of the present invention, and FIG. FIG. 5 is an energy band diagram of a semiconductor layer in a region between a drain / drain region.

FIG. 5A is an energy band diagram of a semiconductor layer below a gate electrode in the p-type FET according to the first embodiment of the present invention, and FIG. FIG. 5 is an energy band diagram of a semiconductor layer in a region between a drain / drain region.

FIG. 6 is a sectional view showing an n-type FET according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing an n-type FET according to a third embodiment of the present invention.

FIG. 8A is a cross-sectional view showing an n-type FET according to a conventional example, and FIGS. 8B and 8C are diagrams below a gate electrode and between a gate electrode and a source / drain region. FIG. 3 is an energy band diagram of a semiconductor layer in a region.

FIG. 9A is a cross-sectional view showing an n-type FET according to another conventional example, and FIGS. 9B and 9C show a portion under a gate electrode and between a gate electrode and a source / drain region. It is an energy band figure of the semiconductor layer of the area | region between.

[Explanation of symbols]

21, 31, 41, semi-insulating substrate, 22, 33, 43 carrier supply layer, 23, 32, 42 channel layer, 24, 34, 44 gate barrier layer, 25, 25a, 35, 45 threshold control layer, 26, 37 , 46 gate electrode, 27 mask, 28a, 28b, 36a, 36b source / drain region, 29a, 29b, 38a, 38b, 47a, 47b source / drain electrode.

Claims (4)

[Claims] 1. A carrier supply layer of one conductivity type on a semi-insulating substrate, a channel layer formed on the carrier supply layer and having a higher electron affinity than the carrier supply layer, and formed on the channel layer. A gate barrier layer having an electron affinity smaller than that of the channel layer; a threshold control layer of an opposite conductivity type partially formed on the gate barrier layer; a gate electrode on the threshold control layer; Source / drain regions formed on both sides of the source / drain region at intervals from an end of the threshold control layer and reaching the channel layer from the surface of the gate barrier layer; And a source / drain electrode. 2. A channel layer on a semi-insulating substrate; a carrier supply layer of one conductivity type formed on the channel layer and having a smaller electron affinity than the channel layer; and formed on the carrier supply layer. A gate barrier layer having a smaller electron affinity than the carrier supply layer; an opposite conductivity type threshold control layer partially formed on the gate barrier layer; a gate electrode on the threshold control layer; Source / drain regions formed on both sides of the source / drain region at intervals from an end of the threshold control layer and reaching the channel layer from the surface of the gate barrier layer; And a source / drain electrode. 3. A channel layer on a semi-insulating substrate, a carrier supply layer of one conductivity type formed on the channel layer and having a smaller electron affinity than the channel layer, and partially on the carrier supply layer. A formed gate barrier layer having a smaller electron affinity than the carrier supply layer, an opposite conductivity type threshold control layer formed on the gate barrier layer, a gate electrode formed on the threshold control layer, A semiconductor device, comprising: source / drain electrodes formed on the carrier supply layer on both sides of a gate electrode and spaced from an end of the threshold control layer. 4. The semiconductor according to claim 1, wherein a threshold voltage is controlled by at least one of an impurity concentration of the carrier supply layer and an impurity concentration of the threshold control layer. apparatus.