JPH1050065A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate a large capacity BiCMOS(bipolar complementary metal oxide semiconductor) static RAM(random access memory), etc., without impeding its low power consumption formation. SOLUTION: A unit word line driving circuit UWD000 provided corresponding to each word line WL000, etc., of a memory array is constituted based on e.g. a three inputs NAND gate NAG1 receiving predecoding signals PX00, PX30 and PX60, etc., at prescribed combination and e.g. an inverter INV1 receiving the output signal of the NAND gate NAG1 and that the output signal becomes a substantial word line selection signal, that is, the word line WL000, and the operation power source of the NAND gate NAG1 is made a source voltage VEE of the same potential as the source voltage VEM to be the operation power source of a static memory cell MC constituting a memory array MARY, and the operation power source of the inverter INV1 is made the source voltage VES that its absolute value is larger than the source voltages VEM and VEE. Thus, a unit word line driving circuit of a two steps structure with its relatively less operation current and capable of operating at high speed is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a large capacity BiCMOS static RA.
The present invention relates to an M (random access memory) and a technique particularly effective when used for speeding up and reducing power consumption.

[0002]

2. Description of the Related Art Bipolar transistors and P-channel and N-channel MOSFETs (metal oxide semiconductor field effect transistors; in this specification, MOSFETs)
And a CMOS (complementary MOS) circuit composed of an insulated gate type field effect transistor).
S) There is a circuit. Further, a memory array in which static memory cells are arranged in a lattice pattern,
There is a so-called BiCMOS static RAM including a peripheral circuit such as a word line drive circuit composed of an iCMOS circuit.

[0003]

Prior to the present invention, the present inventors have attempted to increase the capacity of a BiCMOS static RAM and have noticed the following problem. That is, this BiCMOS static RAM includes a word line driving circuit including a plurality of unit word line driving circuits provided corresponding to each word line of the memory array, and each of the unit word line driving circuits is connected to a previous stage X address. Predecode signal output from decoder XD is received in a predetermined combination, and its output terminal is coupled to a corresponding word line of the memory array, for example, a three-input BiCMOS NOR (N
OR) gate. The predecode signal supplied to each unit word line drive circuit of the word line drive circuit is a so-called ECL (emitter coupled logic) level signal having a relatively small amplitude, and each unit word line drive circuit has a corresponding signal. When both the 3-bit predecode signals are set to the low level, it functions as a decoder for selectively setting the corresponding word line to a selected state, and also converts the word line selection level from the ECL level to the MOS level. Also functions as a level conversion circuit.

However, BiCMOS static RA
As the capacity of M increases, the number of memory cells coupled to the word line increases, the wiring length of the word line itself also increases, and the load capacity for each unit word line drive circuit increases. As a result, in the unit word line driving circuit as described above in which the decoder and the level conversion circuit are integrated, the driving capability is insufficient, and the operation of selecting the word line is delayed by that amount, and the speeding up of the BiCMOS static RAM is restricted. Receive. In order to cope with this, if the drive capability of the unit word line drive circuit is unnecessarily increased, the operation current increases, and the BiCMOS static RAM increases.
Lower power consumption is hindered.

An object of the present invention is to increase the speed of a large-capacity BiCMOS static RAM or the like without hindering the reduction in power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a large-capacity BiCMOS static RAM or the like, a unit word line drive circuit provided corresponding to each word line of a memory array is connected to a first BiCMOS logic gate receiving a predecode signal of a predetermined bit in a predetermined combination. , The first BiCM
A second BiCMOS logic gate which receives an output signal of the OS logic gate and the output signal of which is a substantial word line selection signal is basically configured, and an operation power supply of the first BiCMOS logic gate is configured as a memory array. A second power supply voltage having the same potential as the first power supply voltage as the operation power supply of the static memory cell to be operated, and the absolute value of the operation power supply of the second BiCMOS logic gate is larger than the first and second power supply voltages The third power supply voltage is used.

According to the above means, a unit word line drive circuit having a two-stage structure capable of operating at a high speed with a relatively small operating current can be realized. , Etc., can be speeded up.

[0009]

FIG. 1 is a block diagram showing one embodiment of a BiCMOS static RAM to which the present invention is applied. Referring to FIG.
An outline of the configuration and operation of the iCMOS static RAM will be described. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

Referring to FIG. 1, the BiCMOS of this embodiment
Although not particularly limited, the static RAM includes four memory mats MAT0 to MAT3. Each of these memory mats includes a memory array MARY, a word line drive circuit WD, an X address decoder XD, a Y switch YS, and a write amplifier. WA, sense amplifier SA and Y
And an address decoder YD. The X address decoder XD is supplied with, for example, 9-bit internal X address signals X0 to X8 from the X address buffer XB, and the Y address decoder YD is supplied with the 9-bit internal Y address signal Y0 from the Y address buffer YB. To Y8 are supplied. Further, for example, 8-bit write data is supplied from the data input buffer IB to the write amplifier WA via the input data buses IDB0 to IDB7, and the output signal of the sense amplifier SA is output from the output data bus ODB0.
ＯＤODB7 to the data output buffer OB. The internal control signal RC is supplied from the timing generation circuit TG to the sense amplifier SA, and the data output buffer O
B is supplied with an internal control signal OC.

Although the memory array MARY is not particularly limited, the memory array MARY may be substantially parallel to the horizontal direction in FIG.
It includes 12 word lines and 8 × 512 or 4,096 sets of complementary bit lines, for example, arranged in parallel in the vertical direction in the figure. The intersection of these word lines and complementary bit lines is substantially 512 × 4,096 or 2,0
97,152 static memory cells are arranged in a lattice. Thereby, memory mats MAT0-MAT
Each of the T3s has a storage capacity of 2 megabits, and the BiCMOS static RAM has
It has a relatively large storage capacity of so-called 8 megabits in total.

The 512 word lines constituting the memory array MARY are coupled to a word line drive circuit WD and are selectively selected. As will be described later, the word line drive circuit WD includes 512 unit word line drive circuits provided corresponding to each word line of the memory array MARY, and these unit word line drive circuits include an X address decoder XD. , A 3-bit predecode signal is selectively supplied in a predetermined combination. Each unit word line drive circuit of the word line drive circuit WD selectively sets the corresponding word line of the memory array MARY to a predetermined selection level when the corresponding 3-bit predecode signals are both at the high level. Note that the word line drive circuit W
The specific configuration of D will be described later in detail.

The X address decoder XD has three X predecoders, as will be described later, and these X predecoders receive internal X address signals X0 to X8 in order.
X2, X3 to X5, and X6 to X8 are supplied in units of 3 bits. Each X predecoder of the X address decoder XD has a 3-bit internal X address signal X0.
To X2, X3 to X5 or X6 to X8, respectively, and the corresponding 8-bit predecode signal is alternatively set to a predetermined high level.

The X address buffer XB is connected to an external terminal AX
X address signals AX0 through AX0
AX9 is taken in and held, and internal X address signals X0 to X9 are formed based on these X address signals. Of these, the internal X address signal X of the most significant bit
9 is supplied to the mat selection circuit MS and the other internal X
The address signals X0 to X8 are supplied to the X address decoders XD of the memory mats MAT0 to MAT3 as described above.

On the other hand, memory array MA of each memory mat
The 4,096 sets of complementary bit lines constituting RY are connected to a Y switch YS, and are selectively connected to the write amplifier WA or the sense amplifier SA by eight sets via the Y switch YS.

Here, Y switch YS includes 4,096 pairs of switch MOSFETs provided corresponding to each complementary bit line of corresponding memory array MARY. The gates of these switch MOSFETs are sequentially and commonly connected in groups of eight, and a corresponding bit line selection signal is commonly supplied from a Y address decoder YD. Y switch Y
Each of the S switch MOSFETs is selectively turned on eight sets at a time when the corresponding bit line selection signal is set to a predetermined high level, and the corresponding eight sets of complementary bit lines of the corresponding memory array MARY are written to the corresponding switch MOSFETs. The amplifier WA or the sense amplifier SA is selectively connected.

The Y address decoder YD includes internal Y address signals AY0 to AY0 supplied from a Y address buffer YB.
AY8 is decoded, and the corresponding bit line selection signal is alternatively set to a predetermined high level. The Y address buffer YB captures and holds the Y address signals AY0 to AY9 supplied via the external terminals AY0 to AY9, and forms the internal Y address signals Y0 to Y9 based on these Y address signals. I do. Among them, the internal Y address signal Y9 of the most significant bit is supplied to the mat selection circuit MS, and the other internal Y address signals Y0 to Y8 are
It is supplied to the Y address decoder YD of the memory mats MAT0 to MAT3.

The mat select circuit MS decodes the most significant bits of the internal X address signal X9 and the internal Y address signal Y9 supplied from the X address buffer XB and the Y address buffer YB, and outputs the corresponding mat select signal MS.
L0 to MSL3 are alternatively set to a predetermined high level. The mat selection signals MSL0 to MSL3 are
The memory mats MAT0 to MAT3 are supplied to T0 to MAT3, respectively, to selectively activate these memory mats MAT0 to MAT3.

The data input buffer IB is a BiCMOS
When the static RAM is selected in the write mode, 8-bit write data supplied through the data input / output terminals IO0 to IO7 is taken in and held, and the write amplifier WA is input via the input data buses IDB0 to IDB7. To communicate. At this time, the write amplifier WA is selectively activated in response to the high level of the internal control signal WC, and changes the write data supplied from the data input buffer IB via the input data buses IDB0 to IDB7 to a predetermined complementary write signal. After that, the data is written to the selected eight memory cells of the memory array MARY via the Y switch YS.

On the other hand, the sense amplifier SA is a BiCMOS
When the static RAM is set to the selected state in the read mode, the static RAM is selectively operated in response to the high level of the internal control signal RC. In this operation state, the sense amplifier SA amplifies the read signals output from the selected eight memory cells of the memory array MARY via the Y switch YS, and then reads the read data buses ODB0 to ODB0.
The data is transmitted to the data output buffer OB via the ODB 7.
At this time, the data output buffer OB outputs the internal control signal O
In response to the high level of C, the operating state is selectively activated, and the read data buses ODB0 to ODB from the sense amplifier SA are read.
7 is output to an external device via data input / output terminals IO0 to IO7.

The timing generation circuit TG is provided with a chip enable signal C supplied as a start control signal from an external device.
EB (here, a so-called inverted signal or the like which is selectively set to a low level when it becomes valid is indicated by adding a B to the end of its name. The same applies hereinafter) and a write enable signal WEB. The above-mentioned various internal control signals are selectively formed and supplied to each section of the BiCMOS static RAM.

FIG. 2 shows a substrate layout diagram of one embodiment of the BiCMOS static RAM of FIG. Based on the figure, the BiCMOS static RA of this embodiment
An outline of the M substrate arrangement will be described. In the following description of the substrate arrangement, the top, bottom, left, and right of the semiconductor substrate SUB are represented by the positional relationship of FIG.

Referring to FIG. 2, the BiCMOS of this embodiment
As described above, the static RAM includes the four memory mats MAT0 to MAT3, and these memory mats occupy a large area of the semiconductor substrate SUB and are arranged in a so-called cross-shaped. That is, for example, the semiconductor substrate S
At the upper left of UB, a memory array MARY of memory mat MAT0 is arranged in a horizontal direction so as to extend its word line WL in the horizontal direction, and a corresponding X in the inside thereof, that is, on the vertical center line side of semiconductor substrate SUB. An address decoder XD is provided. At the vertical center of the semiconductor substrate SUB, a peripheral circuit PC including an X address buffer XB is arranged along the vertical center line, and at the upper right of the semiconductor substrate SUB,
Memory array MARY forming memory mat MAT1
And the X address decoder XD are arranged symmetrically around the peripheral circuit PC.

On the other hand, a Y switch YS, a write amplifier WA, a sense amplifier SA, and a Y address decoder YD are arranged on the center line side of the semiconductor substrate SUB of the memory mat MAT0. Further, a peripheral circuit PCL including a Y address buffer YB is arranged at a horizontal center of the semiconductor substrate SUB along a horizontal center line of the semiconductor substrate SUB.
At the lower left and lower right of B, a memory array MARY and an X address decoder XD, etc., constituting the memory mats MAT2 and MAT3 are symmetrically arranged with the peripheral circuit PCL or PCR interposed therebetween.

In this embodiment, the word line driving circuit W
D includes 512 unit word line drive circuits UWD provided corresponding to each word line WL, and these unit word line drive circuits are arranged at the center of the corresponding memory array MARY in the word line extension direction. You. As a result, each memory array MARY is divided into two parts with the word line drive circuit WD interposed therebetween, and a relatively large load capacitance is coupled by arranging the word line drive circuit WD at the center thereof. The transmission delay time of the word line can be reduced, the word line selection operation can be speeded up on average, and the access time of the BiCMOS static RAM can be shortened.

FIG. 3 is a block diagram showing one embodiment of the X address decoder XD and the word line drive circuit WD included in the BiCMOS static RAM of FIG. The outline of the configuration and operation of the X address decoder XD and the word line drive circuit WD included in the BiCMOS static RAM of this embodiment will be described with reference to FIG. FIG. 3 shows the memory mats MAT0 to MAT3.
The memory mats MAT0 to MAT3 include the same X address decoder XD and word line drive circuit WD, respectively. Needless to say.

In FIG. 3, X address decoder XD
Comprises three X predecoders PXD0 to PXD2,
These X predecoders include an X address buffer XB
, A 3-bit internal X address signal X0 to X2, X
3 to X5 and X6 to X8 are supplied, respectively. The X predecoder PXD0 has a 3-bit internal X
The address signals X0 to X2 are decoded, and their output signals, that is, the bits corresponding to the predecode signals PX00 to PX07 are alternatively set to a high level. Similarly, the X predecoder PXD1 has a 3-bit internal X address signal X3
To X5, and their output signals, that is, the corresponding bits of the predecode signals PX30 to PX37 are alternatively set to the high level. The X predecoder PXD2 decodes the 3-bit internal X address signals X6 to X8. The output signal, that is, the corresponding bit of the predecode signals PX60 to PX67 is alternatively set to the high level.

In this embodiment, the internal X address signals X0 to X9 are not particularly limited, but are ECL level signals having signal amplitudes of, for example, about 0.8 V (volts), and X predecoders PXD0 to PXD0. PXD2 output signal, ie, predecode signals PX00 to PX07, P
X30 to PX37 and PX60 to PX67 are also signals of the same ECL level.

Next, the word line drive circuit WD operates substantially 512 word lines WL0 of the corresponding memory array MARY.
And 512 unit word line driving circuits UWD000 to UWD511 provided corresponding to 00 to WL511, respectively.
Each of these unit word line driving circuits includes a first BiCMOS logic gate, that is, a three-input BiCMOS NAND (NAND) gate and a second BiCMOS
CMOS logic gates or BiCMOS inverters.

BiCMO constituting unit word line drive circuits UWD000 to UWD511 of word line drive circuit WD
The first to third input terminals of the S NAND gate receive predecode signals PX00 to PX00 from the X address decoder XD.
X07, PX30 to PX37 and PX60 to PX6
7 are supplied in a predetermined combination one bit at a time. That is, the first to third input terminals of the BiCMOS NAND gates constituting the unit word line drive circuit UWD000 are both connected to the predecode signal P of the least significant bit.
X00, PX30 and PX60 are supplied, respectively, to form the unit word line drive circuit UWD001.
The first to third input terminals of the CMOS NAND gate are connected to the predecode signal PX01 of the second lowest bit and the predecode signals PX30 and PX60 of the least significant bit.
Are supplied respectively.

Similarly, unit word line drive circuit UWD00
2 are connected to the first to third input terminals of the BiCMOS NAND gates, respectively, from the lower third bit predecode signal PX02 and the least significant bit predecode signal PX3.
0 and PX60 are supplied, respectively, and the first to third input terminals of the BiCMOS NAND gate constituting the last unit word line drive circuit UWD511 are supplied with the most significant bit predecode signals PX07, PX37 and PX67, respectively. You.

From these, the unit word line drive circuits UWD000 to UWD which become the substantial word line selection signal
The output signal of 511, that is, the word lines WL000 to WL511 of the memory array MARY are normally connected to each other as described later.
Third power supply voltage VES, that is, CMOS close to -3.3 V
When the corresponding predecode signals PX00, PX30 and PX60 to PX07, PX37 and PX67 are simultaneously set to the non-selection level, and the corresponding predecode signals PX07, PX37, PX67 are set to the high level at the same time, the ground potential of the circuit, that is, CMOS such as 0V, is selected. The level is selected.

As described above, the predecode signal PX00
PX07, PX30 to PX37 and PX60 to P
X67 is an ECL level signal. Therefore,
Unit word line drive circuit UWD0 of word line drive circuit WD
00 to UWD 511 have a function as a decoder for selectively setting the corresponding word lines WL000 to WL511 of the memory array MARY to the selected level by setting the corresponding predecode signals of 3 bits to the high level, and the ECL. It has a function as a level conversion circuit that receives a level predecode signal and selectively sets a corresponding word line to a CMOS level selection level.

FIG. 4 is a circuit diagram showing one embodiment of the unit word line drive circuit UWD000 included in the word line drive circuit WD of FIG. Based on the drawing, the word line drive circuit W of the BiCMOS static RAM of this embodiment
Unit word line drive circuits UWD000 to UW constituting D
The specific configuration and operation of D511 will be described. In the following description, the unit word line drive circuit UWD00
0, the unit word line drive circuit UWD0
00 to UWD 511 will be described. Further, in the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of a P-channel type, and are distinguished from N-channel MOSFETs without an arrow. Further, the bipolar transistors illustrated in the following circuit diagrams are all NPN transistors (hereinafter, bipolar transistors are simply referred to as transistors), although not particularly limited.

In FIG. 4, unit word line drive circuit UW
D000 includes a first BiCMOS logic gate, that is, a three-input BiCMOS NAND gate NAG1 (hereinafter, abbreviated as a NAND gate NAG1), and a second BiCMOS logic gate, that is, a BiCMOS inverter INV1 (hereinafter, abbreviated as an inverter INV1). Of these, NAND gate NAG1 includes a transistor T1 whose collector is coupled to the ground potential of the circuit, and inverter INV1 similarly includes a first transistor T3 whose collector is coupled to the ground potential of the circuit.

The base of the transistor T1 forming the NAND gate NAG1 is coupled to the ground potential of the circuit via three P-channel MOSFETs P1 to P3 in a parallel form, and three N-channels in a series form. Second power supply voltage V through MOSFETs N1 to N3
Combined with EE. The emitter of the transistor T1 is composed of three N-channel MOSFETs in series.
Coupled to power supply voltage VEE via N4 to N6 and to the output terminal of NAND gate NAG1. M
The predecode signal PX60 is commonly supplied to the gates of the OSFETs P1, N1 and N4. Also, MO
The predecode signal PX30 is supplied to the gates of the SFETs P2, N2 and N5.
3 and N6 have a predecode signal PX0
0 is supplied.

Next, the base of the transistor T3 constituting the inverter INV1 is connected to the output terminal of a CMOS logic gate provided in the preceding stage, that is, a CMOS inverter composed of a P-channel MOSFET P4 and an N-channel MOSFET N7. The emitter is connected to a third power supply voltage VE via an N-channel MOSFET N8.
S and the output terminal of the inverter INV1. MOS constituting inverter INV1
The output signals of the preceding NAND gate NAG1 are commonly supplied to the gates of the FETs P4, N7 and N8.

As shown in FIG. 4, a static memory cell MC constituting the memory array MARY includes a P-channel MOSFET PA and an N-channel MOSFET PA.
OSFETNA and P-channel MOSFET PB
And a pair of CMs comprising an N-channel MOSFET NB
A pair of N-channel type latch circuits respectively provided between a latch circuit cross-coupled with an OS inverter and a non-inverting and inverting input / output node of the latch circuit and a corresponding non-inverting bit line BL0T or inverted bit line BL0B. M
OSFET NC and ND, respectively. The gates of the selection MOSFETs NC and ND of each memory cell MC are commonly coupled to the corresponding word lines WL000 to WL511, respectively. Further, the CMOS inverter configuring each latch circuit of the memory cell MC uses the first power supply voltage VEM as an operation power supply.

In this embodiment, the memory array MAR
A power supply voltage VEM serving as an operation power supply of the memory cell MC configuring Y is set to a negative potential such as -2.5 V, for example, and the unit word line drive circuit UWD00 of the word line drive circuit WD.
The power supply voltage VEE serving as an operation power supply of the NAND gate NAG1 constituting 0 is also set to the same potential, that is, a negative potential of -2.5V. However, the inverter INV1 of the unit word line drive circuit UWD000 uses the power supply voltage VES as an operation power supply, and the power supply voltage VES has a negative potential of −3.3 V whose absolute value is larger than the power supply voltages VEM and VEE.

When any of the predecode signals PX00, PX30 or PX60 is at the low level of the ECL level, the NAND gate NAG1 outputs the corresponding MO signal.
One of the SFETs P1 to P3 is turned on, and any of the corresponding MOSFETs N1 to N3 and N4 to N6 is turned off. Therefore, the transistor T1 is turned on, and its emitter potential, that is, the NAND gate N
The output signal of AG1 is at a high level which is lower than the ground potential of the circuit by approximately the base-emitter voltage of transistor T1. At this time, the inverter INV1 receives the high level of the output signal of the NAND gate NAG1, and
ETP4 is turned off and MOSFETs N7 and N8
Is turned on. Therefore, transistor T3 is turned off, and its output signal, that is, memory array MAR
The word line WL000 corresponding to Y is set to a non-selection level such as the power supply voltage VES.

On the other hand, a 3-bit predecode signal PX0
When 0, PX30 and PX60 are all set to the ECL high level, the NAND gate NAG1
The MOSFETs P1 to P3 are turned off all at once, and the MOSFETs N1 to N3 and N4 to N6 are turned on all at once. Therefore, the transistor T1 is turned off, and its emitter potential, that is, the NAND gate NG
1 is at a low level close to the power supply voltage VEE. At this time, the inverter INV1 receives the low level of the output signal of the NAND gate NAG1, and
TN7 and N8 are turned off, and instead, MOSFE
TP4 is turned on, whereby the transistor T
3 is turned on, and its output signal, that is, the corresponding word line WL000 of the memory array MARY is set to the selected level lower than the ground potential of the circuit by the base-emitter voltage of the transistor T3.

As described above, the BiCMOS of this embodiment
The unit word line drive circuits UWD000 to UWD511 that constitute the word line drive circuit WD of the static RAM are:
Predecode signals PX00-PX07, PX30-PX
37, a 3-input BiCMOS NAND gate NAG1 receiving PX60 to PX67 one bit at a time in a predetermined combination, and a BiCMOS inverter INV1 receiving the output signal of the corresponding NAND gate NAG1.
The ECL level predecode signal PX0 has a stage structure.
0-PX07, PX30-PX37 and PX60-
PX67 is converted into a CMOS level in two stages via NAND gate NAG1 and inverter INV1, and unit word line driving circuits UWD000 to UWD000
The driving capability of the WD 511 is also increased in two stages.

In a BiCMOS static RAM developed by the present inventors prior to the present invention, a unit word line drive circuit UWD0 constituting a word line drive circuit WD is provided.
As illustrated in FIG. 5, each of 00 to UWD 511 includes a one-stage three-input BiCMOS NOR (NOR) gate NOG1. Therefore, the word line drive circuit WD
The operation of selecting a word line by the memory device is performed by increasing the capacity of a BiCMOS static RAM and selecting static memory cells coupled to the word line, that is, select MOSFETs NC and N.
As the number of D increases and the wiring length of the word line itself increases, the delay becomes slower. As in this embodiment, the inventors of the present application have shown that the unit word line drive circuits UWD000 to UWD511 have a two-stage structure so that the word line selection operation can be sped up while suppressing an increase in the operation current. Confirmed by simulation. As a result,
The speed of a BiCMOS static RAM or the like can be increased without hindering the reduction in power consumption.

Note that the inverter INV1 forming the unit word line drive circuits UWD000 to UWD511 of the word line drive circuit WD has the power supply voltage VES having a relatively large absolute value.
Is used as an operating power supply, the output signal thereof, that is, the amplitude of the word lines WL000 to WL511 is sufficiently enlarged. Also, a transistor T constituting the inverter INV1
N-channel MOSF of the CMOS inverter of the preceding stage of No. 3
By providing the transistor T2 in the form of a diode on the source side of ETN7, the logic threshold level of the CMOS inverter becomes higher than the power supply voltage VES by the base-emitter voltage of the transistor T2, and the operating power supply of the NAND gate NAG1 and the inverter INV1 The problem that the absolute values of the operating power supplies differ from each other is solved.

The functions and effects obtained from the above embodiment are as follows. That is, (1) In a large-capacity BiCMOS static RAM or the like, a unit word line drive circuit provided corresponding to each word line of a memory array is connected to a first BiCMOS logic gate receiving a predecode signal in a predetermined combination. A second BiCMOS logic gate which receives an output signal of the first BiCMOS logic gate and whose output signal is a substantial word line selection signal,
The operation power supply of the first BiCMOS logic gate is set to a second power supply voltage having the same potential as the first power supply voltage as the operation power supply of the static memory cell, and the operation power supply of the second BiCMOS logic gate has an absolute value. By setting the third power supply voltage higher than the first and second power supply voltages, it is possible to realize a unit word line drive circuit having a two-stage structure that can operate at a high speed with a relatively small operating current. Is obtained.

(2) In the above item (1), the second Bi
N constituting a CMOS logic gate of a CMOS logic gate
By providing a bipolar transistor in the form of a diode on the source side of a channel MOSFET, CM
By increasing the logic threshold level of the OS logic gate by the base-emitter voltage of the bipolar transistor, it is possible to eliminate the problem that the absolute values of the operation power supplies of the first and second BiCMOS logic gates are different. can get. (3) In the above items (1) and (2), the transmission delay time of the word line selection signal in a large-scale memory array is achieved by disposing the unit word line drive circuit at the center of the corresponding memory array. Can be reduced. (4) According to the above items (1) to (3), an effect is obtained that the speed of a semiconductor memory device such as a BiCMOS static RAM can be increased without hindering the reduction in power consumption.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG.
Can have any number of memory mats, each memory mat as well as a BiCMOS static RAM.
Can also be set arbitrarily. The memory array MARY can include any number of redundant elements.
Also, a BiCMOS static RAM is, for example, × 4
An arbitrary bit line configuration such as a bit or × 16 bits can be adopted, and various embodiments can be adopted for a block configuration, an address configuration, a name and a combination of activation control signals, and the like. In FIG. 2, BiCMOS static R
The AM can adopt a so-called vertical arrangement in which the word lines extend in the long side direction of the semiconductor substrate SUB, and the specific arrangement of each part, the shape of the semiconductor substrate, and the like are not limited by the present embodiment.

In FIG. 3, X address decoder XD
Can include multiple stages of predecoders and each X
The combination of the predecoder and the internal X address signal can be set arbitrarily. The memory array MARY can adopt a so-called divided word line system. In this case, the effective level of the word lines WL000 to WL511 may be a low level such as the power supply voltage VEE. In FIG. 4, unit word line drive circuits UWD000 to UWD511
Is not necessarily required to include the diode-type transistor T2. Further, unit word line drive circuits UWD000 to UWD511
Can take various embodiments as long as the same logical condition is obtained. The same applies to the polarity and absolute value of the power supply voltage and the conductivity types of the MOSFET and the bipolar transistor.

In the above description, the invention made mainly by the present inventor is described in the field of application Bi
The case where the present invention is applied to a CMOS static RAM has been described. However, the present invention is not limited to this.
The present invention can also be applied to various memory integrated circuits such as an iCMOS dynamic RAM and a logic integrated circuit device such as a single chip microcomputer incorporating such a memory integrated circuit. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor storage device including at least a word line drive circuit composed of a BiCMOS circuit, and a device or system including the same.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-capacity BiCMOS static RAM or the like, a unit word line drive circuit provided corresponding to each word line of a memory array is connected to a first BiCMOS logic gate receiving a predecode signal of a predetermined bit in a predetermined combination. , The first BiC
A second BiCMOS logic gate which receives an output signal of the MOS logic gate and whose output signal is a substantial word line selection signal; and a first BiCMOS logic gate.
The operation power supply of the logic gate is a second power supply voltage having the same potential as the first power supply voltage, which is the operation power supply of the static memory cells forming the memory array, and the operation power supply of the second BiCMOS logic gate has its absolute value. Is a third power supply voltage higher than the first and second power supply voltages. As a result, a unit word line drive circuit having a two-stage structure that can operate at a high speed with a relatively small operating current can be realized. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a BiCMOS static RAM to which the present invention is applied.

FIG. 2 is a substrate layout diagram showing one embodiment of the BiCMOS static RAM of FIG. 1;

FIG. 3 is a block diagram showing an embodiment of an X address decoder and a word line driving circuit included in the BiCMOS static RAM of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of a unit word line drive circuit included in the word line drive circuit of FIG. 3;

FIG. 5 is a diagram illustrating a B developed by the present inventors prior to the present invention.
FIG. 3 is a circuit diagram illustrating an example of a unit word line drive circuit of a word line drive circuit of an iCMOS static RAM.

[Explanation of symbols]

MAT0 to MAT3: memory mat, MARY: memory array, WD: word line drive circuit, XD: X address decoder, XB: X address buffer, YS ...
Y switch, YD ... Y address decoder, YB ... Y
Address buffer, MS ... Mat selection circuit, WA ...
Write amplifier, SA Sense amplifier, IB Data input buffer, OB Data output buffer, TG
Timing generation circuit, CEB: chip enable signal input terminal, WEB: write enable signal input terminal,
AX0 to AX9 ... X address signal input terminals, AY0 to AY0
AY9 ... Y address signal input terminal, IO0-IO7 ...
... data input / output terminals, X0 to X9 ... internal X address signals, Y0 to Y9 ... internal Y address signals. SUB: Semiconductor substrate, WL: Word line, BL: Bit line, UW
D: Unit word line drive circuit, PC, PCL, PCR ...
... peripheral circuits. PXD0 to PXD2 ... X predecoder,
PX00-PX07, PX30-PX37, PX60-
PX67, PX00B, PX30B, PX60B... Predecode signals, UWD000 to UWD511... Unit word line drive circuits, WL000 to WL511. NAG1 BiCMOS NAND gate, INV1 BiCMOS inverter, NOG1
... BiCMOS NOR (NOR) gate, BL0T... Non-inverted bit line, BL0B.
3, Ta ... NPN type bipolar transistor, P1
P4, PA to PB, Pa to Pc ... P-channel MOS
FET, N1 to N8, NA to ND, Na to Nf... N channel MOSFET, MC... Static memory cell.

Claims (4)

[Claims] A first BiCMOS logic gate receiving a predecode signal in a predetermined combination;
A semiconductor memory device, comprising: a word line drive circuit including a second BiCMOS logic gate receiving an output signal of an iCMOS logic gate and the output signal serving as a substantial word line selection signal. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a memory array in which static memory cells using a first power supply voltage as an operation power supply are arranged in a lattice. The second BiCMOS logic gate has a second power supply voltage having the same potential as the first power supply voltage as an operation power supply, and the second BiCMOS logic gate has an absolute value of the first power supply voltage.
And a third power supply voltage higher than the power supply voltage of the semiconductor memory device is used as an operation power supply. 3. The logic circuit according to claim 2, wherein said second BiCMOS logic gate is said first BiCMOS logic gate.
A CMOS logic gate receiving the output signal of the CMOS logic gate; a first bipolar transistor receiving the output signal of the CMOS logic gate; and a second diode-shaped transistor provided on the source side of the N-channel MOSFET of the CMOS logic gate. And a bipolar transistor. 4. The memory device according to claim 1, wherein the X address decoder for forming the predecode signal is arranged at one end of the corresponding memory array in a word line extending direction. A semiconductor memory device, wherein the word line drive circuit is arranged at the center of the corresponding memory array in the word line extension direction.