JPH1049556A - Timing analyzing method in circuit designing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to perform precise simulation in which actual situation of a circuit is reflected, by analyzing the timing of input and output by using the input slew rate of data and the input slew rate of a clock as variables, and finding a setup time and a hold time. SOLUTION: The input slew rates of the data and clock are prepared as variables of circuit simulation (P1). The variables, i.e., input slew rates are used by cells to be designed to find a setup time and a hold time (P2). The extracted times are written to a look-up table (P3). On the assumption that the circuit to be designed is built in, the input slew rates of data and clocks are found by the cells (P4). The input slew rates which are found uniquely by the object cells are collated against the extraction results in the look-up table (P5). According to the collation result, the setup time and hold time of an actual circuit are found (UP6).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing analysis method in circuit design, and more specifically, to a CAD method.
The present invention relates to a timing analysis method such as logic synthesis, logic simulation, and automatic layout used for LSI design using (Computer Aided Design).

In conventional LSIs, if the logic is correct, the LSI operates without malfunction even if the timing is not so designed at the circuit design stage. However, recent LSIs require large-scale circuits (millions of transistors or more) and high operating speeds, so that the timing can be accurately adjusted at the system layout design stage before the LSI is manufactured (mask fabrication). If the design is not taken into account, malfunctions will occur, so it is essential to analyze the timing at the design stage.

[0003]

2. Description of the Related Art LSI design includes a system design that determines circuit operation and logic, and a layout design that determines the shape of elements such as transistors. In this design process, many CAD systems have been introduced for the purpose of shortening the period (automation, high accuracy). Figure 1 shows an example of the design system.
It is shown in FIG.

[0004] Timing analysis in circuit design can be roughly divided into characteristic extraction processing (characterization),
It is divided into two steps of calculation processing (calculation). First, the characteristic extraction processing (characterization) will be described. This means that various properties of cells constituting a circuit are determined.

In general, logic of an LSI is constructed using about 100 types of cells (small circuits). If the characteristics related to the timing of such cells are surely grasped at the stage of the system layout design, the circuit operation of the LSI can be guaranteed with a considerable probability, and repetition of the prototype can be prevented. Extracting the characteristics of the cell is called characteristic extraction (characterization).

The characterization is performed by a circuit simulation using a netlist including design information such as connection information of elements (transistors and the like) in each cell used for circuit design, and channel width, channel length and capacitance of the transistor. Will be That is, the simulation is performed by performing a circuit simulation for inputting and outputting a signal voltage for each cell (for example, a flip-flop) in the netlist, and obtaining data relating to characteristics of a desired cell.

In a clock-controlled cell such as a flip-flop or a latch as shown in FIG. 6, a malfunction may occur depending on the input / output timing of a clock or data. It must be set for each cell. The timing analysis described below is for calculating these setup time and hold time.

The set-up time is a time indicating how long a circuit such as a flip-flop can take in data after inputting data while maintaining normal operation. The hold time is a time indicating how much the fetched data can be held, and is indispensable for maintaining normal operation with respect to timing.

In order to obtain the setup time and the hold time by the characteristic extraction processing, one value is obtained for one cell by using a simple method, and is used for the timing analysis. For example, as for the setup time, it is necessary to input the step function data (D) and the clock (CK) to the target cell and find the limit at which the malfunction occurs in the output (Q) by the binary search method. Input a typical input slew rate (step function or one ramp function) to the input terminal of the data (D) shown in FIG. 7 and set up the delay time until the data reaches D → N1 → N2 → N3 in FIG. It was calculated by a simple method of setting time (Ts). FIG. 7 is a diagram showing an example of a specific circuit configuration inside the flip-flop.

In general, the hold time is calculated by using a step function as shown in FIG.
Input to the terminal, the limit at which the output (Q) malfunctions is obtained by a binary search method, and the falling edge of (D) shown in FIG.
The time difference from the rise of K) was defined as the hold time (Th). After the set of the set-up time (Ts) and the hold time (Th) obtained in this way is written in the look-up table, thereafter, each step (logical synthesis, layout design, etc.) shown in FIG. In a logic simulation or the like), timing calculation processing based on the above-described characteristic extraction processing is performed.

The calculation processing (calculation) will be described below. The calculation processing differs from the characteristic extraction processing in which the delay time and the like are calculated independently for the cells constituting each circuit.When the circuit to be designed is actually assembled, the characteristics such as the delay time are determined for each cell. This is a process for determining whether the condition is satisfied. At the time of this calculation, it is assumed that a circuit to be designed has already been assembled, so that data input to each cell, signal voltages such as clocks, and the like are uniquely obtained.

The data (D) and clock (CK) uniquely obtained and input to the target cell are referred to the above-mentioned lookup table obtained by the above-described characteristic extraction processing. Therefore, data (D) and clock (CK) of the extraction result and input condition on the lookup table
If they match, the setup time (Ts) to find it,
Hold time (Th), and if they do not match, appropriate setup time (Ts) and hold time (T
h) is obtained by approximation. In this way, the setup time and the hold time (Ts, Th) for each cell when an actual circuit is assembled can be obtained in advance by simulation.

[0013]

In the above conventional timing analysis method, the setup time is obtained by a simple extraction process, and the hold time is obtained by a simple model such as a step function. Only setup time and hold time can be obtained. The signal voltages such as data (D) and clock (CK) input to these cells actually have a distorted signal waveform as shown in FIG. 10, and the input slew rate has a simple function such as a step function. Often different from functions.

Therefore, the setup time and the hold time obtained by the simple extraction processing without considering the actual input slew rate become data with low accuracy.
The graph of FIG. 9 is a graph showing the correlation between the measurement results of the input slew rate and the hold time in the actual circuit. As shown in this graph, when the input slew rate changes, the hold time also changes.

As described above, since the conventional method does not consider the actual situation in an actual circuit, the setup time and the hold time obtained by the conventional method have low accuracy as data, and a highly accurate simulation reflecting the actual situation. Can not. Therefore, the accuracy of the timing analysis is reduced, and in a severe case, even if it operates correctly in a simulation, a malfunction occurs when a device is actually manufactured and a circuit is operated. Was.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks. As shown in FIG. 1, in an automatic circuit design using a CAD system or the like, a clock to which data and a clock are input is provided. For each control-type cell, a simulation is performed to analyze the input / output timing using the data input slew rate and the clock input slew rate as variables, and how much from the time when data is input to the cell in the cell Setup time indicating whether the data can be captured, and the data captured in the cell, a hold time indicating how much the cell can hold, a characteristic extraction process for obtaining as an extraction result , A circuit to be designed, and data and clocks input to each cell for each cell constituting the circuit The input slew rate is compared with the extraction result, and when they match, the calculation result is used. When they do not match, the calculation result is obtained by interpolation, and the setup time of each cell when a circuit to be designed is assembled. The above problem is solved by a timing analysis method in circuit design, which comprises a calculation process for obtaining a hold time.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit design timing analysis method according to an embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, a timing analysis method for obtaining a setup time and a hold time for a clock-controlled circuit such as a flip-flop will be described.

The LSI design includes a system design that determines the circuit operation and logic and a layout design that determines the shape of the transistor. In this design process, many CAD systems have been introduced for the purpose of shortening the period (automation, high accuracy). FIG. 11 shows an example of the design system. Timing analysis in circuit design can be broadly divided into two steps: characteristic extraction processing (characterization) and calculation processing (calculation).

The characterization is based on elements (such as transistors) in each cell used for circuit design.
Connection information, transistor channel width, channel length,
This is performed by circuit simulation using a netlist including design information such as capacity. That is, for each cell (eg, inverter) in this netlist, a circuit simulation is performed in which a load capacitance is applied to the output terminal of the cell, and a signal voltage is input to and output from the cell, and the delay from input to output of the signal voltage is reduced This is performed by obtaining such data.

In a clock-controlled circuit such as a flip-flop or a latch as shown in FIG. 2, a malfunction may occur depending on the input / output timing of a clock or data. It must be set for each cell. Of these, the setup time is the time indicating how far a circuit such as a flip-flop can take in data while maintaining normal operation, and the hold time is
This is a time indicating how much data to be captured can be held, and is essential for maintaining normal timing operation.

In order to determine the setup time and the hold time by the characteristic extraction processing, first, in step P1 of FIG. 1, the input slew rates of data (D) and clock (CK) are prepared as variables for circuit simulation. This is a characteristic step of the present invention. That is, it is known that the setup time (Ts) and the hold time (Th) in a clock control type circuit such as a flip-flop or a latch have a correlation with the slew rate (Ds, CKs) of each of data and clock. As input variables in the simulation, a data input slew rate (Ds) and a clock input slew rate (CKs) as described below are prepared.

[0022]

(Equation 1)

[0023]

(Equation 2)

Specifically,

[0025]

(Equation 3)

[0026]

(Equation 4)

A plurality of values such as are prepared. Next, in step P2 of FIG. 1, the setup time (Ts) and the hold time are set using the above variables, that is, the input slew rates (Ds, CKs) of the data (D) and clock (CK) for each cell to be designed. Time (Th) is obtained.
The simulation at this time will be described below with reference to FIGS.

The cell is a flip-flop (11) as shown in FIG. Using the data / clock input slew rate (Ds, CKs) prepared in step P1, a signal voltage having a slew rate as shown in FIG. 3 is input to the data (D) and clock (CK) terminals. , Output (Q)
The limit at which 誤 malfunctions is found by the binary search method. In the binary search method, specifically, the limit at which the output operates normally is obtained while changing the interval between the data (D) and the clock (CK). The convergence condition is expressed as follows: the time difference between D and CK is represented by T, and the current processing is represented by subscript k.

[0029]

(Equation 5)

Or

[0031]

(Equation 6)

Is as follows. Any appropriate one may be selected depending on the circuit conditions of the design target. The setup time Ts and the hold time Th are as follows, assuming that the arrival times of data and clock are Td and Tck during the timing analysis.

[0033]

(Equation 7)

[0034]

(Equation 8)

If the above condition is not satisfied, it is assumed that an error has occurred and a malfunction has occurred. After obtaining the limit of the malfunction in this way, as shown in FIG. 3, at the limit of the malfunction of the output (Q), when the data (D) rises 50% of the whole at the rise
And the difference between the time when the clock (CK) rises to 50% of the total at the rising time is the setup time (T
s), and when the clock (CK) rises, 5
The hold time (Th) is defined as the difference between the time point when the data (D) falls to 0% and the time point when the data (D) falls to 50% of the entirety.
And

The data / clock input slew rate (D
Since there are a plurality of combinations of (s, CKs), the setup time (Ts) and the hold time (Th) are obtained for all of the combinations. As a result, the setup time (T
s) and the hold time (Th) are represented by a two-dimensional matrix as shown in FIG. As can be seen, the setup time (Ts) and the hold time (Th) are both functions of the data input slew rate (Ds) and the clock input slew rate (CKs).

Next, in step P3 of FIG. 1, the extracted setup time (Ts) and hold time (Th) are written in a look-up table. At this point,
The characteristic extraction processing for obtaining the setup time (Ts) and the hold time (Th) of the cell before the circuit to be designed is assembled ends. After that, each step (logic synthesis,
In a logic simulation or the like), timing calculation processing based on the above-described characteristic extraction processing is performed.

The calculation processing (calculation) will be described below. The calculation process differs from the characteristic extraction process in which the setup time and the hold time are calculated independently for the cells constituting each circuit.When the circuit to be designed is actually assembled, the setup time and the hold time are calculated for each cell. This is a process for obtaining what time will be.

Subsequent to step P3 in FIG. 1, under the assumption that the circuit to be designed is assembled in step P4 in FIG.
Data and clock input slew rates (D
s, CKs). This is uniquely determined from the conditions and circuit constants of the preceding circuit under the assumption that the circuit to be designed is assembled. Next, in step P5 of FIG. 1, the input slew rate (Ds, CKs) of the data / clock uniquely determined in step P4 for each target cell.
With the extraction result on the lookup table.

Thereafter, in step P6 of FIG. 1, the setup time in the actual circuit is
Find the hold time. At this time, the input slew rate (Ds, CKs) of the data / clock uniquely determined
Is completely the same as the calculation result if it matches the extraction result on the look-up table. If not, an interpolation process is performed to obtain an approximate value and the calculation result is obtained.

The calculation result, that is, the setup time (T
s) and the hold time (Th) can be obtained. As described above, according to the timing analysis method according to the present embodiment, the input slew rate (Ds) of the data and the input of the clock, which were not considered in the conventional method, are input variables for the simulation at the stage of the characteristic extraction processing. The slew rate (CKs) is used, and the setup time (Ts) and the hold time (Ts) suitable for the actual situation of the circuit are obtained by using input variables corresponding to the waveform of a dull signal voltage such as actual data / clock. Th) can be obtained,
In addition, a plurality of setup times (T
s) and a hold time (Th) can be prepared.

Therefore, by obtaining the setup time and the hold time in the characteristic extraction process in consideration of the actual input slew rate, the accuracy of the setup time and the hold time as data for simulation is improved.
It is possible to perform an accurate simulation reflecting the actual state of the circuit. Therefore, the accuracy of the timing analysis has been improved, and the problems that have occurred in the past, such as in the worst case, even if it operates correctly in the simulation, but if the device is actually manufactured and the circuit is operated, it will malfunction as much as possible Deterrence becomes possible.

Hereinafter, as an application example of the timing analysis method according to the present embodiment, an application example of critical path and clock skew to violation will be described. That is,
As shown in FIG. 5, two flip-flops (12, 13)
In the circuit in which the logic circuit (LC) is connected between the first and second clocks, the arrival times of the clocks of the preceding and subsequent stages are Tck1 and Tck2, the delay time from the clock of the preceding flip-flop to the output is Tck-q, and the logic circuit (LC) Assuming that the delay at T is Tlogic and the operating frequency is Tcp, the critical path constraint in this case is

[0044]

(Equation 9)

And the clock skew constraint is:

[0046]

(Equation 10)

Is as follows. In this timing analysis, by using the timing analysis method according to the present embodiment and analyzing the input slew rates of these data and clocks, an accurate simulation can be performed.
Of course, the analysis method according to the present embodiment is not limited to such a circuit, and the target cell is not limited to a flip-flop. For example, like a latch, data is synchronized with a clock. It goes without saying that the same effects as those of the present embodiment can be obtained regardless of what controls input / output.

[0048]

As described above, according to the present invention, the input / output timing is analyzed by using the data input slew rate and the clock input slew rate as variables in the characteristic extraction processing for determining the setup time and the hold time. The setup time and the hold time are obtained by simulation, so using the input variables according to the waveform of the dull signal voltage such as actual data / clock, the setup suitable for the actual situation of the circuit Time and hold time can be obtained, and a plurality of setup time and hold time can be prepared for one cell.

Accordingly, the accuracy of the setup time and the hold time as data for simulation is improved, and accurate simulation reflecting the actual situation of the circuit can be performed, and the accuracy of timing analysis can be improved. Become.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a timing analysis method in circuit design according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a cell model used for circuit simulation according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between data and clock input timings, a setup time, and a hold time in the timing analysis method according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a two-dimensional matrix representation of a setup time and a hold time extracted in an embodiment of the present invention.

FIG. 5 is a diagram showing an application example according to the embodiment of the present invention.

FIG. 6 is a diagram showing a flip-flop serving as a model of a cell in circuit simulation according to a conventional example.

FIG. 7 illustrates an example of an internal circuit of a flip-flop.

FIG. 8 is a diagram illustrating a model of a signal voltage used for calculating a setup time and a hold time according to a conventional example.

FIG. 9 is a graph illustrating a relationship between a data input slew rate and a hold time in an actual circuit.

FIG. 10 is a diagram illustrating a conventional problem.

FIG. 11 is a diagram showing a general circuit design CAD system.

Claims (2)

[Claims] In an automatic circuit design using a CAD system or the like, for each clock control type cell to which data and a clock are inputted, the input slew rate of the data and the input slew rate of the clock are input / output as variables.
Perform a simulation to analyze the output timing,
In the cell, a setup time indicating how much the data can be taken from the time when the data is input to the cell, and how much the data can hold the data taken in the cell And a characteristic extraction process for determining a hold time as an extraction result, and combining a circuit to be designed and, for each cell constituting the circuit, an input slew rate of data and clock input to each cell and the extraction result. Collation, when these match, the calculation result is obtained, and when they do not match, the calculation result is obtained by interpolation, and a setup process and a hold time of each cell when a circuit to be designed is assembled are calculated. A timing analysis method in a circuit design, comprising: 2. The method according to claim 1, wherein the clock control type cell is a flip-flop or a latch.