JPH104526A - Image processor and processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the read of a slave video signal in a field memory from getting ahead of the read and write even when an image size of a slave screen and a display position are set optionally in a picture and picture(P & P) display. SOLUTION: A slave video signal is written alternately in memories 3, 4 for each field. A field switching signal wfcng in the case of write is latched by a signal rstat based on a timing when the signal is read from the memory 3 or 4. Based on a latch output from which of the memories 3, 4 a signal is read is selected. In this case, the memory in which no write is conducted is selected, Since the write/read side accesses a different memory at all times, even when the image size and display position at the read side are changed, the read processing of the slave video signal in the memory 3 or 4 does not get ahead of the write.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a special effect device, a television set, or a video tape recorder in a broadcasting station or the like, for displaying a child screen with respect to a parent screen at an arbitrary image size and position on the same screen. The present invention relates to an image processing apparatus and a processing method in which synchronization overtaking does not occur.

[0002]

2. Description of the Related Art Conventionally, a so-called picture-and-picture, in which a child screen which is different from the main screen in synchronization with a main screen, which is an original screen in a television set, is simultaneously displayed.
There has been a television set that performs a picture (hereinafter, referred to as a picture and picture).

For example, in a television set in which channel A is received and a screen is displayed, channel B is received and displayed simultaneously with the screen of channel A in parallel with the television set. FIG. 5 shows an example of the display of the picture and picture. As described above, the screen 100 of the television set is divided, and the parent screen 101 of the channel A and the child screen 102 of the channel B are displayed. In this case, the image is compressed and displayed in the horizontal direction according to the division ratio of the screen. For example, screen 1
When 00 is equally divided, thinning is performed on each of the parent screen 101 and the child screen 102 for each pixel in the horizontal direction. Note that the vertical size is a normal size. Conventionally, the division ratio of the parent screen 101 and the child screen 102 on the screen 100 is fixed, for example, 1: 1.

In a television set that performs such picture-and-picture, a small screen 102
Is written in the field memory. Then, the image data is read from the field memory, and displayed on the screen 100 based on the synchronization of the image data of the main screen 101. At this time, if the synchronization of the image data of the child screen 102 coincides with the synchronization of the parent screen 101, no problem occurs in displaying the parent screen 101 and the child screen 102.

However, as in this example, the parent screen 101
The sub-screen 102 and the sub-screen 102 may be different channels from each other. In this case, there is a possibility that a slight shift occurs in synchronization between the two. Depending on the conditions, in the display of the sub-screen 102, a situation may occur in which reading outstrips writing of image data in the field memory due to the synchronization deviation.

When this overtaking occurs, past images are mixedly displayed on the child screen 102. This is a significant image hindrance, especially when displaying moving images. Further, usually, the parent screen 101 and the child screen 1
Since the deviation from the synchronization with 02 is slight, the image failure due to this overtaking will not be solved for the time being once it occurs.

Therefore, in a television set capable of picture-and-picture, measures have been taken to detect overtaking and eliminate overtaking. FIG.
1 shows an example of the configuration of an image processing apparatus including this overtaking detection circuit according to the related art. A terminal 110 is supplied with a child video signal forming the child screen 102. The child video signal is supplied to the synchronization generation circuit 111 and also to the field memory 112 and the field memory 113.

In the synchronization generation circuit 111, synchronization signals such as a horizontal synchronization signal and a vertical synchronization signal are extracted from the supplied child video signal. Then, based on this synchronization signal, a write-side memory control signal wctl, a write-side field switching signal wfcng, and a write-side passing detection pulse wdet are generated. Signal wctl
Is a line address count generated in response to the scanning of the child video signal. One of the memories 112 and 113 is address-controlled based on this signal wctl, and the writing of the child video signal to one of the memories 112 and 113 is performed. Will be This signal wctl is a signal wf described later.
The data is supplied to the memory 112 or 113 based on the selection of the switch circuit 114 switched by cng.

The signal wfcng is a signal generated corresponding to the field of the child video signal. For example, during the period of the odd and even fields of the child video signal, as shown in FIG. The switching of the switch circuit 114 is controlled. That is, this signal wf
By the control of cng, the switch circuit 114 is switched for each field, and the supply of the signal wctl to the memories 112 and 113 is controlled.

[0010] As shown in FIG. 7B, the pulse wdet is a pulse which is kept at "H" for several H, for example, 3H from the start position of one frame in the child video signal. This pulse wdet is supplied to an overlap detection circuit 115 described later.

The child video signal supplied from the terminal 110 is
The memory 112 selected to supply the signal wctl by switching the switch circuit 114 based on the signal wfcng.
Or, 113 is written for each field based on the signal wctl. These memories 112 or 113
The video signal written to the switch circuit 11 is described later.
6, the memory 112 or 113 is selected and supplied, and is read based on a read-side memory control signal rctl. The read child video signal is supplied to one selection input terminal of the switch circuit 117.

A terminal 120 supplies a parent video signal for forming the parent screen 101. This parent video signal is supplied to the synchronization generation circuit 121 and also to the line memory 122. The parent video signal supplied to the line memory 122 is compressed in the horizontal direction based on a synchronization signal generated in a synchronization generation circuit 122 described later. For example, the image data is compressed to 水平 in the horizontal direction by thinning out each pixel by address control. The horizontally compressed parent video signal is supplied to the other selection input terminal of the switch circuit 117. The switch circuit 117 is switched at a timing corresponding to the ratio of the parent screen 101 and the child screen 102 in the screen 100, and the child image signal and the parent image signal are switched to the picture-and-picture video signal displayed on the same screen. And output to the output terminal 124.

In the synchronization generation circuit 121, synchronization signals such as a horizontal synchronization signal and a vertical synchronization signal are extracted from the supplied parent video signal. Then, based on this synchronization signal,
The read side memory control signal rctl, the read side field switching signal rfcng, the read side overtaking detection pulse rdet, the signal oedet1, and the signal o
edet2 is generated.

As shown in FIG. 7C, the pulse rdet is, for example, 1 pulse from the start position of one frame of the parent video signal.
This pulse is set to 'H' during H. This pulse rde
t is supplied to the overlap detection circuit 115.

The signal rctl is supplied to the memory 112 or 113 via the switch circuit 116, and controls the reading of the child video signal from the memory 112 or 113. Signal oedet1 and signal oedet
2, as shown in FIGS. 7D and 7E, “H” and “L” are switched in an opposite relationship to each other corresponding to the field in the parent video signal. The field memory 112 is in the “H” state, and the field memory 1 is in the “L” state.
13 is selected. Then, the signal rctl for controlling the reading of the child video signal is supplied to the selected memory, whereby the reading of the child video signal from the memory 112 or 113 is performed.

Signals oedet1 and oedet2
Is selected by a switch circuit 123 that is switched based on a control signal supplied from an overlap detection circuit 115 described later, and is used as a control signal for the switch circuit 116.

In the overlap detection circuit 115, overlap detection of the supplied pulses wdet and rdet is performed. When it is determined that the pulses wdet and rdet overlap, it is determined that the possibility of overtaking is high.

First, when the pulses wdet and rdet do not overlap and no overtaking occurs, the switch circuit 123 selects, for example, the signal oedet1. The selected signal oedet1 is the signal rf
The switching of the switch circuit 116 is controlled as cng. In this example, when overtaking has not occurred, the switch circuit 116 selects the field memory 112 side. Then, the signal rctl supplied from the synchronization generation circuit 121 is supplied to the memory 112, and the child video signal is read from the memory 112. This reading is performed by thinning out each pixel in the horizontal direction by, for example, address control at the time of reading.

If the child video signal is out of synchronization with the parent video signal, as described above, the reading of the child video signal from the memory 112 is overtaken by the writing of the child video signal to the memory 112, as described above. May occur. In this picture-and-picture, since the image is not compressed in the vertical direction, the writing speed of the image signal for one field to the memories 112 and 113 is the vertical frequency of each input signal. On the other hand, the reading speed from the memory 112 or 113 is
It depends only on the side that performs synchronous conversion, that is, only on the vertical frequency of the parent video signal.

In the memory 113, the write speed depends on the vertical frequency of the child video signal, and the read speed depends on the vertical frequency of the parent video signal. Occurs. For example, when the parent video signal and the child video signal are both 60 Hz systems, the vertical frequencies of the writing side and the reading side are slightly different, and the overtaking occurs when the writing start timing and the reading start timing almost overlap. Occur.

Therefore, as shown in FIG. 7, a pulse w having a width of about 3H is
The det (FIG. 7B) and the pulse rdet (FIG. 7C) having a width of about 1H are generated on the read side, and the overlap detection circuit 115 detects the overlap between the pulse wdet and the pulse rdet. When these pulses overlap, it is determined that there is a high possibility that overtaking will occur, and a control signal is supplied from the overlap detection circuit 5 to the switch circuit 123. The switch circuit 123 is switched based on this control signal, and the signal oedet2 becomes the signal r.
fcng. Then, based on the signal rfcng, control is performed so as to read the child video signal from the field memory on the opposite side from the normal. As a result, overtaking is avoided.

[0022]

In the above-described picture-and-picture display, the display of the sub-screen 102 is performed on the screen 1
The image was compressed in the horizontal direction at a fixed ratio to 00, resulting in an unnatural screen. Therefore, at present, for example, a television set capable of picture-and-picture display is required to be able to arbitrarily set the image size and display position of the small screen 102.

However, according to the above-described conventional technique, the picture size of the small picture 102 is changed in the vertical and horizontal directions and the display position is arbitrarily set, and at the same time, the synchronization of the small picture signal with the parent picture signal is changed. In such a case, all cases that cause overtaking cannot be detected. FIG. 8 shows the field memory 11 in this case.
The relationship between the line address count and the target field of writing or reading in 2 and 113 is shown. 8A and 8C showing the line address count, the vertical axis represents the line address to be read.

On the write side, in the target field based on the signal wfcng as shown in FIG.
The line address count as shown in FIG.
The sub-video signal is written based on 1). On the other hand, on the read side, the signal r as shown in FIG.
In the target field based on fcng, the line address count (signal rctl) as shown in FIG. 8C
Thus, the reading of the child video signal is performed in a shorter period than the writing. Further, the length of the readout period changes according to the vertical image size of the small screen 102, and the start position changes according to the display position.

As a result, as shown in FIG. 9, an overtaking occurs at a point a where the read-side address count (signal rctl) and the write-side address count (signal wctl) intersect. Is read, and in the period c, past field data is read. As described above, when writing and reading are performed by accessing the same field memory, overtaking may occur depending on the image size and the display position.

This overtaking cannot be detected by the overtaking detection circuit shown in FIG. 6 in most cases. For example, if a moving image is displayed on the screen, the current screen and the past scene are switched on the sub-screen 102, and There is a problem that the display one field before is made, and the screen becomes unsightly.

Therefore, an object of the present invention is to overtake read / write in the field memory even when the picture size is converted and the display position is changed arbitrarily in the picture and picture display. It is an object of the present invention to provide an image processing apparatus and a processing method that do not cause the problem.

[0028]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a first and a second field memory in which a sub-picture signal for forming a sub-picture is written for each field; First switching means for synchronizing and selectively supplying a write-side memory control signal for controlling writing of a child video signal to the first and second field memories to the first and second field memories; And a read-side memory control signal for controlling reading of the child video signal from the first and second field memories in synchronization with the parent video signal forming the parent screen, to the first and second field memories. A second switching means for selectively supplying and a writing means for switching the first switching means based on a field of the child video signal. Means for generating only the field memory switching signal, read start position detecting means for detecting the timing at which the child video signal is read from the first and second field memories in field units, and switching of the writing field memory based on the timing. Detecting means for detecting a signal level, wherein the second switching means selects a field memory on which writing has not been performed based on the detection output. .

According to another aspect of the present invention, there is provided a first and second field memories in which a sub-picture signal for forming a sub-screen is written for each field.
A write-side memory control signal for controlling writing of the child video signal to the first and second field memories in synchronization with the child video signal and selectively supplying a write-side memory control signal to the first and second field memories; 1 and a read-side memory control signal for controlling the reading of the child video signal from the first and second field memories in synchronization with the main video signal forming the main screen. A second switching step for selectively supplying the first field memory to the second field memory, and a writing-side field memory switching signal for switching the first switching step based on the field of the child video signal. Timing at which child video signals are read out from the first and second field memories in field units Detecting, and detecting the level of the write-side field memory switching signal based on the timing. The second switching step selects the field memory on which writing has not been performed based on the detection output. An image processing method is characterized in that the image processing method is performed.

As described above, the present invention latches the write-side field memory switching signal at the timing when the child video signal is read out from the first and second field memories on a field-by-field basis. Since it is configured to select which of the first and second field memories the field memory control signal is to be supplied to, the writing side and the reading side always access different field memories. it can.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. In the present invention, a signal obtained by latching the write-side field switching signal wfcng with the read start pulse rsstat is used as the read-side field switching signal rfcng.

FIG. 1 shows an example of the display of a parent screen and a child screen in a television set to which the image processing apparatus according to the present invention is applied. The user sets the television set 3
For 0, a channel to be displayed as a parent screen is designated and displayed on the screen 31. Then, a channel to be displayed as the sub-screen 36 is separately specified, and at the same time, the size of the sub-screen 36 with respect to the effective screen of the television set and the position at which the sub-screen is displayed are determined by a predetermined method. specify. The user makes this setting by, for example, the mote controller 32 that transmits a command that is infrared-modulated to the infrared receiver 35 of the monitor 30 by infrared.

In the controller 32, the mode key 3
A predetermined command can be transmitted to the monitor 30 by a combination of the operation with the 3 and the direction keys 34. When the user specifies to display the sub-screen 36 with the mode key 33, a frame line is displayed on the screen 31, for example, so as to specify a screen range in which the sub-screen 36 is to be displayed. At this time, the initial setting may be the entire area of the screen 31. The user operates the direction key 34 and the mode key 33 to specify a range in which the sub-screen 36 is displayed, that is, an image size and a display position. This instruction is displayed on the monitor 30
And the range of the original image is displayed on the monitor 31. Based on this range, the horizontal and vertical image sizes N and M of the small screen 36 are obtained by, for example, the number of pixels and the number of lines, respectively. . At the same time, display position information on the screen 31 of the child screen 36 is obtained.
These image size and display position information are stored as setting information of the child screen 36, for example, in a predetermined memory.

FIG. 2 shows an example of the configuration of an image processing apparatus to which the present invention is applied. A small video signal for forming the small screen 36 is supplied to the terminal 1. This child video signal is supplied to the synchronization generation circuit 2 and also to the field memory 3 and the field memory 4. In the synchronization generation circuit 2, synchronization signals such as a horizontal synchronization signal and a vertical synchronization signal are extracted from the supplied child video signal. Then, a write-side memory control signal wctl and a write-side field switching signal wfcng are generated based on these synchronization signals.

The signal wctl is a line address count generated in response to the scanning of the child video signal. The address of the memory 3 or 4 is controlled based on the signal wctl, and the writing of the child video signal to the memory 3 or 4 is performed. Is performed. This signal wctl is a signal wct described later.
The data is supplied to the memory 3 or 4 based on the selection by the switch circuit 5 switched by fcng.

The signal wfcng is a signal generated corresponding to the field of the child video signal. For example, during the period of the odd and even fields of the child video signal, as shown in FIG. And controls the switching of the switch circuit 5. That is, this signal wfcn
The switch circuit 5 is switched for each field by the control of g, and the supply of the signal wctl to the memories 3 and 4 is controlled. Thus, which of the memories 3 and 4 is to be used for writing the child video signal is selected.
The signal wfcng controls the switch circuit 5 and is also supplied to a data input terminal of the latch circuit 8.

On the other hand, a parent video signal for forming a parent screen is supplied from the terminal 9. This parent video signal is supplied to the synchronization generation circuit 1
0, and to the other select input terminal of the switch circuit 12. In the synchronization generation circuit 10, synchronization signals such as a horizontal synchronization signal and a vertical synchronization signal are extracted from the supplied parent video signal. Then, based on these synchronization signals and the setting information of the picture size and display position of the above-mentioned small screen, the above-mentioned read-side memory control signal r
ctl is generated. This signal rctl is supplied to the memory 3 or 4 via the switch circuit 6.

The child video signal supplied from the terminal 1 is written for each field to the memory 3 or 4 selected by the switching of the switch circuit 5 based on the signal wfcng, based on the signal wctl. In this example, in the child video signal, the first field is written to the memory 3 when the signal wfcng is “H”, and the second field is written to the memory 4 when the signal wfcng is “L”. These memories 3
The sub-video signals written in the memory cells 3 and 4 are read out based on a read-side memory control signal rctl, which selects and supplies the memory 3 or 4 by a switch circuit 6 described later. The read child video signal is supplied to one selection input terminal of the switch circuit 12.

Although not shown, the field memory 3
The start timing of reading of the child video signal from the start position detection circuit 4 is detected by the start position detection circuit 7, and a start position pulse rstat is generated. FIG. 3B shows an example of this pulse rsstat. The reading of the child video signal from the memories 3 and 4 is performed in FIG.
It starts with a slight delay from the timing of this pulse rsstat. This pulse rsstat is supplied to the latch signal input terminal of the latch circuit 8. In the latch circuit 8, the signal wfc supplied from the synchronization generation circuit 2 is output.
ng is latched by the pulse rstat.

The latch output of the latch circuit 8 is used as a read-side field switching signal rfcng.
Control signal. FIG. 3D shows an example of the signal rfcng by the latch output. The signal rfcng controls the switch circuit 6 so as to select a field memory on which the writing of the child video signal is not selected by the signal wfcng in the field memories 3 and 4 as a memory from which the child video signal is read. . As described above, in the present invention, the writing and reading of the child video signal are always performed in another field memory.

That is, during the period when the writing to the field memory 3 is selected by the signal wfcng,
If the pulse rsstat is detected, the signal rfcn
The switch circuit 6 is controlled based on g, and the reading of the child video signal from the field memory 4 is selected. The signal rctl generated by the synchronization generation circuit 10 is supplied to the memory 4 via the switch circuit 6.

In the memory 3 or 4, the switch circuit 6
From the side supplied with the signal rctl,
The sub-video signal is read based on 1. FIG. 3C shows the line address count in the memory 3 or 4 at this time. The reading speed of the child video signal from the memory 3 or 4 changes according to the vertical image size of the child screen based on the setting information of the child screen 36 described above. This is because, for example, by address control by the signal rctl,
This is performed by performing line thinning. In the horizontal direction, pixel thinning is performed in the same manner.
Further, the start timing of the reading of the child video signal also changes based on the setting information of the child screen 36 described above. As described above, since the writing and reading of the child video signal are always performed on different memories, even if the reading speed or the start timing of the child video signal is changed, no overtaking occurs in the field memory.

As described above, one and the other selection input terminals of the switch circuit 12 are supplied with the child video signal and the parent video signal, respectively. This switch circuit 12
Switching is performed at a timing corresponding to the display range of the child screen 36 on the screen 31. The child image signal and the parent image signal supplied to one and the other selection input terminals of the switch circuit 12 are converted to a picture-and-picture video signal to be displayed on the same screen, and are derived to the output terminal 13.

FIG. 4 shows a modification of the embodiment of the present invention. In an image processing apparatus according to the present invention, a video signal is converted between a 60 Hz system and a 50 Hz system by synchronous conversion and picture size conversion. It is an example of processing when performing conversion. This example is an example in which a child video signal is a 60 Hz system and a parent video signal is a 50 Hz system. This modification can also be realized by the same image processing device as in the above embodiment. In this case, one-field processing is performed to obtain a natural motion. That is, only one of the odd and even fields is processed. A child video signal of a field to be processed (an even field in this example) is alternately written to the field memories 3 and 4 based on the signal wctl (FIG. 4A). The signal wfcng at this time is as shown in FIG. 4B.

The reading of the child video signal from the memory 3 or 4 is performed based on the cycle of 50 Hz.
Synchronous conversion of the child video signal from a 60 Hz system to a 50 Hz system is performed. FIG. 4C shows a line address count (signal rctl) at the time of this reading.
Based on the line address count, a start position pulse rstat as shown in FIG. 4D is generated. A read-side field switching signal rfcng for switching the reading of the child video signal from the memories 3 and 4
Is generated by latching the signal wfcng with this pulse rsstat. FIG. 4E shows the signal rfcng thus generated.

In this modification, as in the above-described embodiment, the child video signal is transmitted from either of the field memories 3 and 4 based on the signal rfcng generated by latching the signal wfcng with the pulse rstat. Is read. Therefore, the memories accessed for writing and reading do not overlap, and no overtaking occurs.

[0047]

As described above, according to the present invention, access to a field memory in which a video signal of a small picture is written and read is appropriately controlled. Therefore, even if synchronous transfer and image size conversion are performed on the same memory, access to the field memory does not overlap between writing and reading. Therefore, for example, in a television set having a picture-and-picture function, image processing that can arbitrarily set a position and an image size of a sub-screen to be synchronously switched with a main screen and displayed is realized with a small memory capacity. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining reduction of an image on a monitor.

FIG. 2 is a block diagram illustrating an example of a configuration of an image processing device according to the present invention.

FIG. 3 is a timing chart for explaining processing according to the present invention.

FIG. 4 is a timing chart for explaining processing according to a modification of the present invention.

FIG. 5 is a schematic diagram illustrating an example of a picture-and-picture display screen.

FIG. 6 is a block diagram illustrating an example of a configuration of an image processing apparatus according to a conventional technique.

FIG. 7 is a timing chart for explaining overlap detection according to the related art.

FIG. 8 is a timing chart showing a relationship between a line address count and a field to be written or read when an image size is arbitrarily changed.

FIG. 9 is a schematic diagram for explaining overtaking.

[Explanation of symbols]

wfcng: light-side field switching signal, r
fcng read-side field switching signal, wc
tl: Write-side memory control signal, rctl
... Read-side memory control signal, rstat
..Read-side read start pulse, 3, 4... Field memory, 7... Start position detecting circuit, 8.
..Latch circuits, 36, child screens

Continued on the front page (72) Inventor Nobuo Ueki 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (3)

[Claims] An image processing apparatus used in a display system for simultaneously displaying a child screen with an arbitrary image size and position with respect to the display of a parent screen, wherein a child video signal forming the child screen is provided for each field. And a write-side memory control signal for controlling the writing of the child video signal to the first and second field memories in synchronization with the child video signal. First switching means for selectively supplying the first and second field memories with the main video signal forming the main screen, and A read-side memory control signal for controlling the reading of data is selectively supplied to the first and second field memories. Switching means for generating a write-side field memory switching signal for switching the first switching means on the basis of the field of the child video signal, from the first and second field memories. A read start position detecting means for detecting a timing at which the child video signal is read in field units; and a detecting means for detecting a level of the write-side field memory switching signal based on the timing; The image processing apparatus, wherein the means selects the field memory on which the writing is not performed based on the detection output. 2. An image processing method used in a display system in which a child screen is simultaneously displayed at an arbitrary image size and position with respect to a display of a parent screen, wherein a child video signal forming the child screen is provided for each field. And a write-side memory control signal for controlling the writing of the child video signal to the first and second field memories in synchronization with the child video signal. A first switching step for selectively supplying the first and second field memories; and a first and second field memories for synchronizing with a main video signal forming a main screen and storing the sub video signal. A read-side memory control signal for controlling reading from the memory is selectively supplied to the first and second field memories. Supplying a write-side field memory switching signal for switching the first switching step based on the field of the sub-video signal; and the first and second switching. Detecting the timing at which the child video signal is read out from the field memory in units of fields, and detecting the level of the write-side field memory switching signal based on the timing. In the image processing method, the step of selecting the field memory on which the writing is not performed is selected based on the detection output. 3. The image processing device or the image processing method according to claim 1, wherein the parent video signal and the child video signal are signals having different field frequencies. Or the image processing method.