JPH104520A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device with small deterioration in an S/N due to quantization noise while keeping real time performance even in the observation of an animation. SOLUTION: This solid-state image pickup device has two kinds of image pickup modes, a high resolution mode where image pickup data are read in the unit of light receiving unit 130 having a photoelectric conversion element 140 a switch element 150 as a set, and a high speed image pickup mode where image pickup data are read in the unit of light receiving unit 120 being a matrix array (the number of columns is a 1st number and the number of rows is a 2nd number) of the light receiving unit 130 as a unit. In the case of observation of a still image in which a dose is ensured for one image pickup, the image is picked up in the high resolution mode, and in the case of observation of a still image in which a dose is very small for one image pickup, the image is picked up in the high speed image pickup mode, and even in the case of observation of the animation, the real time performance is maintained and the deterioration in the S/N due to quantization noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device suitable for radiation imaging in medical treatment.

[0002]

2. Description of the Related Art In recent years, with the spread of image processing technology, charge transfer devices such as CCDs and BBDs and MOS solid-state imaging devices have been developed as main devices having a photoelectric conversion function. Various solid-state imaging devices are known.

[0003] In the field of medical treatment, image diagnosis using X-ray radiographic film invented in the early 20th century is still used at the forefront, but as the number of patients increases, storage methods and storage locations are increased. Is a major problem. Therefore, in recent years, using an X-ray image intensifier (Image Intensifier; II) technology, an X-ray is converted into an optical image by an electron tube, and is directly transferred to a computer by being read by a CCD or the like. By storing in electronic media, it is possible to provide the user with convenience such as saving a storage place, facilitating retrieval, and enabling image processing even at a later date.

The imaging using X-rays includes a high-speed imaging mode for observing the inside of the body in real time (hereinafter also referred to as a fluoroscopy mode) and a high-resolution mode for observing the inside of the body at a specific time. Observation in these two modes is performed with the same pixel unit.

Further, in this method, a problem such as deterioration of an image occurs in a portion converted by the X-ray II. Recently, first, after converting the X-ray into visible light or the like by a scintillator or the like, a tapered shape is first used. A method of inputting to a photodiode using an optical fiber plate (tapered fiber) and performing photoelectric conversion. Second, after converting X-rays into visible light or the like by a scintillator or the like, without using an optical fiber plate, amorphous silicon or the like can be used. 2. Description of the Related Art A method of directly inputting an image into a large-area image sensor to form an image has been used.

FIG. 8 shows an apparatus used in the first method. The radiation imaging apparatus includes a scintillator plate 1 formed of CsI and converting X-rays into an optical signal. Between the scintillator plate 1 and the solid-state imaging unit 2, tapered fibers 3 bundled in three rows and three columns are provided. Intervened. Solid-state imaging unit 2
Is constituted by arranging square plate-shaped chips 4 in a matrix so as to correspond to the tapered fibers 3. And, as shown in FIG. 9, the one unit chip 4 has
The photodiode and the switch element constitute a set of light receiving elements, and the light receiving elements 5 are formed by arranging the light receiving elements vertically and horizontally in a matrix. A vertical shift register 6 for sequentially selecting light receiving elements one by one and outputting a signal and a charge amplifier for processing a signal from each selected light receiving element are provided near the periphery of the chip 4 around the light receiving section 5. Array 7 is arranged.

[0007]

Generally, when imaging is performed using X-rays, the dose is set low in order to reduce the amount of exposure. However, in the high-speed imaging mode, since the moving image is observed from the imaging result, the irradiation time of the X-rays is inevitably increased, so that the dose of the irradiated X-rays per unit time is extremely small. As a result, a kind of fluctuation called X-ray quantum noise is generated in the transmitted X-ray itself, so that even if one scintillator converts one X-ray photon into a very large number of visible photons, it is noisy. There was a problem that only images could be obtained.

In the conventional radiation imaging apparatus, as shown in FIG. 9, a light receiving section 5 is arranged in one chip 4 and a circuit section of a vertical shift register 6 and a charge amplifier array 7 is provided around the light receiving section 5. Therefore, in order to capture all the optical signals converted by the scintillator plate 1, the light must be narrowed down by using the tapered fiber 3.

[0009] However, tapered fibers are very expensive for reasons of their manufacture. As can be seen from the example using an X-ray film, the subject of image diagnosis in the medical field is a human body, which is also a large area such as the chest, so that a large imaging device is required. Therefore, if an attempt is made to realize a radiation imaging apparatus having an area corresponding to a human body using an expensive taper fiber, there is a problem that the cost per system becomes enormous.

[0010] Further, the tapered fiber has a problem that an image cannot be obtained at a position corresponding to a corner of the fiber or the image is slightly distorted because four corners of the fiber are rounded at the time of manufacturing.

On the other hand, in the case of the second method using amorphous silicon, although a large area can be easily achieved,
There is a problem that it is not possible to reduce the video line capacity, which causes noise most, because it is not possible to apply fine processing technology, especially when the sensor is enlarged to the size of the human body,
This problem became more serious, and it was difficult to obtain a better S / N ratio than the II system.

To solve these problems, an example using a MOS image sensor has been known. For example, as disclosed in Japanese Patent Application Laid-Open No. 4-3588, there is a method of dividing a video line by arranging an integrator for each horizontal light receiving unit of a two-dimensional MOS sensor to increase an S / N ratio. If this method is used, the pixel size per unit of the MOS image sensor can be increased to 200 μm × 200 μm or more, so that it is conceivable to increase the area.

However, since there is a restriction that the area of the chip itself cannot be made larger than the size of the semiconductor wafer, the size of the light receiving section is limited to the size of the wafer, and a number of the chips are combined to construct a human body. I have to adopt a method. However, even in this method, since there is an area occupied by the amplifier array and the horizontal and vertical shift registers for each connection of the respective light receiving sections, a large gap exists between the chips by several mm corresponding to the occupied area. Since a blank area is generated, there is a drawback that it becomes a serious obstacle in practical use.

Further, when manufacturing such a large-area chip, an offset variation is particularly problematic.
Although the threshold voltage Vth of a MOS device varies in the manufacturing process, the Vth variation becomes even more remarkable especially when a large-area chip is configured. However, in the device described in JP-A-4-3588, the device is not devised, and it is clear that the effect appears as fixed pattern image noise.
It cannot be practical without a solution.

Further, even if the pixel size per unit is increased, when a large area chip is used and the number of light receiving elements in each vertical line is increased, the wiring capacitance, which is one component of the video line capacitance, is increased together with the chip size. Increase
Further, since the total capacitance of the switching elements of the light receiving elements connected to each video line, which is another component of the video line capacitance, also increases, such an increase in the capacitance cannot be ignored even in a MOS device.

In response to such an increase in the capacity of the video line, as disclosed in Japanese Patent Application Laid-Open No. 63-185281,
It is conceivable to provide a switch for connection path setting in addition to the switch element of the light receiving element to reduce the number of connection switch elements in the video line during operation. Switch element ON
The effect of the switching noise accompanying the / OFF operation increases.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a solid-state imaging device which maintains real-time performance even when observing a moving image and has small S / N deterioration due to quantum noise. Aim.

It is another object of the present invention to provide a solid-state imaging device capable of obtaining an image having a good S / N ratio without any omission or distortion in the image.

[0019]

According to a first aspect of the present invention, there is provided a solid-state imaging device for capturing an input two-dimensional optical image. A photoelectric conversion element for converting to a signal, and a switch element having a first terminal connected to a signal output terminal of the photoelectric conversion element and for outputting a current signal generated by the photoelectric conversion element from the second terminal in accordance with a row scanning signal. And the light receiving unit as a set is the first
Are arranged in a matrix with the second number being the number of rows and the second number being the number of rows, to form light receiving elements, and the light receiving elements are arranged such that the third number is the number of columns and the fourth number is the number of rows A light receiving unit, which is formed in a matrix and has the second terminals of the switch elements in the same column electrically connected to each other, and (b) a current signal output for each column of the light receiving unit, respectively. And a first number and a third number that integrate or non-integrate an electric charge relating to the current signal into a capacitive element connected between the input and output terminals of the charge amplifier in response to the reset instruction signal. A fifth number of integrating circuits that are products, (c) a fifth number of signal processing circuits that input the respective integrated signals output from the respective integrating circuits and perform signal processing, and (d) respective light receptions An output signal from the first number of signal processing circuits corresponding to the element, and a mode designation signal. When the mode specifying signal specifies the high resolution mode, the output signals from the first number of signal processing circuits are output as they are, and when the mode specifying signal specifies the high-speed imaging mode, , First
A third number of output signal processing units for outputting a signal of the sum of output signal values from the number of signal processing circuits, (e) a signal output from the output signal processing unit, and a signal output instruction A signal inputting section, an output signal selecting section for selectively outputting a signal output from the output signal processing section in accordance with an instruction of the signal output instruction signal, and (f) a mode specifying signal, When the high-resolution mode is specified, the switch element is selected for each light-receiving unit, and a row-direction scanning signal for sequentially selecting the light-receiving unit is output. When the mode specifying signal specifies the high-speed imaging mode, A row direction scanning instruction unit for simultaneously selecting a second number of switch elements in the light receiving elements and outputting a row direction scanning signal for sequentially selecting the light receiving elements as a unit; and (g) inputting a mode instruction signal; Mode specification signal is high If the mode designation signal specifies the high-speed imaging mode, an output instruction signal for sequentially selecting the signals output from the output signal processing unit according to the light reception unit is output. An output signal selection instructing unit for outputting an output instruction signal for sequentially selecting signals output from the output signal processing unit in accordance with (h), and (h) a control unit for outputting a mode signal and controlling a signal reading operation. It is characterized by the following.

Here, the first number is 2, and the second number is 2
It is possible.

In the solid-state imaging device according to the first aspect, prior to reading out the imaging data corresponding to the amount of received light accumulated in the photoelectric conversion element of the light receiving unit, the control unit may perform one of the high-speed imaging mode and the high-resolution mode. Is output to a row direction scanning instruction unit, an output signal processing unit, and an output signal selection instruction unit. Hereinafter, the row direction is also referred to as a vertical direction, and the column direction is also referred to as a horizontal direction.

First, the reading operation when the high resolution mode is set will be described. In this mode, a signal corresponding to the amount of received light is read out using the unit of received light as a unit.

After initializing the settings relating to the read operation, a row direction scanning signal is output in which only the first light receiving unit switch element in the row direction of each column is turned "ON". When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit. Then, it is instantaneously accumulated in the feedback capacitance by the integration circuit and output as an integration signal reflecting the amount of received light in the voltage value.

Each integrated signal is input to a corresponding signal processing circuit, and is output after being subjected to, for example, a clamping process or a sampling process. The signal output from the signal processing circuit is input to an output signal processing unit. In the output signal processing section,
Since the high-resolution mode operation is instructed by the mode designating signal, the input signal is output as it is to the output signal selection unit as an output signal corresponding to each light receiving unit.

In this state, the output signal selection instruction section outputs an output signal selection instruction signal. In the output signal selection instruction section,
Since the high-resolution mode operation is instructed by the mode designation signal, an output instruction signal for sequentially selecting signals output from the output signal processing unit in accordance with the light receiving unit is output to the output signal selection unit.

The output signal selector sequentially outputs an output signal in the column direction for each light receiving unit according to the input output instruction signal. The output signals sequentially output in this manner are sequentially collected to obtain an imaging result for the first row of each column.

Subsequently, after initializing the settings relating to the read operation, a row direction scanning signal for turning ON only the switch element of the second light receiving unit in the row direction of each column is output. Thereafter, in the same manner as above, an imaging result for the second row of each column is obtained.

Thereafter, a row-direction scanning signal in which only the switch elements of the third to last light-receiving units in the row direction of each column are turned ON while initializing the setting relating to the read operation each time is performed. The images are sequentially output, and imaging results for all rows in each column are obtained.

Next, the reading operation when the high-speed imaging mode is set will be described. In this mode, a signal corresponding to the amount of received light is read for each light receiving element.

After initializing the settings relating to the read operation, a row direction scanning signal is output which turns on all the switching elements of the first light receiving element in the row direction of each column of the light receiving elements. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit. Then, each is instantaneously accumulated in the feedback capacitance by the integration circuit and is output as an integration signal reflecting the amount of received light in the voltage value. That is, an electric charge of the sum of electric charges accumulated in the second number of photoelectric conversion elements in the same column in which the switch element is simultaneously turned “ON” is accumulated in the feedback capacitance.

Each integrated signal is input to a corresponding signal processing circuit, and is output after being subjected to, for example, a clamping process or a sampling process. One set of signals corresponding to the light receiving elements output from the signal processing circuit is input to an output signal processing unit.
Since the high-speed imaging mode operation is instructed to the output signal processing unit by the mode designating signal, 1 according to the light receiving element is output.
A signal of the sum of the input signal values of the set is output to the output signal selection unit as an output signal corresponding to the light receiving element.

In this state, the output signal selection instruction section outputs an output signal selection instruction signal. In the output signal selection instruction section,
Since the high-speed imaging mode operation is instructed by the mode designation signal, an output instruction signal for sequentially selecting signals output from the output signal processing unit in accordance with the light receiving element is output to the output signal selection unit.

The output signal selector sequentially outputs an output signal in the horizontal direction for each light receiving element in accordance with the input output instruction signal. The output signals sequentially output in this manner are sequentially collected to obtain an imaging result for the first horizontal line in units of light receiving elements.

Subsequently, after initializing the settings relating to the read operation, a row direction scanning signal is output which turns ON only the switch element of the second light receiving element in the row direction of each column of the light receiving elements. Thereafter, in the same manner as above, an imaging result for the second horizontal line in units of light receiving elements is obtained.

Thereafter, the vertical scanning in which only the switch elements of the third to last light receiving elements in the row direction of each column of the light receiving elements are turned "ON" while initializing the setting relating to the read operation each time. Signals are sequentially output to obtain imaging results for all rows in units of light receiving elements.

According to a third aspect of the present invention, in the solid-state imaging device of the first aspect, the row-direction scanning instruction unit and the control unit are disposed on a first plane different from the arrangement plane of the light receiving units. Circuit, output signal processing circuit, output signal selection unit,
The output signal selection instructing unit is provided on a second plane different from the light receiving unit arrangement plane, and (i) is provided in the vicinity of the outer periphery of the light receiving unit. 5
A sixth number of gate electrode pads, which are the product of the second number and the fourth number, commonly connected to the gate terminals of the number of switch elements, and a fifth number of the row of switch elements. An electrode pad on which a fifth number of output electrode pads commonly connected to the output terminal are arranged; and (ii) disposed on a first plane.
A signal output pad for a row direction scanning signal for selecting a light receiving unit, and (iii) a signal input pad arranged on the second plane for inputting a signal from an output electrode pad;
(Iv) a connection means for electrically connecting the gate electrode pad and the signal output pad and electrically connecting the output electrode pad and the signal input pad.

[0037] In the solid-state imaging device according to the third aspect,
The portion other than the light receiving portion, which is a useless space for light reception in imaging, is provided on a plane different from the light receiving portion, and has only a light receiving portion as a light receiving element group and a small electrode pad portion. Therefore, in this solid-state imaging device, a normal optical fiber plate can be used. Thereby, a solid-state imaging device can be provided at low cost. Further, since the tapered fiber is not used, the image is not lost or deteriorated. Furthermore, there is no reduction in S / N as in the case of using amorphous silicon.

The connection means between the light receiving section and parts other than the light receiving section is as follows:
(I) being arranged perpendicularly to the arrangement plane of the light receiving units and being provided with a gate wiring corresponding to a plurality of gate electrode pads or an output wiring corresponding to the plurality of output electrode pads, An output signal processing circuit, an output signal selection unit, an output signal selection instruction unit, a row direction scanning instruction unit, and at least one wiring board on which a control unit is mounted; (ii) an electrode pad of a light receiving unit and the wiring board; A wiring means for electrically connecting the wiring with the wiring means;

Here, the wiring means can suitably employ (i) a bonding wire or (ii) a flexible cable.

In connection by wire bonding, the area required for connection is reduced.

As a flexible cable, TCP, which has recently become common in mounting liquid crystal panels, etc.
(Tape Carrier Package) can be suitably used. The use of a flexible cable makes connection easy and reliable even in a small space.

Further, the connecting means comprises: (i) a first electrically connected directly to the gate electrode pad and the signal output pad.
And (ii) a second electrode electrically connected directly to the output electrode pad and the signal input pad.
And a ball grid array wiring member of the above.

Also in this case, the portion other than the light receiving portion, which is a useless space for the light receiving at the time of imaging, is provided on a plane different from the light receiving portion, and the light receiving portion and the circuit portion other than the light receiving portion are first and second. It is electrically connected directly by the second ball grid array wiring member, and the light receiving surface has only a light receiving portion as a light receiving element group and a small electrode pad portion. Therefore, in this solid-state imaging device, a normal optical fiber plate can be used. Thereby, a solid-state imaging device can be provided at low cost.

According to a fourth aspect of the present invention, there is provided the solid-state imaging device according to the third aspect, wherein the circuit unit other than the light receiving unit is located in a region opposite to a region where the light receiving unit exists.

In the solid-state imaging device according to the fourth aspect, the radiation is converted into an optical signal by a scintillator plate, and the optical signal is transmitted by an optical fiber, for example. At this time, since a component that blocks radiation such as Pb can be present in the optical fiber, there is little adverse effect due to the radiation, but by arranging the circuit portion in a region opposite to the region where the light receiving portion exists, The circuit section other than the light receiving section can be completely protected from radiation without reducing the imaging area.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a solid-state imaging device according to the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention. As shown in FIG.
(A) A photoelectric conversion element 1 that converts an input optical signal into a current signal
40 and a terminal 15 as a signal output terminal of the photoelectric conversion element 140.
1 is connected, and the switch element 150 that outputs a current signal generated by the photoelectric conversion element 140 from the terminal 152 in accordance with the row direction scanning signal is a set. The light receiving elements 120 are formed by being arranged in a matrix as a number, and the light receiving elements 120
Are formed in a matrix with M as the number of columns and N as the number of rows, and the light receiving unit 100 in which the terminals 152 of the switch elements 150 in the same column are electrically connected to each other;
(B) A current signal output for each column of the light receiving unit 100 is individually input, and a charge related to the current signal is integrated or non-integrated into the capacitor 212 connected between the input and output terminals according to the reset instruction signal KRS. (C) 2M signal processing circuits 220 for inputting the integrated signals DS output from the respective integration circuits 210 and performing signal processing; d) When two output signals from the signal processing circuit 220 and the mode designation signal MD corresponding to the respective light receiving elements 120 are input, and the mode designation signal MD designates the high resolution mode, the signal processing is performed. The two output signals from the circuit 220 are output as they are, and when the mode designation signal MD designates the high-speed imaging mode, a signal of the sum of the two integrated signals is output. No. a processing unit 250 inputs the signal output from the (e) output signal processing section 250, the signal output instruction signal _{HS j (j = 1~2M),} HS k (k = 1~M), the signal output An output signal selection unit 260 for selectively outputting a signal output from the output signal processing unit 250 in response to the instruction of the instruction signals HS _j and HS ^k , and (f) a mode designation signal M
D, and when the mode designation signal MD designates the high resolution mode, the switch element 1
Select 50, when the light receiving unit 130 sequentially outputs selection row direction scanning signal VS _{i (i} = 1~2N) as a unit, the mode designating signal MD designates a high-speed imaging mode, the light receiving element 120 simultaneously with selecting two switching elements 150, type row direction scanning instruction unit 320 for outputting a row direction scanning signal VS _i for sequentially selecting the light receiving element 120 as a unit, the (g) mode instruction signal MD,
When the mode designation signal MD designates the high-resolution mode, an output instruction signal HS _j for sequentially selecting signals output from the output signal processing unit 250 according to the light receiving unit 130.
Outputs, mode when the specified signal MD designates a high-speed imaging mode, the output signal selection for outputting an output instruction signal HS ^k for sequentially selecting signals output from the output signal processing section 250 in response to the receiving component 120 An instruction unit 330;
And a control unit 310 that outputs a mode signal MD and controls a signal read operation. Then, two integrating circuits 210 corresponding to each light receiving element 120, and 2
One signal processing circuit 220 and one output signal processing unit 25
0 and one output signal selector 260 constitute a vertical signal processor 200 _k . Further, (i) a data signal output circuit 280 that receives a signal output from the vertical signal processing unit 200 _k and outputs an output data signal as a device is further provided.

The integration circuit 210 has (i) a charge amplifier 211 for inputting an output signal from the light receiving section 100 and amplifying the charge of the input current signal, and (ii) one terminal connected to the input terminal of the charge amplifier 211. A capacitor 212 having the other terminal connected to the output terminal of the charge amplifier 211,
(Iii) One terminal is connected to the input terminal of the charge amplifier 211, the other terminal is connected to the output terminal of the charge amplifier 211, and if the reset instruction signal KRS is significant, “O
N "state, and the switch element 213 which becomes" OFF "when the reset instruction signal KRS is insignificant;
(Iv) a capacitor 214 having one terminal grounded and the other terminal connected to the output terminal of the charge amplifier 211;

FIG. 2 is a configuration diagram of the signal processing circuit 220. As shown in FIG. 2, the signal processing circuit 220 includes (i)
A signal DS output from the integration circuit 210 is input, and a clamp circuit 221 that clamps an input signal in accordance with the clamp instruction signal CP, and (ii) a signal output from the clamp circuit 221 is input, and a sample instruction signal SP is input. Sample and hold circuit 226 that performs a sample and hold operation according to
And

The clamp circuit 221 includes (i) the integrator circuit 2
(Ii) an amplifier 223 which receives and amplifies and outputs a signal via the capacitive element 222;
i) one terminal is connected to the input terminal of the amplifier 223,
A capacitor 224 having the other terminal connected to the output terminal of the amplifier 223; and (iv) one terminal connected to the input terminal of the amplifier 223, the other terminal connected to the output terminal of the amplifier 223, and a clamp instruction signal. A switch element 225 is set to an “ON” state when the CP is significant, and is set to an “OFF” state when the clamp instruction signal CP is insignificant.

The sample-and-hold circuit 226 (i) inputs the signal output from the clamp circuit 221 to one terminal, and when the sample instruction signal SP is insignificant, the sample-and-hold circuit 226 is in an OFF holding state, and When the signal SP is significant, the switch element 227 is set to a sample state of “ON”, and (ii) a capacitor element 228 that accumulates signal charges via the switch element 227 is provided.

FIG. 3 is a configuration diagram of the output signal processing unit 250. As shown in FIG. 3, the output signal processing unit 250
(I) A buffer amplifier 251 that receives and amplifies output signals VT1 and VT2 of the two signal processing circuits 220 according to the k-th (k = 1 to M) light receiving element, amplifies the output signals, and converts and outputs impedance. _1, and 251 _2, the signal output from the (ii) a buffer amplifier 251 _1, 251 _2,
Each of the switch elements 252 ₁ and 252 _{2 that} are input to the first terminal and are “ON” when the mode instruction signal MD indicates the high resolution mode and “OFF” when the mode instruction signal MD indicates the high-speed imaging mode. When the signal output from the (iii) a buffer amplifier 251 _1, 251 _2, respectively, first
And the switch element 2 is turned "OFF" when the mode instruction signal MD indicates the high-resolution mode, and "ON" when the mode instruction signal MD indicates the high-speed imaging mode.
53 _1, and 253 _2, (iv) switching elements 252 _1, 25
2 ₂ are input from the first terminal, respectively, and the output signal V corresponding to the light receiving unit 130, which is an AC component, is output.
Capacitive element 25 for outputting O _2k-1 and VO _2k from the second terminal
4 _1, and 254 _2, (v) switching elements 253 _1, 253 ₂
Are input from the first terminal, respectively, and an output signal VO ^k corresponding to the sum regarding the light receiving unit 130 in the light receiving element 120, which is an AC component, is output from the second terminal.
Capacitors 255 ₁ and 255 ₂ to which the second terminals are connected.
And

The output signal selection section 260 outputs (i) the signals VO _2k-1 and VO _2k corresponding to each light receiving unit 130,
"ON" when input from the first terminal and the output signal selection instruction signals HS _2k-1 and HS _2k for each light receiving unit 130 are significant.
(Ii) a signal VO ^k corresponding to each light receiving element 120 is input from a first terminal, and an output signal selection instruction signal HS ^k for each light receiving element 120 is input.
And a switch element 263 that is turned “ON” when is significant.

The data signal output circuit 280 receives (i) the signal output from the output signal selection unit 260 and amplifies the charge of the input current signal;
i) a capacitor 282 having one terminal connected to the input terminal of the charge amplifier 281 and the other terminal connected to the output terminal of the charge amplifier 281; and (iii) one terminal connected to the input terminal of the charge amplifier 281. The other terminal is connected to the output terminal of the charge amplifier 281. When the initial potential setting instruction signal GRS is significant, it is turned on, and when the initial potential setting instruction signal GRS is insignificant, it is turned off. And a switching element 283 to be in a state.

FIG. 4 is a configuration diagram showing an outline of a geometric configuration of the present embodiment. As shown in FIG. 4, the solid-state imaging device according to the present embodiment includes a photodiode chip 1 having a light receiving unit 100 in which light receiving elements 120 are arranged in a matrix.
1 and a wiring board 13 arranged between the adjacent light receiving units 100 with the board surface perpendicular to the photodiode chip 11.
a, 13b, a vertical shift register chip 14, which is a row direction scanning instruction section 320 provided on the wiring board 13a as shown in FIG. 4, and an integrating circuit 210, a signal processing circuit also provided on the wiring board 13b. 220, output signal processing unit 2
50, an output signal selection unit 260, a control unit 310,
And a charge amplifier array chip 15 including an output signal selection instructing section (horizontal shift register) 300.

Around the light receiving section 100 of the photodiode array chip 11, a plurality of gate electrode pads 44a commonly connected to the gate terminals of the switch elements 150 in each horizontal light receiving column of the plurality of light receiving units 130, A plurality of output electrode pads 44b commonly connected to the output terminals of the switch elements 150 in the row (vertical light receiving row) are arranged. That is, around the light receiving portion 100 of the photodiode array chip 11, an electrode pad portion 44 composed of a gate electrode pad 44a and an output electrode pad 44b is provided.
Are formed.

[0057] The vertical shift register chip 14, the signal output pads 45a for outputting a row direction scanning signal VS _i instructing the vertical position of the light receiving unit 130 for reading an optical detection result is formed.

As shown in FIG. 5, the solid-state imaging device according to the present embodiment has a pedestal 35 of the photodiode array chip 11.
Are mounted and supported by a horizontal (arrow X direction) wiring board 13b and a vertical (arrow Y direction) wiring board 13a. On the opposite side in the X direction of the square plate-shaped pedestal 35, there are formed a central first protrusion 36 having a cut-out corner and a pair of second protrusions 37 projecting the corner. A notch 38 is formed in the middle part of both sides of the wiring board 13a in the direction, and the notch 38 of the wiring board 13a is formed.
The thickness of the upper plate is smaller than that of the lower plate, and a step is formed on the surface on the back side of the wiring board 13a in FIG.

The pedestal 35 has its first convex portion 36 engaged with the step portion of the wiring board 13a in the front in the Y direction, and a pair of second convex portions 37 formed in the notches 38 of the rear wiring board 13a. It is fitted and supported by the wiring board 13a in the Y direction.

Further, at the upper part on both sides of the wiring board 13a in the Y direction, a convex portion 39 and a convex portion 40 which are stepped are formed. Then, the lower convex portion 40 of the Y-direction wiring board 13a is fitted into the notch 41 formed on the upper side of the X-direction wiring board 13b, and the adjacent wiring board is placed on the fitted convex portion 40. Wiring boards 13a and 13b in the X and Y directions are vertically and horizontally assembled in a three-dimensional manner by fitting the projections 39 on the upper side of 13a so as to overlap.

As shown in FIG. 5, around the two adjacent sides of the light receiving portion 100 of the photodiode array chip 11 mounted on the pedestal 35, that is, in the vicinity of the two outer peripheral sides of the photodiode array chip 11, As shown in the figure, the corresponding number of electrode pads 44a and 44b are formed for each of the horizontal light receiving rows and the vertical light receiving rows of the light receiving element 120. On the other hand, as shown in FIG. 5, the notch 3 is formed on the wiring board 13a in the Y direction and the wiring board 13b in the X direction.
A number of gate wirings 46a and output wirings 46b corresponding to the respective gate electrode pads 44a and output electrode pads 44b are provided by wiring such as gold plating over the eight positions in the vertical direction.

Then, as shown in FIG. 4, the pedestal 35 on which the photodiode array chip 11 is mounted is mounted on the wiring board 13.
a, 13b, the gate electrode pad 44a of the photodiode array chip 11 and the gate wiring 46a of the wiring board 13a in the Y direction, and the output electrode pad 44b and the output wiring of the wiring board 13b in the X direction. 46b
Are electrically connected to each other by a bonding wire 47.

In the wiring board 13a in the Y direction, the area opposite to the area where the photodiode array chip 11 exists (the lower part of the wiring board 13a) is shown in FIGS.
As shown in FIG. 7, the vertical shift register chip 14 is die-bonded with an adhesive. Similarly, on the wiring board 13b in the X direction, the photodiode array chip 1
The charge amplifier array chip 15 is die-bonded to the area opposite to the area where 1 is present (the lower part of the wiring board 13b) with an adhesive.

The signal output pad 45a of the vertical shift register chip 14, the gate wiring 46a of the wiring board 13a in the Y direction, and the charge amplifier array chip 15
The signal input pad 45b and the output wiring 46b of the wiring board 13b in the X direction are electrically connected by bonding wires 47, respectively.

The solid-state imaging device according to the present embodiment reads out imaging data corresponding to the light image received by the light receiving section 100 as follows.

First, the read operation when the high resolution mode is set will be described. In this mode, a signal corresponding to the amount of received light is read in units of the light receiving unit 130. FIG. 6 is a timing chart of the imaging data read operation according to the present embodiment when the high resolution mode is set.

When the control section 310 designates the high resolution mode by the mode instruction signal MD, the switch element 252 of the output signal processing section 250 is turned "ON" and the switch element 253 is turned on.
Is "OFF".

[0068] First, prior to the execution of the read, together with the control unit 310 significantly all of the clamp instruction signal CP _j, an integrating circuit reset instruction signal KRS considered significant, the output of the output and the integrating circuit 210 of the clamp circuit 220 The reference potential is Vref.

[0069] Further, prior to execution of the read, the significant horizontal scanning signal HS _j and initial potential setting instruction signal GRS corresponding to all of the horizontal lines. As a result, all of the switch elements 261 and 262 are turned ON, and the capacitance element 25
4 are all set to the reference potential Vref which is the initial potential of the data output circuit 280.

Next, the control unit 310 to all of the clamp instruction signal CP _j insignificant, the integrating circuit reset instruction signal K
With the RS insignificant, the horizontal scanning signal corresponding to the all horizontal lines HS _j and initial potential setting instruction signal GR
While S is kept significant _, the switch element 150 of the _first light receiving unit 130 _{1, j} in the vertical scanning of the light receiving unit 100
With a significant vertical scanning signal VS _i to "ON" only, to significantly sample instruction signal SP _j corresponding to all of the horizontal lines. When the switch element 150 is turned “ON”, the electric charge accumulated in the photoelectric conversion element 140 due to the light reception up to that time is output from the light receiving unit 100 as a current signal. Then, the voltage is instantaneously accumulated in the capacitance element 212 as the feedback capacitance by the integration circuit 210 and output as a voltage. The signal output from the integration circuit 210 is input to the capacitance element 254 via the clamp circuit 221, the sample hold circuit 226, the buffer amplifier 251, and the switch element 252. As a result, the capacitance element 254
A voltage corresponding to the amount of light received by the photoelectric conversion element 140 is applied to the signal input terminal of the.

[0071] Then, after the horizontal scanning signal HS _j and initial potential setting instruction signal GRS corresponding to all of the horizontal line and the non-significant, the setting of the horizontal scanning signal HS _j, 1st light receiving unit in the vertical direction 130 Start reading data for _{1, j} .

The timing control section 310 sets the horizontal selection signal HS ₁ to be significant, so that a horizontal scanning signal for instructing ON of only the switch element 261 corresponding to the first light receiving unit 130 _1,1 in the horizontal direction. HS ₁ is significant, and the switching element 15 corresponding to the first light receiving unit 130 _1,1
In addition to turning ON only 0, the initial potential setting instruction signal GRS becomes temporarily significant, and the data output circuit 280
Is set to the reference potential Vref.

When the switch element 261 corresponding to the first light receiving unit 130 _1,1 is turned “ON”, the output terminal of the capacitor 254 and the input terminal of the data output circuit 280 are connected. Since the potential of the output terminal of the element 254 remains the potential at the time when the switch elements 261 and 262 were previously opened, that is, the reference potential Vref which is the initial potential of the input terminal of the data output circuit 280, Is stable without any fluctuation.

Next, the first light receiving unit 13 in the horizontal direction
0 _1,1 a significant a clamp instruction signal CP ₁ and the sample instruction signal SP ₁ in accordance with the. As a result, the clamp circuit 22
1 changes to the reference potential Vref which is the clamp potential, and this change is applied to the first light receiving unit 130 _1,1 in the horizontal direction via the sample hold circuit 226, the capacitor 254, and the data output circuit 280. It is output as an output data signal V _O corresponding to the amount of incident light.

Subsequently, the horizontal scanning signal HS ₁ for instructing the selection of only the switch element 261 in accordance with the first light receiving unit 130 _1,1 in the horizontal direction, and the first light receiving unit 130 _1,1 in the horizontal direction. The corresponding clamp instruction signal CP ₁ and sample instruction signal SP ₁ are made insignificant, and the data reading for the first light receiving unit 130 _{1,1 in the} horizontal direction ends.

Next, the first light receiving unit 13 in the horizontal direction
In the same manner as 0 _1,1 , data reading is performed for the second and subsequent light receiving units 130 _{1, j in} the horizontal direction.

[0077] Then, the control unit 310 is considered significant for all the clamp instruction signal CP _j integrating circuit reset instruction signal KRS, while setting the output of the output and the integrating circuit 210 of the clamp circuit 221 to the reference potential Vref, a light receiving Part 10
Second and subsequent light receiving units 130 in vertical scanning of 0
_The data reading for _{i and j} is executed.

In this manner, a light image formed by the light input to the light receiving unit 100 is captured, and image data is obtained with high resolution for each light receiving unit 130.

Next, the reading operation when the high-speed imaging mode is set will be described. In this mode, a signal corresponding to the amount of received light is read for each light receiving element 120. FIG. 7 is a timing chart of the reading operation of the imaging data of the present embodiment when the high-speed imaging mode is set.

When the control section 310 designates the high-speed imaging mode by the mode instruction signal MD, the switch element 252 of the output signal processing section 250 is turned off, and
3 is "ON".

[0081] First, prior to the execution of the read, together with the control unit 310 significantly all clamp instruction instructing signal CP _j, an integrating circuit reset instruction signal KRS considered significant, the output of the output and the integrating circuit 210 of the clamp circuit 221 Is the reference potential Vref.

[0082] Further, prior to execution of the read, the significant horizontal scanning signal HS _j and initial potential setting instruction signal GRS corresponding to all of the horizontal lines. As a result, all of the switch elements 263 are turned ON, and all outputs of the capacitor 255 are set to the reference potential Vref which is the initial potential of the data output circuit 280.

Next, control section 310 makes all clamp instruction signals CP _j insignificant and integrate circuit reset instruction signal K
With the RS insignificant, the horizontal scanning signal corresponding to the all horizontal lines HS _j and initial potential setting instruction signal GR
While S remains significant, the vertical scanning signals VS ₁ and VS ₂ that turn on all the switching elements 150 of the first light receiving elements 120 _{1 and j} in the vertical scanning of the light receiving section 100 are made significant. , to significant sample instruction signal SP _j corresponding to all of the horizontal lines. When the switch element 150 is turned “ON”, the electric charge accumulated in the photoelectric conversion element 140 by the light reception up to that time becomes a current signal and becomes a light signal.
Output from 00. That is, each signal from the light receiving unit 100 includes two photoelectric conversion elements 140 in the same vertical light receiving column.
Is output as a current signal. Then, the voltage is instantaneously accumulated in the capacitance element 212 as the feedback capacitance by the integration circuit 210 and output as a voltage. The signal output from the integration circuit 210 is input to the capacitance element 255 via the clamp circuit 221, the sample hold circuit 226, the buffer amplifier 251, and the switch element 253. As a result, the capacitance element 255 ₁ ,
A voltage corresponding to the amount of light received by the photoelectric conversion element 140 is applied to each of the signal input terminals 255 ₂ .

Next, after the horizontal scanning signal HS ^k and the initial potential setting instruction signal GRS corresponding to all the horizontal lines are made insignificant, the first light receiving element 120 in the vertical direction is set by setting the horizontal scanning signal HS ^k. Start reading data for _{1, j} .

The timing control section 310 makes the horizontal selection signal HS ¹ significant, so that the horizontal scanning signal for instructing the ON state of only the switch element 263 corresponding to the first light receiving element 120 ₁ , 1 in the horizontal direction. The switching element 26 corresponding to the first light receiving element 120 _1,1 with HS ¹ being significant
3 is turned ON, and the initial potential setting instruction signal GRS becomes temporarily significant, and the data output circuit 280
Is set to the reference potential Vref.

When the switch element 263 corresponding to the first light receiving element 120 _1,1 is turned “ON”, the output terminal of the capacitive element 255 and the input terminal of the data output circuit 280 are connected. Since the potential of the output terminal of the element 255 remains the potential at the time when the switch element 262 was previously opened, that is, the reference potential Vref which is the initial potential of the input terminal of the data output circuit 280, the data output circuit 280
Of the input terminal does not fluctuate and remains stable.

Next, the first light receiving element 12 in the horizontal direction
The clamp instruction signals CP ₁ and CP ₂ and the sample instruction signals SP ₁ and SP ₂ corresponding to 0 _1,1 are made significant. As a result, the output of the clamp circuit 221 changes to the reference potential Vref which is the clamp potential.
26, the capacitance element 255, and the data output circuit 280, the first light-receiving element 120 _1,1
It is output as an output data signal Vo corresponding to the amount of light incident on the two photoelectric conversion elements 140.

Subsequently, the horizontal scanning signal HS ¹ for instructing selection of only the switch element 263 in accordance with the first light receiving element 120 _1,1 in the horizontal direction is applied to the first light receiving element 120 _1,1 in the horizontal direction. The corresponding clamp instruction signals CP ₁ , CP ₂
And the sample indication signals SP ₁ and SP ₂ are insignificant,
The data reading for the first light receiving element _{1201,1 in the} horizontal direction ends.

Next, the first light receiving element 12 in the horizontal direction
In the same manner as 0 _1,1 , data reading is performed for the second and subsequent light receiving elements 120 _{1, k in} the horizontal direction.

[0090] Then, the control unit 310 is considered significant for all the clamp instruction signal CP _j integrating circuit reset instruction signal KRS, while setting the output of the output and the integrating circuit 210 of the clamp circuit 221 to the reference potential Vref, a light receiving Part 10
The second and subsequent light receiving elements 120 in the vertical scanning of 0
_The data reading for _{i and k} is executed.

In this way, the light image formed by the light input to the light receiving unit 100 is captured, and the useless space for the imaging on the imaging plane is reduced at high speed for each of the light receiving elements 120 including the four light receiving units 130. Obtain imaging data.

The present invention is not limited to the above embodiment, and can be modified. For example, in the above-described embodiment, the light receiving elements are configured by 2 rows × 2 columns = 4 light receiving units. However, from the relationship between the imaging speed of one screen and the resolution to be achieved, the number of other rows and other columns are different. It is possible to constitute a light receiving element from a number of light receiving units. Further, in the above embodiment, the wiring board and the bonding wire are used to connect the electrode pads. However, a flexible cable can be used instead of the bonding wire, and the wiring board and the bonding wire can be used instead. It is also possible to use ball grid wiring.

[0093]

As described in detail above, claim 1 is as follows.
According to the solid-state imaging device, imaging in the high-resolution mode for collecting imaging data for each light receiving unit and imaging in the high-speed imaging mode for collecting imaging data for each light receiving element composed of a plurality of light receiving units are possible. By using the high-resolution mode when observing a still image and using the high-speed imaging mode when observing a moving image, it is possible to perform imaging while maintaining real-time properties even when observing a moving image and with small S / N deterioration due to quantum noise.

According to the solid-state imaging device of the third aspect,
In the solid-state imaging device according to the first aspect, since the circuit unit other than the light receiving unit, which is a useless space for imaging, is provided on a plane different from the light receiving surface of the light receiving unit, a normal optical fiber plate can be used. . Thereby, a solid-state imaging device can be provided at low cost. Further, since the tapered fiber is not used, the image is not lost or deteriorated. Further, there is no decrease in the S / N ratio as in the case of using amorphous silicon.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a signal processing circuit of the embodiment.

FIG. 3 is a circuit configuration diagram of an output signal processing unit of the embodiment.

FIG. 4 is an explanatory diagram of a geometric arrangement of the solid-state imaging device according to the embodiment;

FIG. 5 is an explanatory diagram of a geometric arrangement of the solid-state imaging device according to the embodiment;

FIG. 6 is a timing chart of an operation in a high resolution mode of the solid-state imaging device of the embodiment.

FIG. 7 is a timing chart of an operation in a high-speed imaging mode of the solid-state imaging device of the embodiment.

FIG. 8 is a perspective view showing a conventional solid-state imaging device.

FIG. 9 is a plan view illustrating a solid-state imaging unit of a conventional solid-state imaging device.

[Explanation of symbols]

10: solid-state imaging device, 11: photodiode array chip, 12: light receiving unit, 13a, 13b: wiring board,
14 vertical shift register chip, 15 charge amplifier array chip, 26 vertical shift register, 35 pedestal, 44 electrode pad portion, 44a gate electrode pad, 44b output electrode pad, 45a signal output pad 45b: signal input pad, 46a: gate wiring,
46b: output wiring, 47: bonding wire, 10
0: light receiving section, 120: light receiving element, 130: light receiving unit, 1
40: photoelectric conversion element, 150: switch element, 200:
Vertical signal processing unit, 210 integration circuit, 220 signal processing circuit, 221 clamp circuit, 226 sample hold circuit, 250 output signal processing unit, 260 output signal selection unit, 280 data signal output circuit, 310 Control unit,
320: row direction scanning instruction unit, 330: output signal selection instruction unit.

Claims (4)

[Claims] 1. A solid-state imaging device for capturing an input two-dimensional optical image, wherein a photoelectric conversion element that converts an input optical signal into a current signal, and a first terminal is connected to a signal output terminal of the photoelectric conversion element. And
A light receiving unit having a pair of a switch element that outputs a current signal generated by the photoelectric conversion element from a second terminal in accordance with a row direction scanning signal, and the first number is defined as the number of columns, and the second number is defined as The light receiving elements are formed by being arranged in a matrix as the number of rows, and the light receiving elements have a third number as the number of columns,
A light receiving unit in which the fourth number is arranged in a matrix with the number of rows being arranged in a matrix and the second terminals of the switch elements in the same column are electrically connected to each other; and an output for each column of the light receiving unit The first and second current signals are individually input, and the charge associated with the current signal is integrated or non-integrated with a capacitor connected between the input and output terminals of the charge amplifier according to a reset instruction signal. A fifth number of integrators, which is a product of the number of the third number and the third number; and a signal processing of the fifth number for inputting the integrated signals output from the respective integrators and performing signal processing. A circuit and, according to each of the light receiving elements, an output signal from the first number of signal processing circuits and a mode designation signal are input, and when the mode designation signal designates a high resolution mode, , The first number of signal processing circuits And outputting the sum of the output signals from the first number of signal processing circuits when the mode designation signal designates a high-speed imaging mode. Number of output signal processing units, a signal output from the output signal processing unit, and a signal output instruction signal, and a signal output from the output signal processing unit according to an instruction of the signal output instruction signal An output signal selection unit for selectively outputting a signal, and when the mode designating signal is inputted, when the mode designating signal designates a high resolution mode, the switch element is selected for each light receiving unit, and the light receiving A row direction scanning signal for sequentially selecting a unit as a unit is output, and when the mode designation signal designates a high-speed imaging mode, the second number of switch elements in the light receiving elements are simultaneously selected and A row direction scanning instruction unit for outputting a row direction scanning signal for sequentially selecting the light receiving elements as a unit, and inputting the mode instruction signal, and when the mode designation signal designates a high resolution mode, Outputs an output instruction signal for sequentially selecting signals output from the output signal processing unit in response to the output signal processing unit. When the mode designation signal designates a high-speed imaging mode, the output signal processing unit A solid-state imaging device, comprising: an output signal selection instruction unit that outputs an output instruction signal for sequentially selecting output signals; and a control unit that outputs the mode signal and controls a signal read operation. 2. The solid-state imaging device according to claim 1, wherein the first number is two, and the second number is two. 3. The apparatus according to claim 2, wherein the row direction scanning instruction unit and the control unit include:
The integration circuit, the output signal processing circuit, the output signal selection unit, and the output signal selection instruction unit are disposed on a first plane different from the light reception unit arrangement plane, and the light reception unit array is provided. The light-receiving unit is disposed on a second plane different from the plane, is disposed near the outer periphery of the light-receiving unit, and is commonly connected to gate terminals of the fifth number of the switch elements in each row of light-receiving units. A sixth number of gate electrode pads, which is a product of the second number and the fourth number, and the fifth number of columns of the switch elements commonly connected to output terminals of the switch elements; A fifth number of output electrode pads, a signal output pad disposed on the first plane for a row direction scanning signal for selecting the light receiving unit, and a signal output pad disposed on the second plane Also, a signal input pad for inputting a signal from the output electrode pad. 2. The device according to claim 1, further comprising: a connection unit configured to electrically connect the gate electrode pad and the signal output pad, and electrically connect the output electrode pad and the signal input pad. 3. Solid-state imaging device. 4. The integration circuit, the output signal processing circuit,
The output signal selection unit, the output signal selection instruction unit, the row direction scanning instruction unit, and the control unit are located in a region opposite to a region where a light receiving surface of the light receiving unit exists. The solid-state imaging device according to claim 3.