JPH104321A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption in a low output power mode by setting the drain current of a 1st FET set nearest an antenna at a level lower than the prescribed value in a non-signal transmission mode. SOLUTION: To always keep the current consumption (idling current IdsO) flowing to the drain of a 1st FET in a non-signal transmission mode at a level lower than the current consumption in a largest power output mode, it is required make the current IdSO not exceed the current consumption least necessary for output of the largest power to be transmitted from an antenna. Thereby, the current IdSO is shown as IdsO<=Pa/Vdd, where Pa shows the largest power that is transmitted through the antenna of an electronic device such as a portable telephone terminal, etc., with Vdd showing the (source power) voltage that is applied to the drain of the 1st FET. A high output amplifier consists of the 1st FET set nearest the antenna, a 2nd FET which is used for a driver, and an impedance matching circuit. The performance of this amplifier is decided by the performance of the 1st FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-output amplifier for transmission, an antenna, and a semiconductor device including the same, and more particularly to a semiconductor device suitable for reducing power consumption.

[0002]

2. Description of the Related Art FIG. 2 shows a microwave transmitting / receiving device used for an electronic device such as a portable telephone terminal. This device includes a receiving unit that receives radio waves from a base station and a transmitting unit that emits radio waves toward the base station. After the radio wave received by the antenna is amplified by the low noise amplifier, the phase shift is adjusted by the phase shifter according to the reception direction of the radio wave.
Next, the signal is mixed with a signal from a local oscillator in a mixer section, converted into an intermediate frequency that is easy to handle, and then demodulated.
On the transmission side, on the other hand, the modulated intermediate frequency wave is converted to a higher frequency in the mixer section, amplified, and then radiated from the antenna toward the base station.

[0003] Conventionally, research on high-efficiency operation at the maximum output power has been actively conducted in order to reduce power consumption. For example, Kunihisa et al., "Low-Voltage GaAs Power MMICs for Mobile Communication", Spring 1995 IEICE, C-9
4, pp94.

[0004]

In the above prior art, no consideration is given to high efficiency operation at low output power. That is, the conventional high-output amplifier has a problem that the current consumption increases when no signal is transmitted, which should originally reduce the current consumption. Here, at the time of no-signal transmission, it means the time of DC bias, and the consumption current means the idling current.

[0005]

SUMMARY OF THE INVENTION An electronic device according to the present invention has a microwave transmitting / receiving device. The microwave transmitting / receiving device has a transmitting modulator, a transmitting high-power amplifier, and an antenna. The output amplifier has one or a plurality of field effect transistors (FETs).
The consumption current flowing through the drain of the first FET closest to the antenna among the ETs is equal to or less than a value obtained by dividing the maximum power transmitted from the antenna by the voltage applied to the drain of the first FET.

[0006]

FIG. 1 shows the drain of a first FET (generally called a power FET) closest to an antenna among FETs constituting a high-power amplifier used in an electronic device such as a portable telephone terminal. It shows the output power dependence of the current consumption. As shown in the figure, in order to keep the consumption current (idling current) flowing through the drain of the first FET at the time of no signal transmission always smaller than the consumption current at the time of maximum power output, the maximum power transmitted from the antenna is required. It is sufficient that the current consumption does not exceed the minimum consumption current required for the output. Therefore, the idling current Ids0 is expressed by the following equation.

Ids0 ≦ Pa / Vdd Pa: maximum power transmitted from an antenna of an electronic device such as a mobile phone terminal Vdd: voltage applied to the drain of the first FET (power supply voltage) For example, a mobile communication system is a PHS (Personal Handy
-phone System), when one Li-ion battery is used and the battery voltage is 2.7V or more, the maximum transmission power is 80m
Since it is W, the required idling current is 30 mA or less. Similarly, PDC (Japanese Personal Digita
l In case of Cellular phones, the maximum transmission power is 800
mW required idling current is 300m
A or less. Furthermore, CDMA (Code Division Multipl
In the case of eAccess), the required maximum idling current is 150 mA or less because the maximum transmission power is 400 mW.

FIG. 3 is a configuration diagram of a high-output amplifier. The high power amplifier includes a first FET (power FET) closest to the antenna, a second FET for a driver, and an impedance matching circuit provided between the input side, the output side, and the FET. The performance of the high power amplifier is the first FE
Determined by the performance of T.

FIG. 4 shows an electrode pattern of the first FET. In the figure, reference numerals 1, 2, and 3 denote a drain electrode, a gate electrode, and a source electrode, respectively. The gate electrode 2 is electrically connected in parallel by a gate electrode pattern 4, and is connected to a bonding pad 5 for the gate. The structure as shown in FIG. 4 is called a comb gate FET because the gate electrode has a comb shape. The reason for adopting the comb tooth structure is to allow as much current as possible between the source and the drain to flow for the same chip area.

FIG. 5 is a sectional view taken along the line AB in FIG. A semi-insulating GaAs substrate 11, two layers each having a thickness of 50 nm
Undoped superlattice A with a total thickness of 300 nm repeated three times
l _y Ga _{1 over} y As / GaAs buffer layer (y = 0.28) 1
2, an undoped In _x Ga _{1 -x} As channel forming layer (x = 0.25) 13 having a thickness of 8 nm, an undoped GaAs spacer layer 14 having a thickness of 2 nm, and n-type GaAs having a thickness of 13 nm
Electron supply layer 15, undoped GaAs high breakdown voltage layer 16 having a thickness of 45 nm, undoped Al _z Ga ₁ -z having a thickness of 10 nm
As etching stopper layer (z = 0.1) 17, thickness 1
It is composed of a 60 nm n + type GaAs cap layer 18, a drain electrode 1, a gate electrode 2, and a source electrode 3.

Next, the operating conditions of the first FET will be described with reference to FIG. As the load line, a load line with a low drain conductance (the load line of the present invention in the figure) is used.
This makes it possible to reduce the idling current from Ids0B to Ids0 as compared with the case where a conventional load line is used. A load line with low drain conductance is obtained by increasing the impedance of the matching circuit on the output side of the first FET.

According to the present invention, it has been newly found that an upwardly convex graph as shown in FIG. 7 can be obtained. That is, FIG. 7 shows the 1.9 GHz band P
In the HS system specification, the first FET is operated at a power supply (drain) voltage of 3 V, and an adjacent channel (6 in the PHS system).
(00 kHz detuning) shows the measurement results of the power added efficiency with respect to the idling current when the leakage power is −60 dBc. Here, the upwardly convex graph also includes a linear graph that rises to the left and is indicated by □ in the figure, and the power added efficiency increases when the idling current decreases. Therefore, the first FE from which an upwardly convex graph is obtained
By using T, it is possible to realize an electronic device that consumes less power at low output power (small idling current) and has a long total transmission time per battery (large power addition efficiency).

Next, the measurement conditions in FIG. 7 are shown. Four types of first FETs having a gate width of 3.6 mm were prepared. ■
Is the first FET of FIG. Δ, □, and ○ indicate (a) shorten the gate length (0.6 → 0.35 μm) in order to increase the transconductance gm as compared with the first FET of FIG.
m), (b) undoped In _x Ga _{1 -x} from gate electrode 2
The thickness up to the As channel formation layer 13 is reduced (6
(0 → 52 nm), and (c) increase the In composition ratio x of the undoped In _x Ga _{1 -x} As channel forming layer 13 (0.
25 → 0.35), with Δ being (a), □ being (a) (b), and ○ being (a)
(C) is adopted.

The PHS system is another PDC system or CDMA.
The demand for adjacent channel leakage power is stricter than in the system. Therefore, in the case of the PDC system and the CDMA system, the power addition efficiency becomes larger than that of the PHS system,
The total transmission time per battery can be further lengthened.

The mutual conductance gm of the four types of first FETs used in the measurement of FIG. 7 when the idling current is 30 mA is 270 mS / mm or more. In other words, the transconductance gm at the time of the current consumption of 8.3 mA per 1 mm of the gate width flowing to the drain is 7
5 mS / mm or more.

[0016]

According to the present invention, the power consumption at the time of low output power can be reduced.

[Brief description of the drawings]

FIG. 1 shows a first FET (power F) in one embodiment of the present invention.
FIG. 7 is a diagram illustrating output power dependence of current consumption of the ET).

FIG. 2 is a block diagram of a conventional microwave transmitting / receiving device.

FIG. 3 is a configuration diagram of a high-power amplifier in one embodiment of the present invention.

FIG. 4 shows a first FET (power F) in one embodiment of the present invention.
FIG. 5 is an electrode pattern diagram of (ET).

FIG. 5 is a sectional structural view of a first FET (power FET) in FIG. 4;

FIG. 6 shows a first FET (power F) in one embodiment of the present invention.
FIG. 4 is an explanatory diagram of a load curve of (ET).

FIG. 7 shows a first FET (power FE) in an embodiment of the present invention.
It is a figure which shows the idling current dependence of the power addition efficiency of T).

[Description of Signs] 1 ... Drain electrode, 2 ... Gate electrode, 3 ... Source electrode,
5 ... Gate bonding pad, 11 ... Semi-insulating G
aAs substrate, 12 ... undoped superlattice Al _y Ga _{1 over} y A
s / GaAs buffer layer (y = 0.28), 13... undoped In _x Ga _{1 -x} As channel forming layer (x = 0.2
5), 14 ... undoped GaAs spacer layer, 15 ... n
-Type GaAs electron supply layer, 16 ... undoped GaAs high withstand voltage layer, 17 ... undoped Al _z Ga _{1 over} z As etching stopper layer (z = 0.1), 18 ... n + -type GaAs cap layer.

Claims (11)

[Claims] 1. An electronic device having a microwave transmitting / receiving device, wherein the microwave transmitting / receiving device has a modulator for transmission, a high power amplifier for transmission, and an antenna, and the high power amplifier has one or a plurality of electric fields. Effect transistor (F
ET), and the current consumption flowing through the drain of the first FET closest to the antenna among the FETs when no signal is transmitted is determined by the maximum power transmitted from the antenna by the first F
An electronic device characterized by being equal to or less than a value divided by a voltage applied to a drain of ET. 2. The electronic device according to claim 1, wherein said modulator performs QPSK modulation. 3. The electronic device according to claim 1, wherein said first FET is made of a compound semiconductor. 4. The electronic device according to claim 1, wherein the gate length of said first FET is 0.35 μm or less. 5. The electronic device according to claim 1, wherein the first FET has a channel thickness of 60 nm or less. 6. The electronic device according to claim 1, wherein the first FET has a transconductance of 75 mS at a current consumption of 8.3 mA per 1 mm of gate width flowing to the drain.
/ Mm or more. 7. The electronic device according to claim 1, wherein said electronic device is driven by a battery. 8. The electronic device according to claim 7, wherein said battery is one Li-ion battery, and said modulator performs π / 4 shift QPSK modulation for PHS which is one of mobile communication systems. And the first FET when no signal is transmitted.
An electronic device characterized in that the current consumption flowing through the drain of the device is 30 mA or less. 9. An electronic device according to claim 7, wherein said battery is one Li-ion battery, and said modulator performs π / 4 shift QPSK modulation for PDC which is one of mobile communication systems. And the first FET when no signal is transmitted.
An electronic device characterized in that the current consumption flowing through the drain of the device is 300 mA or less. 10. The electronic device according to claim 7, wherein said battery is one Li-ion battery, and said modulator is an offset QPSK for CDMA which is one of mobile communication systems.
The first FE is modulated when no signal is transmitted.
An electronic device, wherein a current consumption flowing to a drain of T is 150 mA or less. 11. The electronic device according to claim 1, wherein the first FET has an upwardly convex graph of power added efficiency with respect to an idling current.