JPH1042575A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a high withstand voltage IC for driving a switching element from being destroyed at the time of large-current driving. SOLUTION: A clamp diode 110 is connected between an upper arm switching element driving signal reference output terminal VS1 and a lower arm switching element driving signal reference output terminal VS0 of a high withstand voltage IC100. The clamp diode 110 turns on, only when the voltage V (VS1-VS0) between the upper and the lower reference output terminals VS1, VS0 is negative, to keep the voltage (VS1-VS0) at the on-voltage of the clamp diode 110. The negative voltage, which results in the destruction of the high withstand voltage IC generated by the small inductance of the pattern of a diode tip or the wiring of a current detector, is clamped by the clamp diode. Therefore, it is possible to prevent the high withstand voltage IC from being destroyed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to the prevention of breakdown of a high breakdown voltage IC for driving an inverter device and a bridge circuit of the inverter device.

[0002]

2. Description of the Related Art Conventionally, a method for detecting a current of a three-phase inverter circuit described in Japanese Patent Application Laid-Open No. 4-54461 is known. FIG.
The configuration of the three-phase inverter circuit described in Japanese Patent No. 54461 is schematically shown. This three-phase inverter circuit has np
Six switching elements T1,
T2, T3, T4, T5, T6, and six diodes D1, D2, D3 connected in parallel to the respective switching elements T1, T2, T3, T4, T5, T6.
It has a voltage source inverter 1 composed of D4, D5 and D6.

The three-phase inverter circuit has a load such as a motor 2 driven by the inverter circuit and six switching elements T1, T2, T3, T4, T
5, a driving device such as a high-voltage IC (not shown) for driving T6 is connected. Further, a current detector 3 is provided in the three-phase inverter circuit. The output voltage of the current detector 3 is converted into a digital signal by an A / D (analog / digital) converter 4 and supplied to a processing unit (CPU) 5. The CPU 5 is connected to an interrupt pulse generator 6 that generates a start signal for interrupt processing of the CPU 5. When the current value detected by the current detector 3 reaches a predetermined value, the CPU 5
It is programmed to execute the processing of a predetermined interrupt routine.

The switching elements T1, T3, and T5 are switching elements on the upper arm side (hereinafter, referred to as upper arm switching elements, respectively). The switching elements T2, T4, and T6 are switching elements on the lower arm side (hereinafter, referred to as lower arm switching elements, respectively). The upper-arm switching element T1 and the lower-arm switching element T2, the upper-arm switching element T3 and the lower-arm switching element T4, and the upper-arm switching element T5 and the lower-arm switching element T6 form a pair to form a three-phase inverter. I have.

[0005] Each upper arm switching element T1, T3,
A positive power supply voltage is applied to the collector of T5. The emitter of each upper arm switching element T1, T3, T5 is
Each is connected to the collectors of the lower arm switching elements T2, T4, T6. The emitters of the lower arm switching elements T2, T4, T6 are commonly connected and connected to the negative power supply voltage line via the current detector 3. The gates of the upper arm switching elements T1, T3, T5 and the lower arm switching elements T2, T4, T6 are connected to a drive signal output terminal (not shown) of a driving device such as a high withstand voltage IC. T1, T
2, T3, T4, T5, and T6 are driven by drive signals supplied from a drive unit (not shown).

Further, each upper arm switching element T1,
Diodes D1 and D5 are connected to collectors of T3 and T5, respectively.
The cathodes of the upper and lower switching elements T1, T3, and T5 are connected to the anodes of diodes D1, D3, and D5, respectively. The cathodes of the diodes D2, D4, D6 are connected to the collectors of the lower arm switching elements T2, T4, T6, respectively. The anodes of the diodes D2, D4, and D6 are directly connected to the negative power supply voltage line without passing through the current detector 3. That is, the diodes D1, D
2, D3, D4, D5, and D6 are connected in anti-parallel to the switching elements T1, T2, T3, T4, T5, and T6, respectively.

[0007] The three-phase inverter circuit shown in FIG. 15 is configured as described above, and the current detector 3 outputs a current obtained by combining only the currents flowing through the lower arm switching elements T2, T4, and T6. It is designed to detect. The inverter circuit having the configuration shown in FIG.
Conventionally used.

The three-phase inverter circuit shown in FIG.
As shown in FIG. 5, the lower arm switching elements T2, T4,
Instead of providing the current detector 3 only between each emitter of T6 and the negative power supply voltage line, the current detector 7 is connected to the wiring path of the drive current flowing from the inverter circuit to the load such as the motor 2.
Is provided. Six switching elements T1, T
2, T3, T4, T5, and T6 each have a diode D
The configuration of the voltage source inverter 1 in which 1, D2, D3, D4, D5, and D6 are connected in anti-parallel is the same as the configuration shown in FIG. The inverter circuit having the configuration shown in FIG. 16 is also commonly used. In addition, although illustration was omitted,
Needless to say, the A / D converter 4, the CPU 5, and the interrupt pulse generator 6 are connected to the current detector 7 so that an interrupt process can be performed according to the detected current value.

The three-phase inverter circuit shown in FIG.
As shown in FIG. 5, the lower arm switching elements T2, T4,
Instead of providing the current detector 3 between each emitter of T6 and the negative power supply voltage line, the lower arm switching element T
2, T4, T6 emitters and corresponding diode D
The current detector 8 is provided on a bus bar which is commonly connected to the anodes of D2, D4 and D6.

[0010] Six switching elements T1, T2, T
3, T4, T5 and T6 have diodes D1 and D
The configuration of the voltage-source inverter 1 in which the components 2, D3, D4, D5, and D6 are connected in anti-parallel is the same as the configuration shown in FIG. The inverter circuit having the configuration shown in FIG. 17 is also often used conventionally. Although not shown, the A / D converter 4, the CPU 5, and the interrupt pulse generator 6 are connected to the current detector 7 so that an interrupt process can be performed according to the detected current value. Nor.

FIG. 18 shows a general single-phase inverter device in which upper and lower arm switching elements of an inverter circuit are driven by a high withstand voltage IC. The single-phase inverter circuit of this example has a configuration corresponding to a one-phase inverter portion of the three-phase inverter circuit shown in FIG. That is, the upper arm switching element T
1 and a pair of switching elements T1 and T2 each having the emitter connected to the collector of the lower arm switching element T2.
, Upper and lower diodes D1 and D2 are connected in anti-parallel.

The emitter of the lower arm switching element T2 and the anode of the diode D2 connected in anti-parallel to the lower arm switching element T2 are connected in common, and a current detector 106 is provided on a bus leading to the negative (-) terminal of the DC power supply 108. Is provided. The collector of the upper arm switching element T1 and the cathode of the diode D1 connected in anti-parallel to it are commonly connected to the positive (+) terminal of the DC power supply 108.
A drive signal is input from the high voltage IC 100 to each of the gates G1 and G2 of the upper arm switching element T1 and the lower arm switching element T2.

The inverter circuit having the above configuration has three
Three external connection terminals P, U, and N are provided. The external connection terminal P is a power supply terminal for applying a positive power supply voltage to the inverter circuit, that is, a terminal to which the collector of the upper arm switching element T1 and the cathode of the diode D1 are commonly connected. The external connection terminal N is connected to a power supply terminal for applying a negative power supply voltage to the inverter circuit, that is, the other end of the current detector 106 in which the emitter of the lower arm switching element T2 and the anode of the diode D2 are commonly connected to one end. Terminal.

That is, the external connection terminal P and the external connection terminal U
, A DC power supply 108 is connected with the external connection terminal P being on the positive side. The external connection terminal U is connected to a connection node E1 on the emitter side of the upper arm switching element T1. A reactor (inductance value: inductance value) is provided between the external connection terminal U and the external connection terminal N as a load.
LL) 107 is connected.

In a wiring section between the connection node E1 and the collector of the lower arm switching element T2, there is a parasitic reactor having an inductance value of L1. Diode D2
A parasitic reactor having an inductance value of L2 exists in the cathode-side wiring portion of (1). Parasitic reactors having inductance values L3 and L4 exist in series in the anode-side wiring portion of the diode D2. The wiring between the connection node E0 and the connection node N1 provided on the opposite side of E0 across the current detector 106 (that is, between the current detector 106 and the external connection terminal N) has an inductance value of L5. There are parasitic reactors.

The DC power supply 108 is configured by connecting a power supply main body 108a for generating electromotive force and a capacitor 108b in parallel.

The high withstand voltage IC 100 receives an output signal from the input buffer a1 by temporarily holding an externally input signal via the drive signal input terminals UPi and UNi of the IC 100, and receives the output signal of the input buffer a1. A level shifter a2 for generating a signal of a floating potential floating from the potential, an upper arm side driver circuit a3 for receiving an output signal of the level shifter a2 and driving the upper arm switching element T1, and a lower arm switching element for receiving an output signal of the input buffer a1 Lower arm side driver circuit a4 for driving T2, overcurrent detector a for detecting overcurrent
5, an error signal generator a6 that receives a detection signal output from the overcurrent detector a5 and generates an error signal.

The upper arm side driver circuit a3 has a high withstand voltage I
The upper arm switching element T via an upper arm switching element drive signal output terminal UPo provided in C100
1 to output a drive signal. Further, positive and negative floating voltages are externally applied to the upper arm side driver circuit a3 via the floating power supply positive input terminal VB1 and the floating power supply negative input terminal VS1 provided in the high breakdown voltage IC 100, respectively. The floating power supply negative side input terminal VS1 also serves as an upper arm switching element drive signal reference output terminal.

The lower arm side driver circuit a4 has a high withstand voltage I
C100 via a lower arm switching element drive signal output terminal UNo provided in C100.
2 to output a drive signal. Further, a positive power supply voltage is externally applied to the lower arm side driver circuit a4 via a positive power supply terminal VCC provided in the high withstand voltage IC 100.
The lower arm side driver circuit a4 is connected to a lower arm switching element drive signal reference output terminal VS0 provided in the high voltage IC 100.

The overcurrent detector a5 is connected to a current detection terminal OC provided on the high voltage IC 100.

The error signal generator a6 is a high voltage IC 10
An error signal is output to an external control device (not shown) or an alarm notifying unit via an error output terminal Fo provided at 0.

The positive power supply terminal VCC and the negative power supply terminal VSS provided on the high voltage IC 100 are connected to the positive and negative electrodes of the external power supply 101, respectively. The negative power supply terminal VSS is grounded.

The high voltage IC 100 includes the external power supply 10
1, a diode 102, a capacitor 103 and a constant voltage diode 109 are externally provided. That is, the diode 102 has its anode connected to the positive power supply terminal VCC and its cathode connected to the floating power supply positive input terminal VB1. Capacitor 103
Is connected between the floating power supply positive input terminal VB1 and the floating power supply negative input terminal VS1. The constant voltage diode 109 is provided for overvoltage protection of the lower arm switching element drive signal reference output terminal VS0, and is connected between the lower arm switching element drive signal reference output terminal VS0 and the negative power supply terminal VSS.

The high voltage IC 100 is connected to an inverter circuit including a pair of upper and lower arm switching elements T1 and T2 and a DC power supply 108 as follows. That is, the floating power supply negative side input terminal (upper arm switching element drive signal reference output terminal) VS1 of the high withstand voltage IC 100 is connected to the connection node E1 on the emitter side of the upper arm switching element T1. The upper arm switching element drive signal output terminal UPo has a gate resistance 1
04, the gate G of the upper arm switching element T1
1 connected.

The lower arm switching element drive signal reference output terminal VS0 is connected to the lower arm switching element T2.
Is connected to the connection node E0 on the emitter side. The lower arm switching element drive signal output terminal UNo is connected to the gate G2 of the lower arm switching element T2 via the gate resistor 105. The current detection terminal OC is connected to the connection node E0. The negative power supply terminal VSS is connected to the connection node N1 of the inverter circuit. These connection nodes E0 and N1
As described above, the current detector 106 is provided between them, so that the detection voltage of the current detector 106 is applied to the current detection terminal OC.

The wiring between the lower arm switching element drive signal reference output terminal VS0 and the connection node E0 and the wiring between the negative power supply terminal VSS and the connection node N1 have parasitic inductors having inductance values L6 and L7, respectively. Exists.

Here, the maximum value of the breakdown voltage of the upper arm switching element drive signal reference output terminal VS1 of the high breakdown voltage IC 100 is slightly different depending on the application, for example, [(the potential of the lower arm switching element drive signal reference output terminal VS0). )
+600] volts, and the minimum value is about [(potential of the lower arm switching element drive signal reference output terminal VS0) -5] volts for any application. That is, the upper arm switching element drive signal reference output terminal V
This means that a voltage of -5 V or less cannot be applied between S1 and the lower arm switching element drive signal reference output terminal VS0.

This is generally based on a CMOSFET (complementary insulated gate field effect transistor).
C also has bipolar TTL (transistor t)
Even for an IC constituted by a transistor logic, a voltage of -0.5 with respect to a potential lower than the power supply voltage of the IC.
It is considered that only about V is guaranteed, so that it is weakened in principle with respect to a potential lower than the power supply voltage.

FIG. 19 shows the operation timing of the inverter device shown in FIG. In FIG. 19, S
(UPo) and S (UNo) are high voltage ICs
100 upper arm switching element drive signal output terminal U
Po and the signals output from the lower arm switching element drive signal output terminal UNo. The upper arm switching element T1 and the lower arm switching element T
2 is a driving signal. I1 is a current flowing through the upper arm switching element T1, I2 is a current flowing through the diode D2, and I3 is a current flowing through the reactor 107.

Upper and lower arm switching elements T1, T2
Drive signals S (UPo) and S (UNo) are relatively low potential (low) level (hereinafter referred to as L level).
, The upper and lower arm switching elements T1, T2
Are both in the off state. Therefore, the L-level drive signals S (UPo) and S (UNo) are switching element off signals.

The drive signals S (UPo) and S (UNo) are both switching element off signals (ie, L level).
When only the drive signal S (UPo) rises and changes to a signal of a relatively high potential (high) level (hereinafter, referred to as H level) (that is, a switching element ON signal), the drive signal S (UPo) ) Is at the H level (period A in FIG. 19), the DC power supply 10 is connected via the external connection terminal P, the upper arm switching element T1, the reactor 107 and the external connection terminal N from the positive terminal of the DC power supply 108.
A current flows in a path leading to the negative electrode 8.

Here, in the inverter device shown in FIG. 18, for example, the output voltage VDC of the DC power
V, the inductance value LL of the reactor 107 is 3 m
H, if the time width (period A) Ton when the drive signal S (UPo) is at the H level is 1 ms, the reactor 10
The peak current Ip of No. 7 is 100 A (ampere) from the following formula. Ip = VDC · Ton / LL = {300 · 1 · (E−3)} / {3 · (E−3)} = 100 [A] In this specification, “(E−n)” is used. Means 10 to the power of-(minus) n. Here, n is a natural number.

Subsequently, when the drive signal S (UPo) falls to L level, the upper arm switching element T1
Switches to the off state. As a result, the current I1 flowing through the upper arm switching element T1 starts to decrease, and becomes zero with a delay of a predetermined time (period B in FIG. 19).
On the other hand, the current I2 flowing through the diode D2 is
(UPo) begins to increase in synchronization with the falling edge, and B
Reaches the peak current Ip after the lapse of the period. In the period B, the amount of change in current per unit time (di / d
Since t) is large, even a small wiring inductance generates an induced voltage of several volts. The diode D2 generates an on-voltage of about 2 V when a current flows.

Here, in the inverter device shown in FIG. 18, the combined inductance value of the wiring inductances L1, L2, L3, and L4 is 20 nH, the ON voltage VF of the diode D2 is 2 V, and the switching speed Toff of the upper arm switching element T1 is 400 ns. Using the value 100A of the peak current Ip, the voltage V (E1-E0) applied between the connection node E1 on the emitter side of the upper arm switching element T1 and the connection node E0 on the emitter side of the lower arm switching element T2. Is-
7V. V (E1-E0) =-(L1 + L2 + L3 + L4) .I
p / Toff-VF =-{20. (E-9) .100} / {400. (E-
9)｝ -2 = -7 [V]

As described above, even if the wiring inductance is small, when a large current flows as in the period B in FIG. 19, the withstand voltage on the negative side of the high-voltage IC 100, ie, [(VS0 potential) -5] volts is exceeded ( Voltage (below the minimum).

The wiring inductance L5 is set to 20 nH.
And the switching speed Toff of the upper arm switching element T1.
Is used, the connection node E0 on the emitter side of the lower arm switching element T2 during the period B in FIG.
And a voltage V (E0−N) induced between the current detector 106 and a connection node N1 opposite to the connection node E0 with the current detector 106 interposed therebetween.
1) becomes -5 V by the following formula. V (E0−N1) = − L5 · Ip / Toff = − {20 ・ (E-9) ・ 100} / {400 ・ (E−
9)｝ = -5 [V]

The induced voltage V (E0-N1) causes a path from connection node N1 to connection node E0 via the parasitic reactor of wiring inductance L7, constant voltage diode 109 and the parasitic reactor of wiring inductance L6. Electric current flows. Here, assuming that the wiring inductance values L6 and L7 are equal, the induced voltage V (E
0-N1) is applied between the negative power supply terminal VSS and the connection node N1, and between the connection node E0 and the lower arm switching element drive signal reference output terminal VS0 by 1/2. Therefore, the voltage V (VSS-N) applied between the negative power supply terminal VSS and the connection node N1 during the period B in FIG.
1) is -2.5 V by the following formula. V (VSS-N1) = V (E0-N1) /2=-2.5
[V]

In the period B of FIG. 19, the connection node E0
And lower arm switching element drive signal reference output terminal VS
The voltage V (E0-VS0) acting between 0 and -0 is also -2.5V according to the following formula. V (E0−VS0) = V (E0−N1) /2=−2.5
[V]

Since no voltage is applied between the upper arm switching element drive signal reference output terminal VS1 and the connection node E1 during the period B in FIG. 19, the voltage V (VS1-E1) between them is applied. Is 0V.

From the above considerations, the voltage V (VS1-VS0) acting between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0 during the period B in FIG. 19 is -9.5V according to the following equation. Becomes V (VS1-VS0) = V (VS1-E1) + V (E1
−E0) + V (E0−VS0) = 0−7−2.5 = −9.5 [V]

As described above, even if the wiring inductance is small, when a large current flows as in the period B of FIG. 19, the rated voltage is applied between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0 of the high withstand voltage IC 100. A voltage lower than the minimum range of the breakdown voltage (−5 V) is applied, and the high breakdown voltage IC 100 causes breakdown.

FIG. 20 shows another example of a general single-phase inverter device in which upper and lower arm switching elements of an inverter circuit are driven by a high-voltage IC. The single-phase inverter circuit of this example has a structure shown in FIG.
This is a configuration corresponding to a one-phase inverter portion of the phase inverter circuit. That is, the emitter of the upper arm switching element T1 and the lower arm switching element T2
Switching elements T connected to the collectors of
1 and T2, upper and lower diodes D1 and D2 are connected in anti-parallel.

The emitter of the lower arm switching element T2 is connected to one end of the current detector 106.
The other end of the current detector 106 is connected to a negative electrode of the DC power supply 108 via an external connection terminal N. The anode of the diode D2 is connected to the negative power supply terminal VSS of the high voltage IC 100. The collector of the upper arm switching element T1 and the cathode of the diode D1 are commonly connected to an external connection terminal P and are connected to the positive (+) terminal of the DC power supply 108. A drive signal is input from the high-voltage IC 100 to each of the gates G1 and G2 of the upper arm switching element T1 and the lower arm switching element T2.

It should be noted that the other configuration of the inverter circuit, the configuration of the high-voltage IC 100, and the inverter circuit and the high-voltage I
The connection with C100 is the same as that of the configuration shown in FIG. 18, and therefore, the same reference numerals are given and the duplicate description will be omitted.

Also in the example of the configuration shown in FIG.
In the same manner as in the configuration example, the connection node E1 on the emitter side of the upper arm switching element T1 and the lower arm switching are connected by the on-voltage VF of the diode D2 and the voltage induced by the wiring inductance of the diode D2 and the chip of the lower arm switching element T2. A voltage V (E1-E) applied between the element T2 and the connection node E0 on the emitter side.
0) is about -7V.

As in the consideration of the configuration of FIG. 18, the combined inductance value of the wiring inductances L1, L2, L3, and L4 is 20 nH, the ON voltage VF of the diode D2 is 2 V, and the switching speed Toff of the upper arm switching element T1 is set. Is 400 ns and the peak current Ip is 100 A. However, in the example of FIG. 20, since the current flowing through diode D2 does not pass through current detector 106, no voltage is generated between connection node E0 and lower arm switching element drive signal reference output terminal VS0.

Therefore, the voltage V (E1-E0) is applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. That is, a voltage (-7 V) lower than the minimum range of the rated withstand voltage (-5 V) is applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. As a result, the high breakdown voltage IC 100 causes breakdown breakdown.

At the moment when the current flowing through the lower arm switching element T2 is cut off, a voltage is generated by a parasitic reactor having a wiring inductance value L5 which is parasitic between the connection node E0 and the current detector 106, The generated voltage is divided into the parasitic reactors having the wiring inductance values L6 and L7.

Therefore, the voltage V is applied between the connection node E0 and the lower arm switching element drive signal reference output terminal VS0.
(E0−VS0) occurs. As in the consideration of the configuration in FIG. 18, when the wiring inductance L5 is 20 nH, the peak current Ip is 100 A, and the switching speed Toff of the upper arm switching element T1 is 400 ns, V (E0−VS0) becomes −2.5V. .

The parasitic reactor having the wiring inductance value L1, the reactor having the combined inductance value L8 parasitic on the wiring pattern of the lower arm switching element T2, and the ON voltage Vce of the switching element T2 cause a connection between the connection nodes E1 and E0. Generates a voltage V (E1-E0). The combined inductance value of L1 and L8 is 20n
H, when the Vce is 2 V, the peak current Ip is 100 A, and the switching speed Toff of the upper arm switching element T1 is 400 ns, the voltage V (E1-E
The value of 0) is -3 V according to the following formula. V (E1-E0) =-(L1 + L8) Ip / Toff + Vce =-{20. (E-9) .100} / {400. (E-9)} + 2 = -3 [V]

Since no voltage is applied between the upper arm switching element drive signal reference output terminal VS1 and the connection node E1, the voltage V (VS1-E
1) is 0V.

From the above considerations, the voltage V (VS1-VS0) acting between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0 can be calculated by using the following equation.
It becomes 5V. V (VS1-VS0) = V (VS1-E1) + V (E1-E0) + V (E0-VS0) = 0-3-2.5 = -5.5 [V]

As described above, also in the device having the structure shown in FIG. 20, when a large current flows, the upper and lower arm switching element drive signal reference output terminals VS1 and VS1
A voltage lower than the minimum range of the rated withstand voltage (−5 V) is applied between S0 and S0, and the high withstand voltage IC 100 causes breakdown withstand voltage.

According to the above-mentioned consideration of the devices having the configurations shown in FIGS. 18 and 20, the value of the voltage V (VS1-VS0) differs depending on the arrangement of the current detector 106, but the slight inductance of the wiring of the chip and Due to the slight inductance of the wiring of the current detector 106, a negative voltage lower than the minimum value of the rated withstand voltage is generated between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0 in the case of large current drive. It is understood that there is.

The above considerations apply to the case where no current detector is provided as shown in FIG. 21, that is, the case where current detection is not performed. A negative voltage lower than the minimum rated withstand voltage may be generated between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0. Therefore, the high breakdown voltage IC 100 causes breakdown breakdown. In the inverter device having the configuration shown in FIG. 21, the constant voltage diode 109 is not provided.

FIG. 22 shows a general three-phase inverter device in which three pairs of upper and lower arm switching elements of an inverter circuit are driven by a high breakdown voltage IC. The three-phase inverter circuit of this example has a configuration corresponding to the three-phase inverter circuit shown in FIG. That is, in the first phase, upper and lower diodes D1 and D2 are connected in anti-parallel to a pair of switching elements T1 and T2 in which the emitter of the upper arm switching element T1 and the collector of the lower arm switching element T2 are connected. I have.

In the second phase, a pair of switching elements T3 and T3, which are formed by connecting the emitter of the upper arm switching element T3 and the collector of the lower arm switching element T4.
4, upper and lower diodes D3 and D4 are connected in anti-parallel. In the third phase, a pair of switching elements T5 and T5 in which the emitter of the upper arm switching element T5 and the collector of the lower arm switching element T6 are connected.
Upper and lower diodes D5 and D6 are connected in anti-parallel to T6.

Then, each lower arm switching element T
2, the emitters of T4 and T6 and the anodes of diodes D2, D4 and D6 connected in anti-parallel to them are commonly connected to one end of a current detector 214. The other end of the current detector 214 is connected to the external connection terminal N. Each upper arm switching element T1, T3, T5
And the diode D connected to them in anti-parallel
The cathodes of 1, D3 and D5 are commonly connected to an external connection terminal P. Each upper arm switching element T1, T
3, G5 of gates T1, T3 and G5 of each lower arm switching element T2, T4, T6.
A drive signal is input to each of the G6 from the high voltage IC 200.

In addition, in addition to the external connection terminals P and N, three external connection terminals U and
V and W are provided. The external connection terminal U is connected to a connection node E1 on the emitter side of the first phase upper arm switching element T1. The external connection terminal U is connected to a connection node E1 on the emitter side of the first phase upper arm switching element T1. The external connection terminal V is connected to the second
It is connected to the connection node E2 on the emitter side of the upper arm switching element T3 of the phase. The external connection terminal W is connected to a connection node E3 on the emitter side of the upper arm switching element T5 of the third phase.

Although not shown, the wiring portions of the lower arm switching elements T2, T4, T6 and the diodes D
Parasitic reactors exist in the wiring portions 2, D4 and D6, respectively. Further, each lower arm switching element T2,
The connection node E0 on the emitter side of T4 and T6 and the opposite side of E0 across the current detector 214 (that is, the current detector 2
There is also a parasitic reactor in the wiring between the connection node N1 provided between the external node 14 and the external connection terminal N).

The high withstand voltage IC 200 has drive signal input terminals UPi, UNi, VPi, VNi, WP of the IC 200.
i, an input buffer b1 for temporarily holding a signal externally input through WNi, and three level shifters for receiving an output signal of the input buffer b1 and generating a floating potential signal floating from the potential of the signal. b2
b3, b4 and the output signals of the level shifters b2, b3, b4, respectively, and receive the upper arm switching elements T
1, upper driver circuits b5, b6, b7 for driving T3, T5, and lower signals for receiving the three signals output from the input buffer b1 and driving the lower arm switching elements T2, T4, T6, respectively. Arm-side driver circuits b8, b9, b10, overcurrent detector b11 for detecting overcurrent, error signal generator b for receiving a detection signal output from overcurrent detector b11 and generating an error signal
12 are provided.

Each upper arm side driver circuit b5, b6, b
7 are upper arm switching element drive signal output terminals UPo, VPo, W provided on the high-voltage IC 200, respectively.
Each of the upper arm switching elements T1, T3,
A drive signal is output to T5. In addition, each of the upper arm side driver circuits b5, b6, b7 has a floating power supply positive side input terminal VB provided in the high withstand voltage IC 200, respectively.
1, VB2, VB3 and floating power supply negative side input terminals VS1, VS2, VS3 apply positive and negative floating voltages from outside. Each floating power supply negative side input terminal VS1, VS2, VS3 also serves as an upper arm switching element drive signal reference output terminal for each of the upper arm switching elements T1, T3, T5.

Each lower arm side driver circuit b8, b9, b
Reference numeral 10 denotes lower arm switching element drive signal output terminals UNo, VNo,
Each lower arm switching element T2, T via WNo
4, and outputs a drive signal to T6. Each of the lower arm side driver circuits b8, b9, and b10 has a high withstand voltage IC 200.
A positive power supply voltage is applied from the outside via a positive power supply terminal VCC provided at the power supply. Each lower arm side driver circuit b
8, b9, b10 are commonly connected to a lower arm switching element drive signal reference output terminal VS0 provided in the high breakdown voltage IC 200.

The overcurrent detector b11 is a high voltage IC 200
Are connected to a current detection terminal OC provided at the terminal.

The error signal generator b12 is a high voltage IC2
An error signal is output to an external control device (not shown), an alarm notifying unit, and the like via an error output terminal Fo provided at 00.

The positive power supply terminal VCC and the negative power supply terminal VSS provided on the high voltage IC 200 are connected to the positive and negative electrodes of the external power supply 201, respectively. The negative power supply terminal VSS is grounded.

The high voltage IC 200 has the external power supply 20
1, three diodes 202, 203, 204,
Three capacitors 205, 206, 207 and a constant voltage diode 215 are externally provided. That is, the diodes 202, 203, and 204 have their anodes connected in common to the positive power supply terminal VCC and their cathodes connected to the floating power supply positive input terminals VB1, VB2, and VB3, respectively.
It is connected to the. The capacitor 205 is connected between the floating power supply positive input terminal VB1 and the floating power supply negative input terminal VS1.

The capacitor 206 is connected between the floating power supply positive input terminal VB2 and the floating power supply negative input terminal VS2. The capacitor 207 is
It is connected between the floating power supply positive input terminal VB3 and the floating power supply negative input terminal VS3. The constant voltage diode 215 is provided for overvoltage protection of the lower arm switching element drive signal reference output terminal VS0.
It is connected between S0 and the negative power supply terminal VSS.

The high-voltage IC 200 is connected to the three-phase inverter circuit as follows. That is, three floating power supply negative side input terminals (upper arm switching element drive signal reference output terminals) V of the high voltage IC 200
S1, VS2 and VS3 are connected to the respective connection nodes E on the emitter side of the upper arm switching elements T1, T3 and T5.
1, E2 and E3.

The three upper arm switching element drive signal output terminals UPo, VPo, WPo are respectively connected to the gates G1, G3, G5 of the upper arm switching elements T1, T3, T5 via gate resistors 208, 209, 210, respectively. It is connected. The lower arm switching element drive signal reference output terminal VS0 is connected to the lower arm switching element T2,
It is connected to a connection node E0 on the emitter side of T4 and T6.

The three lower arm switching element drive signal output terminals UNo, VNo, WNo are connected to the gates G2, G4, G6 of the lower arm switching elements T2, T4, T6 via gate resistors 211, 212, 213, respectively. It is connected. The current detection terminal OC is connected to the connection node E0.

The negative power supply terminal VSS is connected to the connection node N1 of the inverter circuit. Since the current detector 214 exists between the connection node E0 and the connection node N1 as described above, the detection voltage of the current detector 214 is applied to the current detection terminal OC.

Although not shown, the wiring between the lower arm switching element drive signal reference output terminal VS0 and the connection node E0 and the wiring between the negative power supply terminal VSS and the connection node N1 each have a parasitic reactor. doing.

In the three-phase inverter device shown in FIG. 22, similarly to the single-phase inverter device shown in FIG. 18, when a large current flows, upper and lower arm switching element drive signal reference output terminals VS1, VS0, VS2. And VS0,
A voltage lower than the minimum range of the rated withstand voltage is applied between VS3 and VS0, and the high withstand voltage IC 200 causes breakdown withstand voltage.

FIG. 23 shows another example of a general three-phase inverter device in which three pairs of upper and lower arm switching elements of an inverter circuit are driven by a high breakdown voltage IC. The three-phase inverter circuit of this example has a configuration corresponding to the three-phase inverter circuit shown in FIG.
That is, in the first phase, the upper arm switching element T
1 and a pair of switching elements T1 and T2 each having the emitter connected to the collector of the lower arm switching element T2.
, Upper and lower diodes D1 and D2 are connected in anti-parallel.

In the second phase, a pair of switching elements T3 and T3 each having the emitter of the upper arm switching element T3 and the collector of the lower arm switching element T4 connected to each other.
4, upper and lower diodes D3 and D4 are connected in anti-parallel. In the third phase, a pair of switching elements T5 and T5 in which the emitter of the upper arm switching element T5 and the collector of the lower arm switching element T6 are connected.
Upper and lower diodes D5 and D6 are connected in anti-parallel to T6.

Then, each lower arm switching element T
The emitters of T2, T4 and T6 are connected to one end of the current detector 214. The other end of the current detector 214 is connected to the external connection terminal N. Each diode D2, D4
The anode of D6 is the negative power supply terminal V of the high voltage IC 200.
Connected to SS. Each upper arm switching element T
1, T3, T5 collector and each diode D1, D3
The cathode of D5 is commonly connected to an external connection terminal P. Drive signals from the high-voltage IC 200 are input to the gates G1, G3, G5 of the upper arm switching elements T1, T3, T5 and the gates G2, G4, G6 of the lower arm switching elements T2, T4, T6. It has become.

The remaining structure of the three-phase inverter circuit, the structure of the high-voltage IC 200, and the connection between the inverter circuit and the high-voltage IC 200 are the same as those of the structure shown in FIG. And a duplicate description will be omitted.

In the example of the structure shown in FIG.
2, D4, and D6 do not pass through the current detector 214, so that no voltage is generated between the connection node E0 and the lower arm switching element drive signal reference output terminal VS0. Upper and lower arm switching element drive signal reference output terminals VS1, VS0, VS
2 and VS0 and between VS3 and VS0, a voltage lower than the minimum range of the rated withstand voltage is applied.
C200 causes breakdown voltage.

The same applies to the case where no current detector is provided as shown in FIG. 24. In the case of large current drive, the upper and lower arm switching element drive signal reference output terminals V
A voltage lower than the minimum range of the rated withstand voltage is applied between S1 and VS0, VS2 and VS0, and VS3 and VS0, respectively. In the inverter device having the configuration shown in FIG. 24, the constant voltage diode 215 is not provided.

[0081]

As described above, in the conventional single-phase and three-phase inverter devices using the high withstand voltage ICs 100 and 200 for driving the switching elements, the lower arm switching elements T2, T4 and T6 at the time of driving a large current. And diodes D2, D4, D6 and current detectors 106, 214
Due to the slight inductance of the connection pattern etc.,
There is a problem that a voltage exceeding the rated voltage may be applied to the high voltage ICs 100 and 200, and the high voltage ICs 100 and 200 may be broken.

The present invention has been made to solve the above problems, and has as its object to provide an inverter device capable of preventing a high breakdown voltage IC for driving a switching element from being broken at the time of driving a large current. .

[0083]

To achieve the above object, an inverter device according to the present invention comprises a high-voltage IC for driving switching elements above and below a single-phase inverter circuit.
The clamp diode is connected between the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal.

According to the inverter device of the present invention,
In a single-phase inverter device, the negative voltage applied between the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal of the high breakdown voltage IC determines the minimum rated withstand voltage between those terminals. It can be prevented from falling below.

The inverter device according to the next invention has three upper arm switching element drive signal reference output terminals and lower arm switching element drive signal reference output terminals of a high breakdown voltage IC for driving upper and lower switching elements of a three-phase inverter circuit. And a clamp diode connected between them.

According to the inverter device of the present invention,
In the three-phase inverter device, the negative voltage applied between each of the three upper arm switching element drive signal reference output terminals and the lower arm switching element drive signal reference output terminal of the high breakdown voltage IC is the rated withstand voltage between these terminals. It can be prevented from falling below the minimum value.

In the inverter device according to the next invention, the clamp diode is an external component of the high-voltage IC.

According to the inverter device of the present invention,
It is not necessary to change the design of the high breakdown voltage IC, and the present invention can be applied to an inverter device using an existing high breakdown voltage IC.

The inverter device according to the next invention operates by a power supply that is independent of a drive power supply for a high-voltage IC that drives upper and lower switching elements of an inverter circuit having current detection means, and outputs from the current detection means. A transmission means for transmitting the signal to be transmitted to the high withstand voltage IC is provided.

According to the inverter device of the present invention,
By providing the means for transmitting the output from the current detector to the high withstand voltage IC, it is possible to equalize the potentials of the negative power supply terminal and the lower arm switching element drive signal reference output terminal. A negative voltage is prevented from being applied between the signal reference output terminal and the lower arm switching element drive signal reference output terminal by a wiring pattern of a current detector or the like.

In the inverter device according to the next invention, the transmitting means is constituted by an operational amplifier, and is used as an external component of the high-voltage IC.

According to the inverter device of the present invention,
It is not necessary to change the design of the high breakdown voltage IC, and the present invention can be applied to an inverter device using an existing high breakdown voltage IC.

In the inverter device according to the next invention, the wiring connected to the upper arm switching element drive signal reference output terminal of the high breakdown voltage IC for driving the upper and lower switching elements of the single-phase inverter circuit is connected to the vicinity of the cathode of the lower arm diode. And the wiring connected to the lower arm switching element drive signal reference output terminal is connected to the anode of the diode of the lower arm.

According to the inverter device of the present invention,
When the current detector is not provided, the voltage generated by the inductance caused by the conventional wiring pattern is eliminated, and the voltage is applied between the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal. Since the negative voltage that can be generated is almost only the ON voltage of the lower arm diode, the negative voltage between the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal that is lower than the rated withstand voltage minimum value. Is prevented from being applied. When the current detector is provided, if the negative voltage generated by the current detector between the upper and lower arm switching element drive signal reference output terminals is low, the upper arm switching element drive signal reference output terminal and the lower arm switching element drive This prevents a negative voltage lower than the minimum rated withstand voltage from being applied to the signal reference output terminal.

[0095] In the inverter device according to the next invention, a dedicated bonding pad connected to the other end of the wiring having one end connected to the lower arm switching element drive signal reference output terminal is provided in the three-phase inverter circuit portion. High-voltage IC that drives switching elements above and below a three-phase inverter circuit
And three wirings respectively connected to the three upper arm switching element drive signal reference output terminals are respectively connected near the cathodes of the three lower arm diodes, and the dedicated bonding pad and the three lower arm diodes are connected. The anode and the anode are electrically connected by wires.

According to the inverter device of the present invention,
In the three-phase inverter device, a main current does not flow through each wiring path from each cathode of the three diodes of the lower arm to each upper arm switching element drive signal reference output terminal of the high voltage IC. ,
High breakdown voltage I from each anode of the three diodes in the lower arm
When the current detector is not provided, the three upper arm switching elements are not provided since the main current does not flow through the respective wiring paths leading to the respective lower arm switching element drive signal reference output terminals of C. Since the negative voltage that can be applied between the drive signal reference output terminal and the lower arm switching element drive signal reference output terminal is substantially only the ON voltage of three lower arm diodes, the three upper arm switching element drive signal reference A negative voltage lower than the minimum rated withstand voltage is prevented from being applied between the output terminal and the lower arm switching element drive signal reference output terminal. When the current detector is provided, if the respective negative voltages generated by the current detector between the upper and lower arm switching element drive signal reference output terminals are low, the upper arm switching element drive signal reference output terminal and the lower arm switching This prevents a negative voltage lower than the minimum rated withstand voltage from being applied to the element drive signal reference output terminal.

The inverter device according to the next invention uses a diode having a larger current capacity than the other switching elements and the upper arm diode as the lower arm diode of the inverter circuit driven by the high withstand voltage IC. .

According to the inverter device of the present invention,
By using only the lower-arm diode having a large current capacity, the on-voltage of the lower-arm diode, which is one of the causes of destruction of the high-withstand-voltage IC, can be suppressed to a low level. It gets bigger.

[0099]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a schematic diagram showing an example of a single-phase inverter device to which the present invention is applied. The inverter device according to the first embodiment is different from the general inverter device shown in FIG. 18 in that the high withstand voltage IC 100 is connected between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. The clamp diode 110 is connected, and only when the voltage V (VS1-VS0) between the upper and lower reference output terminals VS1 and VS0 becomes a negative voltage, the clamp diode 110 turns on and clamps the voltage V (VS1-VS0). The on-voltage of the diode 110 is maintained.

In FIG. 1, T1 and T2 are upper-arm switching elements and lower-arm switching elements, D1 and D2 are diodes connected in anti-parallel to upper-arm switching element T1 and lower-arm switching element T2, respectively, and G1 and G2 are The gates of the upper arm switching element T1 and the lower arm switching element T2, 104 and 105 are resistors connected to the gates G1 and G2 of the upper arm switching element T1 and the lower arm switching element T2, respectively, 106 is a current detector, 107 Is the reactor as the load, 108
Is a DC power supply composed of a power supply body 108a and a capacitor 108b.

E1 and E0 are connection nodes on the emitter side of the upper arm switching element T1 and the lower arm switching element T2, P is a power supply terminal for applying a positive power supply voltage to the inverter circuit, and N is a negative terminal for the inverter circuit. U is a power supply terminal for applying a power supply voltage, U is an output terminal of the inverter circuit, and L1, L2, L3, L4, L5, L6
And L7 are reactors I1 and I parasitic on a wiring portion.
2 and I3 are a current flowing through the upper arm switching element T1, a current flowing through the diode D2, and a reactor 1 respectively.
07. The current detector 106 is provided on a bus where the emitter of the lower arm switching element T2 and the anode of the diode D2 are commonly connected.

In FIG. 1, reference numeral 100 denotes a high-voltage IC for driving a switching element of an inverter circuit; 101, an external power supply for supplying a driving voltage to the high-voltage IC 100;
Is a diode, 103 is a capacitor, 109 is a constant voltage diode, a1, a2, a3, a4, a5 and a6 are circuit blocks inside the high voltage IC 100, a1 is an input buffer, a2 is a level shifter, and a3 is upper arm switching. Upper arm side driver circuit for driving the element T1, a
4 is a lower arm side driver circuit for driving the lower arm switching element T2, a5 is an overcurrent detector, and a6 is an error signal generator.

Further, UPi, UNi, UPo, UNo,
VB1, VS1, VS0, OC, Fo, VCC, VSS
Is an input / output terminal of the high voltage IC 100, UPi and UNi are drive signal input terminals, UPo is an upper arm switching element drive signal output terminal for outputting a drive signal of the upper arm switching element T1, and UNo is a lower arm switching element T2. VB1 is a floating power supply positive side input terminal, VS1 is a floating power supply negative side input terminal and an upper arm switching element drive signal reference output terminal, and VS0 is a lower arm switching terminal. An element drive signal reference output terminal, OC is a current detection terminal, Fo is an error output terminal, and VCC and VSS are positive-side and negative-side power supply terminals, respectively.

In the configuration of the inverter device shown in FIG. 1, the same components as those of the inverter device shown in FIG. 18 are denoted by the same reference numerals, and redundant description will be omitted.

Generally, the minimum withstand voltage of the upper arm switching element drive signal reference output terminal VS1 of the high voltage IC 100 is about [(potential of the lower arm switching element drive signal reference output terminal VS0) -5] volts. . That is, the minimum rated withstand voltage of the voltage V (VS1-VS0) between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0 of the high withstand voltage IC 100 is approximately -5V.

Therefore, in the first embodiment, the clamp diode 110 is not particularly limited.
For example, a general diode having an ON voltage of about 0.7 V to 2 V is used. Then, when a negative voltage is applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0, the voltage between them becomes the clamp diode 1
It is clamped to an ON voltage of 10, that is, about -0.7V to -2V. Preferably, the clamp diode 11
0 is the reference output terminal VS0 and VS of the high withstand voltage IC 100.
1, it is preferable that the wiring length from the terminals VS0 and VS1 to the clamp diode 110 be kept as short as possible.

The operation of the inverter having the configuration shown in FIG. 1 will be described. Only when a negative voltage which may cause the IC 100 to be destroyed is applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 100, the clamp diode. 110 is turned on, and a voltage V (VS1-V1) between the terminals VS1 and VS0.
S0) is clamped to the ON voltage (about 0.7 V to 2 V). Therefore, the voltage V (VS1-VS0) is -0.7V-
-2V, and those terminals VS of the high withstand voltage IC 100
It does not fall below the minimum rated withstand voltage -5 V between 1 and VS0.

As described above, according to the first embodiment, a negative voltage is applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 100. The terminal voltage V (VS1-VS0) when applied is -0.7V
−２2V, and these terminals V of the high-voltage IC 100
Since it is possible to prevent the rated breakdown voltage between S1 and VS0 from falling below the minimum value of -5V, it is possible to prevent breakdown of the high breakdown voltage IC 100.

Incidentally, as in the single-phase inverter device shown in FIG. 2, the anode of the diode D2 is directly connected to the negative power supply terminal VSS without passing through the current detector 106, and only the emitter of the lower arm switching element T2 is connected. Current detector 10
20, the clamp diode 110 is connected between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 100. Can be provided. Then, the voltage V (VS1−VS0) between the terminals VS1 and VS0 of the high-withstand-voltage IC 100 can be prevented from falling below the minimum rated withstand voltage −5 V, so that the high-withstand-voltage IC 100 can be prevented from withstand voltage breakdown.

Also, like the single-phase inverter device shown in FIG. 3, in the inverter device having the structure shown in FIG. 21 in which the current detector is not provided, the upper arm switching element drive signal reference output terminal of the high breakdown voltage IC 100 is also provided. VS1 and lower arm switching element drive signal reference output terminal VS0
May be provided with a clamp diode 110. Then, those terminals VS of the high voltage IC 100
Since the voltage V (VS1−VS0) between 1 and VS0 can be prevented from falling below the minimum rated withstand voltage value of −5V, the high withstand voltage IC1 can be prevented.
00 withstand voltage breakdown can be prevented.

(Embodiment 2) FIG. 4 is a schematic diagram showing an example of a three-phase inverter device to which the present invention is applied. The inverter device according to the second embodiment is different from the general inverter device shown in FIG. 22 in that between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 200, Between the upper arm switching element drive signal reference output terminal VS2 and the lower arm switching element drive signal reference output terminal VS0, and between the upper arm switching element drive signal reference output terminal VS3 and the lower arm switching element drive signal reference output terminal VS0. The clamp diodes 216, 217, and 218 are respectively connected.

The upper reference output terminals VS1 and V
The voltages V (VS1-VS0), V (VS2-VS0), V between S2, VS3 and the lower reference output terminal VS0.
Only when each of (VS3-VS0) becomes a negative voltage, the corresponding clamp diode 216, 217, 218 turns on to turn on each of the voltages V (VS1-VS0), V (VS2-V
S0) and V (VS3-VS0) are kept at the ON voltages of the clamp diodes 216, 217 and 218, respectively.

In FIG. 4, T1, T3, T5 and T5
2, T4 and T6 are upper arm switching elements and lower arm switching elements, respectively, and D1, D3 and D5 and D2, D4 and D6 are upper arm switching elements T1, T3 and T5 and lower arm switching element T, respectively.
2, a diode connected in antiparallel to T4 and T6,
G3, G5 and G2, G4, G6 are the gates of the upper arm switching elements T1, T3, T5 and the lower arm switching elements T2, T4, T6, respectively.

Further, 208, 209, 210 and 21
1, 212, and 213 are gates G1, G3, and G5 of the upper arm switching elements T1, T3, and T5, and gates G of the lower arm switching elements T2, T4, and T6, respectively.
2, a resistor connected to G4, G6, 214 is a current detector, E1, E2, E3 are connection nodes on the emitter side of the upper arm switching elements T1, T3, T5, respectively, E0
Is a common connection node on the emitter side of the lower arm switching elements T2, T4, T6, P is a power supply terminal for applying a positive power supply voltage to the inverter circuit, N is a power supply terminal for applying a negative power supply voltage to the inverter circuit, U, V, and W are output terminals of the three-phase inverter circuits, respectively. The current detector 214 is connected to each lower arm switching element T2, T
4, the emitter of T6 and the anodes of the diodes D2, D4, D6 are provided on a commonly connected bus.

In FIG. 4, reference numeral 200 denotes a high withstand voltage IC for driving a switching element of an inverter circuit; 201, an external power supply for supplying a drive voltage to the high withstand voltage IC 200;
2, 203 and 204 are diodes, 205, 206 and 2
07 is a capacitor, 215 is a constant voltage diode, b1,
b2, b3, b4, b5, b6, b7, b8, b9, b
10, b11 and b12 are circuit blocks inside the high voltage IC 200, b1 is an input buffer, b2, b3 and b
4 is a level shifter, b5, b6, and b7 are upper arm driver circuits for driving the upper arm switching elements T1, T3, and T5, respectively, and b8, b9, and b10 are lower arms for driving the lower arm switching elements T2, T4, and T6, respectively. The side driver circuit, b11 is an overcurrent detector, and b12 is an error signal generator.

Further, UPi, UNi, VPi, VNi,
WPi, WNi, UPo, VPo, WPo, UNo, V
No, WNo, VB1, VB2, VB3, VS1, VS
2, VS3, VS0, OC, Fo, VCC, VSS are input / output terminals of the high-voltage IC 200, and UPi, VPi,
WPi and UNi, VNi, and WNi are drive signal input terminals, respectively, and UPo, VPo, and WPo are upper arm switching element drive signal output terminals that output drive signals for upper arm switching elements T1, T3, and T5, respectively.
o, VNo, WNo are lower arm switching element drive signal output terminals for outputting drive signals of the lower arm switching elements T2, T4, T6, respectively, VB1, VB2, VB
3 is a floating power supply positive side input terminal, VS1, VS
2, VS3 is a floating power supply negative side input terminal and an upper arm switching element drive signal reference output terminal, VS0 is a lower arm switching element drive signal reference output terminal, OC is a current detection terminal, Fo is an error output terminal,
VCC and VSS are positive and negative power supply terminals, respectively.

In the configuration of the inverter device shown in FIG. 4, the same components as those of the inverter device shown in FIG. 22 are denoted by the same reference numerals, and redundant description will be omitted.

Here, as described in the first embodiment,
Generally, the minimum withstand voltage of each of the upper arm switching element drive signal reference output terminals VS1, VS2, and VS3 of the high withstand voltage IC 200 is about [(potential of the lower arm switching element drive signal reference output terminal VS0) -5] volts. . That is, the voltages V (VS1-VS0) and V (VS2-VS) between the upper arm switching element drive signal reference output terminals VS1, VS2, VS3 and the lower arm switching element drive signal reference output terminal VS0 of the high voltage IC 200.
0) and V (VS3-VS0) have a minimum rated withstand voltage of approximately -5V.

Therefore, in the second embodiment, as the clamp diodes 216, 217, and 218, although not particularly limited, for example, a general diode having an ON voltage of about 0.7 V to 2 V is used. Then, the upper arm switching element drive signal reference output terminals VS1, VS
2, VS3 and the lower arm switching element drive signal reference output terminal VS0, when a negative voltage is applied, the voltage between them becomes the clamp diodes 216, 217, 2
18 is clamped to the ON voltage of about 18, that is, about -0.7V to -2V.

Preferably, each clamp diode 2
16, 217 and 218 are provided immediately adjacent to the reference output terminals VS0 and VS1, VS2 and VS3 of the high voltage IC 200, and these terminals VS0 and VS1, VS2 and VS3 are provided.
It is preferable to keep the wiring length from the clamp diodes 216, 217, and 218 to as short as possible.

The operation of the inverter device having the configuration shown in FIG. 4 will be described. Upper arm switching element drive signal reference output terminals VS1, VS2, VS of high withstand voltage IC 200
3 and lower arm switching element drive signal reference output terminal V
Only when a negative voltage that may cause the IC 200 to be destroyed is applied between the terminals VS and S0, the clamp diodes 216, 217, and 218 are turned on, and their terminals VS
, VS2, VS3 and VS0 (VS1-
VS0), V (VS2-VS0), V (VS3-VS
0) is clamped to the ON voltage (approximately 0.7 V to 2 V). Therefore, the voltages V (VS1−VS0), V (V
S2-VS0) and V (VS3-VS0) are-
It is about 0.7V to -2V, and does not fall below the minimum rated withstand voltage -5V between the terminals VS1, VS2, VS3 and VS0 of the high withstand voltage IC 200.

As described above, according to the second embodiment, between the upper arm switching element drive signal reference output terminals VS1, VS2, and VS3 of the high breakdown voltage IC 200 and the lower arm switching element drive signal reference output terminal VS0. Between terminals when a negative voltage is applied to the terminal (VS1-VS)
0), V (VS2-VS0) and V (VS3-VS0) are about -0.7V to -2V, respectively.
00 can be prevented from falling below the minimum rated withstand voltage -5V between the terminals VS1, VS2, VS3 and VS0, so that the withstand voltage breakdown of the high withstand voltage IC 200 can be prevented.

As in the three-phase inverter device shown in FIG. 5, the anodes of the diodes D2, D4, and D6 are connected directly to the negative power supply terminal VSS without passing through the current detector 214, so that the switching of each lower arm is performed. In the inverter device shown in FIG. 23 in which only the emitters of the elements T2, T4, and T6 are connected to the current detector 214, the upper arm switching element drive signal reference output terminals VS1, VS2, and VS3 of the high withstand voltage IC 200 are also provided. Clamp diodes 216, 217, and 218 may be provided between the lower arm switching element drive signal reference output terminal VS0. Then, the voltage V (VS1-V1) between the terminals VS1, VS2, VS3 and VS0 of the high withstand voltage IC 200 is obtained.
VS0), V (VS2-VS0), V (VS3-VS
0) can be prevented from falling below the rated withstand voltage minimum value of -5 V, respectively, so that the withstand voltage breakdown of the high withstand voltage IC 200 can be prevented.

Further, like the three-phase inverter device shown in FIG. 6, in the inverter device shown in FIG. 24 in which the current detector is not provided, each upper arm switching element drive signal reference output of the high voltage IC 200 is also provided. Terminal VS
1, VS2, VS3 and the lower arm switching element drive signal reference output terminal VS0 can be provided with clamp diodes 216, 217, 218, respectively. Then, those terminals VS1, VS of the high voltage IC 200
2, the voltage V (VS1-VS0) between VS3 and VS0, V
(VS2−VS0) and V (VS3−VS0) can be prevented from falling below the minimum rated withstand voltage of −5V, respectively, so that the withstand voltage breakdown of the high withstand voltage IC 200 can be prevented.

(Embodiment 3) FIG. 7 is a schematic diagram showing an example of a single-phase inverter device to which the present invention is applied. The inverter device according to the third embodiment is different from the general inverter device shown in FIG. 18 in that an operational amplifier 111 and a resistor 112 for determining the gain of the operational amplifier 111 are used as signal transmitting means for transmitting the signal of the current detector 106 to the high-voltage IC 100. , 113 are connected to the operational amplifier 111, and the negative power supply terminal VSS and the lower arm switching element drive signal reference output terminal VS0 are connected to have the same potential, so that the upper arm switching element drive signal reference output terminal VS1 This prevents a negative voltage from being applied to the lower arm switching element drive signal reference output terminal VS0.

In FIG. 7, T1 and T2 are upper-arm switching elements and lower-arm switching elements, D1 and D2 are diodes connected in antiparallel to upper-arm switching element T1 and lower-arm switching element T2, respectively, and G1 and G2 are The gates of the upper arm switching element T1 and the lower arm switching element T2, 104 and 105 are resistors connected to the gates G1 and G2 of the upper arm switching element T1 and the lower arm switching element T2, respectively, 106 is a current detector, 107 Is the reactor as the load, 108
Is a DC power supply composed of a power supply body 108a and a capacitor 108b.

E1 and E0 are connection nodes on the emitter side of the upper arm switching element T1 and the lower arm switching element T2, respectively, and N1 is a current detector 1
06, the connection node on the opposite side of the connection node E0,
P is a power supply terminal for applying a positive power supply voltage to the inverter circuit, N is a power supply terminal for applying a negative power supply voltage to the inverter circuit, U is an output terminal of the inverter circuit, L1, L2, L
Reference numerals 3, L4, L5, and L6 denote reactors parasitic on the wiring portion, and I1, I2, and I3 denote currents flowing through the upper arm switching element T1, currents flowing through the diode D2, and currents flowing through the reactor 107, respectively. The current detector 106 is provided on a bus where the emitter of the lower arm switching element T2 and the anode of the diode D2 are commonly connected.

In FIG. 7, reference numeral 100 denotes a high withstand voltage IC for driving a switching element of an inverter circuit; 101, an external power supply for supplying a drive voltage to the high withstand voltage IC 100;
Is a diode, 103 is a capacitor, a1, a2, a
Reference numerals 3, a4, a5, and a6 denote circuit blocks inside the high withstand voltage IC 100, wherein a1 is an input buffer, a2 is a level shifter, a3 is an upper arm driver circuit for driving the upper arm switching element T1, and a4 is a lower arm switching element. A lower arm side driver circuit for driving T2, a5 is an overcurrent detector, and a6 is an error signal generator.

Also, UPi, UNi, UPo, UNo,
VB1, VS1, VS0, OC, Fo, VCC, VSS
Is an input / output terminal of the high voltage IC 100, UPi and UNi are drive signal input terminals, UPo is an upper arm switching element drive signal output terminal for outputting a drive signal of the upper arm switching element T1, and UNo is a lower arm switching element T2. VB1 is a floating power supply positive side input terminal, VS1 is a floating power supply negative side input terminal and an upper arm switching element drive signal reference output terminal, and VS0 is a lower arm switching terminal. An element drive signal reference output terminal, OC is a current detection terminal, Fo is an error output terminal, and VCC and VSS are positive-side and negative-side power supply terminals, respectively.

In the configuration of the inverter device shown in FIG. 7, the same components as those of the inverter device shown in FIG. 18 are denoted by the same reference numerals, and redundant description will be omitted.

The operational amplifier 111 has a negative power supply different from the high-voltage IC 100, and has a positive input terminal connected to a connection node E near the emitter of the lower arm switching element T2.
0, and its negative input terminal is connected to the connection node N1. The output terminal of the operational amplifier 111 has a high withstand voltage I
Overcurrent detector a5 via current detection terminal OC of C100
It is connected to the.

The current detection terminal OC is connected to the anode of a clamp diode 114 for preventing a negative voltage from being applied to the terminal OC. The cathode of the clamp diode 114 is connected to the ground point. Since the clamp diode 114 only clamps the output of the operational amplifier 111, it may be a small signal diode.

Preferably, the negative power supply terminal VSS of the high withstand voltage IC 100 and the lower arm switching element drive signal reference output terminal VS0 are connected immediately adjacent to the high withstand voltage IC 100.

The operation of the inverter having the configuration shown in FIG. 7 will be described. Normally, a voltage having a polarity indicated by “+” and “−” in FIG. 7, that is, a potential difference such that the connection node E0 is higher than the connection node N1 is generated in the current detector 106. As a result, a positive voltage is applied to the current detection terminal OC. When the current is cut off and a negative voltage is induced by a small wiring inductance as described in the above-described related art, the operational amplifier 111 has a negative voltage because the operational amplifier 111 has a negative voltage.
The operational amplifier 111 will not be destroyed within the negative voltage range. At this time, the negative voltage output from the operational amplifier 111 is applied to the current detection terminal OC of the high withstand voltage IC. However, since the potential of the current detection terminal OC is clamped by the clamp diode 114, the high withstand voltage I
C100 does not break.

As described above, according to the third embodiment, the output from current detector 106 is supplied to high-voltage IC 10
0, the negative power supply terminal V
Since the potential of SS and the lower arm switching element drive signal reference output terminal VS0 can be made equal, the current between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 is A negative voltage can be prevented from being applied by the wiring pattern of the detector 106, etc.
Can be prevented from breakdown.

Note that, as in the single-phase inverter device shown in FIG. 8, the anode of the diode D2 is not passed through the current detector 106, and only the emitter of the lower arm switching element T2 is connected to the current detector 106. In the inverter device having the configuration shown in FIG. 20 as well, the operational amplifier 111 and the operational amplifier 11 serve as signal transmitting means for transmitting the signal of the current detector 106 to the high voltage IC 100.
The resistors 112 and 113 that determine the gain of 1 are connected to the operational amplifier 1
11, the negative power supply terminal VSS and the lower arm switching element drive signal reference output terminal VS0 may be connected to have the same potential. By doing so, it is possible to prevent a negative voltage from being applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. be able to.

Further, as in the three-phase inverter device shown in FIG. 9, current is detected on a bus in which the emitters of the lower arm switching elements T2, T4, T6 and the anodes of the diodes D2, D4, D6 are commonly connected. Also in the inverter device having the configuration shown in FIG. 22 provided with the detector 214, the operational amplifier 111 and the resistors 112 and 113 for determining the gain of the operational amplifier 111 are used as signal transmitting means for transmitting the signal of the current detector 214 to the high voltage IC 200. It is also possible to connect the negative side power supply terminal VSS and the lower arm switching element drive signal reference output terminal VS0 so that they have the same potential.

The current detection terminal OC is clamped by the clamp diode 114. By doing so, it is possible to prevent a negative voltage from being applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. be able to.

Further, unlike the three-phase inverter device shown in FIG. 10, the anodes of the diodes D2, D4 and D6 are not connected to the current detector 214, but only the emitters of the lower arm switching elements T2, T4 and T6. The current detector 2
Also, in the inverter device having the configuration shown in FIG.
The operational amplifier 111 and a resistor 112 for determining the gain of the operational amplifier 111
113 may be connected to the operational amplifier 111, and the negative power supply terminal VSS and the lower arm switching element drive signal reference output terminal VS0 may be connected to have the same potential.

The current detection terminal OC is clamped by the clamp diode 114. By doing so, it is possible to prevent a negative voltage from being applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0. be able to.

Further, in the third embodiment, the outputs of the current detectors 106 and 214 are connected to the high-voltage ICs 100 and 200.
Although the operational amplifier 111 is used as a means for transmitting the signal to the amplifier, the same effect can be obtained by using an insulating amplifier, an analog photocoupler, or the like instead of the operational amplifier 111.

(Embodiment 4) FIG. 11 is a schematic diagram showing an example of a chip arrangement of an inverter circuit in a single-phase inverter device according to the present invention. This inverter circuit includes a chip of the upper arm switching element T1 (hereinafter, referred to as an upper arm switching element chip) 301 and a chip of a diode D1 connected in anti-parallel to the upper arm switching element T1 (hereinafter, referred to as an upper arm diode chip). 302, chip of lower arm switching element T2 (hereinafter referred to as lower arm switching element chip) 3
03 and a diode D2 chip 304 (hereinafter referred to as a lower arm diode chip) connected in antiparallel to the lower arm switching element T2, and a bonding pad (hereinafter referred to as a main pad) serving as a power supply terminal P for applying a positive power supply voltage to the inverter circuit. In the fourth embodiment, a bonding pad P), a bonding pad serving as a power supply terminal N for applying a negative power supply voltage to the inverter circuit (hereinafter also referred to as a bonding pad N), and an output terminal U of the inverter circuit. The structure includes a bonding pad (hereinafter, also referred to as a bonding pad U).

Upper arm switching element chip 301
Is provided with a gate 301G (a region surrounded by a square) on a part of its surface, and the chip surface other than the region of the gate 301G is formed to be a collector 301C. The back surface of the upper arm switching element chip 301 is an emitter 301E. The collector 301C of the upper arm switching element T1 is in direct contact with the bonding pad P.

An emitter 301E of the upper arm switching element T1 is electrically connected to the bonding pad U via a wire W1. Although not particularly limited, in FIG. 11, the wire W1 is a wire bundle including three wires. Gate 301G of upper arm switching element T1
Is a high withstand voltage IC 100 via a bonding wire W2.
It is electrically connected to the upper arm switching element drive signal output terminal UPo (omitted in FIG. 11).

The upper arm diode chip 302 is formed so that the front surface is the anode 302A and the back surface is the cathode 302C. Cathode 3 of diode D1
02C is in direct contact with the bonding pad P, and the anode 302A is electrically connected to the bonding pad U via a wire W3. Although not particularly limited, FIG.
In 1, the wire W3 is a wire bundle composed of three wires.

Lower Arm Switching Element Chip 303
Is provided with a gate 303G (a region surrounded by a square) on a part of its surface, and the chip surface other than the region of the gate 303G is formed to be a collector 303C. The back surface of the lower arm switching element chip 303 is an emitter 303E. The collector 303C of the lower arm switching element T2 is in direct contact with the bonding pad U.

An emitter 303E of the lower arm switching element T2 is electrically connected to the bonding pad N via a wire W4. Although not particularly limited, in FIG. 11, the wire W4 is a wire bundle including three wires. Gate 303G of lower arm switching element T2
Is a high withstand voltage IC 100 via a bonding wire W5.
It is electrically connected to a lower arm switching element drive signal output terminal UNo (omitted in FIG. 11).

The lower arm diode chip 304 is formed so that the front surface is the anode 304A and the back surface is the cathode 304C. Cathode 3 of diode D2
04C is in direct contact with the bonding pad U, and the anode 304A is electrically connected to the bonding pad N via a wire W6. Although not particularly limited, FIG.
In 1, the wire W6 is a wire bundle composed of three wires.

The anode 304A of the lower arm diode chip 304 is electrically connected to the lower arm switching element drive signal reference output terminal VS0 of the high voltage IC 100 (not shown) via the bonding wire W7. Near the lower arm diode chip 304 of the bonding pad U, an upper arm switching element drive signal reference output terminal VS1
Is electrically connected to the bonding wire W7.

FIG. 12 is a circuit diagram of the inverter circuit having the configuration shown in FIG. In FIG. 12, the hatched wiring portions are the P, U, and N bonding pads, and the wiring portions indicated by solid lines are bonding wires. As is apparent from FIG. 11, according to the configuration shown in FIG. 11, the bonding wire W7 connected to the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 100 (not shown) is drawn out from the anode 304A of the diode D2. And high withstand voltage IC 100 (not shown) from near the cathode 304C of the diode D2.
Upper arm switching element drive signal reference output terminal VS
It can be seen that the bonding wire W8 connected to No. 1 is pulled out.

In FIGS. 11 and 12, wiring portions indicated by broken lines with reference numerals X1 and X0 are respectively connected to upper and lower arm switching element drive signal reference output terminals VS1 and VS0 in a conventional inverter circuit. Bonding wire provided to

As described above, according to the fourth embodiment, the bonding wire W7 is connected to the anode 304A of the diode D2, and the bonding wire W8 is connected near the cathode 304C of the diode D2. When the current detector is not provided, the inductances La and L caused by the conventional wiring pattern are obtained.
b (see FIG. 12), the negative voltage that can be applied between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 is substantially the ON voltage of the diode D2. VF (generally, at most about 3 V), so that the rated withstand voltage minimum value between the upper arm switching element drive signal reference output terminal VS1 and the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 100. -5
The application of a negative voltage lower than V is prevented, and the breakdown voltage of the high breakdown voltage IC 100 can be prevented.

According to the fourth embodiment, when current detector 106 is provided, upper arm switching element drive signal reference output terminal VS0 and lower arm switching element drive signal reference output terminal VS0 when high voltage IC 100 is provided. A negative voltage due to various factors as described in the related art is generated and applied in addition to the ON voltage VF of the diode D2, and the inductances La and Lb ( The voltage generated by the current detector 106 is lower between the upper and lower arm switching element drive signal reference output terminals VS1 and VS0, so that the breakdown voltage of the high breakdown voltage IC 100 is reduced. Can be prevented.

(Embodiment 5) FIG. 13 is a schematic diagram showing an example of a chip arrangement of an inverter circuit when a current detector is not provided in a three-phase inverter device according to the present invention.

This inverter circuit comprises upper arm switching element chips T1, T3, T5 (hereinafter referred to as upper arm switching element chips) 401, 402, 4
03 and upper arm switching elements T1, T3, T5
D1, D3, D connected in anti-parallel to
5 (hereinafter, referred to as upper arm diode chips) 407, 408, 409, lower arm switching elements T2, T4, T6 (hereinafter, referred to as lower arm switching element chips) 404, 405, 406, and lower Each chip of diodes D2, D4, and D6 connected in antiparallel to arm switching elements T2, T4, and T6 (hereinafter, referred to as lower arm diode chip) 4
10, 411, 412, a bonding pad serving as a power supply terminal P for applying a positive power supply voltage to the inverter circuit (hereinafter referred to as a bonding pad P in the fifth embodiment), and a negative power supply voltage applied to the inverter circuit. Bonding pads serving as power supply terminals N (hereinafter also referred to as bonding pads N), and bonding pads serving as output terminals U, V and W of the inverter circuit (hereinafter also referred to as bonding pads U, V and W, respectively). And a dedicated bonding pad (hereinafter referred to as a VS0 bonding pad) 420 to which a bonding wire W10 connected to the lower arm switching element drive signal reference output terminal VS0 is electrically connected.

The upper arm switching element chip 401,
402 and 403 each have a gate 4 on a part of its surface.
01G, 402G, and 403G (regions surrounded by squares) are provided.
The chip surface other than the area of G is the collector 401 respectively.
C, 402C, and 403C.
Each upper arm switching element chip 401, 402, 4
03 have emitters 401E, 402E, 4
03E. Each upper arm switching element T
Collectors 401C, 402C, 403 of 1, T3, T5
C is in direct contact with the bonding pad P. Emitter 401 of each upper arm switching element T1, T3, T5
E, 402E, and 403E are electrically connected to the bonding pad U via wires W11, W12, and W13, respectively.

Although not particularly limited, in FIG.
Each of 1, W12, and W13 is a wire bundle including three wires. Each upper arm switching element T
Gates 401G, 402G, 403G of 1, T3, T5
Are electrically connected to upper arm switching element drive signal output terminals UPo, VPo, and WPo via a bonding wire (not shown) respectively.

Upper arm diode chips 407, 40
8, 409 have anodes 407A, 4
08A and 409A, each with a cathode 407
C, 408C, and 409C.
Cathodes 407C, 4 of each diode D1, D3, D5
08C and 409C are in direct contact with the bonding pad P, and the anodes 407A, 408A and 409A are electrically connected to the bonding pad U via wires W14, W15 and W16. Although not particularly limited, FIG.
Each of the wires W14, 15, 16 is a wire bundle composed of three wires.

The lower arm switching element chip 404,
405 and 406 are gates 40 on a part of each surface.
4G, 405G, and 406G (regions surrounded by squares) are provided, and the respective gates 404G, 405G, and 406G are provided.
The chip surfaces other than the area of the collector are the collectors 404C,
405C and 406C are formed. Each lower arm switching element chip 404, 405, 406
Are the emitters 404E, 405E, and 406, respectively.
E.

Each lower arm switching element T2, T4,
The collectors 404C, 405C, and 406C of T6 are in direct contact with the bonding pad U. Emitter 404E, 405 of each lower arm switching element T2, T4, T6
E and 406E are electrically connected to the bonding pad N via wires W17, W18 and W19, respectively. Although not particularly limited, the wires W17 and W1 in FIG.
8 and W19 are wire bundles composed of three wires. Each lower arm switching element T2, T4
The gates 404G, 405G, and 406G of T6 are each connected to a high withstand voltage IC
00 (not shown) are electrically connected to lower arm switching element drive signal output terminals UNo, VNo, WNo.

Lower arm diode chips 410 and 41
1, 412 have anodes 410A, 4
11A and 412A each have a cathode 410
C, 411C, and 412C.
Cathode 410C, 4 of each diode D2, D4, D6
11C and 412C are in direct contact with the bonding pad U, and the anodes 410A, 411A and 412A are electrically connected to the bonding pad N via wires W20, W21 and W22. Although not particularly limited, FIG.
Each of the wires W20, 21, 22 is a wire bundle composed of three wires.

Each lower arm diode chip 41
0, 411, 412 anodes 410A, 411A, 4
12A is a bonding wire W23, 24,
25, it is electrically connected to the VS0 bonding pad 420.

Further, each of the bonding pads U, V, W
Are the lower arm diode chips 410 and 41, respectively.
1,412, the bonding wires W26, W2
7, pattern-formed wiring portion 42 via W28
1, 422, 423. The wiring portions 421, 422, and 423 are connected to the high-voltage IC 200 via bonding wires W29, 30, 31, respectively.
(Not shown) are electrically connected to the upper arm switching element drive signal reference output terminals VS1, VS2, VS3.

As described above, according to the fifth embodiment, the high breakdown voltage IC2 is connected to the cathodes 410C, 411C, 412C of the diodes D2, D4, D6 of the lower arm.
The main current does not flow in the wiring path leading to the upper arm switching element drive signal reference output terminals VS1, VS2, VS3 of No. 00, and the anodes 410A, 411A, 41 of the diodes D2, D4, D6.
Since a main current does not flow through the wiring path from 2A to the lower arm switching element drive signal reference output terminal VS0 of the high breakdown voltage IC 200, the upper and lower arm switching element drive signal reference output terminals VS1,
A voltage V (V applied between VS2, VS3 and VS0)
S1-VS0), V (VS2-VS0), V (VS3-
VS0) is the ON voltage V of each diode D2, D4, D6.
Only F, it is possible to prevent high voltage breakdown of the high breakdown voltage IC 200.

According to the fifth embodiment, when current detector 214 is provided, each upper arm switching element drive signal reference output terminal VS1,
Diodes D2, D4, D4 are connected between VS2, VS3 and the lower arm switching element drive signal reference output terminal VS0.
In addition to the on-state voltage VF of No. 6, a negative voltage is generated and applied due to various factors as described in the above-mentioned prior art, but the voltage generated by the inductance generated by the conventional wiring pattern is reduced. , Upper and lower arm switching element drive signal reference output terminals VS1, VS
2, if the negative voltage generated by the current detector 214 between VS3 and VS0 is low, it is possible to prevent breakdown of the high breakdown voltage IC 200.

(Embodiment 6) Next, Embodiment 6 of the present invention will be described. The feature of the sixth embodiment is that, of the plurality of switching elements and diodes used in the inverter circuit, only the diode connected in anti-parallel to the lower arm switching element has a larger current capacity than other switching elements and diodes. Is to use. That is, when the current capacity of the lower arm diode increases, the ON voltage VF of the diode decreases, and the negative voltage applied between the upper and lower arm switching element drive signal reference output terminals of the high withstand voltage IC decreases. is there.

FIG. 14 shows an example of the voltage VF / current IF characteristics of the diode used in the inverter device. Generally, when the output is short-circuited, the current is 300
A may flow. In such a case, as shown in FIG. 14, a diode having a current capacity of 50 A has an on-state voltage VF of 5 V, and the diode alone reaches the rated voltage of the high breakdown voltage IC. However, for example, in a diode having a current capacity of 75 A, the ON voltage is only about 3.5 V, so that the high breakdown voltage IC is not destroyed by itself. In the conventional inverter circuit, the diode in the lower arm has the same current capacity as the other switching elements and diodes.

Therefore, according to the seventh embodiment, by using only the lower arm diode having a large current capacity, the ON voltage VF of the lower arm diode, which is one of the causes of destruction of the high breakdown voltage IC, is suppressed to be low. Therefore, the margin for the breakdown voltage of the high breakdown voltage IC is increased, and the high breakdown voltage IC is hardly broken.

It is needless to say that the current capacity of the lower arm diode is not limited to 75A.

[0170]

As described above, according to the inverter device of the present invention, in the single-phase inverter device, the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output of the high withstand voltage IC. Since the negative voltage applied between the terminals can be prevented from falling below the minimum rated withstand voltage between the terminals, the high withstand voltage I
C withstand voltage breakdown can be prevented.

According to the inverter device of the next invention, in the three-phase inverter device, each of the three upper arm switching element drive signal reference output terminals and the lower arm switching element drive signal reference output terminal of the high withstand voltage IC is provided. Since the applied negative voltage can be prevented from falling below the minimum rated withstand voltage between the terminals, the withstand voltage breakdown of the high withstand voltage IC can be prevented.

According to the inverter device of the next invention, in addition to the above effects, since there is no need to change the design of the high breakdown voltage IC, it is possible to prevent the breakdown of the high breakdown voltage IC at almost the same cost as the conventional one. In addition to this, the present invention can be applied to an inverter device using an existing high-withstand voltage IC, and the effect of preventing destruction of the high-withstand voltage IC of the existing device can be obtained.

According to the inverter device of the next invention, the means for transmitting the output from the current detector to the high withstand voltage IC is provided, so that the negative power supply terminal and the lower arm switching element drive signal reference output terminal are connected. Since the potentials can be equalized, a negative voltage is prevented from being applied between the upper arm switching element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal by a wiring pattern of a current detector or the like. Therefore, the breakdown voltage of the high breakdown voltage IC can be prevented.

According to the inverter device of the next invention, in addition to the above-mentioned effects, since there is no need to change the design of the high withstand voltage IC, it is possible to prevent the destruction of the high withstand voltage IC at almost the same cost as the conventional one. In addition to this, the present invention can be applied to an inverter device using an existing high-withstand voltage IC, and the effect of preventing destruction of the high-withstand voltage IC of the existing device can be obtained.

According to the inverter device of the next invention, in the single-phase inverter device, when the current detector is not provided, the voltage generated by the inductance generated by the conventional wiring pattern is eliminated, and the upper arm switching element Since the negative voltage that can be applied between the drive signal reference output terminal and the lower arm switching element drive signal reference output terminal is substantially only the ON voltage of the lower arm diode, the upper arm switching element drive signal reference output terminal and the lower arm The application of a negative voltage lower than the minimum rated withstand voltage between the switching element drive signal reference output terminal and the switching element drive signal reference output terminal is prevented, and the withstand voltage breakdown of the high withstand voltage IC can be prevented. In the case where the current detector is provided, if the negative voltage generated by the current detector between the upper and lower arm switching element drive signal reference output terminals is low, the breakdown voltage of the high breakdown voltage IC can be prevented.

According to the inverter device of the next invention, in the three-phase inverter device, each wiring path from each cathode of the three diodes of the lower arm to each upper arm switching element drive signal reference output terminal of the high voltage IC. The main current does not flow, and the main wiring is also provided to each wiring path from each anode of the three diodes of the lower arm to each lower arm switching element drive signal reference output terminal of the high voltage IC. Since the current does not flow, if no current detector is provided, a negative voltage that can be applied between the three upper arm switching element drive signal reference output terminals and the lower arm switching element drive signal reference output terminal is provided. Since the voltages are only the ON voltages of the three lower-arm diodes, respectively, the three upper-arm switches It is possible to prevent a negative voltage lower than the minimum rated withstand voltage from being applied between the element drive signal reference output terminal and the lower arm switching element drive signal reference output terminal, thereby preventing the breakdown voltage of the high breakdown voltage IC. . In the case where the current detector is provided, if the respective negative voltages generated by the current detector between the upper and lower arm switching element drive signal reference output terminals are low, the breakdown voltage of the high breakdown voltage IC can be prevented.

According to the inverter device of the next invention, by using only the lower arm diode having a large current capacity, the ON voltage of the lower arm diode, which is one of the causes of destruction of the high breakdown voltage IC, is suppressed to be low. Therefore, the margin for the breakdown voltage of the high breakdown voltage IC is increased, and the high breakdown voltage IC is hardly broken.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment in which the present invention is applied to a high-voltage IC driven single-phase inverter device.

FIG. 2 is a circuit diagram showing another example of the first embodiment in which the present invention is applied to a high-voltage IC driven single-phase inverter device.

FIG. 3 is a circuit diagram showing still another example of the first embodiment in which the present invention is applied to a high-voltage IC driving single-phase inverter device.

FIG. 4 is a circuit diagram showing a second embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 5 is a circuit diagram showing another example of the second embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 6 is a circuit diagram showing still another example of the second embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 7 is a circuit diagram showing a third embodiment in which the present invention is applied to a high-voltage IC driven single-phase inverter device.

FIG. 8 is a circuit diagram showing another example of the third embodiment in which the present invention is applied to a high-voltage IC driven single-phase inverter device.

FIG. 9 is a circuit diagram showing a third embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 10 is a circuit diagram showing another example of the third embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 11 is a schematic diagram showing a fourth embodiment in which the present invention is applied to a high-voltage IC driven single-phase inverter device.

FIG. 12 is a circuit diagram showing a fourth embodiment.

FIG. 13 is a schematic diagram showing a fifth embodiment in which the present invention is applied to a high withstand voltage IC driven three-phase inverter device.

FIG. 14 is a graph showing an example of a voltage VF / current IF characteristic of a diode for describing Embodiment 6 of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a general three-phase inverter circuit.

FIG. 16 is a circuit diagram showing a configuration of a general three-phase inverter circuit.

FIG. 17 is a circuit diagram showing a configuration of a general three-phase inverter circuit.

FIG. 18 is a circuit diagram showing a conventional single-phase inverter device.

FIG. 19 is a timing chart showing operation timing of the conventional single-phase inverter device.

FIG. 20 is a circuit diagram showing a conventional single-phase inverter device.

FIG. 21 is a circuit diagram showing a conventional single-phase inverter device.

FIG. 22 is a circuit diagram showing a conventional three-phase inverter device.

FIG. 23 is a circuit diagram showing a conventional three-phase inverter device.

FIG. 24 is a circuit diagram showing a conventional three-phase inverter device.

[Explanation of symbols]

D1, D3, D5 Upper arm diode, D2, D
4, D6 Lower arm diode, VS1, VS2, V
S3 Upper arm switching element drive signal reference output terminal, VS0 Lower arm switching element drive signal reference output terminal, T1, T3, T5 Upper arm switching element, T2, T4, T6 Lower arm switching element, 1
00, 200 High voltage IC, 106, 214 Current detector, 108 DC power supply, 110, 216, 217, 21
8 Clamp diode, 111 operational amplifier (transmission means), 112, 113 resistance (transmission means), 420 V
Bonding pad for S0

Claims (8)

[Claims] 1. An upper arm section comprising an upper arm switching element and a diode connected in antiparallel to each other and a lower arm section comprising a lower arm switching element and a diode connected in antiparallel to each other are connected in series,
A single-phase inverter circuit having one inverter section connectable between the positive and negative electrodes of the DC power supply; a high-voltage IC driving the switching element of the upper arm and the switching element of the lower arm, respectively; A cathode is connected to an upper arm switching element drive signal reference output terminal of the breakdown voltage IC, which outputs a reference potential of the drive signal of the upper arm switching element, and a reference potential of the drive signal of the lower arm switching element is set to An inverter device comprising: a clamp diode having an anode connected to a lower arm switching element drive signal reference output terminal for outputting. 2. An upper arm section comprising an upper-arm switching element and a diode connected in anti-parallel to each other and a lower arm section comprising a lower-arm switching element and a diode connected in anti-parallel to each other are connected in series.
A three-phase inverter circuit having three inverter sections connectable between the positive and negative electrodes of a DC power supply; a high-withstand voltage IC for driving the switching element of the upper arm and the switching element of the lower arm; Cathodes are respectively connected to three upper arm switching element drive signal reference output terminals of the breakdown voltage IC that output a potential serving as a reference of the drive signal of the upper arm switching element. An inverter device comprising: three clamp diodes each having an anode connected to a lower arm switching element drive signal reference output terminal that outputs a potential. 3. The inverter device according to claim 1, wherein the clamp diode is externally attached to the high withstand voltage IC. 4. An upper arm section comprising an upper arm switching element and a diode connected in antiparallel to each other and a lower arm section comprising a lower arm switching element and a diode connected in antiparallel to each other in series,
An inverter circuit having at least one inverter unit connectable between the positive and negative electrodes of the DC power supply; a high-voltage IC driving the upper-arm switching element and the lower-arm switching element, respectively; Current detecting means for detecting an amount of current flowing through the high voltage IC; and a transmitting means which operates by an independent power supply different from a driving power supply for the high voltage IC and transmits a signal output from the current detecting means to the high voltage IC. And an inverter device comprising: 5. The inverter device according to claim 4, wherein said transmission means is constituted by an operational amplifier, and is externally attached to said high withstand voltage IC. 6. An upper arm section comprising an upper arm switching element and a diode connected in antiparallel to each other and a lower arm section comprising a lower arm switching element and a diode connected in antiparallel to each other, and connected in series;
And a single-phase inverter circuit having one inverter unit that can be connected between the positive and negative electrodes of the DC power supply; and a high-withstand voltage IC for driving the switching element of the upper arm and the switching element of the lower arm, respectively. The other end of the wiring, one end of which is connected to the upper arm switching element drive signal reference output terminal for outputting a potential serving as a reference of the drive signal of the upper arm switching element of the high breakdown voltage IC, is located near the cathode of the lower arm diode. And the other end of a wire having one end connected to a lower arm switching element drive signal reference output terminal for outputting a potential serving as a reference of a drive signal of the lower arm switching element is connected to an anode of a diode of the lower arm. An inverter device characterized in that: 7. An upper arm portion including an upper arm switching element and a diode connected in antiparallel to each other and a lower arm portion including a lower arm switching element and a diode connected in antiparallel to each other are connected in series,
A three-phase inverter circuit having three inverter sections connectable between the positive and negative electrodes of a DC power supply; a high-withstand voltage IC for driving the switching element of the upper arm and the switching element of the lower arm; A dedicated bonding pad connected to the other end of the wiring, one end of which is connected to the lower arm switching element drive signal reference output terminal for outputting a potential serving as a reference of the drive signal of the arm switching element; The other ends of three wires each having one end connected to three upper arm switching element drive signal reference output terminals for outputting a potential serving as a reference for the drive signal of the upper arm switching element are connected to the three lower arm diodes. Connected near the cathode of
An inverter device, wherein the bonding pad for the lower arm switching element drive signal reference output terminal and the anodes of the diodes of the same three lower arms are electrically connected by wires. 8. An upper arm section comprising an upper arm switching element and a diode connected in antiparallel to each other and a lower arm section comprising a lower arm switching element and a diode connected in antiparallel to each other, and connected in series.
And an inverter circuit having at least one inverter unit that can be connected between the positive and negative electrodes of the DC power supply; and a high withstand voltage IC for driving the switching element of the upper arm and the switching element of the lower arm, respectively. An inverter device, wherein a diode having a larger current capacity than a switching element and an upper arm diode is used as the lower arm diode.