JPH104163A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH104163A
JPH104163A JP8156903A JP15690396A JPH104163A JP H104163 A JPH104163 A JP H104163A JP 8156903 A JP8156903 A JP 8156903A JP 15690396 A JP15690396 A JP 15690396A JP H104163 A JPH104163 A JP H104163A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor package
semiconductor device
cooling fluid
dimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8156903A
Other languages
Japanese (ja)
Other versions
JP2792507B2 (en
Inventor
Kazuyuki Mitsukubo
和幸 三窪
Naoharu Senba
直治 仙波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8156903A priority Critical patent/JP2792507B2/en
Publication of JPH104163A publication Critical patent/JPH104163A/en
Application granted granted Critical
Publication of JP2792507B2 publication Critical patent/JP2792507B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves heat dissipation of a high-speed high-frequency semiconductor package and a three dimensional semiconductor package and is applicable under the equipment conditions wherein the wind speed in forced air cooling is limited. SOLUTION: On a high density mounting board 1, a high-speed high-frequency semiconductor package 2 and a plurality of three dimensional semiconductor packages 3 are mounted. The semiconductor packages 2 and 3 on the high density mounting board 1 are covered with an air duct 4, the local flow speed near the three dimensional semiconductor package 3 mounted under the wind is increased, and heat transmission is efficiently promoted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高速高周波用半導
体チップと複数のメモリー用半導体チップを高密度に三
次元搭載した半導体装置に関する。
The present invention relates to a semiconductor device in which a high-speed high-frequency semiconductor chip and a plurality of memory semiconductor chips are three-dimensionally mounted at high density.

【0002】[0002]

【従来の技術】図5は、従来の半導体装置を説明する斜
視図、図6(a)は、図5のA部拡大正面図、図6
(b)は、図5のA部拡大側面図である。
2. Description of the Related Art FIG. 5 is a perspective view for explaining a conventional semiconductor device, FIG. 6A is an enlarged front view of a portion A in FIG.
FIG. 6B is an enlarged side view of a portion A in FIG. 5.

【0003】図において、電気特性上有効な理由から高
密度実装基板1の中央部に高速高周波用半導体パッケー
ジ2が搭載される。半導体パッケージ2は、高速高周波
用半導体チップとキャリア基板を金属バンプ接合し、該
半導体チップ裏面に接着剤を介し放熱フィンを接合され
た構造のものである。
In FIG. 1, a high-speed and high-frequency semiconductor package 2 is mounted at the center of a high-density mounting substrate 1 because of its electrical characteristics. The semiconductor package 2 has a structure in which a semiconductor chip for high-speed and high-frequency waves and a carrier substrate are bonded by metal bumps, and radiation fins are bonded to the back surface of the semiconductor chip via an adhesive.

【0004】また基板1の周辺には、複数の三次元半導
体パッケージ3が搭載される。三次元半導体パッケージ
3は、キャリア基板20にメモリー半導体チップ21を
金属バンプ22aで接合した半導体パッケージと、該半
導体パッケージと同構成の半導体パッケージ同士を金属
バンプ22bで接合して立体的に積み上げた構造のもの
であった。
[0004] A plurality of three-dimensional semiconductor packages 3 are mounted around the substrate 1. The three-dimensional semiconductor package 3 has a structure in which a semiconductor package in which a memory semiconductor chip 21 is bonded to a carrier substrate 20 by metal bumps 22a and a semiconductor package having the same configuration as the semiconductor package is bonded in three dimensions by metal bumps 22b. It was.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の半導体
装置は、強制対流冷却の風速が制約される環境下におい
て、半導体チップより発生する熱の放散性が悪く、動作
時のチップジャンクション温度は許容値以上となるとい
う問題があった。
In the above-mentioned conventional semiconductor device, in an environment where the wind speed of forced convection cooling is restricted, the heat generated from the semiconductor chip is poorly dissipated, and the chip junction temperature during operation is allowed. There was a problem that it was more than the value.

【0006】その第1の理由は、特に高速高周波用半導
体パッケージの後に搭載される三次元半導体パッケージ
ブロック列は、強制対流冷却時において風下となること
から、風上ブロック列の放熱の影響を受け、チップジャ
ンクション温度が最大となるためである。
The first reason is that a three-dimensional semiconductor package block row mounted particularly after a high-speed high-frequency semiconductor package is leeward during forced convection cooling, and is thus affected by heat radiation from the windward block row. This is because the chip junction temperature becomes maximum.

【0007】また第2の理由は、三次元半導体パッケー
ジの多段接続によって熱放散性は、急激に低下し、特に
上下に挾まれるチップジャンクション温度が最大となる
ためである。
The second reason is that the heat dissipation is rapidly reduced by the multi-stage connection of the three-dimensional semiconductor package, and the temperature of the chip junction sandwiched between the upper and lower parts is particularly maximized.

【0008】本発明の目的は、機器小型化,騒音等で強
制対流冷却時の風速が0.5m/s程度に制約されるパ
ソコンなどパーソナル機器に適用できる放熱性能に優れ
た半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device having excellent heat radiation performance applicable to personal equipment such as a personal computer in which the wind speed at the time of forced convection cooling is restricted to about 0.5 m / s due to downsizing of equipment and noise. It is in.

【0009】[0009]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、風洞を有し、高速高周
波用半導体パッケージの周囲に複数の三次元半導体パッ
ケージを搭載した半導体装置であって、風洞は、前記高
速高周波用半導体パッケージ及び三次元半導体パッケー
ジを覆い、両パッケージに対して冷却流体を強制的に導
入するものである。
In order to achieve the above object, a semiconductor device according to the present invention has a wind tunnel, and has a plurality of three-dimensional semiconductor packages mounted around a high-speed and high-frequency semiconductor package. The wind tunnel covers the high-speed and high-frequency semiconductor package and the three-dimensional semiconductor package, and forcibly introduces a cooling fluid into both packages.

【0010】また前記風洞は、冷却流体入口側よりも冷
却流体出口側の流路面積が狭くなっているものである。
In the wind tunnel, the flow passage area on the cooling fluid outlet side is smaller than that on the cooling fluid inlet side.

【0011】また前記風洞は、各パッケージに対して脱
着可能である。
Further, the wind tunnel is detachable from each package.

【0012】また前記三次元半導体パッケージは、キャ
リア基板と半導体チップが金属バンプで接合された半導
体パッケージと、該半導体パッケージと同一構成の半導
体パッケージ同士を金属バンプで接合して立体的に積み
上げたものであり、該三次元半導体パッケージの最上段
のキャリア基板裏面に形成されたグランド電位導体パタ
ーン上に接着剤により接合された放熱フィンを備え、前
記グランド電位導体パターンは、キャリア基板と半導体
チップのグランド電位のみ選択し、熱的及び電気的に結
合されたものである。
Further, the three-dimensional semiconductor package is formed by stacking a semiconductor package in which a carrier substrate and a semiconductor chip are joined by metal bumps and a semiconductor package having the same configuration as the semiconductor package by joining with metal bumps. A radiation fin joined by an adhesive to a ground potential conductor pattern formed on the back surface of the uppermost carrier substrate of the three-dimensional semiconductor package, wherein the ground potential conductor pattern comprises a ground between the carrier substrate and the semiconductor chip. Only the potential is selected and thermally and electrically coupled.

【0013】また前記放熱フィンは、強制対流冷却流体
の風向と同一となるように少なくとも2種類有するもの
である。
The heat radiation fins have at least two kinds of radiation fins so as to have the same wind direction as the forced convection cooling fluid.

【0014】また前記三次元半導体パッケージを構成す
る複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備えたものである。
Further, a gap is provided on the back surface of each of the plurality of semiconductor chips constituting the three-dimensional semiconductor package, and a heat sink is provided in the gap.

【0015】また前記三次元半導体パッケージを構成す
る複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備え、該放熱板の先端は、放熱フ
ィンの側面壁に接着剤により接合されたものである。
Further, a gap is provided on the back surface of each of the plurality of semiconductor chips constituting the three-dimensional semiconductor package, and a heat radiating plate is provided in the gap. It has been joined.

【0016】また前記三次元半導体パッケージを構成す
る複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備え、該放熱板の先端は周囲冷却
流体中に突出しているものである。
Further, a gap is provided on the back surface of each of the plurality of semiconductor chips constituting the three-dimensional semiconductor package, and a heat sink is provided in the gap, and a tip of the heat sink projects into the surrounding cooling fluid. is there.

【0017】[0017]

【作用】半導体装置に搭載された半導体チップより発生
する熱は、高密度実装基板全体を覆う傾斜型風洞を備え
ることで特に風下に搭載された三次元半導体パッケージ
ブロック列の熱伝達が促進される。
The heat generated by the semiconductor chip mounted on the semiconductor device is provided with an inclined wind tunnel that covers the entire high-density mounting substrate, so that the heat transfer particularly to the three-dimensional semiconductor package block row mounted leeward is promoted. .

【0018】また、三次元半導体パッケージに設けた、
半導体チップ,キャリア基板から放熱フィンに通じるグ
ランド電位の放熱パスと、半導体チップ裏面から放熱板
に通じる放熱パスを設けることで周囲冷却流体中に効率
良く熱放散できる。
The three-dimensional semiconductor package further comprises:
By providing a heat-dissipating path of the ground potential from the semiconductor chip and the carrier substrate to the heat-dissipating fins and a heat-dissipating path from the back of the semiconductor chip to the heatsink, heat can be efficiently dissipated in the surrounding cooling fluid.

【0019】本発明によれば、強制対流冷却時の風速が
制約されるパソコンなどパーソナル機器環境下でも動作
時のチップジャンクション温度を許容値以下とする半導
体装置が可能となる。
According to the present invention, it is possible to provide a semiconductor device in which the chip junction temperature during operation is not more than an allowable value even in a personal device environment such as a personal computer in which the wind speed during forced convection cooling is restricted.

【0020】[0020]

【発明の実施の形態】以下、本発明の実施形態を図によ
り説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0021】(実施形態1)図1及び図2は、本発明の
実施形態1を示す構成図である。
(Embodiment 1) FIGS. 1 and 2 are configuration diagrams showing Embodiment 1 of the present invention.

【0022】電気特性上、実装基板上に搭載する半導体
チップ間の伝搬時間が高速動作に大きな役割を占めるこ
とから、図1に示すように高密度実装基板1において、
高速高周波用半導体パッケージ2を中心として周辺に三
次元半導体パッケージ3を配置し、かつ三次元半導体パ
ッケージ3を高速高周波用半導体パッケージ2に可能な
限り近付けて高密度搭載する。この場合、単位面積当た
りの発熱密度は急激に上昇するため、最適な放熱対策が
必要となる。
In terms of electrical characteristics, the propagation time between semiconductor chips mounted on a mounting board plays a large role in high-speed operation. Therefore, as shown in FIG.
The three-dimensional semiconductor package 3 is arranged around the high-speed and high-frequency semiconductor package 2 as a center, and the three-dimensional semiconductor package 3 is mounted as close as possible to the high-speed and high-frequency semiconductor package 2 with high density. In this case, since the heat generation density per unit area rises sharply, optimal heat dissipation measures are required.

【0023】そこで、本発明では、最も消費電力の大き
な高速高周波用半導体パッケージ2は、半導体チップ裏
面に高熱伝導性の接着剤を介して放熱フィンを直接接合
して実装基板1の中央部に搭載する。また、メモリー半
導体チップを立体的に積み上げてなる三次元半導体パッ
ケージ3は、放熱フィン,高熱伝導性の放熱板を熱伝導
パスとして備えており、その搭載位置は、高速高周波用
半導体パッケージ2と可能な限り隣接しており、複数個
の三次元半導体パッケージ3を搭載する。尚、三次元半
導体パッケージ3の構造の詳細については、実施形態2
で説明する。
Therefore, according to the present invention, the semiconductor package 2 for high-speed and high-frequency operation, which consumes the most power, is mounted on the center of the mounting substrate 1 by directly bonding the radiation fins to the back surface of the semiconductor chip via an adhesive having high thermal conductivity. I do. The three-dimensional semiconductor package 3 in which memory semiconductor chips are three-dimensionally stacked is provided with heat-radiating fins and a heat-radiating plate having high thermal conductivity as heat-conducting paths. As close as possible, a plurality of three-dimensional semiconductor packages 3 are mounted. The details of the structure of the three-dimensional semiconductor package 3 are described in the second embodiment.
Will be described.

【0024】さらに本発明では、図1及び図2に示すよ
うに、高密度実装基板1全体を覆う傾斜型風洞4又は5
がL字型溝10,コ字型溝11により高密度実装基板1
に固着されている。
Further, in the present invention, as shown in FIGS. 1 and 2, the inclined wind tunnel 4 or 5 covering the entire high-density mounting substrate 1 is provided.
Is a high-density mounting substrate 1 with an L-shaped groove 10 and a U-shaped groove 11.
It is stuck to.

【0025】傾斜型風洞4,5は、基板1から上方に立
上った側壁4c,5cと、側壁4c,5c間に設けられ
た屋根部4d,5dからなっており、屋根部4d,5d
は、冷却流体の入口側4aが高く、流体出口側4bに向
けて低くなって傾斜している。
The inclined wind tunnels 4 and 5 are composed of side walls 4c and 5c rising upward from the substrate 1 and roofs 4d and 5d provided between the side walls 4c and 5c.
Is inclined such that the cooling fluid inlet side 4a is higher and the cooling fluid outlet side 4b is lower.

【0026】また図2に示す傾斜型風洞5は、屋根部5
dが平面ではなく、3面に折り曲げて形成されている。
The inclined wind tunnel 5 shown in FIG.
d is not a flat surface but is formed by bending it into three surfaces.

【0027】したがって傾斜型風洞4,5は、起立した
側壁4c,5cで基板1上の半導体パッケージ3の側面
を覆い、屋根部4d,5dで半導体パッケージ2,3の
上部を覆うこととなる。
Therefore, the inclined wind tunnels 4 and 5 cover the side surfaces of the semiconductor package 3 on the substrate 1 with the upright side walls 4c and 5c, and cover the upper portions of the semiconductor packages 2 and 3 with the roof portions 4d and 5d.

【0028】本発明の実施形態によれば、高密度実装基
板1上に搭載された半導体パッケージ2,3のチップが
消費する総消費電力量は、20W相当(単位面積当たり
0.5W/cm2)であり、冷却方式は強制対流冷却を
採用することになる。
According to the embodiment of the present invention, the total power consumption of the chips of the semiconductor packages 2 and 3 mounted on the high-density mounting substrate 1 is equivalent to 20 W (0.5 W / cm 2 per unit area). ), And forced convection cooling is adopted as the cooling method.

【0029】近年、パソコンなどパーソナル機器の騒音
問題,筐体の小型化による制約により、風速は、せいぜ
い1m/s以下に制限される。
In recent years, the wind speed is limited to 1 m / s or less at most due to noise problems in personal devices such as personal computers and restrictions due to downsizing of the housing.

【0030】したがって、風速0.5m/s,筐体内の
環境温度40℃の条件で動作時の半導体チップのジャン
クション温度が許容値以下となる放熱構造が前提条件と
なる。例えば、図5に示すように傾斜型風洞4,5を備
えず、更には三次元半導体パッケージ3に放熱フィンや
放熱板を備えない従来の半導体装置に、20W相当供給
し、風速0.5m/s,筐体内の環境温度を40℃とし
た場合、搭載された全ての半導体チップのジャンクショ
ン温度は、許容値以上となった。特に風向きに対し風下
に搭載された三次元半導体パッケージ3のブロック列の
発熱量が最大となった。
Therefore, a precondition is a heat radiation structure in which the junction temperature of the semiconductor chip during operation at a wind speed of 0.5 m / s and an environmental temperature of 40 ° C. in the housing is below an allowable value. For example, as shown in FIG. 5, 20 W is supplied to a conventional semiconductor device which does not include the inclined wind tunnels 4 and 5 and further does not include the heat radiation fins or the heat radiation plate in the three-dimensional semiconductor package 3 and has a wind speed of 0.5 m / s, when the environmental temperature in the housing was 40 ° C., the junction temperatures of all the mounted semiconductor chips were higher than the allowable value. In particular, the calorific value of the block row of the three-dimensional semiconductor package 3 mounted leeward with respect to the wind direction became the maximum.

【0031】つまり、図5の従来構造では、風下に配置
された三次元半導体パッケージ3に対して、上流側に配
置された三次元半導体パッケージ3及び高速高周波用半
導体パッケージ2などで発生する熱が冷却流体中に拡散
し空気温度を上昇させ流動抵抗分までも含まれるので、
局所流速は数段小さくなる。更に、流れ方向に相隣る三
次元半導体パッケージ間に澱み域が生じ、有効な伝熱面
積が減少する。
That is, in the conventional structure shown in FIG. 5, heat generated in the three-dimensional semiconductor package 3 and the high-speed high-frequency semiconductor package 2 arranged on the upstream side is generated with respect to the three-dimensional semiconductor package 3 arranged on the leeward side. Since it diffuses into the cooling fluid and raises the air temperature and includes the flow resistance,
The local flow velocity is several steps smaller. Furthermore, a stagnation region is formed between three-dimensional semiconductor packages adjacent to each other in the flow direction, and the effective heat transfer area is reduced.

【0032】そこで、本発明は、図1,図2に示すよう
に高密度実装基板1全体を覆う強制対流冷却流体の入口
側4a,5aから出口側4b,5bにかけて屋根部4
d,5dを傾斜させた風洞4、あるいは風洞5を備える
ことにより、前述した従来の問題を解決したものであ
る。
Therefore, according to the present invention, as shown in FIGS. 1 and 2, the roof portion 4 extends from the inlet side 4a, 5a to the outlet side 4b, 5b of the forced convection cooling fluid covering the entire high-density mounting board 1.
By providing the wind tunnel 4 or the wind tunnel 5 in which d and 5d are inclined, the above-mentioned conventional problem is solved.

【0033】実施形態1によると、図1に示した傾斜型
の風洞4を備えた構成では、冷却流体の入口側4aの強
制対流冷却流体の風速が1.0m/sとなる筐体構造と
し、この風洞4により基板1の半導体パッケージ2,3
を被覆し、環境温度40℃,電力20W相当供給し、風
洞4により冷却流体を半導体パッケージ2,3に強制的
に吹き付けた場合、ジャンクション温度は、許容温度以
下となることが示された。
According to the first embodiment, the structure having the inclined wind tunnel 4 shown in FIG. 1 has a casing structure in which the wind speed of the forced convection cooling fluid on the cooling fluid inlet side 4a is 1.0 m / s. The semiconductor packages 2 and 3 of the substrate 1 are formed by the wind tunnel 4.
When the cooling fluid is forcibly sprayed onto the semiconductor packages 2 and 3 through the wind tunnel 4 and the environment temperature of 40 ° C. and the power of 20 W are supplied, the junction temperature becomes lower than the allowable temperature.

【0034】また、図2に示した傾斜型の風洞5を備え
た構成では、冷却流体の入口側5aの強制対流冷却流体
の風速が0.5m/sとなる筐体構造とし、図1と同じ
ように環境温度40℃,電力20W相当供給したとき
に、ジャンクション温度は、許容値以下となることが示
された。
Further, in the configuration having the inclined wind tunnel 5 shown in FIG. 2, the casing structure is such that the forced convection cooling fluid at the inlet side 5a of the cooling fluid has a wind velocity of 0.5 m / s. Similarly, when an environment temperature of 40 ° C. and a power of 20 W were supplied, the junction temperature was shown to be below the allowable value.

【0035】以上のように、容器内に流入する流量と流
出する流量は一定となる物理的な原理から、第1に、冷
却流体出口側4b,5bに屋根部4d,5dを傾斜して
設けることにより、流路面積が小さくなる風下の半導体
パッケージ3のブロック近傍(冷却流体出口側4a,5
b)の局所流速は、入口側4a,5aに比べて数倍速く
なり、冷却流体出口側4b,5bの流路面積を、すなわ
ち基板1と側壁4c,5cと屋根部4d,5dとで形成
される流路の開口面積を可能な限り小さくする程、この
傾向は顕著となる。
As described above, based on the physical principle that the flow rate flowing into the container and the flow rate flowing out are constant, first, the roof portions 4d and 5d are provided at the cooling fluid outlet sides 4b and 5b with inclination. Accordingly, the vicinity of the block of the leeward semiconductor package 3 (the cooling fluid outlet side 4a, 5
The local flow velocity b) is several times faster than the inlet side 4a, 5a, and the flow area of the cooling fluid outlet side 4b, 5b is formed by the substrate 1, the side walls 4c, 5c, and the roof parts 4d, 5d. This tendency becomes more remarkable as the opening area of the flow path is made as small as possible.

【0036】第2に、冷却流体が風洞4,5の傾斜した
屋根部4d,5dの内面に衝突することにより、冷却流
体のベクトル方向に乱れが生じ、特に傾斜角度の大きい
下流ブロック域で乱流効果となる。
Second, when the cooling fluid collides with the inner surfaces of the inclined roof portions 4d and 5d of the wind tunnels 4 and 5, the cooling fluid is disturbed in the vector direction, particularly in the downstream block region having a large inclination angle. Flow effect.

【0037】したがって、傾斜型風洞を備えない従来の
半導体装置に比べて、数段熱抵抗値を小さくすることが
可能となる。尚、傾斜型風洞4及び5を構成する材料に
ついては、特に限定はしないが、例えば加工性の優れ,
軽量かつ低コストな薄板製のアルミ板などでもよい。
Therefore, it is possible to reduce the thermal resistance by several stages as compared with a conventional semiconductor device having no inclined wind tunnel. The materials forming the inclined wind tunnels 4 and 5 are not particularly limited.
A lightweight and low-cost thin aluminum plate may be used.

【0038】次に、図1に示すL字型溝10及びコ字型
溝11について説明する。例えば、自然対流冷却におい
て風洞を備えることは逆効果となるので、この場合はL
字型溝10及びコ字型溝11を横方向に開いて取り外し
て使用する。また、固着する場合においては、L字型溝
11と基板1の側面部をネジ止めして用いても良い。
Next, the L-shaped groove 10 and the U-shaped groove 11 shown in FIG. 1 will be described. For example, providing a wind tunnel in natural convection cooling has an adverse effect.
The U-shaped groove 10 and the U-shaped groove 11 are opened and removed in the horizontal direction and used. In the case of fixing, the L-shaped groove 11 and the side surface of the substrate 1 may be screwed and used.

【0039】(実施形態2)図3(a),図4(a)
は、本発明の実施形態2に係る三次元半導体パッケージ
を拡大した正面図、図3(b),図4(b)は、同側面
図である。
(Embodiment 2) FIGS. 3A and 4A
FIG. 3 is an enlarged front view of a three-dimensional semiconductor package according to a second embodiment of the present invention, and FIGS. 3B and 4B are side views of the same.

【0040】メモリー大容量化の手段として有効な三次
元半導体パッケージ3は、キャリア基板20の接続パッ
ドとメモリー半導体チップ21の電極パッドを金属バン
プ22aで接合した半導体パッケージと、該半導体パッ
ケージと同構成の半導体パッケージ同士を金属バンプ2
2bによって接合して立体的に積み上げて構成される。
例えば、図に示す3段積み上げ構成のメモリー半導体チ
ップ21当たりの消費電力が1Wであれば、単位面積当
たりの発熱密度は単純に3倍となる。
The three-dimensional semiconductor package 3, which is effective as a means for increasing the memory capacity, includes a semiconductor package in which connection pads of a carrier substrate 20 and electrode pads of a memory semiconductor chip 21 are joined by metal bumps 22a, and has the same configuration as the semiconductor package. Bumps between two semiconductor packages
It is configured by being joined three-dimensionally and stacked three-dimensionally.
For example, if the power consumption per memory semiconductor chip 21 in the three-stage stacked configuration shown in the figure is 1 W, the heat generation density per unit area simply triples.

【0041】図5に示す従来の三段積み上げた三次元半
導体パッケージを用い、電力3W,風速0.5m/s,
環境温度40℃とした場合、半導体チップのジャンクシ
ョン温度は、許容値をはるかに越えてしまうことが示さ
れた。特に、上下に挾まれる真中のメモリー半導体チッ
プ21が最大温度となる。
Using the conventional three-dimensional three-dimensional semiconductor package shown in FIG. 5, the power is 3 W, the wind speed is 0.5 m / s,
It has been shown that when the ambient temperature is 40 ° C., the junction temperature of the semiconductor chip far exceeds the allowable value. In particular, the temperature of the middle memory semiconductor chip 21 sandwiched between the upper and lower sides becomes the maximum.

【0042】そこで、図3に示す本発明の三次元半導体
パッケージ3の構成によれば、キャリア基板20裏面に
グランド電位導体パターン23が形成され、最上段のキ
ャリア基板20及びグランド電位導体パターン23上に
接着剤を介し接合した放熱フィン24を備える。
Therefore, according to the configuration of the three-dimensional semiconductor package 3 of the present invention shown in FIG. 3, the ground potential conductor pattern 23 is formed on the back surface of the carrier substrate 20, and the uppermost carrier substrate 20 and the ground potential conductor pattern 23 Is provided with a radiation fin 24 joined through an adhesive.

【0043】この構成では、キャリア基板20裏面の放
熱フィン搭載用のグランド電位導体パターン23は、多
段接続されたそれぞれのキャリア基板20や半導体チッ
プ21のグランド電位のみ選択し、電気的及び熱的に接
続されているので、半導体チップより発生した熱伝導パ
スとなる。
In this configuration, the ground potential conductor pattern 23 for mounting the radiating fins on the rear surface of the carrier substrate 20 selects only the ground potential of each of the carrier substrates 20 and the semiconductor chips 21 connected in multiple stages, and electrically and thermally. Since they are connected, they become heat conduction paths generated from the semiconductor chip.

【0044】したがって、この熱伝導パスから放熱フィ
ン24を通じて効率良く冷却流体中に熱放散することが
可能となる。次に、ほとんどのメモリー半導体チップ2
1の辺の長さは、ほぼ3:1の割合で長方形であり、こ
れらを多段接続してなる三次元半導体パッケージ3の搭
載方向は少なくとも2方向を有することで高密度実装が
可能となる。また、グランド電位導体パターン23と放
熱フィン24は、導電性の接着剤を用いて接合すること
でグランド同電位となり、電位の強化によるノイズ低減
や、熱的にも伝導バスが拡大されるので放熱性能は向上
する。
Accordingly, heat can be efficiently dissipated from the heat conduction path into the cooling fluid through the radiation fins 24. Next, most of the memory semiconductor chips 2
The length of one side is rectangular at a ratio of approximately 3: 1. The mounting direction of the three-dimensional semiconductor package 3 formed by connecting these in multiple stages has at least two directions, thereby enabling high-density mounting. The ground potential conductor pattern 23 and the radiating fins 24 are connected to each other by using a conductive adhesive to have the same potential as the ground. Performance improves.

【0045】したがって、図3に示すように放熱フィン
24のフィン方向も三次元半導体パッケージ3の搭載位
置により2方向を有する。即ち、放熱フィン24のフィ
ン方向21aは三次元半導体パッケージ3の一辺の長い
面側が冷却流体の風向側に搭載されたケースにおいて用
い、放熱フィン24のフィン方向24bは三次元半導体
パッケージ3の一辺が短い面側が冷却流体の風向側に搭
載されたケースにおいて用いることで、半導体チップよ
り発生する熱が前述したキャリア基板20や半導体チッ
プ21のグランド電位のみ選択された熱伝導パスを通
じ、2方向を有するこれらの放熱フィン24a,24b
によって効率よく冷却流体中に熱拡散することが可能と
なる。
Therefore, as shown in FIG. 3, the fins of the radiation fins 24 have two directions depending on the mounting position of the three-dimensional semiconductor package 3. That is, the fin direction 21a of the radiation fin 24 is used in a case where one long side of the three-dimensional semiconductor package 3 is mounted on the wind direction side of the cooling fluid, and the fin direction 24b of the radiation fin 24 is one side of the three-dimensional semiconductor package 3. By using the case where the short surface side is mounted on the wind direction side of the cooling fluid, heat generated from the semiconductor chip has two directions through the heat conduction path selected only for the ground potential of the carrier substrate 20 or the semiconductor chip 21 described above. These radiation fins 24a, 24b
Thereby, heat can be efficiently diffused into the cooling fluid.

【0046】次に、図3に示す3段接続構造を用いた本
実施形態によると、前述した放熱フィン24に通じるグ
ランド電位が選択された熱伝導パスのみの構成では、動
作時のチップのジャンクション温度を許容値以下とする
ことは、できなかった。特に、メモリー半導体チップ2
0の上下に挾まれる真中のチップが最大温度となった。
Next, according to the present embodiment using the three-stage connection structure shown in FIG. 3, in the above-described configuration having only the heat conduction path in which the ground potential connected to the radiation fin 24 is selected, the junction of the chip during operation is The temperature could not be reduced below the permissible value. In particular, the memory semiconductor chip 2
The temperature of the chip in the middle sandwiched above and below 0 reached the maximum temperature.

【0047】そこで、それぞれのメモリー半導体チップ
20の素子面から発生する熱がチップ裏面に達すると
き、図3に示すようにメモリー半導体チップ21裏面と
キャリア基板20裏面間に金属バンプ22bの高さをコ
ントロールして隙間を設け、該隙間に放熱板25aを備
ける。放熱板25aは0.1mm程度で特に材料には限
定しないが、高熱伝導性のCuあるいはシリコンと熱膨
張係数の近いCu/Mo複合材料などを用いてもよい。
尚、接合部分は熱抵抗となる接着剤による接合は行わな
くともよい。
Therefore, when the heat generated from the element surface of each memory semiconductor chip 20 reaches the back surface of the chip, the height of the metal bump 22b is reduced between the back surface of the memory semiconductor chip 21 and the back surface of the carrier substrate 20 as shown in FIG. A gap is provided by control, and a heat sink 25a is provided in the gap. The heat radiating plate 25a is about 0.1 mm and is not particularly limited to a material, but may be Cu or Mo composite material having a high thermal expansion coefficient close to that of high thermal conductivity Cu or silicon.
Note that the joining portion does not have to be joined with an adhesive that becomes a heat resistor.

【0048】この構成では、直接メモリー半導体チップ
21裏面に放熱板25を備えることで、メモリー半導体
チップ21裏面から冷却空気中に放散するための新たな
熱伝導パスが備えられたことになる。更に、図3に示す
ように三次元半導体パッケージ3の一辺の長い面側が冷
却流体の風向側に搭載されたケースにおいて、放熱板2
5の放熱板先端25aを放熱フィン24の側面壁に高熱
伝導性の接着剤で接合する。
In this configuration, since the heat radiating plate 25 is provided directly on the back surface of the memory semiconductor chip 21, a new heat conduction path for dissipating the cooling air from the back surface of the memory semiconductor chip 21 is provided. Furthermore, as shown in FIG. 3, in the case where one long side of the three-dimensional semiconductor package 3 is mounted on the wind direction side of the cooling fluid,
5 is joined to the side wall of the radiating fin 24 with an adhesive having high thermal conductivity.

【0049】一方、図4に示すように三次元半導体パッ
ケージ3の一辺の短い面側が冷却流体の風向側に搭載さ
れたケースでは、放熱板24の側面壁に放熱板25を接
合することは冷却流体を妨げることになるので、図4に
示すように放熱板25の先端25bを可能な限り周辺の
冷却空気中に突出することで効果的な熱伝達が促進され
る。
On the other hand, as shown in FIG. 4, in the case where the short side of one side of the three-dimensional semiconductor package 3 is mounted on the wind direction side of the cooling fluid, joining the heat radiating plate 25 to the side wall of the heat radiating plate 24 requires cooling. Since the fluid is hindered, effective heat transfer is promoted by protruding the distal end 25b of the radiator plate 25 into the surrounding cooling air as much as possible as shown in FIG.

【0050】即ち、多段化されたそれぞれの半導体チッ
プより発生する熱は、前述のメモリー半導体チップとキ
ャリア基板のグランド電位を選択して放熱フィンに通じ
る第1の放熱パスと、それぞれの半導体チップ裏面から
放熱板に通じる第2の放熱パスを備え、更に放熱板先端
を放熱フィンに接合することで前述の第1,第2の放熱
パスが共通の放熱パスとなることから、三次元半導体パ
ッケージ3の熱放散性が向上する。
That is, the heat generated from each of the multi-staged semiconductor chips is generated by selecting the ground potential of the memory semiconductor chip and the carrier substrate and leading to the heat radiation fins and the back surface of each semiconductor chip. And a second heat radiation path leading to the heat radiating plate, and furthermore, by joining the tip of the heat radiating plate to a heat radiating fin, the first and second heat radiating paths become a common heat radiating path. Improves the heat dissipation of

【0051】[0051]

【発明の効果】以上説明したように本発明によれば、強
制対流冷却の風速が0.5m/s〜1.0m/sの環境
条件でも、チップジャンクション温度が許容値以下とな
り、したがって、騒音などの問題で強制対流冷却時の風
速が制約されるパソコンなどパーソナル機器環境条件下
に、本半導体装置が適用できる。
As described above, according to the present invention, even when the wind speed of forced convection cooling is 0.5 m / s to 1.0 m / s, the chip junction temperature becomes lower than the allowable value, and therefore The present semiconductor device can be applied under the environmental conditions of a personal device such as a personal computer in which the wind speed at the time of forced convection cooling is restricted due to such a problem.

【0052】その第1の理由は、三次元半導体パッケー
ジを構成するそれぞれのメモリー半導体チップから発生
する熱を、第1の放熱パスとしてグランド電位を熱流路
として放熱フィンに至る放熱パスと、第2の放熱パスと
して半導体チップ裏面に接合した放熱板先端から放熱フ
ィンに至る放熱パスと、放熱板先端の突出部から周囲冷
却流体中に至る放熱パスを備えることにより、効率的な
熱放散を行うことができるためである。
The first reason is that the heat generated from each of the memory semiconductor chips constituting the three-dimensional semiconductor package is transferred to a radiating fin using a ground potential as a first radiating path and to a radiating fin using a ground potential as a heat flow path. Efficient heat dissipation by providing a heat dissipation path from the tip of the heat sink joined to the backside of the semiconductor chip to the heat dissipation fins and a heat dissipation path from the protrusion of the tip of the heat sink to the surrounding cooling fluid. This is because

【0053】また第2の理由は、複数の半導体パッケー
ジが搭載される高密度実装基板全体を覆う傾斜型風洞を
備えることにより、特に風下に搭載される半導体パッケ
ージブロック領域の局所流速は入口流速より数段速くな
るので、効率よく熱伝達が促進され、傾斜型風洞出口の
流路面積を可能な限り小さくするほど効果が大となるた
めである。
The second reason is that by providing an inclined wind tunnel covering the entire high-density mounting substrate on which a plurality of semiconductor packages are mounted, the local flow velocity of the semiconductor package block region mounted leeward is more than the inlet flow velocity. This is because heat transfer is promoted efficiently by several steps, and the effect increases as the flow passage area of the inclined wind tunnel outlet is made as small as possible.

【0054】また、風洞の傾斜角度の大きくなる下流ブ
ロック域ほど冷却流体の乱流効果により熱抵抗値を小さ
くすることが可能となる。
Further, the thermal resistance can be reduced by the turbulence effect of the cooling fluid in the downstream block region where the inclination angle of the wind tunnel is increased.

【0055】以上説明したように、本発明によると、電
力20W相当,強制対流冷却流体の風速を0.5m/
s,環境温度40℃の条件下でもチップジャンクション
温度は許容温度以下となることが示された。
As described above, according to the present invention, the wind speed of the forced convection cooling fluid is 0.5 m /
It was shown that the chip junction temperature was lower than the allowable temperature even under the condition of s and the environmental temperature was 40 ° C.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態1に係る半導体装置を示す斜
視図である。
FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の実施形態1に係る半導体装置を示す斜
視図である。
FIG. 2 is a perspective view showing a semiconductor device according to the first embodiment of the present invention.

【図3】(a)は本発明の実施形態2に係る半導体装置
を示す正面図、(b)は同側面図である。
FIG. 3A is a front view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 3B is a side view thereof.

【図4】(a)は本発明の実施形態2に係る半導体装置
を示す正面図、(b)は同側面図である。
FIG. 4A is a front view showing a semiconductor device according to a second embodiment of the present invention, and FIG. 4B is a side view thereof.

【図5】従来の半導体装置を示す斜視図である。FIG. 5 is a perspective view showing a conventional semiconductor device.

【図6】(a)は、従来例を示す正面図、(b)は同側
面図である。
FIG. 6A is a front view showing a conventional example, and FIG. 6B is a side view thereof.

【符号の説明】[Explanation of symbols]

1 高密度実装基板 2 高速高周波用半導体パッケージ 3 三次元半導体パッケージ 4 傾斜型風洞 4a 冷却流体入口側 4b 冷却流体出口側 5 傾斜型風洞 5a 冷却流体入口側 5b 冷却流体出口側 10 L字型溝 11 コ字型溝 20 キャリア基板 21 メモリー半導体チップ 22a 金属バンプ 22b 金属バンプ 23 グランド電位導体パターン 24 放熱フィン 24a 放熱フィン方向 24b 放熱フィン方向 25 放熱板 25a 放熱板先端 25b 放熱板先端 REFERENCE SIGNS LIST 1 high-density mounting substrate 2 high-speed high-frequency semiconductor package 3 three-dimensional semiconductor package 4 inclined wind tunnel 4 a cooling fluid inlet side 4 b cooling fluid outlet side 5 inclined wind tunnel 5 a cooling fluid inlet side 5 b cooling fluid outlet side 10 L-shaped groove 11 U-shaped groove 20 Carrier substrate 21 Memory semiconductor chip 22a Metal bump 22b Metal bump 23 Ground potential conductor pattern 24 Radiation fin 24a Radiation fin direction 24b Radiation fin direction 25 Radiator plate 25a Radiator plate tip 25b Radiator plate tip

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 風洞を有し、高速高周波用半導体パッケ
ージの周囲に複数の三次元半導体パッケージを搭載した
半導体装置であって、 風洞は、前記高速高周波用半導体パッケージ及び三次元
半導体パッケージを覆い、両パッケージに対して冷却流
体を強制的に導入するものであることを特徴とする半導
体装置。
1. A semiconductor device having a wind tunnel and a plurality of three-dimensional semiconductor packages mounted around a high-speed and high-frequency semiconductor package, wherein the wind tunnel covers the high-speed and high-frequency semiconductor package and the three-dimensional semiconductor package. A semiconductor device wherein a cooling fluid is forcibly introduced into both packages.
【請求項2】 前記風洞は、冷却流体入口側よりも冷却
流体出口側の流路面積が狭くなっていることを特徴とす
る請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the flow channel area of the wind tunnel on the cooling fluid outlet side is smaller than that on the cooling fluid inlet side.
【請求項3】 前記風洞は、各パッケージに対して脱着
可能であることを特徴とする請求項1に記載の半導体装
置。
3. The semiconductor device according to claim 1, wherein the wind tunnel is detachable from each package.
【請求項4】 前記三次元半導体パッケージは、キャリ
ア基板と半導体チップが金属バンプで接合された半導体
パッケージと、該半導体パッケージと同一構成の半導体
パッケージ同士を金属バンプで接合して立体的に積み上
げたものであり、 該三次元半導体パッケージの最上段のキャリア基板裏面
に形成されたグランド電位導体パターン上に接着剤によ
り接合された放熱フィンを備え、 前記グランド電位導体パターンは、キャリア基板と半導
体チップのグランド電位のみ選択し、熱的及び電気的に
結合されたものであることを特徴とする請求項1に記載
の半導体装置。
4. The three-dimensional semiconductor package is formed by three-dimensionally stacking a semiconductor package in which a carrier substrate and a semiconductor chip are joined by metal bumps and a semiconductor package having the same configuration as the semiconductor package by joining with metal bumps. A radiation fin joined by an adhesive onto a ground potential conductor pattern formed on the back surface of the uppermost carrier substrate of the three-dimensional semiconductor package, wherein the ground potential conductor pattern is formed of a carrier substrate and a semiconductor chip. 2. The semiconductor device according to claim 1, wherein only the ground potential is selected and thermally and electrically coupled.
【請求項5】 前記放熱フィンは、強制対流冷却流体の
風向と同一となるように少なくとも2種類有することを
特徴とする請求項4に記載の半導体装置。
5. The semiconductor device according to claim 4, wherein said radiating fins have at least two types so as to have the same wind direction as the forced convection cooling fluid.
【請求項6】 前記三次元半導体パッケージを構成する
複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備えたものであることを特徴とす
る請求項1に記載の半導体装置。
6. The semiconductor according to claim 1, wherein a gap is provided on the back surface of each of the plurality of semiconductor chips constituting the three-dimensional semiconductor package, and a heatsink is provided in the gap. apparatus.
【請求項7】 前記三次元半導体パッケージを構成する
複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備え、該放熱板の先端は、放熱フ
ィンの側面壁に接着剤により接合されたものであること
を特徴とする請求項6に記載の半導体装置。
7. A gap is provided on the back surface of each of the plurality of semiconductor chips constituting the three-dimensional semiconductor package, a heat sink is provided in the gap, and a tip of the heat sink is attached to a side wall of the heat radiation fin by an adhesive. 7. The semiconductor device according to claim 6, wherein the semiconductor device is joined by:
【請求項8】 前記三次元半導体パッケージを構成する
複数個のそれぞれ前記半導体チップの裏面に隙間を設
け、該隙間に放熱板を備え、該放熱板の先端は周囲冷却
流体中に突出しているものであることを特徴とする請求
項7に記載の半導体装置。
8. A plurality of semiconductor chips constituting the three-dimensional semiconductor package, wherein a gap is provided on the back surface of each of the semiconductor chips, and a heat sink is provided in the gap, and a tip of the heat sink projects into the surrounding cooling fluid. The semiconductor device according to claim 7, wherein
JP8156903A 1996-06-18 1996-06-18 Semiconductor device Expired - Fee Related JP2792507B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8156903A JP2792507B2 (en) 1996-06-18 1996-06-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8156903A JP2792507B2 (en) 1996-06-18 1996-06-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH104163A true JPH104163A (en) 1998-01-06
JP2792507B2 JP2792507B2 (en) 1998-09-03

Family

ID=15637924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8156903A Expired - Fee Related JP2792507B2 (en) 1996-06-18 1996-06-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2792507B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117320362A (en) * 2023-11-29 2023-12-29 四川赛狄信息技术股份公司 Heat dissipation case, determination method of heat dissipation part and signal processing equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117320362A (en) * 2023-11-29 2023-12-29 四川赛狄信息技术股份公司 Heat dissipation case, determination method of heat dissipation part and signal processing equipment
CN117320362B (en) * 2023-11-29 2024-02-13 四川赛狄信息技术股份公司 Heat dissipation case, determination method of heat dissipation part and signal processing equipment

Also Published As

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