JPH1041498A - Gate turn-off thyristor stack - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the best use of the performance of a GTO thyristor preventing a current from concentrating on its region where more stress is induced when an unbalanced load is applied to the GTO thyristor by a method wherein the first region of a unit device is set smaller in current density than the second region when the unit device is equal in ON-state voltage. SOLUTION: A water-cooled fin 1 is equipped with an electrode lead-out terminal in one piece. The water-cooled fin is inserted between a diode 2 of small electrode diameter and a gate turn-off thyristor (GTO) 3 with electrodes larger in diameter than those of the diode 2. The GTO thyristor 3 is formed of a semiconductor pellet composed of a region A of the same diameter with the diode 2 and an outer region B, wherein the region A is smaller in current density than the region B when the GTO thyristor 3 is uniformly pressurized in an ON-state. The GTO thyristor is so formed as to make the region A shorter in a turn-off time than the region B. By this setup, a GTO thyristor stack can be enhanced in controllable current and lessened in size and cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GTO stack in which a gate turn-off thyristor (hereinafter abbreviated as GTO) and a semiconductor element having a smaller diameter than the GTO are stacked and pressed.

[0002]

2. Description of the Related Art In a large-capacity power converter such as a steel inverter, semiconductor devices such as a GTO, a freewheel diode (flywheel diode) connected in anti-parallel to the GTO, and a diode of a snubber circuit are used. You. In these semiconductor elements, a semiconductor pellet is housed in a flat package and is brought into electrical contact with an external electrode by pressure welding. Such flat GTOs and diodes are stacked and cooled together with cooling fins therebetween.
That is, the GTO and the diode are pressed together and
Construct a TO stack. As a result, the GTO and the diode are connected close to each other, so that the wiring inductance can be reduced.

[0003] Normally, the GTO and the diode have different current capacities, and the diode has a smaller current capacity. For this reason,
Diode electrode diameter (diameter of package electrode post)
Is smaller than GTO. Therefore, GTO as described above
In the stack, GTOs and diodes having different electrode diameters are integrally laminated.

[0004] As a technique relating to the above-mentioned conventional technique, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 7-273279.

[0005]

A GTO in which a plurality of small-capacity unit element regions (hereinafter referred to as a unit GTO) are arranged in parallel in a semiconductor substrate and a diode having a smaller electrode diameter than the GTO are formed in the same stack. The following problems occur in the case of pressure contact.

Now, consider a portion where a GTO having a large electrode diameter and a diode having a small electrode diameter are adjacent via a cooling fin. In this part, since the cooling fins warp to the diode side with a small electrode diameter due to the large pressure contact force of the GTO stack, the GTO with a large electrode diameter receives an uneven load in which the load at the periphery is smaller than that at the center. Become. When an unbalanced load occurs in the GTO plane as described above, the contact resistance between the unit GTO and the electrode in the same region (hereinafter, referred to as region A) with the electrode diameter of the diode which becomes heavily loaded inside the package becomes low load. The unit GTO is smaller than the unit GTO in a region outside the region A (hereinafter, referred to as a region B). Therefore, the current easily flows in the region A, and the current hardly flows in the region B.

When the current flowing through the unit GTO increases, the amount of carriers to be swept off at the time of turning off increases, and it takes time to turn off. Then, the current is successively transferred to the unit GTO whose turn-off operation is delayed from the unit GTO whose turn-off operation is earlier. Further, when an excessive current exceeding the current allowed per unit GTO flows, the GTO is thermally destroyed. Therefore, in order to maximize the capacity of the GTO, it is necessary to make the current balance between the units GTO good, make the turn-off operation uniform, and prevent the current from concentrating on a specific unit GTO. However, when accommodating press-contact type semiconductor elements having small electrode diameters in a conventional stack of the integral tightening method, an eccentric load generated in the GTO cannot be avoided, and current concentrates on the unit GTO having a strong load. There is a problem in that the current of the unit GTO in this portion cannot be cut off to shift to the blocking state, and the current cutoff capability of the GTO is reduced.

An object of the present invention is to store a semiconductor element having a smaller electrode diameter than that of a GTO in the same stack, and to prevent a current from concentrating in a region where the load is strong even if an uneven load is generated.
An object of the present invention is to obtain a GTO stack that can make maximum use of the TO capability.

[0009]

In the GTO stack of the present invention, a flat GTO in which semiconductor pellets are accommodated in a flat package and a flat semiconductor element having a smaller electrode area than the flat GTO are stacked. And are integrally pressed together to be pressed together. A plurality of unit elements (units GTO) are formed in a flat GTO semiconductor pellet.

In the GTO semiconductor pellet, the unit element located in the first area where the electrode of the flat semiconductor element is projected, that is, the area immediately below or directly above the electrode of the flat semiconductor element, and the second area which is the other area The electrical characteristics of the unit element located in the region are different as follows.

That is, in the present invention, when the forward voltage drop (ON voltage) of the unit element is the same value, the current density of the unit element located in the first region is reduced by the unit element located in the second region. Is smaller than the current density.

According to the present invention, the unit element in the first region, which has a higher load than that in the second region, has a characteristic that current does not easily flow than the unit element in the second region. The current density in the first region is prevented from increasing with the load. Therefore, the current density is prevented from becoming non-uniform in the GTO plane, so that excessive current concentration does not occur locally at the time of turn-off. Therefore, the current interruption capability of the GTO stack is improved.

Incidentally, specifically, the GTO in the present invention
The semiconductor pellet has a configuration in which the carrier concentration, conduction area, or turn-off time of the unit element in the first region during conduction is smaller than that of the unit element in the second region. For example, the unit element in the first region has a larger anode short-circuit rate, a smaller current amplification factor in the transistor region, a shorter lifetime, or a smaller area of the cathode-side emitter layer than the unit element in the second region. small.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a GTO embodying the present invention.
In the figure, reference numeral 1 denotes a water-cooled fin, which has a water passage therein, and cools the semiconductor element by flowing water therethrough. This water-cooled fin 1 is also provided integrally with a terminal for taking out an electrode. These are diodes 2 with small electrode diameters.
And water-cooled fins 1 are inserted on both sides of the GTO 3 having a larger electrode diameter than the diode.
GTO and water-cooled fins are stacked. Reference numeral 4 denotes an insulating spacer. The stacked GTO stacks are pressurized and held at a specified pressure of 10,000 kgf. GTO3 used in the GTO stack of FIG.
Means that the semiconductor pellet is divided into a region A having the same diameter as the diode 2 and a region B outside the region A, and the current density in the GTO-on state in a state where the GTO alone is uniformly pressed is a region A.
Is smaller than the region B, and the turn-off time is shorter in the region A than in the region B.

FIG. 2 shows a partial plan view of the semiconductor pellet of the GTO 3 in FIG. 1 and a distribution of the surface pressure applied to the GTO 3. The GTO pellet 5 shown in FIG.
A large number of rings and radially elongated units GTO are arranged, and a cathode electrode 6 and a gate electrode 7 are provided.
Further, a common gate electrode 8 for extracting a gate current connected to the gate circuit is provided at the center. The surface pressure of the GTO is substantially uniform in the four inner rings, ie, the region A, immediately below the diode pressing portion, but is lower in the outer two rings, ie, the region B, than in the region A. Thus, in the GTO stack of FIG. 1, the eccentric load is applied to the GTO 3.

FIG. 3 is a cross-sectional view along the line aa 'including the boundary between the regions A and B of the GTO pellet 5 in FIG. The GTO pellet 5 includes an anode electrode 9, a cathode electrode 6, a gate electrode 7, an n emitter layer 10, a p base layer 11, an n base layer 12, a p emitter layer 13, and n.
An anode short-circuit layer 14 in which the p-emitter and n-base are short-circuited at ⁺ (n-type high impurity concentration). One surface of n base layer 12 is adjacent to p base layer 11, and a part of the other surface of p base layer 11 is adjacent to a plurality of n emitter layers 10. On the other surface of the n base layer 12, a plurality of p emitter layers 13 and anode short-circuit layers 14 which are alternately arranged are adjacent to each other.

The thickness of the n ⁺ anode short-circuit layer 14 is larger than that of the p emitter layer 13,
Are arranged so that one surface of the substrate enters the n base layer. The anode short-circuit layer 14 in the projection of the n-emitter layer 10 on the anode side has a strip shape. The longitudinal direction of the strip-shaped anode short-circuit layer is along the longitudinal direction of the n-emitter layer 10. The anode short-circuit layer 14 has the effect of suppressing injection of holes from the p-emitter layer 13 and shortening the turn-off time.

A cathode electrode 6 is provided on the other surface of the n-emitter layer 10, a gate electrode 7 is provided on a surface of the p-base layer 11 other than the n-emitter layer 10, and a plurality of p-emitter layers 1 are provided.
An anode electrode 9 is in ohmic contact with the other surface of each of the 3 and n ⁺ anode short-circuit layers 14.

Assuming that the length of the strip-shaped anode short-circuit layer 14 is XA in the region A and XB in the region B, XA is longer than XB in the present GTO. For this reason, the degree of hole injection from the p emitter layer in the region A can be suppressed more than in the region B. This prevents the current density in the area A from being higher than that in the area B even when the area A has a high load, and the current density in both areas can be made uniform. In addition, since the residual carriers in the n base layer 12 at the time of turn-off are discharged to the outside through the anode short-circuit layer 14, the turn-off time can be shortened in the region A, and when incorporated in the GTO stack, the turn-off times can be made the same. As a result, local current concentration at the time of turn-off can be prevented, and current can be uniformly interrupted in the GTO plane. As a result, the controllable current of the GTO stack is improved.

Further, the GTO stack embodying the present invention eliminates the need to use a diode having a current rating larger than necessary in order to match the diode with the electrode diameter of the GTO, or to incorporate the diode in a separate stack. It is possible to reduce the size and cost of the stack.

In this embodiment, the length of the anode short-circuit layer is changed in the regions A and B, but the width may be changed. Further, the anode short-circuit layer may have the same shape, and the length or width of the p-emitter layer may be changed. That is, the ratio of the area of the anode short-circuit layer to the area of the p-emitter layer, that is, the short-circuit rate,
What is necessary is just to make the area A larger than the area B. In addition, the shape of the anode short-circuit layer is not limited to a strip shape,
Various shapes such as a dot shape and a ring shape can be used.

(Embodiment 2) In the previous embodiment, the regions A,
Although the short-circuit rate was changed in B, even if the impurity concentration of the p base layer was changed, the current densities in both regions can be made uniform.

FIG. 4 shows a GTO according to another embodiment of the present invention.
This shows the impurity concentration of the pellet. Stack configuration and GT
The regions A and B of the O pellet are the same as in the first embodiment. FIG. 4 shows an n emitter layer 10, a p base layer 11, and an n base layer 1 related to the present embodiment.
2, only the anode side p emitter layer 13 and the n ⁺ anode short circuit layer 14 are omitted. The difference between the region A and the region B is that the impurity concentration of the p base layer 11 indicated by a dotted line in the region is higher in the region A than in the region B. As a technique for increasing the impurity concentration in a local region such as the region A, there is an ion implantation method using a photoresist film or an oxide film as a mask.

As described above, when the impurity concentration of the region A is increased,
The injection efficiency from the n emitter in the region B is higher than that in the region A, and the n emitter layer 10, the p base layer 11, and the n base layer 1
The current amplification factor in the three layers 2 is higher in the region B than in the region A. By increasing the current amplification factor in the region B in this manner, it is possible to prevent the current density in the region A from becoming higher than that in the region B due to an unbalanced load when incorporated in the GTO stack, and to make the current densities in both regions uniform. Furthermore, the turn-off time can be shortened by reducing the excess carriers in the region A, and the turn-off time can be made uniform within the plane when incorporated in a GTO stack. As a result, local current concentration at the time of turn-off can be prevented, and in-plane current can be uniformly cut off. As a result, the controllable current of the GTO stack is improved.

(Embodiment 3) FIG. 5 shows G in another embodiment.
2 shows a cross section of a TO pellet. This cross section corresponds to the cross section in FIG. The second embodiment is different from the second embodiment in that the anode short-circuit structure is a uniform structure over the entire surface, the impurity concentration of the p base layer 11 is uniform over the entire surface, and a local crystal defect layer 15 is formed in the n base layer 12 in the region A. It is different in forming. The crystal defect layer 15 can be formed by selectively irradiating the n base layer 12 in the region A with accelerated ions such as hydrogen and helium.

Since the resistance of the n base layer 12 in the region A is increased by forming the crystal defect layer in the region A in this manner, the current density in the region A is reduced even when the region A is under a high load.
And the current density in both regions can be made uniform. Further, by forming a crystal defect layer having a short lifetime in the region A, excess carriers in the region A can be reduced faster than in the region B. As a result G
When incorporated in a TO stack, the turn-off times are the same, preventing local current concentration at the time of turn-off and enabling uniform current interruption in the GTO plane. In addition,
The same effect can be obtained by a method in which the irradiation energy and the irradiation amount are different between the region A and the region B and more crystal defects are formed in the region A than in the region B.

As a method of changing the lifetime of the vertical cross section of the n-base layer 12 in the regions A and B, a method of irradiating a highly transmissive radiation such as an electron beam or a gamma ray may be employed. The same effect can be obtained by changing the irradiation energy.

Embodiment 4 FIG. 6 shows a cross section of a GTO pellet unit GTO in still another embodiment.
This cross section corresponds to the bb 'cross section and the cc' cross section in FIG. The width of the n-emitter layer 10 on the cathode side is set to WA in the region A and WB in the region B, so that WA is narrower than WB. As shown in FIG.
When the emitter width is reduced, the gate pull-out resistance at the time of turning off the GTO is reduced, so that carriers can be rapidly drawn to the gate and the turn-off time can be shortened. In addition, since the width of current supply in the ON state becomes narrower and the absolute value of carriers extracted to the gate becomes smaller, the turn-off time becomes shorter.
From the above effects, the turn-off operation can be made uniform in the plane, local current concentration at the time of turn-off can be prevented, and the in-plane current can be cut off uniformly.

Incidentally, any of the configurations of the above embodiments can be used together.

In each of the above embodiments, a large number of units GTO are arranged on a circular semiconductor substrate in the form of six concentric rings and the common gate electrode is taken out from the center of the circular semiconductor substrate. The position may be changed, or the position of the common gate electrode may be located at the outermost periphery of the GTO pellet. In the above embodiments, the cooling fins integrated with the electrode extraction terminals are provided. However, these may be used alone, and the number and arrangement of the components to be incorporated in the stack may be changed according to the electric circuit. You may. Embodiment 5 FIG. 7 shows an example of a power converter using a GTO stack according to the present invention, showing a main circuit of an inverter device. When the GTO stack of FIG. 1 is shown in the circuit, GT
O and a snubber diode and a flywheel diode connected in parallel to the GTO are integrally tightened. Compared with the conventional GTO stack, the GTO stack according to the present invention has a larger controllable current, so that the GTO stack required for the desired inverter power capacity is obtained.
The number of TOs can be reduced. Therefore, it is effective in miniaturizing the inverter device and improving the reliability.

[0032]

According to the present invention, even if semiconductor elements having different electrode diameters are housed in the same stack and an eccentric load is generated in the GTO plane, the GTO stack can be more interrupted than before.

[Brief description of the drawings]

FIG. 1 shows a GTO stack embodying the present invention.

FIG. 2 is a partial plan view of a semiconductor pellet of GTO3 in FIG. 1;

FIG. 3 is a view showing a region A and a region B of the GTO pellet 5 shown in FIG. 2;
It is sectional drawing which followed -a '.

FIG. 4 shows an impurity concentration of a GTO pellet according to another embodiment of the present invention.

FIG. 5 shows a cross section of a GTO pellet according to another embodiment of the present invention.

FIG. 6 shows a cross section of a GTO pellet unit GTO according to still another embodiment of the present invention.

FIG. 7 shows a main circuit of an inverter device using a GTO stack according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Water-cooled fin, 2 ... Diode, 3 ... GTO, 4 ... Insulating spacer, 5 ... GTO pellet, 6 ... Cathode electrode, 7
... gate electrode, 8 ... common gate electrode, 9 ... anode electrode, 10 ... n emitter layer, 11 ... p base layer, 12 ... n
Base layer, 13: p emitter layer, 14: anode short-circuit layer, 15: crystal defect region.

Claims (5)

[Claims] 1. A gate turn-off thyristor stack in which a flat gate turn-off thyristor and a flat semiconductor element having an electrode area smaller than that of the flat gate turn-off thyristor are stacked and integrally fastened. In the semiconductor pellet, a plurality of unit elements are formed, and when the ON voltage of the unit element is the same, the current density of the unit element located in the first region of the semiconductor pellet where the electrode of the flat semiconductor element is projected is reduced. A gate turn-off thyristor stack having a lower current density than a unit element located in a second region outside the first region. 2. The gate turn-off thyristor stack according to claim 1, wherein said flat gate turn-off thyristor is an anode-emitter short-circuit type gate turn-off thyristor, and said unit element located in said first region has an anode short-circuit rate of said second region. 2. A gate turn-off thyristor stack, wherein the gate turn-off thyristor stack is larger than the anode short-circuit rate of the unit element located in the area No. 2. 3. The gate turn-off thyristor stack according to claim 1, wherein a current amplification factor of a cathode-side transistor region of a unit element located in said first region is equal to said second-side transistor region.
A gate turn-off thyristor stack characterized by being smaller than the current amplification factor of the unit element located in the region of (1). 4. The gate turn-off thyristor stack according to claim 1, wherein a local low lifetime region is formed inside the unit element located in said first region. 5. The gate turn-off thyristor stack according to claim 1, wherein the width of the cathode-side emitter layer of the unit element located in the first region is equal to the width of the cathode-side emitter layer of the unit element located in the second region. Gate turn-off thyristor stack characterized by being narrower than width.