JPH1041463A - Mos capacitor and its formation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS capacitor, which reduces voltage dependability of capacitance even when the dielectric of the MOS capacitor is thinned and can be used for highly accurate A/D and D/A converters, and provide its formation which reduces the production cost and improves the yield. SOLUTION: A MOS capacitor is formed of a top electrode, which is a gate electrode 3, a dielectric, which is a gate oxide film 4, and a bottom electrode formed of an N<++> layer 9 formed by implanting arsenic with an acceleration voltage of 20-690KeV and a dose of 4×10<14> -1×10<15> cm<-2> and an N<+> layer 10 formed by implanting phosphorus with an acceleration voltage of 120KeV and a dose of 1×10<14> cm<-2> . Thus, voltage dependability of the capacitance of the capacitor is suppressed, reduction of absolute value of the capacitance due to the increase of dielectric film thickness by multiplied oxidation is suppressed and deterioration of junction breakdown strength at the junction of a silicon substrate 1a and the bottom electrode is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS capacitor used for A / D, D / A circuits and the like, and a method of forming the same.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing a structure of a conventional MOS capacitor used for an A / D, D / A converter or the like of a semiconductor device. In the figure, 1 is a P-type well, 1
a is a P-type silicon substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is a gate oxide film, 5 is an N ⁺ layer, and 6 is a source / drain region. MOS capacitor is an upper electrode and the gate electrode 3, a gate oxide film 4 of the dielectric, is composed of the lower electrode as a N ⁺ layer 5, the N ⁺ layer 5 acceleration voltage 1
It is formed by implanting phosphorus under the conditions of 20 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² .

[0003]

The conventional MOS type capacitor is as described above. The gate oxide film has been reduced in thickness with the recent miniaturization of devices, and the gate oxide film has been used as a dielectric. Therefore, the thickness of the dielectric of the MOS capacitor is also reduced.

As the thickness of the dielectric of a MOS capacitor is reduced, the acceleration voltage is 120 KeV and the dose is 1 × 10 ¹⁴ cm.
N ⁺ formed by injecting phosphorus under the condition of ^-2
In the layer, the concentration of the impurity diffusion layer in the lower electrode is too low, and when a negative charge is applied to the gate electrode, the depletion layer expands and the capacitance of the capacitor decreases. That is, there is a problem that the voltage dependence of the capacitance value of the capacitor is increased, and the capacitor cannot be used for a high-precision A / D, D / A converter or the like.

Therefore, the capacitor is formed in a process different from that of the transistor. However, since the number of manufacturing steps is increased, the yield is reduced and the manufacturing cost is increased.

Further, Japanese Patent Application Laid-Open No. 61-101078,
Japanese Patent Application Laid-Open No. 64-20648 discloses a MOS type capacitor in which the impurity diffusion layer of the lower electrode is formed of two layers, a high concentration layer and a low concentration layer.
There is a problem that the density is not appropriate for use in a D / D / A converter or the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. Even if the thickness of the dielectric of a MOS capacitor is reduced, the voltage dependence of the capacitance value of the capacitor can be reduced, and high precision A It is an object of the present invention to provide a good MOS type capacitor which can be used for a / D, D / A converter and the like, and a method for forming the same which can reduce the manufacturing cost and improve the yield.

[0008]

According to a first aspect of the present invention, in a MOS type capacitor, an impurity diffusion layer of a lower electrode includes:
The first high impurity concentration first layer formed on the upper surface side of the silicon substrate
And a second diffusion layer in contact with the first diffusion layer and formed on the bottom surface of the silicon substrate and having a lower impurity concentration than the first diffusion layer. Arsenic dose 4 × in silicon substrate or P-type well
It is formed by injecting at 10 ^{14 -1} × 10 ¹⁵ cm ^-2 .

According to a second aspect of the present invention, there is provided a method of forming a MOS capacitor, comprising: forming an underlying oxide film on a P-type silicon substrate or a P-type well; and forming a resist pattern on the underlying oxide film. Removing the underlying oxide film in the opening of the resist pattern;
６０60 KeV, dose amount 4 × 10 ^{14 -1} × 10 ¹⁵ cm ^-2
Forming a first diffusion layer by implanting with
Forming a second diffusion layer at a position deeper than the first diffusion layer in contact with the first diffusion layer by injecting phosphorus using the resist pattern as a mask; Removing the oxide film; forming a gate oxide film by thermally oxidizing the P-type silicon substrate; forming a gate electrode on the gate oxide film; Forming a source / drain region using the mask as a mask.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a sectional view showing the structure of the MOS capacitor of the present invention, and FIGS. 2A to 2E are sectional views showing steps of a method for forming the MOS capacitor of FIG. This will be described sequentially with reference to FIG.

First, as shown in FIG. 2A, after a field oxide film 2 is formed on a P-type silicon substrate 1a, an underlying oxide film 7 is formed.

Next, as shown in FIG. 2B, after forming a resist pattern 8 and removing the underlying oxide film 7 at the opening, an acceleration voltage of 20 to 60 KeV and a dose of 4 × 10 ^{14 are used.}
By implanting arsenic under the condition of about 1 × 10 ¹⁵ cm ⁻² , an N ⁺⁺ layer 9 as a first diffusion layer is formed. At this time,
Since arsenic has a large atomic weight, if it is implanted through the underlying oxide film 7, oxygen atoms in the oxide film are knocked out to the silicon substrate to break the crystallinity of silicon and cause a junction leak, so the underlying oxide film 7 is removed. Perform injection. Subsequently, phosphorus is implanted under the conditions of an acceleration voltage of 120 KeV and a dose of 1 × 10 ¹⁴ cm ⁻² to form N ^{+ as} a second diffusion layer.
The layer 10 is formed. However, the order of injection of arsenic and phosphorus may be reversed.

Next, as shown in FIG. 2C, after removing the resist pattern 8, the underlying oxide film 7 is removed.
Thereafter, a P-type well 1 or an N-type well is formed.

Next, as shown in FIG. 2D, a gate oxide film is formed by thermally oxidizing the P-type silicon substrate 1a, and polysilicon for the gate electrode is formed on the entire surface. Is formed to form a gate composed of the gate oxide film 4 and the gate electrode 3.

Next, as shown in FIG. 2E, after forming sidewalls 11 made of an oxide film on both sides of the gate, the source / drain 6 is formed using the gate as a mask.

Through the above steps, as shown in FIG. 1, the upper electrode is formed of a gate electrode 3, a dielectric is a gate oxide film 4, and the lower electrode is formed of an N ⁺⁺ layer 9 and an N ⁺ layer 10.
An OS capacitor can be formed.

The N ⁺⁺ layer 9, which is the lower electrode of this MOS capacitor, has an acceleration voltage of 20 to 60 KeV and a dose of 4.times.1.
It is formed by implanting arsenic under the condition of 0 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . The accelerating voltage may be in the range of 20 KeV, which is the energy for extracting the charged ions, to 60 KeV, which is the energy required for being located at the shallow portion of the P-type silicon substrate 1a. Here, if the dose is set to 4 × 10 ¹⁴ cm ⁻² or less, the expansion of the depletion layer increases, and the voltage dependence of the capacitance value of the capacitor increases.

Further, when forming the N ⁺⁺ layer 9, if the injection amount of arsenic more than 1 × 10 ¹⁵ cm ^-2 concentration of N ⁺⁺ layer 9 can be further darker, a capacitance value Voltage dependency can be further reduced. However, by implanting arsenic, the crystallinity of the silicon constituting the P-type silicon substrate 1a is destroyed, and when the gate oxide film 4 constituting the dielectric of the capacitor is formed, the P-type silicon Since the substrate 1a is multiplied and oxidized and the gate oxide film 4 is formed thick, the absolute value of the capacitance value of the capacitor becomes very small.

[0019] In this experiment, the acceleration voltage 50 KeV, with implantation conditions arsenic that dose of 5 × 10 ¹⁴ cm ^-2 is the voltage dependence of the capacitance value can be suppressed to a conventional 1/3 or less, proliferation oxide It has been found that this is an optimal injection amount that can also suppress a decrease in the absolute value of the capacitor value due to an increase in the dielectric film thickness due to the above.

When the lower electrode is only the N ⁺⁺ layer 9, the concentration profile at the junction with the P-type well 1 or the P-type silicon substrate 1a becomes steep, and the junction breakdown voltage decreases. Therefore, an acceleration voltage of 120 KeV and a dose of 1 × 1
By implanting phosphorus under the condition of 0 ¹⁴ cm ⁻² to form the N ⁺ layer 10, the concentration profile at the junction with the P-type well 1 or the P-type silicon substrate 1 a can be moderated and the junction breakdown voltage can be improved. be able to.

Thus, the MOS type transistor and the MOS type capacitor for the A / D and D / A converter can be formed at the same time, so that the number of manufacturing steps is reduced as compared with the case where the capacitor and the transistor are formed in separate steps. The manufacturing cost can be reduced, and the yield can be improved.

[0022]

As described above, according to the present invention, the impurity diffusion layer of the lower electrode is formed on the upper surface side of the silicon substrate and has a high impurity concentration and is in contact with the first diffusion layer. A second diffusion layer having an impurity concentration lower than that of the first diffusion layer formed on the bottom surface of the silicon substrate; the first diffusion layer having a dose of arsenic of 4 in a P-type silicon substrate or a P-type well; Since it is formed by implanting at a dose of × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² , the concentration of the lower electrode is high, the spread of the depletion layer can be suppressed as much as possible, and the voltage dependency of the capacitor can be sufficiently suppressed. And a decrease in the absolute value of the capacitance value of the capacitor due to an increase in the dielectric film thickness due to multiplication oxidation can be suppressed.
There is an effect that a capacitor for the A converter can be obtained.

Also, a P-type silicon substrate or a P-type wafer
Forming an underlying oxide film on the substrate,
A resist pattern is formed on the film, and the resist pattern
Removing the underlying oxide film in the opening of the
Arsenic is accelerated to 20 with the resist pattern as a mask.
~ 60 KeV, dose 4 × 10¹⁴~ 1 × 10^Fifteencm ^-2
Forming a first diffusion layer by implanting with
Phosphorus is implanted using the above resist pattern as a mask.
And the first diffusion layer is in contact with the first diffusion layer
Forming a second diffusion layer at a deep position;
Removing the underlying oxide film after removing the pattern
And by thermally oxidizing the P-type silicon substrate
Forming a gate oxide film and forming a gate oxide film on the gate oxide film.
Forming a gate electrode, the gate electrode and the gate
Form source / drain regions using oxide film as mask
Process for the MOS transistor.
And A / D, D / A converter MOS capacitor at the same time
The capacitor and the transistor can be formed in
The manufacturing process can be reduced compared to forming in a separate process.
To reduce manufacturing costs and improve yield
There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a MOS capacitor according to the present invention.

FIG. 2 is a process sectional view illustrating a method for forming the MOS capacitor of FIG. 1;

FIG. 3 is a sectional view showing the structure of a conventional MOS capacitor.

[Explanation of symbols]

1 P-type well, 1a P-type silicon substrate, 3 gate electrode, 4 gate oxide film, 6 source / drain, 7
Underlay oxide film, 8 resist pattern, 9 N ⁺⁺ layer, 1
0 N ⁺ layer.

Claims (2)

[Claims] An upper electrode formed of a gate electrode of a MOS transistor formed on a silicon substrate;
A MOS type including a dielectric formed of a gate oxide film of an S-type transistor and a lower electrode formed of an impurity diffusion layer of a conductivity type opposite to that of the silicon substrate or the semiconductor well formed in the silicon substrate or the semiconductor well. In the capacitor, the impurity diffusion layer of the lower electrode has a first diffusion layer having a high impurity concentration formed on an upper surface side of the silicon substrate, and an impurity diffusion layer formed on a bottom surface side of the silicon substrate in contact with the first diffusion layer. A second diffusion layer having an impurity concentration lower than that of the first diffusion layer, wherein the first diffusion layer is formed by implanting arsenic into a P-type silicon substrate or a P-type well in a dose of 4 × 10 ¹⁴ to 1 × 10
A MOS-type capacitor formed by implantation at ¹⁵ cm ^-2 . 2. A step of forming an underlying oxide film on a P-type silicon substrate or a P-type well, forming a resist pattern on the underlying oxide film, and removing the underlying oxide film in an opening of the resist pattern. And arsenic is accelerated at an acceleration voltage of 20 to 6 using the resist pattern as a mask.
Forming a first diffusion layer by implanting at 0 KeV and a dose of 4 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^−2; and implanting phosphorus using the resist pattern as a mask to form the first diffusion layer. Forming a second diffusion layer at a position deeper than the first diffusion layer in contact with the substrate; and removing the underlying oxide film after removing the resist pattern;
Forming a gate oxide film by thermally oxidizing the P-type silicon substrate; forming a gate electrode on the gate oxide film; forming source / drain regions using the gate electrode and the gate oxide film as a mask; Forming a MOS capacitor.