JPH1038612A - Amplifier circuit for electronic measuring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To linearly control the gain of an amplifier circuit by using P-channel transistors for a source-common differential amplifying section and a load section and N-channel transistors for a current mirror section and respectively connecting the differential amplifying section and current mirror section to the current mirror section and load section. SOLUTION: A preamplifier 240 contains an amplifying stage having the same structure as those of three stages 241, etc. The PMOS transistors(Trs) 320 and 330 of the stage 241 are connected to NMOS Trs 340-370 and constitute a source-common differential amplifying section. The NMOS Trs 340-370 are connected to PMOS Trs 380 and 390 and constitute a current mirror section. The PMOS Trs 380 and 390 constitute a load section. Since the PMOS Trs 320, 330, 380, and 390 and NMOS Trs 340, 350, 360, and 370 are manufactured in the same manufacturing process step, the mutual conductance parameters of the Trs become nearly equal to each other. Therefore, the gain of the stage 241 is independent from the mutual conductance parameters of the PMOS Trs 320, 330, 380, and 390. The same can be said to other two stages.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to the structure and operation of a preamplifier for amplifying a signal received from a transducer of an electronic measurement system. In particular, the present invention relates to the structure and operation of a fast-response amplifier circuit.

[0002]

BACKGROUND ART US Patent 4,420,754 4,878,013 4,87
Electronic measurement systems, capacitive or inductive calipers, linear scales, and the like shown in 9,508 and 5,023,559 are well known. As illustrated in FIG. 1, a conventional measurement system 20 includes a ROM 28, an amplification circuit 40, a demodulator 50, an integrator 52, and a microprocessor controller 22 that controls an analog-to-digital (A / D) converter 54. Oscillator 26 is connected to microprocessor controller 22 and modulator 30.

[0003] An 8-bit data output of a ROM 28 based on a control signal from, for example, a microprocessor controller 22 is received by a modulator 30. The modulator 30 has a ROM 28
The oscillator signal from the oscillator 26 is adjusted on the basis of the data from the controller 26 and output to the transducer 32. Transducer
32 is a well known relative or absolute capacitive position encoder, inductive position encoder or similar transducer. The modulated signal is input from the transducer 32. Transducer 32 also modulates the signal based on the relative or absolute position between the slide and the scale. This signal is output to the amplifier 40.

The amplifying section 40 amplifies the signal from the transducer 32 based on the control signal from the microprocessor control device 22. The amplified signal is output to demodulator 50. The demodulator 50 controls the amplification circuit 40 based on a control signal from the microprocessor controller 22.
It is possible to provide a sample and hold circuit for sampling and holding the signal amplified by. Demodulator 50 then demodulates the sampled signal based on a control signal from microprocessor controller 22. Next, the demodulator 50 outputs the demodulated signal to the integrator 52.

[0005] The integrator 52 is a demodulator based on a control signal from the microprocessor controller 22.
A / D converter integrating multiple signals from 50
Output to 54. The A / D converter 54 then converts the integrated signal into a digital signal based on a control signal from the microprocessor controller 22. A
/ D converter 54 is the next microprocessor control unit
A digital signal is output to 22.

Next, the microprocessor control unit 22
The digital signal from the A / D converter 54 is processed to define the relative or absolute position of the transducer 32 slider on the transducer 32 scale.
The operator can confirm the obtained relative or absolute position by outputting it to the display 24. A separate controller instead of the position signal output of the microprocessor controller 22;
For example, it can be output to a computer such as a control device of a numerically controlled machine tool or the like.

FIG. 2 shows an amplifier circuit known as an amplifier circuit 40. A signal input from the transducer 32 is connected to one electrode plate of the capacitor 42. The other plate of the capacitor 42 is connected to the base of the PMOS transistor 44, the NMO
It is connected to the base of the S transducer 46 and one pole of the switch 48. Transistors 44 and 46 are connected to supply voltage VD
Connected in series between D and ground. The output of the amplifier circuit 40 is connected between a PMOS transistor 44 and an NMOS transistor 46, which are connected to the input of the demodulator 50. The other pole of switch 48 is directly connected to the output of amplifier circuit 40. Resets the amplifier circuit 40, and thus switches 48
When is closed, the input to the amplifier circuit 40 is connected directly to the output of the amplifier circuit 40 as described below.

In operation, when the transducer 32 outputs a voltage signal to the amplifier circuit 40, an NMOS transistor
The 46 and the PMOS transistor 44 operate together to expand the input voltage signal input to the amplifier circuit 40 in order to obtain an amplified output voltage signal from the amplifier circuit 40. The gain of the amplitude of the amplified output voltage signal output near amplifier circuit 40 is the transconductance g4 of PMOS transistor 44.
4. The output conductance c44 and the mutual conductance g46 of the NMOS transistor 46, the output conductance c
Based on 46. In particular, the gain G provided from the amplifier circuit 40
Is

G =-(g44 + g46) / (c44 + c46)

The transconductances g44 and g46 are the PMOS transconductance parameters K'p and NM, respectively.
It is a function of the OS transconductance parameter K'N. Output conductances c44 and c46 are respectively PMO
It is a function of the S channel length modulation parameter λP and the NMOS channel length modulation parameter λN. Each of these parameters depends on the manufacturing process of the transistor and is independent of each other.

When the switch is closed, the output to demodulator 50 stabilizes at the midpoint of the curve shown in FIG. When the switch 48 is open, the amplifier circuit 40 amplifies the input signal from the transducer 32 at high speed and high gain.

[0012]

However, since the fabrication steps required to form the PMOS transistor 44 and the NMOS transistor 46 are different, the transconductance parameters k'P, K'N the channel length modulation parameters λP and λN shows different values. Therefore, the transconductance g44 and the output conductance c44 of the PMOS transducer 44, and the transconductance g46 and the output conductance c46 of the NMOS transistor 46 are obtained.
It is extremely difficult to match 46. Therefore, the amplification unit
The amount of amplification at 40 is unlikely to be as designed. However, the amplifier circuit needs to be able to control the gain linearly. Since the manufacturing processes of the transistors 44 and 46 are different, the manufacturing process of forming the PMOS transistor 44 and the NMOS transistor 46 is difficult to control, and therefore, it is difficult to accurately predict the gain to be obtained.

The transconductance g of a PMOS or NMOS transistor is a function of the transconductance parameter K ', while the output conductance c of a PMOS or NMOS transistor is a function of the channel length modulation parameter λ. However, such MOS
Each of the transistor transconductance parameter K ′ and the channel length modulation parameter λ may vary by ± 30% due to uncontrollable manufacturing process variations. Therefore, the transconductance g and the output conductance c of such a MOS transistor are difficult to predict.

FIG. 4 shows another amplifier circuit 40 '. Amplifier circuit
40 'is substantially the same as the amplifier circuit 40 shown in FIG. However, in the amplifier circuit 40 'shown in FIG. 4, the gate of the PMOS transistor 44 is connected not to the capacitor 42 but to a node between the transistors 44 and 46. The gain G of the amplifier circuit 40 'shown in FIG.

G = (-g44 / g46) 1/2

G44 is the transconductance of the PMOS transducer 44 and g46 is the transconductance of the NMOS transistor 46. In general, the gain G of the amplifier circuit 40 'depends greatly on the manufacturing process dependent transconductance parameters K'P and K'N of the transistors 44 and 46,
However, it does not depend on the channel length modulation parameters λP and λN. Therefore, the gain can be designed and predicted from the previous amplifier circuit 40. To achieve a certain amplification, NMOS
Transconductance g46 of transistor 46 is PMOS
It must be much larger than the transconductance g44 of transistor 44.

Furthermore, the outputs of the amplifier circuits 40 and 40 ', as in the curves shown in FIG. 3, are generally not perfectly linear. In order to compensate for this non-linearity, two amplifier circuits 401 'and 402' are connected to inverting and non-inverting inputs of an operational amplifier such as an amplifier circuit 40 '' illustrated in FIG. For the amplifier circuit 40 '', the transducer 32 has two signals IN
Output +, signal IN-. These signals IN + and IN- are input to a pair of capacitors 47, respectively. Signals IN + and IN-
Are connected to the amplifier circuits 401 ′ and 402 ′ of the amplifier circuit 40 ″, respectively. First and second amplifier circuit 40 ''
The outputs of 401 ', 402' are shown at points A and B, respectively, as follows:

VA = K (VIN + / 2 + VCM) VB = K (VIN- / 2 + VCM)

VIN + and VIN- are the transducers 32
, And VCM is a common voltage.

In the amplifier circuit 40 ″ shown in FIG. 5, the nonlinearity of the amplifier circuits 401 ′ and 402 ′ is allowed by self-correction. Therefore, a common voltage VCM is introduced. Voltage signal IN
Since the outputs of + and IN- cannot be completely independent of each other, the common voltage VCM rises. this is,
This is caused by noise in the electronic measurement system 20, noise picked up from the transducer 32, and crosstalk between the signals IN + and IN- in the transducer 32.

Since the margin is lost due to the saturation of the transistor, the common voltage VCM becomes inappropriate. That is, as illustrated in FIG. 6, the margin MO between the saturation voltage VS and the input voltage VIN / 2 is much larger than the margin MCM.

Further, as illustrated in FIG. 6, when the common voltage VCM is present, the signal received from the transducer 32 is not in the linear operating range O of the amplifier circuit 40 ''. Therefore, the linearity is lost in the amplifier circuit 40 ″ by the common voltage VCM. Further, there is a possibility that the operation of other circuits may become unstable due to this.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an amplifier circuit for an electronic measurement system that can control the gain linearly while achieving high speed and high gain amplification. . Further, according to the present invention, it is possible to provide an amplifier circuit for an electronic measurement system in which the gain is linearly controlled by a plurality of stages.

[0024]

The present invention is characterized by the following constitution in order to achieve the above object. The amplifier circuit of the present invention includes a common source differential amplifier using the same type of transistor (P type or N type). Thus, the uncontrollable manufacturing process variation affecting the transconductance parameter of each of the transistors is the same for both transistors, and therefore the transconductance g of the transistors of the source common differential amplifier is about the same value. It is expected to be.

The amplifier circuit of the present invention also includes a current mirror and a load. The source common differential amplifier is connected to the current mirror. The current mirror unit is configured by a transistor of a type different from the transistor configuring the common source differential amplification unit. The current mirror section is then connected to a load section that uses transistors of the same type as the common source differential amplifier section. Therefore, the common source differential amplifier, the current mirror, and the load can be integrated together.

The amplifying circuit of the present invention can be used in a plurality of stages connected in series. This can provide more than one stage of amplification.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. In all the drawings, components denoted by the same reference numerals represent the same components.

FIG. 7 shows a first preferred embodiment of an electronic measurement system 100 including the amplifier circuit of the present invention. The electronic measurement system 100 includes a control device 110, a signal generation processing circuit,
120, transducer 130, display unit 140, clock 150
, And an RC timing circuit 160.

In particular, the clock signal of clock 150 is output to controller 110 via signal line 152. The control device 110 is connected to a signal generation processing circuit 120 via a signal line 112.
Output control signal to Signal generation processing circuit 120
Generates a plurality of drive signals to the transducer 130 based on the control signal supplied from the controller 110. Next, the transducer 130 outputs a plurality of signals indicating the position to the signal generation processing circuit 120.

The signal generation processing circuit 120 samples the output signal from the transducer 130 based on the RC timing circuit 160 and generates a digital signal indicating the position. This digital signal is output from the signal generation processing circuit 120 to the control device 110 via the signal line 292.

Next, the controller 110 performs further signal processing, and outputs a position signal to the display unit 140 via the signal line 114. Next, the display unit 140 displays the position indicated by the position signal to the operator.

The controller 110 shown in FIG. 7 is preferably implemented using a programmed microprocessor or microcontroller, or one or more integrated circuit elements. The controller 110 also includes
Programmed general purpose computer, special purpose computer, and ASIC and other integrated circuits, or PLD, PLA, PA
L or similar electronic circuits such as discrete circuit elements or programmable logic elements. In general, any device capable of generating the control signals described herein can be used to implement the controller 110.

The display unit 140 may be any display such as a CRT, LCD, or LED. Further, the display unit 140 can be replaced by connecting to a control device of a numerically controlled machine tool or a control system such as a general-purpose computer.

As exemplified in FIG. 7, a signal generation processing circuit
120 includes a control / timing circuit 200 for inputting a control signal output from the control device 110 via a signal line 112. The control / timing circuit 200 is a control device
It processes the control signal from 110 and outputs the control signal to various elements of the signal generation processing circuit 120. In particular, burst clock circuit 210 receives a control signal from control / timing circuit 200 via signal line 201. When the burst clock circuit 210 operates, a high frequency (preferably 2 MHz) clock signal is generated from the burst clock 210 and output to the control / timing circuit 200 via signal line 211.

The control / timing circuit 200 includes a signal line
The pulse data is output to the transmitter pulse generation circuit 220 via 209. The transmitter pulse generation circuit 220 outputs a driver signal to the signal lines 221a to 221h based on the pulse data input on the signal line 209. Each of the signal lines 221a-221h is connected to one of the transmitter drivers 222a-222h.

The signal line 202 from the control / timing circuit 200 is connected to the transmitter drivers 222a to 222h.
Connected with each other. The signal line 202 is connected to the sample hold delay circuit 25 of the signal generation processing circuit 120.
Connected to 0. The synchronization signal output on signal line 202 is
Transmitter drivers 221a-221h are controlled to provide the appropriate modulation signal to transducer 130 via signal lines 224a-224h.

As mentioned above, in FIG. 7, the transducer 130 may be an absolute or relative capacitance position encoder, an inductive position encoder, or the like. Further, the eight modulated signals are applied to signal lines 224a-224.
While input to the transducer 130 via h, any number of signals can be generated and input to the transducer 130 by the signal generation processing circuit 120. Similarly, fewer or more transmitter drivers 222 may be used than shown in FIG. For example, the transducer 130 may be 16 kinds of modulation signals.

Generally, the transducer 130 includes a slide member that is movable relative to the scale member along the measurement axis. The signal line 224 is connected to one or more capacitance or inductive circuit members provided on either the slide member or the scale member. The transfer function of the capacitance or induction between the slide member and the scale member of the transducer 130 is based on the signal line 224a based on the relative or absolute position of the scale member and the slide member.
Change the signal input of -224h. Output lines for multiple signals
132-138 are connected to the capacitance or induction member provided on the slide member or the scale member of the transducer 130.

The output signal lines 132-138 are connected to the input multiplexer 230 of the signal generation processing circuit 120. The input multiplexer 230 is connected to the input signal lines 132-138
Two of the signal lines connected to the preamplifier 240
Selectively connect to 232 and 234. Preamplifier 240 is based on control signals on signal lines 204 and 205 from control / timing circuit 200, and is based on an input multiplexer.
Amplify the signals on signal lines 232 and 234 from 230. Next, the preamplifier 240 outputs the amplified signal to the sample and hold circuit 260 via the signal lines 242 and 244.

The sample hold circuit 260 samples the amplified signal output via the signal lines 242 and 244 based on the control signal on the signal line 254 from the sample hold delay circuit 250. Based on the control signal from control / timing circuit 200 to sample / hold delay circuit 250, sample / hold delay circuit 250 outputs a control signal to RC timing circuit 160 via signal line 252.

The RC timing circuit 160 outputs a delayed control signal corresponding to the control signal on the signal line 252 from the sample hold delay circuit 250 to the signal line 162. Sample and hold delay circuit 250 outputs a control signal on signal line 254 based on the synchronization signal on signal line 202 from control / timing circuit 200 and the delayed control signal on signal line 162 from RC timing circuit 160. . The sample hold delay circuit 250 further generates and outputs a control signal on a signal line 254 based on the second control signal on the signal line 203 from the control / timing circuit 200.

The sample hold circuit 260 is connected to a signal line
After sampling the amplified signals on 242 and 244,
The signal once held is output to demodulator 270 via signal lines 262 and 264. The control / timing circuit 200 outputs a plurality of control signals to the demodulator 270. Demodulator
270 demodulates the signal from the sample and hold circuit 260 and outputs it to the integrator 280 via the signal line 272.

The integrator 280 outputs a signal from the demodulator 270 to the signal line 27 based on a plurality of control signals output on the signal line 207 from the control / timing circuit 200.
2 Integrate the demodulated signal output output above. The integrator 280 then outputs the integrated signal to the A / D converter 290 via the signal line 282. Based on the control signal from the control / timing circuit 200 on the signal line 208, the A / D converter 290 converts the integrated signal input from the integrator 280 via the signal line 282 into a digital signal. This digital signal is then output to controller 110 via signal line 292.

FIG. 8 shows a sample hold delay circuit 25.
0, RC timing circuit 160, sample hold circuit 26
0, demodulator 270, and integrator 280 are shown in detail. In particular, the sample hold delay circuit 250 includes a D-type flip-flop 253, a driver 256, and a Schmitt trigger element 258. The D input of the D-type flip-flop 253 is connected to the control / timing circuit 200.
Is connected to a control signal line 203 from
The clock input for the D-type flip-flop 253 is connected to the signal line 202 and the control / timing circuit 200
Input a synchronization signal from The driver 256 is connected between the Q output of the D-type flip-flop 253 and the signal line 252. The input of the Schmitt trigger element 258 is connected to the input signal line 162, while
The output of 258 is connected to signal line 254.

The RC timing circuit 160 includes a resistor 164 and a capacitor 166. Resistor 164, driver 256
Input signal line 252 and Schmidt trigger element 258
Is connected between the output signal lines 162 connected. Capacitor 166 is connected between output signal line 162 and ground. Therefore, when the output signal is output from the driver 256 to the RC timing circuit 160 via the signal line 252, the RC timing circuit 16 on the output signal line 162
The signal of 0 changes based on the resistance value of the resistor 164 and the capacitance of the capacitor 166.

The Schmitt trigger element 25 on the signal line 254
The output from 8 is used as a control signal. In particular, signal line 254 is connected to switches 265 and 266 of sample and hold circuit 260. Sample hold circuit 26
One pole of the zero switch 265 is connected to the input line 242. The other pole of switch 265 is connected to output line 262. Similarly, one pole of switch 266 is connected to input signal line 244, while the other pole of switch 266 is connected to output signal line 264. First capacitor 267
Is connected between output signal line 262 and ground, while a second capacitor 268 is connected between signal line 264 and ground.

Switch 265 of sample / hold circuit 260
And 266 are closed, the input signal lines 242 and 244
The input signal received from the switch is passed through switches 265 and 266 and output to output lines 262 and 264. At the same time, capacitors 267 and 268 are charged. Then switch 26
When 5 and 266 are opened, the voltage amplitudes on signal lines 262 and 264 are supplied by the voltages stored on capacitors 267 and 268, respectively.

Demodulator 270 includes two sets of switches 271a and 271b and 273a and 273b, respectively. Input signal line 262 is connected to one pole of each of switches 271a and 273b. Input signal line 264 is similarly connected to one pole of each of switches 273a and 271b. The first control signal line 206a from control / timing circuit 200 is used to control switches 271a and 271b. Switch 273a and
Control / timing circuit to control 273b
A second control signal line 206b from 200 is used.

The other pole of each of the switches 271a and 273a is connected to the inverting input of an operational amplifier 274. Similarly, the other pole of each of switches 271b and 273b is connected to the non-inverting input of operational amplifier 274. The inverting input of the operational amplifier 274 is connected to the output signal line 272 of the operational amplifier 274 by a capacitor 277 and a switch 275a connected in parallel. Similarly, the non-inverting input of the operational amplifier 274 is connected to the reference voltage Vref by a capacitor 276 and a switch 275b connected in parallel. Switch 275a and
Control / timing circuit to control 275b
A third control signal line 206c from 200 is used.

Operational amplifier of demodulator 270 on signal line 272
The output of the demodulated signal from 274
0 is input to the capacitor 281. Capacitor 281 is
The first switch 283 and the second switch 284 are connected to the inverting and non-inverting inputs of the operational amplifier 285, respectively. The first switch 283 is controlled by a control signal from the control / timing circuit 200 on the first signal line 207a. Second switch 284
Is similarly controlled by a control signal from the control / timing circuit 200 of the second signal line 207b.

The output signal line 282 of the integrator 280
Is connected to the output of the operational amplifier 285. Operational Amplifier 285
Is fed back to an inverting input of an operational amplifier 285 through a capacitor 287 and a switch 286 connected in parallel. The control signal for switch 286 is input from control / timing circuit 200 via third control signal line 207c.

FIG. 9 shows a first preferred embodiment of the preamplifier 240. The preamplifier 240 has three amplification circuit stages, a first stage 241 and a second stage.
243, and a third stage 245. Input signal lines 232 and 234 to preamplifier 240 are connected to IN + and IN- of first stage 241 respectively. Output signal lines 242 and 244 of preamplifier 240 are connected to OUT- and OUT + terminals of third stage 245, respectively.
Similarly, the OUT- and OUT + terminals of the first stage 241
Through a pair of first capacitors 248a and 248b via signal lines 241a and 241b, IN + of the second stage 243 and
Connected to each IN- terminal. The OUT- and OUT + terminals of the second stage 243 are connected to signal line 24.
A pair of second capacitors 249a and 249b via 3a and 243b
, And connected to the IN + and IN- terminals of the third stage 245, respectively.

The first pole of each of the switches 246a-246f is connected to a reference voltage Vref. Switch 246a, 246
c and the second pole of 246e are signal lines 232, 241
a and 243a and nodes 232a, 241c and 243, respectively
Connected at c. Switches 246b, 246d, and 246
The second pole of f is connected to signal lines 234, 241b and 243b at nodes 234a, 241d and 243d, respectively. Switches 246a-246f are controlled by control signals from control / timing circuit 200 on signal line 204a.

The first poles of switches 247a, 247c and 247e are connected to signal lines 232, 241a and 243a and node 232, respectively.
a, 241c, and 243c, respectively. Switch 2
The other poles of 47a, 247c, and 247e are connected to signal lines 241a, 2
43a and 242 are connected to nodes 241e, 243e, and 242a, respectively. Similarly, switches 247b, 247d,
And the first pole of 247f are connected to signal lines 234, 241b and
243b and nodes 234a, 241d, and 243d, respectively. The second poles of switches 247b, 247d, and 247f are connected to signal lines 241b, 243b, and 244 and node 24.
Connected at 1f, 243f, and 244a, respectively.

Each of the switches 247a-247f is controlled by a control signal from the control / timing circuit 200 via a signal line 205. The first capacitor 248a is located between nodes 241e and 241c on signal line 241a. Similarly, a first capacitor 248b is located between nodes 241f and 241d on signal line 241b. Similarly 2
The second capacitor 249a is connected to node 24 on signal line 243a.
Located between 3e and 243c. Similarly, the second capacitor 24
9b is located between nodes 243f and 243d on signal line 243b. The first pair of capacitors 248a and 248b, and 2
The second pair of capacitors 249a and 249b is connected to switch 247a-2
When 47f is closed, the first to third stages 241,
The stages are separated by storing the reset bias voltages supplied to 243 and 245.

FIG. 10 shows the first stage 241 in detail. The circuit shown in FIG. 10 includes an integrated, common source differential amplifier. The structures of the second stage 243 and the third stage 245 are the same.

In particular, as illustrated in FIG. 10, the signal line 232 is connected to the gate of the first PMOS transistor 320 through the IN + terminal of the first stage 241. Another signal line 234 is connected to the IN- terminal to the gate of the second PMOS transistor 330.
First and second PMOS transistors 320 and 330
Are connected to a common current source 310. The common current source 310 outputs a current Ib.

The drain of the first PMOS transistor 320 is connected to the gate and source of the first NMOS transistor 340. Similarly, the second PMOS transistor 33
The drain of 0 is connected to the gate and source of the second NMOS transistor 350. The gate of the second NMOS transistor 350 is also connected to the gate of the third NMOS transistor 360, while the gate of the first NMOS transistor 340 is also connected to the gate of the fourth NMOS transistor 370. The source of the fourth NMOS transistor 370 is connected to the OU of the first stage 241.
Connected to signal line 241b through T + terminal. 3
Similarly, the source of the NMOS transistor 360 is 1
The OUT-terminal of the second stage 241 is connected to the output signal line 241a. The drains of the first to fourth NMOS transistors 340 to 370 are connected to the ground.

The source of the third NMOS transistor 360 is also connected to the gate and drain of the third PMOS transistor 380. Similarly, the source of the fourth NMOS transistor 370 is connected to the gate and the drain of the fourth PMOS transistor 390. 3rd PM
The sources of the OS transistor 380 and the fourth PMOS transistor 390 are connected to a common voltage VCOM.

Accordingly, the first and second PMOS transistors 320 and 330 constitute a common source differential amplifier. First to fourth NMOS transistors 340-370
Constitutes a current mirror unit. Third and fourth PMOS
Transistors 380 and 390 are PMOS transistors 320
And 330 constitute a load section of the same transistor type as the common source differential amplifier section.

FIG. 11 shows a voltage supply circuit 400 of the preamplifier 240 for generating the common voltage VCOM. As illustrated in FIG. 11, the power supply voltage VDD is set to the fifth PMOS transistor 410 and the sixth PMOS transistor 48.
Connected to 0 source. Fifth and sixth PMO
The gates of S-transistors 410 and 480 are connected through a first switch 460. In particular, the gate of the fifth PMOS transistor 410 is connected to the first switch 460
And the first electrode plate of the capacitor 440. The gate of the sixth PMOS transistor 480 is connected to the second pole and drain of the first switch 460. The drain of the fifth PMOS transistor 410 is connected to the source of the seventh PMOS transistor 420,
And third and fourth PMOS transistors 380 and 39
Connected to zero source. Therefore, the common voltage VCOM is 5
It is supplied from the drain of the PMOS transistor 410.

The gate and drain of the seventh PMOS transistor 420 are connected together and to the first pole of the second switch 450 and one end of the second current source 430. The gate and drain of the sixth PMOS transistor 480 are also connected to one end of the third current source 490. The other ends of the second and third current sources 430 and 490 are connected to ground.

The second and third current sources 430 and 490 output currents of KIb / 2, respectively. The constant K is an appropriate bias current for the third and fourth PMOS transistors.
380 and 390 are chosen to ensure that they are supplied. Another embodiment includes a common voltage generation circuit 400 at each of the stages 241, 243 and 245.
In each case, the individual common voltage generator 400
Is selected based on the number of stages driven by. Generally, "K" is preferably set to twice the number of stages to be driven. Therefore,

K = (2 * n) +1

Here, n is the number of stages driven by the common voltage generation circuit 400.

The second pole of the second switch 450 is connected to the second plate of the capacitor 440 and the third switch.
Connected to the first pole of 470. Third switch 470
Is connected to the reference voltage Vref. 2
The second switch 450 is controlled by a control signal on the control line 204c from the control / timing circuit 200. First and third switches 460 and 470
Is controlled by a control signal on a control line 204b from the control / timing circuit 200.

First and second PMOS transistors 32
0 and 330 form the input in the first stage 241 with a classic PMOS differential pair. Transistor 32
The output currents i320 and i330 of 0 and 330 are copied by the first to fourth NMOS transistors 340-370.
Thus, the current in the differential input stage formed by transistors 320 and 330 is as follows:

I320-i330 = g320 * (VIN +-VIN-)

Here, g 320 is the first PMOS transistor 320 and the second PMOS transistor 330
Is the transconductance of

As described above, the first and second PMOSs
Transistors 320 and 330 are both P-type transistors and their transconductances are nearly identical. Although the transconductance is highly dependent on uncontrollable manufacturing process variables, transistors 320 and 330 are both PMOS transistors and are therefore formed in the same manufacturing process step. Particularly uncontrollable manufacturing steps affect the uncontrollable transconductance parameter K'P of the PMOS transistors 320 and 330, but have the same value for both transistors.

That is, the PMOS transistors 320 and 33
Since 0 is made under the same manufacturing process step, the transconductance parameter K'P is affected to the same extent.
Therefore, this parameter takes close values and is almost the same. For the same reason, the transconductance g of the first and second NMOS transistors 340 and 350 is almost the same. Similarly, the transconductance g of the third and fourth NMOS transistors 360 and 370 is almost the same. Finally, the third and fourth PMOS for the same reason
Transconductances g of transistors 380 and 390 are almost the same.

Further, the transconductance of the first to fourth NMOS transistors 340 to 370 of the current mirror section is made proportional to increase the gain of the circuit. In particular, the third and fourth NMOS transistors 360 and 370
Are the second and first N
This is a multiple of the transconductance of MOS transistors 350 and 340. Preferably, transistors 360 and 370 are the same multiple. Therefore,

I360 = k * i330 and i370 = k * i320

Accordingly, the output PMOS transistors 380 and 390 of the load section to which the diode is connected are differential outputs, and are as follows.

VOUT + -VOUT-= (i360-i370) / g380

Here, g380 is the third PMOS PMOS.
Transistor 380 and fourth PMOS transistor
390 transconductances. Therefore, the voltage gain AV of the first stage 241 is as follows.

AV = (VOUT + -VOUT-) / (VIN + -VIN-) = K * (g320 / g380)

Further, the transconductance g of the PMOS transistor has a width W and a length 1 and is biased by a current i.

G = (2 * K'P * i * (W / l)) 1/2

Here, K′P is a PMOS transistor 320
, 330, 380 and 390 are process dependent transconductance parameters.

Finally, while the bias current of the first stage 241 of the first and second PMOS transistors 320 and 330 is Ib / 2, the first for the third and fourth PMOS transistors 380 and 390 The bias current of the stage 241 is K * Ib / 2. Thus, the gain AV for the first stage 241 is:

AV = K * [(2 * K'P * Ib (W320 / l320)) / (2 * K'P * K (Ib / 2) * (W380 / l380))] 1/2 = [( 2 * K (W320 / l320)) / (W380 / l380)] 1/2

Therefore, the gain A of the first stage 241
V is the PMOS transistors 320, 330, 380 and 39
0 is independent of the transconductance parameter K'P, which is highly dependent on uncontrollable changing manufacturing process parameters that occur during the manufacture of O.sub.0. The first, second and third stages 241, 243 and 245 are almost identical.
The first and second PMOS transistors 320 and 330 are
It can be made up of multiple transistors to form a first stage that can switch the form of the circuit inside or outside for various gain settings.

In the common mode bias circuit shown in FIG. 11, the fifth and sixth PMOS transistors 420 and 480 have the same bias current as the transistors 380 and 390 of the first stage 241 shown in FIG. Multiply. In addition, the seventh PMOS
Transistor 420 is compatible with the third and fourth PMOS transistors 380 and 390 and has a bias condition (VIN
+-VIN- = 0)

VCOM-V401 = VCOM-VOUT + = VVCOM-VOUT-

The control signal input of the signal lines 204c and 204b is such that the signal of the signal line 204c is high,
The signal of 204b does not overlap as high. Therefore, at the beginning of each cycle, the signal on signal line 204b
It is high. The capacitor 440 is charged to V402-Vref. The sixth PMO to have a large W / l ratio
Since S-transistor 480 is designed, V402 is a few millivolts above the threshold voltage. Furthermore, when the signal line 204b is high, the signal line 204a is high, thus the first stage input lines 232 and 234
Vref. Voltage V403 is the sixth PMOS
It becomes the bias voltage of transistor 480. 6th PM
The bias voltage of OS transistor 480 is approximately the correct voltage to ensure that the correct bias current is supplied to the load.

Next, when switches 460 and 470 are opened and switch 450 is closed, the fifth PMOS transistor 410 operates as a high gain voltage amplifier with a current source load to control the common voltage VCOM. . Assuming that the fifth PMOS transistor 410 is appropriately sized to supply the required bias current to the seventh PMOS transistor 420, the first, second, and third stages 241, 243 and
Due to the full output of the 245 PMOS transistors 380 and 390, the fifth PMOS transistor 410 is
A necessary current is supplied to the same gate voltage as that of the OS transistor 480. That is, when switches 460 and 470 are opened and switch 450 is closed, an inverting feedback loop is formed. The inverting feedback loop includes a capacitor 440, a fifth PMOS transistor 410, a seventh PMOS transistor 420, and a switch 450.
Therefore, even if the voltage V401 deviates from the voltage Vref,
The output of the fifth PMOS transistor 410 is the voltage Vre
Properly adjusted to return voltage V401 to be equal to f. Therefore, VCOM changes voltage V401 to voltage Vref.
Is the voltage output by the fifth PMOS transistor 410 to make it equal to Therefore,

V403 = V402 V401 = Vref

If the fifth PMOS transistor 410 cannot supply enough current to maintain the required voltage, transistor imbalance will occur. Therefore, the transconductance g410 is large. Fifth and sixth PMO
Because S transistors 410 and 480 have a large W / l ratio, V403 and V402 are very close to each other and just above the threshold voltage. Therefore, this only affects V401 at tens of millivolts.

FIG. 12 is a timing diagram showing input and output signals on the various control and signal lines shown in FIGS. In particular, as shown in FIG.
When the signal on the signal line 204a goes low, the switches 246a-246f open to open the input terminals IN +, IN + of the first, second and third stages 241, 243 and 245.
-Is disconnected from the reference voltage Vref. Next, at time t1, when the signal on the signal line 205 goes high, the switch 2
47a-247f closes. Next, the signal on the signal line 207c is low.
, Switch 286 opens. This is an operational amplifier 285
After the reset process for the above, it is permitted to start the integration operation for the next measurement cycle.

Next, at time t2, the signal line 205
Goes low, while the signal on signal line 254 goes high. Thus, the appearance of the signal on signal lines 232 and 234 from input multiplexer 230 is
It is amplified by 240 to form a signal on signal lines 242 and 244.

Next, at time t3, the signal on the signal line 254 goes low, and the switches 265 and 266 are opened to sample and hold the signals appearing on the signal lines 242 and 244, whereby the signal shown in FIG. Output the signal on lines 262 and 264.

Next, at time t4, the preamplifier 240
The signal on signal line 205 goes high again to reset the first, second and third stages 241, 243 and 245. At the same time, the signals on signal lines 206c and 207b go low, while the signals on signal lines 206a and 207a go high.
gh. The signals on signal lines 206b and 207c remain low. Thus, switches 271a and 271b are closed, switches 273a and 273b are open, switches 275a and 275b are closed, switch 283 is closed, switch 284 is open, and switch 286 continues to open. Therefore,
The falling edge of the output signal line 272 is
4 and the positive voltage step
And appear on output line 282.

Next, at time t5, the signal line 254
, 206c and 207b go high while the signals on signal lines 205, 206a and 207a go low. this is,
The output of op amp 274 is returned to its to level, thus resetting the demodulator for another measurement cycle.
Next, at time t 6, the signal on signal line 254 is again applied to resample the amplified output signal output from transducer 130 through preamplifier 240.
w Next, at time t7, the signals on signal lines 206c and 207b go low, and signal lines 206a and 207c
Remain low while signal lines 205, 206b and
The signal at 207a goes high. Thus, at time t7, switches 271a, 271b and 286 continue to open and switch 27a
3a and 273b are closed and switches 275a and 275b are open. At the same time, switch 283 closes again and switch 284 opens again. When the falling edge occurs again at the output of the signal on signal line 272 from operational amplifier 274, the signal is stored by integrator 280 and output on signal line 282 in another step.

The operation from time t8 to t10 is the same as the operation from time t2 to t4. Similarly, the operation at time t11-t13 is
The same operation as at time t5-t7 is performed. Therefore, the time t8-
The operation of t13 is performed by the integrator 28 at times t10 and t13.
0 again stores an additional step (clock) and outputs it on signal line 282. Thus, at time t13, the output of integrator 280 on signal line 282 is high for four unit steps (clocks). Next, at time t14, the A / D converter 290 switches to the signal line 282.
After converting this signal to a digital signal and outputting it to the signal line 292 to the controller 110, the signals on the signal lines 204a and 207c become high, resetting the preamplifier 240 and the integrator 280. Therefore, the electronic measurement system
100 is ready for the next measurement cycle.

Although the invention has been described with reference to particular embodiments, it is not intended that the invention be limited to this. Many substitutions and changes may be made technically without departing from the spirit of the invention.

[0098]

According to the present invention, there is provided an amplifier circuit for an electronic measurement system which can control a linear and predictable gain while achieving high speed and high gain amplification.

[Brief description of the drawings]

FIG. 1 shows a conventional electronic measurement system.

FIG. 2 shows a first embodiment of a conventional amplifier circuit used in the electronic measurement system of FIG.

FIG. 3 shows an input / output curve in the first embodiment of the amplifier circuit shown in FIG. 2;

FIG. 4 shows a second embodiment of a conventional amplifier circuit used in the electronic measurement system of FIG.

FIG. 5 shows a third embodiment of a conventional amplifier circuit used in the electronic measurement system of FIG.

FIG. 6 shows an input / output curve in the amplifier circuit shown in FIG.

FIG. 7 shows a first preferred embodiment of the electronic measurement system of the present invention.

FIG. 8 shows in detail a sample hold delay circuit, an RC timing circuit, a sample hold circuit, a demodulator, and an integrator of the first preferred embodiment of the electronic measurement system of the present invention.

FIG. 9 shows in detail the preamplifier of the electronic measurement system of the present invention.

FIG. 10 shows a first stage in the preamplifier of the present invention in detail.

FIG. 11 shows a control circuit of the preamplifier of the present invention in detail.

FIG. 12 is a timing diagram showing signals of various elements of the electronic measurement system of the present invention.

[Explanation of symbols]

 20 measurement system, 22 microprocessor controller, 30 modulator, 32 transducer, 40 amplifier circuit, 50 demodulator, 44 PMOS transistor, 46 NMOS transistor, 100 electronic measurement system, 110 controller, 120 signal generation processing circuit, 130 transducer , 140 display, 150 clock, 160 RC timing circuit, 200 control / timing circuit, 220 transmitter pulse generation circuit, 241 first stage, 243 second stage, 245 third stage, 250 sample hold delay circuit, 260 sample hold circuit , 270 demodulator, 280 integrator, 290 A / D converter, 400 common voltage supply circuit

Claims (4)

[Claims] 1. An electronic measurement system amplifier circuit for amplifying a two-phase electric signal indicating a relative or absolute position output from a transducer of an electronic measurement system. A source common differential amplifying unit configured by a type transistor; a load unit configured by a P-type transistor that outputs a two-phase amplified electric signal to the outside based on the amplified two-phase electric signal; An amplifier circuit for an electronic measurement system, comprising: a current mirror section configured by an N-type transistor connecting between the common source differential amplifier section and the load section. 2. The amplifying circuit for an electronic measurement system according to claim 1, further comprising a common voltage supply circuit including a P-type transistor for supplying a common voltage to said load section. 3. An amplifier circuit for an electronic measurement system, wherein a plurality of amplifier circuits for an electronic measurement system according to claim 1 and 2 are connected in series. 4. The amplifier circuit for an electronic measurement system according to claim 1, wherein all circuit elements are integrated on one IC chip.