JPH103793A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the speed of writing operation of a nonvolatile semiconductor memory having a floating gate. SOLUTION: A reference transistor 31 is connected in parallel with a memory cell transistor 30, and a word line 35 and a source line 36 are respectively connected in common. A signal potential Vsig corresponding to storage information is applied to a floating gate of the reference transistor 31, and an ON- resistance value is fixed. A writing pulse ϕw is applied to the memory cell transistor 30 and the reference transistor 31 and a current is made to flow, and electric charge is injected to a floating gate of the memory cell transistor 30. At the same time, writing is stopped at the time of coincidence of both potentials when reading out potentials of a drain side of the memory cell transistor 30 and the reference transistor 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate.

[0002]

2. Description of the Related Art An electrically erasable programmable ROM (EEPROM: Elmer) in which a memory cell comprises a single transistor.
(ectrically Erasable Programmable ROM)
Each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. Then, data is read by detecting a difference in operation characteristics of the memory cell transistor depending on whether or not charge is injected into the floating gate.

FIG. 4 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
FIG. 5 is a cross-sectional view taken along the line XX. This figure shows a split gate structure in which a part of the control gate is arranged side by side with the floating gate. A plurality of isolation regions 2 made of a selectively thick oxide film (LOCOS) are formed in a strip shape in a surface region of a P-type silicon substrate 1 to partition an element region. A floating gate 4 is arranged on a silicon substrate 1 with an oxide film 3 interposed between adjacent isolation regions 2.
This floating gate 4 is arranged independently for each memory cell. Also, the oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 and makes the end of the floating gate 4 an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation. On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, control gates 6 are arranged corresponding to each column of the floating gates 4. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other. N-type first diffusion layers 7 and second diffusion layers 8 are formed in a substrate region between control gates 6 and a substrate region between floating gates 4. The first diffusion layers 7 are surrounded by the isolation regions 2 between the control gates 6 and are independent of each other.
The second diffusion layer 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, first diffusion layer 7, and second diffusion layer 8 constitute a memory cell transistor. Then, aluminum wiring 10 is arranged on control gate 6 via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to first diffusion layer 7 through contact hole 11.

In the case of such a memory cell transistor having a double gate structure, the on-resistance value varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is varied, and the difference in operating characteristics of each memory cell transistor caused by this is associated with data to be stored. I have.

FIG. 6 is a circuit diagram of the memory cell portion shown in FIG. In this figure, memory cells are divided into 3 rows × 3
This shows a case in which they are arranged in columns. In the memory cell transistor 20 having the double gate structure, the control gate 6 is connected to the word line 21 and the first diffusion layer 7 and the second diffusion layer 8
Are connected to the bit line 22 and the source line 23, respectively. Each bit line 22 is connected to a select transistor 24
Are connected to the data lines 25, and each source line 23
Each is connected to a power line 26. Normally, the control gate 6 itself of each memory cell transistor 20 is a word line 21, and the second diffusion layer 8 itself continuous in the direction in which the control gate 6 extends is a source line 23. Then, the aluminum wiring 10 connected to the first diffusion layer 7 is operated as the bit line 22.

The row decoder 27 is connected to each word line 21, and selects one of the word lines 21 in response to the row selection information, whereby the memory cell transistor 20 is selected.
Activate a specific row of The column decoder 28 is connected to each of the selection transistors 24 and
Is turned on in response to the column selection information,
Activate the memory cell transistor 20 in a specific column.

When data is written to these memory cell transistors 20, the data line 25 applies a ground potential (eg, 0 V) to the memory cell transistors 20.
And a power supply potential for writing (for example, 12 V) is applied from the power line 26. Thereby, the row decoder 27
In the specific memory cell transistor 20 activated by the selection operation of the column decoder 28, data is written, that is, charge is injected into the floating gate 4. When data written in the memory cell transistor 20 is read, a power supply potential (for example, 2 V) for reading is applied from the data line 25 to the memory cell transistor 20, and a ground potential (for example, 0 V) is applied from the power line 26. Is applied. At this time, by detecting the value of the current flowing through the specific memory cell transistor 20 activated by the selection operation of the row decoder 27 and the column decoder 28, data is read, that is, the on-resistance value of the memory cell transistor 20 is detected. Is performed.

[0008]

In the case of the memory cell transistor 20 having the floating gate 4, analog information can be stored by utilizing the fact that the on-resistance changes according to the amount of charge injected into the floating gate 4. It is possible. In this case, since the write characteristics of each memory cell transistor 20 are not necessarily uniform, it is difficult to write analog information to a plurality of memory cell transistors 20 with good reproducibility by controlling only write conditions. is there. Therefore, it has been considered that the writing operation (charge injection) is stopped when the reading result becomes a desired value while repeating stepwise writing and reading for each memory cell transistor 20.

However, the memory cell transistor 2
To increase the accuracy of writing data to 0, the amount of writing in one cycle of the writing operation must be reduced, and it is difficult to complete the writing in a short time. That is, although the resolution of the memory cell transistor 20 increases as the writing amount decreases in one cycle of the writing operation, the time required to complete the writing of the desired amount increases, and the operation speed decreases. Have.

Accordingly, an object of the present invention is to write data with high precision without lowering the operation speed.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is that a control gate is disposed so as to overlap an electrically independent floating gate. A memory cell transistor in which a source region and a drain region are arranged adjacent to a floating gate and a control gate; the memory cell transistor has the same structure as that of the memory cell transistor, and is connected in parallel to the memory cell transistor so that the floating gate corresponds to stored information; A reference transistor to which a signal potential to be applied is applied; a write circuit for applying a fixed potential difference between the memory cell transistor and the source / drain of the reference transistor to inject electric charge into a floating gate of the memory cell transistor; A selection circuit that applies a predetermined voltage to a control gate of the transistor and the reference transistor to simultaneously activate the memory cell transistor and the reference transistor, and a comparison circuit that compares the amount of current flowing through the memory cell transistor and the reference transistor. And that the potential difference given from the write circuit to the memory cell transistor and the reference transistor is changed in response to a comparison result of the comparison circuit.

This makes it possible to constantly monitor the state of writing data to the memory cell transistor, and it is not necessary to repeat the writing operation and the reading operation when writing data. Therefore, the data writing time is reduced.

[0013]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
Is a timing chart for explaining the operation. In these figures, only a single memory cell is shown, and a circuit for selecting a column is omitted. The nonvolatile semiconductor memory device of the present invention includes a memory cell transistor 30, a reference transistor 31, a write pulse generation circuit 32,
A selection signal generation circuit 33 and a comparison circuit 34 are included. Memory cell transistor 30 and reference transistor 3
1 are the memory cell transistors 20 shown in FIG.
And has a floating gate and a control gate. However, an electrode is connected to the floating gate of the reference transistor 31 so that the potential can be directly controlled by a signal potential Vsig corresponding to write data. The control gates of the memory cell transistor 30 and the reference transistor 31 are connected to a common word line 35, and open and close simultaneously upon receiving the selection signal LS. Further, the memory cell transistor 30 and the reference transistor 31
Are connected between the source line 36 and the resistors 37 and 38, respectively. In a data write operation, a write pulse φw is applied from the source line 36, and at the same time, a ground potential Vgnd is applied via the resistors 37 and 38.

The write pulse generation circuit 32 generates a write pulse φw having a constant period in response to a write start instruction supplied from outside the device, and supplies the write pulse φw to the source line 36. The period and peak value of the write pulse φw are set according to the operation characteristics and operation purpose of the memory cell transistor 20. For example, when writing to the memory cell transistor 30 can be performed at a low voltage, the peak value is set low, and when the operation is performed to increase the resolution, the cycle is set short. The selection signal generation circuit 33 is connected to the word line 35, and raises the selection signal LS in response to a write start instruction. The comparator 34 receives the potential Vp1 at the connection point between the memory cell transistor 30 and the resistor 37 and the potential Vp2 at the connection point between the reference transistor 31 and the resistor 38, and writes the comparison result as a write stop signal WS
To the write pulse generation circuit 32. With the rise of the write stop signal WS, the output of the write pulse φw of the write pulse generation circuit 32 is stopped.

When the selection signal LS rises and a write pulse φw is applied in response to the write instruction, the control gates of the memory cell transistor 30 and the reference transistor 31 are turned on, and the memory cell transistor 30 and the reference transistor 31 are turned on. Current flows through When the memory cell transistor 30 is in a state where data is not written first (a state where no electric charge is stored in the floating gate), the on-resistance value is small and the flowing current is large. When a current starts to flow through the memory cell transistor 30, hot electrons generated near the drain are accelerated in the source region in the channel region, pass through the gate insulating film, and are injected into the floating gate. As a result, the charge amount Q injected into the floating gate of the memory cell transistor 30 gradually increases with time in accordance with the rise of the write pulse φw. Then, depending on the amount of charge injected into the floating gate,
The on-resistance value of the memory cell transistor 30 increases, and the potential Vp1 determined by the ratio between the on-resistance value and the resistance value of the resistor 37 gradually decreases as shown in FIG. On the other hand, the reference transistor 31
Since the potential of the floating gate is fixed at the signal potential Vsig, the on-resistance is always constant regardless of the passage of time, and the potential Vp2 determined by the ratio of this on-resistance to the resistance of the resistor 38 Also, as shown in FIG.
It will be constant.

Therefore, the potential Vp1 on the memory cell transistor 30 side and the potential Vp2 on the reference transistor 31 side
Are compared by the comparator 34, and when the potential Vp1 drops to the potential Vp2, the write stop signal WS is raised to stop the supply of the write pulse φw. Therefore, charge injection into the floating gate of the memory cell transistor 30 is repeated until the on-resistance value of the memory cell transistor 30 matches the on-resistance value of the reference transistor 31 determined by the signal potential Vsig. At this time, charge injection into the floating gate of the memory cell transistor 30 is performed while monitoring a change in the on-resistance value of the memory cell transistor 30, so that there is no need to repeat writing and reading of data.

The information stored in the memory cell transistor 30 as described above is read out by detecting a current flowing to the resistor 37 through the memory cell transistor 30 when a constant potential is applied to the source line 36. FIG. 3 shows a second embodiment of the nonvolatile semiconductor memory device according to the present invention.
13 is a circuit diagram showing the embodiment, and shows a configuration in the case where memory cell transistors 30 are arranged in 3 rows × 3 columns. FIG.

The memory cell transistor 30 and the reference transistor 31 are the same as those in FIG. 1, and each have a floating gate and a control gate. The memory cell transistors 30 arranged in 3 rows × 3 columns have a common word line 41 and a common source line 42 for each row.
Connected to. Each source line 42 is connected to a power line 43
Connected to. In addition, the memory cell transistor 30
Each column is connected to a common bit line 44. Each bit line 44 is connected to a data line 46 via a selection transistor 45. Reference transistor 31
Are arranged in parallel, one for each row of the memory cell transistors 30, and are connected to a word line 41 and a source line 42 that are common to each memory cell transistor 30. Further, each reference transistor 31 is connected to a reference line 47 arranged in parallel with the bit line 44. The data input line 48 is connected to the floating gate of each reference transistor 31, and the signal potential Vsig associated with the stored data is applied. The structures of the memory cell transistor 30 and the reference transistor 31 are the same as those in FIGS. 4 and 5, and the floating gate and the control gate are arranged in each row so as to be line-symmetric with the adjacent row.

The row decoder 51 generates row selection signals LS1 to LS3 for selecting a specific row in response to the row selection information, and supplies them to each word line 41. This row decoder 51
Is equivalent to the selection signal generation circuit 33 of FIG.
As a result, the control gates of the specific row (the same row) of the memory cell transistor 30 and the reference transistor 31 are simultaneously turned on. Column decoder 52
Generates column selection signals CS1 to CS3 for selecting a specific column in response to column selection information, and supplies them to the gate of each selection transistor 45. As a result, a specific column of the memory cell transistor 30 is activated, and the bit line 44 in the selected column is connected to the data line 46. The comparator 53 compares the potential Vp1 of the data line 46 to which the resistor 54 is connected with the potential Vp2 of the reference line 47 to which the resistor 55 is connected,
The comparison result is output as a write stop signal WS.
That is, the comparator 53 calculates the potential Vp1 determined by the ratio between the on-resistance value of the selected memory cell transistor 30 and the resistance value of the resistor 54, the on-resistance value of the selected reference transistor 31, and the resistance of the resistor 55. The value is compared with a potential Vp2 determined by a ratio with the value. Write pulse generation circuit 56
Is a write pulse φw having a predetermined period and a peak value.
And supplies it to the power line 43. The write pulse generation circuit 56 is the same as the write pulse generation circuit 32 of FIG. 1, and is configured to stop the generation of the write pulse φw in response to the write stop signal WS supplied from the comparator 53. You. Note that the write pulse φw is
The voltage is applied to all the columns of the memory cell transistors 30 at the same time. In the non-selected columns, the potential of the bit line 44 is set high so that the control gate of the memory cell transistor 30 is not turned on. Does not occur.

When a write instruction is input, first,
One of the row selection signals LS1 to LS3 and the column selection signal CS1
To CS3 are activated, and the specific memory cell transistor 30 and the reference transistor 31 are selected. The same row is selected for the memory cell transistor 30 and the reference transistor 31. The selected memory cell transistor 30 is connected to the bit line 44
And the data line 46 is connected via the selection transistor 45, and the control gate is turned on. At the same time, the control gate of the selected reference transistor 31 is turned on. After the selection operation of the memory cell transistor 30 and the reference transistor 31 by the row decoder 51 and the column decoder 52 is completed, the circuit configuration becomes the same as that of FIG. That is, by applying the write pulse φw from the power line 43 to the memory cell transistor 30, charges are injected into the floating gate of the memory cell transistor 30, and the on-resistance value of the memory cell transistor 30 decreases according to the amount of injection. Then, the potential V determined by the ratio between the on-resistance value of the memory cell transistor 30 and the resistance value of the resistor 54 is determined.
p1 decreases, and the potential V determined by the ratio between the on-resistance value of the reference transistor 31 and the resistance value of the resistor 55 is reduced.
The supply of the write pulse φw is stopped at the time when the value matches p2. Therefore, the row decoder 51 and the column decoder 5
The on-resistance value of the specific memory cell transistor 30 specified by the selection operation 2 matches the on-resistance value of the reference transistor 31 when the signal potential Vsig is applied to the floating gate.

In the above embodiment, the case where the memory cell transistors 30 are arranged in 3 rows × 3 columns is exemplified. However, it is easy to arrange the memory cell transistors 30 in 4 rows or more or 4 columns or more. . Further, the reference transistors 31 do not necessarily need to be provided for each row, and one reference transistor 31 may be commonly used for each row of the memory cell transistors 30. In this case, the circuit is liable to be affected by variations in characteristics of each row, but the circuit scale can be reduced.

[0022]

According to the present invention, in a memory cell transistor having a floating gate and a control gate, analog information or multi-valued information can be stored with good reproducibility without lowering the data writing speed. Therefore, even data including time information, such as an audio signal, can be directly stored without using a time axis conversion means, so that the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a timing chart illustrating an operation of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 5 is a sectional view taken along line XX of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Isolation region 3, 5, 9 Oxide film 4 Floating gate 6 Control gate 7 First diffusion layer 8 Second diffusion layer 10 Aluminum wiring 11 Contact hole 20, 30 Memory cell transistor 21, 35, 41 Word line 22, 44 bit line 23, 36, 42 source line 24, 45 selection transistor 25, 46 data line 26, 36, 43 power line 27, 51 row decoder 28, 52 column decoder 31 reference transistor 32, 56 write pulse generation circuit 33 selection signal generation Circuit 34, 53 Comparator 37, 38, 54, 55 Resistor 47 Reference line 48 Data input line

Claims (2)

[Claims] 1. A memory cell transistor in which a control gate is arranged so as to overlap an electrically independent floating gate, and a source region and a drain region are arranged adjacent to the floating gate and the control gate. A reference transistor having a structure, connected in parallel to the memory cell transistor, and having a floating gate to which a signal potential associated with stored information is applied; and a source / source of the memory cell transistor and the reference transistor.
A write circuit for applying a certain potential difference between the drains to inject charges into the floating gate of the memory cell transistor; and applying a predetermined voltage to the control gates of the memory cell transistor and the reference transistor to apply a predetermined voltage to the memory cell transistor and the reference. A selection circuit for simultaneously activating the transistors,
A comparison circuit for comparing the amount of current flowing through the memory cell transistor and the reference transistor, wherein a potential difference given to the memory cell transistor and the reference transistor from a write circuit in response to a comparison result of the comparison circuit A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. The method according to claim 1, wherein a plurality of memory cell transistors are connected in parallel to one reference transistor, and a potential difference is selectively applied from the write circuit to one of the plurality of memory cell transistors. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: