JPH10341042A - Method for bonding semiconductor substrates through minute area - Google Patents

Method for bonding semiconductor substrates through minute area

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Publication number
JPH10341042A
JPH10341042A JP14938197A JP14938197A JPH10341042A JP H10341042 A JPH10341042 A JP H10341042A JP 14938197 A JP14938197 A JP 14938197A JP 14938197 A JP14938197 A JP 14938197A JP H10341042 A JPH10341042 A JP H10341042A
Authority
JP
Japan
Prior art keywords
bonding
tightly
substrate
substrates
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14938197A
Other languages
Japanese (ja)
Inventor
Masatake Akaike
正剛 赤池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP14938197A priority Critical patent/JPH10341042A/en
Publication of JPH10341042A publication Critical patent/JPH10341042A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To enhance bonding strength even if the electric coupling area is small by decreasing the residual stress through a method for applying a pressing force while observing an I-V characteristic chart under a state where the electric coupling faces and bonding parts face each other, respectively. SOLUTION: Substrates 1, 2 are disposed oppositely each other and heat treated while being applied with a load in a pressure reduced hydrogen gas flow. Consequently, bonding members 10, 11 abutting each other are bonded gradually through plastic deformation due to creep phenomenon proceeding with time. Plastic deformation proceeds until electric bonding faces 3, 4 are brought into contact with each other and bonded tightly. During plastic deformation, I-V characteristic chart presented on a curve tracer can be observed. Application of load is interrupted when a best I-V characteristic chart is presented on the curve tracer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は同種あるいは異種材
料基板間の微小領域での接着及び電気的結合を低温で行
う密着接合法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adhesive bonding method for bonding and electrical bonding in a small area between substrates of the same or different materials at a low temperature.

【0002】[0002]

【従来の技術】従来、光放出素子の作製のために異種半
導体同士を直接接合させる方法として、応用物理第63
巻第1号(和田浩、上條健、p.53,1994年)に
記載されているように、InP/GaAs及びInP/
Siの組み合わせの接合は、非接合面を清浄化した後、
基板に重りを載せて水素雰囲気中700℃で30分間熱
処理することによって得られている。
2. Description of the Related Art Conventionally, as a method of directly joining different kinds of semiconductors to each other for manufacturing a light emitting device, there is a method applied in Applied Physics No. 63
Vol. 1 (Hiroshi Wada, Ken Kamijo, p. 53, 1994), InP / GaAs and InP /
Bonding of the combination of Si, after cleaning the non-bonded surface,
It is obtained by placing a weight on a substrate and performing a heat treatment at 700 ° C. for 30 minutes in a hydrogen atmosphere.

【0003】そして、Appl. Phys. Lett. (Lincaln La
b. Z.L.Lian, 56(8), 19, Feb. 1990, p.737) に記載さ
れているように、InP/GaAsの組み合わせの接合
は、被接合表面を清浄化し、その後グラファイト/クオ
ーツ反応器の中で水素雰囲気中750℃で熱処理するこ
とによって得られている。
[0003] Appl. Phys. Lett. (Lincaln La
b. As described in ZLLian, 56 (8), 19, Feb. 1990, p. 737), bonding of the InP / GaAs combination cleans the surface to be bonded and then the graphite / quartz reactor. In a hydrogen atmosphere at 750 ° C.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来例では接合が約700℃の高温で、かつ基板同士で接
合を行うため以下のような欠点があった。
However, in the above-mentioned conventional example, since the bonding is performed at a high temperature of about 700 ° C. and the substrates are bonded to each other, there are the following disadvantages.

【0005】1.熱膨張係数の異なる異種半導体同士の
接合する場合、高温で接合後室温までの冷却中に、ある
いは冷却後に接合基板が反り返る現象が生ずる。すなわ
ち残留応力が生ずる。
[0005] 1. In the case of joining different kinds of semiconductors having different coefficients of thermal expansion, a phenomenon occurs in which the joined substrate warps during cooling to room temperature after joining at a high temperature or after cooling. That is, a residual stress occurs.

【0006】2.電気的な結合と、機械的な接合強度
(引き剥されないための接合強度)を兼ね合わせた接合
であるため、接合面積を小さくすることは接合強度を小
さくすることになる。このため、該接合強度の低下は、
プロセス中における接合個所での剥離の要因になり、接
合面積を小さくすることは困難である。
[0006] 2. Since bonding is a combination of electrical bonding and mechanical bonding strength (bonding strength for preventing peeling), reducing the bonding area decreases bonding strength. For this reason, the decrease in the bonding strength
It becomes a factor of peeling at the joining portion during the process, and it is difficult to reduce the joining area.

【0007】本願発明は上記従来の方法の欠点を解消し
て残留応力が小さくまた電気的結合面積が小さくても接
合強度の大きな接合方法を提供するものである。
The present invention solves the above-mentioned drawbacks of the conventional method and provides a bonding method having a high bonding strength with a small residual stress and a small electric coupling area.

【0008】[0008]

【課題を解決するための手段】本発明者等は上記課題を
解決するため鋭意検討を行い本発明に到達した。即ち、
本発明は以下の発明及び以下の実施態様を含む。
Means for Solving the Problems The present inventors have made intensive studies to solve the above-mentioned problems, and have reached the present invention. That is,
The present invention includes the following inventions and the following embodiments.

【0009】(a) 同種あるいは異種材料から成る半
導体基板間の微小領域での電気的接合(以後、電気的結
合と呼ぶ)を得る方法において、電気的結合を生ずる密
着接合領域と、接合力を与えるための接着素子から成る
接合領域と、I−V特性線図をカーブトレーサーで観測
しながら密着接合する構成から成り、該構成が(1)該
接合領域に絶縁膜を形成する過程と、(2)該絶縁膜上
に接合力を与えるための接着素子を形成する過程と、
(3)該微小領域での該密着結合領域の電気的結合面と
なる部分に微小な点状の傷を1つあるいは複数個形成す
る過程と、(4)該微小領域での該密着結合領域の該微
小な点状の傷をエッチング液によって異方性エッチング
によるエッチピットに形成する過程と、(5)両接合用
基板の接合面に対して反対側の面に、I−V特性線図観
測用の電極を形成する過程と、(6)該同種あるいは異
種材料基板上の該接着素子同士及び該密着結合領域同士
がそれぞれ相対向するように整合し、該同種あるいは異
種材料基板同士に押圧力を印加する過程、及び(7)該
押圧力を印加する過程において、該電気的結合面での電
気的結合によって生ずるI−V特性をカーブトレーサで
電気的結合の状況を観察するI−V特性線図観測過程か
ら成る同種あるいは異種材料基板間の電気的結合を常温
乃至250℃までの低温で行うことを特徴とする半導体
基板間の密着接合方法。
(A) In a method for obtaining electrical bonding (hereinafter referred to as “electrical coupling”) in a microscopic region between semiconductor substrates made of the same or different materials, a method is used in which an adhesive bonding region that produces electrical coupling and a bonding force are reduced. (1) a process of forming an insulating film in the bonding region; and (b) forming a bonding region formed of an adhesive element to be applied and closely bonding while observing an IV characteristic diagram with a curve tracer. 2) forming an adhesive element for providing a bonding force on the insulating film;
(3) a step of forming one or a plurality of small point-like scratches in a portion of the minute region that becomes an electrical coupling surface of the tightly-bonded region; and (4) a step of forming the tightly-bonded region in the minute region. And (5) an IV characteristic diagram showing the process of forming the minute point-like scratches into etch pits by anisotropic etching using an etchant, and And (6) aligning the adhesive elements and the tightly-bonded regions on the same or different material substrate so that they face each other, and pressing the same or different material substrate. In the step of applying pressure and (7) the step of applying the pressing force, the IV characteristic generated by the electric coupling on the electric coupling surface is used to observe the state of the electric coupling with a curve tracer. Homogeneous or composed of characteristic diagram observation process Adhesion bonding method between the semiconductor substrate and performing at a low temperature of the electrical coupling between the different material substrate to a room temperature to 250 ° C..

【0010】(b) 該半導体基板が、Si,In P,
GaAs,GaNから選ばれた少なくとも1種であり、
またはこれらの半導体基板上に成膜した化合物半導体か
ら成ることを特徴とする(a)記載の半導体基板間の密
着接合法。
[0010] (b) the semiconductor substrate, Si, I n P,
At least one selected from GaAs and GaN,
Alternatively, the method according to (a), wherein the semiconductor substrate is made of a compound semiconductor formed on the semiconductor substrate.

【0011】(c) 電気的結合を生ずる密着結合領域
が平面状、あるいは1つあるいは複数のV状の溝から成
ることを特徴とする(a)記載の半導体基板間の密着接
合法。
(C) The method for tightly bonding semiconductor substrates according to (a), wherein the tightly-bonded region where the electrical connection is made is made up of one or a plurality of V-shaped grooves.

【0012】(d) 該接合領域における接着素子同士
が該押圧力によって常温乃至250℃の低温で互いに接
合し、該同種あるいは異種材料基板間の接合力を得るこ
とを特徴とする(a)記載の半導体基板間の密着接合
法。
(D) The bonding elements in the bonding area are bonded to each other at a low temperature of room temperature to 250 ° C. by the pressing force to obtain a bonding force between the substrates of the same or different materials. Bonding method between semiconductor substrates.

【0013】(e) 該接着素子が塑性変形能を有する
材料から成るものであることを特徴とする(a)記載の
半導体基板間の密着接合法。
(E) The method according to (a), wherein the adhesive element is made of a material having plastic deformability.

【0014】(f) 該塑性変形を有する材料が金属材
料であることを特徴とする(e)記載の半導体基板間の
密着接合法。
(F) The method according to (e), wherein the material having plastic deformation is a metal material.

【0015】(g) 該金属材料がAl,Au,In,
Ga,Sn,Cu,Ti,Zn,Pbの少なくとも1種
であることを特徴とする(f)記載の半導体基板間の密
着接合法。
(G) The metal material is Al, Au, In,
The method of (f), wherein the semiconductor substrate is at least one of Ga, Sn, Cu, Ti, Zn, and Pb.

【0016】(h) 絶縁膜がSi酸化膜、Si窒化
膜、Al酸化膜より選ばれた少なくとも1種であること
を特徴とする(a)記載の半導体基板間の密着接合法。
(H) The method according to (a), wherein the insulating film is at least one selected from a Si oxide film, a Si nitride film, and an Al oxide film.

【0017】(i) 該接着素子が凸状、球状、あるい
は半球状であることを特徴とする(a)記載の半導体基
板間の密着接合法。
(I) The method according to (a), wherein the adhesive element is convex, spherical or hemispherical.

【0018】(j) 該押圧力印加によって該密着結合
領域(電気的結合部)を密封することを特徴とする
(a)記載の半導体基板間の密着接合法。
(J) The method for tightly bonding semiconductor substrates according to (a), wherein the tightly bonded region (electrically connected portion) is sealed by applying the pressing force.

【0019】(k) 該押圧力を実質的に酸素を含まな
い雰囲気中で該押圧印加を行うことによって該密着結合
領域(電気的結合部)を雰囲気中に封止することを特徴
とする(a)記載の半導体基板間の密着接合法。
(K) The tightly-bonded region (electrically-coupled portion) is sealed in an atmosphere by applying the pressure in an atmosphere substantially free of oxygen. a) The method for tightly bonding between semiconductor substrates described in a).

【0020】(l) 該実質的に酸素を含まない雰囲気
が真空中、減圧中、あるいは減圧した還元ガスあるいは
不活性ガス中であることを特徴とする(k)記載の半導
体基板間の密着接合法。
(1) The close contact between the semiconductor substrates according to (k), wherein the substantially oxygen-free atmosphere is in a vacuum, under reduced pressure, or in a reduced or inert gas under reduced pressure. legal.

【0021】(m) 該還元ガスあるいは不活性ガスが
水素ガス、アルゴンガス、窒素ガスまたはこれ等の混合
物であることを特徴とする(l)記載の密着接合法。
(M) The contact bonding method according to (1), wherein the reducing gas or the inert gas is hydrogen gas, argon gas, nitrogen gas or a mixture thereof.

【0022】[0022]

【発明の実施の形態】上記の目的を達成するため、本出
願に係わる第1の発明は塑性変形能を有する材料同士の
接合のみにより基板同士に接合力を与え、そして該接合
力で半導体同士を密着させ、該半導体間に電気的に結合
を与える。該塑性変形を有する材料同士の接合過程での
該材料の塑性変形中、すなわち該半導体間の電気的結合
過程中に、該半導体間のI−V特性線図を観察しながら
最も良好な電気的結合が生じた時点で該接合過程を終了
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to achieve the above object, a first invention according to the present application provides a bonding force between substrates only by bonding materials having plastic deformability, and a bonding force between semiconductors by the bonding force. Are brought into close contact with each other to provide electrical coupling between the semiconductors. During the plastic deformation of the material in the joining process of the materials having the plastic deformation, that is, during the electrical coupling process between the semiconductors, the best electrical characteristics are observed while observing the IV characteristic diagram between the semiconductors. The joining process is terminated when the joining occurs.

【0023】さて、上記手段において、まず一方の半導
体基板上に半導体同士の電気的結合を生ずる密着結合領
域及び接合力を与える接着素子から成る接合領域をそれ
ぞれ設け、他方の半導体基板上にも同様に、半導体同士
の電気的結合を生ずる領域及び接合力を与える領域を設
ける。そして、該密着結合領域及び接着素子から成る該
接合領域同士がそれぞれ相対向するように該両基板を位
置決めし、この後、両側から該両基板に荷重を印加す
る。
In the above means, first, a tightly-bonded region for forming an electrical connection between semiconductors and a bonding region comprising an adhesive element for providing a bonding force are provided on one semiconductor substrate, and the same is applied to the other semiconductor substrate. In addition, a region where the semiconductors are electrically coupled to each other and a region where a bonding force is applied are provided. Then, the two substrates are positioned so that the tightly bonded region and the bonding region formed of the adhesive element face each other, and thereafter, a load is applied to both the substrates from both sides.

【0024】該荷重印加により接合領域は塑性変形を生
じながら、同時に接合し、そして密着結合領域は原子オ
ーダーの距離まで近づき電気的結合を生じ始める。この
とき、該両基板間のI−V特性を観察しながら最も良好
な該I−V特性が生じた時点で、該荷重印加を停止す
る。
The application of the load causes the joining region to undergo plastic deformation while joining at the same time, and the tightly joined region approaches the distance on the order of atoms and starts to produce electrical coupling. At this time, the application of the load is stopped when the best IV characteristic occurs while observing the IV characteristic between the two substrates.

【0025】半導体材料は低温において塑性変形を生じ
ないことから、該荷重印加によって、まず最初に接合領
域の塑性変形能を有する材料が塑性変形を開始し、さら
に荷重を増加して行った場合、該半導体同士の間で密着
が生ずる。この半導体同士の密着が進行中、最も良好な
該I−V特性が生じた時点で該接合を完了する。すなわ
ち、該荷重印加を停止することにより該半導体基板の該
電気的結合個所に過度の圧縮応力を印加しないで済むこ
とになり、該電気的結合個所を保護することになる。こ
の時点で印加荷重を除去した場合、該接合領域は接合し
たままの状態を保持し、該半導体同士は密着結合した状
態を維持する。すなわち、半導体同士の密着結合領域で
圧縮力を、そして結合領域で引張力をそれぞれ担うよう
に構成している。したがって、該電気的結合個所での半
導体同士は互いに接合力を有する必要がなく、密着によ
って電気的結合をするだけでよい。このため、該電気的
結合面積を、限りなく微小にすることが可能となる。
Since the semiconductor material does not undergo plastic deformation at a low temperature, by applying the load, first, the material having the plastic deformation ability in the joining region starts plastic deformation, and when the load is further increased, Adhesion occurs between the semiconductors. While the adhesion between the semiconductors is in progress, the bonding is completed when the best IV characteristic occurs. That is, by stopping the application of the load, it is not necessary to apply an excessive compressive stress to the electrical coupling portion of the semiconductor substrate, and the electrical coupling portion is protected. When the applied load is removed at this time, the bonding region maintains a state of being bonded, and the semiconductors maintain a state of being tightly bonded. That is, the semiconductor device is configured to bear a compressive force in the tightly bonded region and a tensile force in the bonded region. Therefore, it is not necessary for the semiconductors at the electrical coupling points to have a bonding force with each other, and it is only necessary to perform electrical coupling by close contact. Therefore, the electrical coupling area can be made extremely small.

【0026】なお、上記該接合過程後のプロセスにおい
て、加熱プロセスを生ずる場合、ボイルシャルルの法則
によって生ずる該密着結合領域空間での陽圧発生による
該電気的結合の剥れを防止するため、該接合は減圧ガス
雰囲気中で行うことが望ましい。
When a heating process is performed in the process after the joining process, the electrical connection is prevented from peeling off due to the generation of a positive pressure in the space of the tightly-bonded region caused by the Boyle-Charles law. The joining is desirably performed in a reduced-pressure gas atmosphere.

【0027】さらに、一方の半導体基板の密着結合領域
に異方性エッチングによる一つあるいは複数のエッチピ
ットを形成することによって、該電気的結合面積を微小
化することができ、電気的結合個所での電流密度を増加
することが可能となる。該エッチピットを形成する際、
該エッチピットを必要とする個所に微小な点状の傷を付
けることにより、その後のエッチングによって該エッチ
ピットを形成可能となる。そして、該エッチピットの大
きさは該エッチング時間を制御することにより制御可能
となる。
Further, by forming one or a plurality of etch pits by anisotropic etching in the tightly bonded region of one semiconductor substrate, the electrical coupling area can be reduced, and the electrical coupling area can be reduced. Can be increased. When forming the etch pit,
By forming a small point-like scratch at a place where the etch pit is required, the etch pit can be formed by subsequent etching. Then, the size of the etch pit can be controlled by controlling the etching time.

【0028】上記手法によって同様あるいは異種半導体
基板同士の接合において微小面積での電気的結合を可能
にし、これにより同一電流値で流した場合に該電気的結
合個所での電流密度を増加することが可能となる。
According to the above-mentioned method, it is possible to electrically connect a similar or different semiconductor substrate with each other in a very small area at the time of bonding, thereby increasing the current density at the electrical connection point when the same current value is applied. It becomes possible.

【0029】なお、本発明で微小面積で電気的結合する
との意味特に数値的限定はないが、電気的接合部分が約
5μ径またはそれ以下で、本発明の方法ではサブミクロ
ン径の該電気的結合面積での結合も十分にできる。
In the present invention, the meaning of electrical coupling in a small area is not particularly limited numerically. However, in the method of the present invention, the electrical connection portion is about 5 μm or less in diameter, and the method of the present invention has a submicron diameter. The bonding in the bonding area can be sufficiently performed.

【0030】本発明で接合する基板は電気的に基板を接
合する必要のある同種または異種の基板であり、最も典
型的には半導体基板である。半導体基板は通常使用され
ている公知の基板であって特に制限はないが、Si,I
n P,GaAs,GaNから選ばれた少なくとも1種で
あり、またはこれらの半導体基板上にAlAs、GaA
lAs、GaInAsPなどを成膜した化合物半導体が
用いられる。
The substrates to be bonded in the present invention are the same or different types of substrates that need to be electrically bonded to each other, and are most typically semiconductor substrates. The semiconductor substrate is a commonly used well-known substrate and is not particularly limited.
n P, GaAs, at least one selected from GaN, or AlAs these semiconductor substrates, GaA
A compound semiconductor formed of GaAs, GaInAsP, or the like is used.

【0031】接合領域に形成される絶縁膜は半導体の製
造に通常用いられる絶縁膜であれば特に制限はないが、
例えばSi酸化膜、Al酸化膜及びSi窒化膜が例示さ
れる。
The insulating film formed in the bonding region is not particularly limited as long as it is an insulating film usually used for manufacturing a semiconductor.
For example, a Si oxide film, an Al oxide film, and a Si nitride film are exemplified.

【0032】本発明の方法において絶縁膜上に形成され
る接着素子は塑性変形能を有する材料からであれば利用
でき、好ましくは金属材料であり、特に好ましくは該金
属材料がAl,Au,In,Ga,Sn,Cu,Ti,
Zn,Pbの少なくとも1種またはその混合物が用いら
れる。またポリイミド等の樹脂も使用可能である。
The adhesive element formed on the insulating film in the method of the present invention can be used as long as it is made of a material having a plastic deformability, and is preferably a metal material, and particularly preferably the metal material is Al, Au, In. , Ga, Sn, Cu, Ti,
At least one of Zn and Pb or a mixture thereof is used. Also, a resin such as polyimide can be used.

【0033】接着素子を押圧する温度は20℃〜250
℃、好ましくは20〜60℃であり、従来の方法のよう
に高温での接着を必要としないし、接着は十分に大きな
面積で行えるので容易に接着することができ、また残留
応力が生じないので目的とした形状を保つことができ
る。
The temperature at which the adhesive element is pressed is 20 ° C. to 250 ° C.
° C, preferably 20 to 60 ° C, and does not require high-temperature bonding unlike conventional methods. Bonding can be performed with a sufficiently large area so that bonding can be easily performed and no residual stress is generated. Therefore, the desired shape can be maintained.

【0034】また接着素子を押圧するは好ましくは実質
的に酸素を含まない雰囲気中で行うことによって該密着
結合領域(電気的結合部)を該雰囲気中に封止すること
を特徴とするものであり、該雰囲気が好ましくは真空
中、減圧中、あるいは減圧した還元ガスあるいは不活性
ガス中であり、還元ガスあるいは不活性ガスとして水素
ガス、アルゴンガス、窒素ガスまたはこれ等の混合物が
例示される。これによって電気的接合の経時的変化を防
止することができる。
Further, the pressing of the adhesive element is preferably performed in an atmosphere substantially free of oxygen, thereby sealing the tightly-bonded region (electrically connecting portion) in the atmosphere. The atmosphere is preferably in vacuum, under reduced pressure, or in reduced pressure reducing gas or inert gas, and examples of the reducing gas or inert gas include hydrogen gas, argon gas, nitrogen gas or a mixture thereof. . As a result, it is possible to prevent the electrical connection from changing over time.

【0035】接着素子を押圧する際はI−V特性を観察
しながらできるので電気的に必要かつ十分接合が可能と
なり電気的な接合部分に過度の圧縮応力を印加しないで
接合できるので該接合を保護することが可能となる。
When the adhesive element is pressed, it is possible to observe while observing the IV characteristics, so that it is possible to electrically and necessaryly join the elements, and to join without applying excessive compressive stress to the electrical joint. It becomes possible to protect.

【0036】[0036]

【実施例】【Example】

(第1の実施例)図1及び図2は本発明の特徴を最もよ
く表わす図画であり、同図において、1は密着接合する
ための基板、2は密着接合するための基板、3は基板1
における凸部から成る電気的結合面(密着結合領域)、
4は基板2における平面部から成る電気的結合面(密着
結合領域)、6は相対向する基板2と互いに接合するた
めの接合部、7は相対向する基板1と互いに接合するた
めの接合部、8は電気的絶縁をするための絶縁膜、9は
電気的絶縁をするための絶縁膜、10は絶縁膜8上の接
合部材、11は絶縁膜9上の接合部材、12は密着接合
領域の空間部、13はI−V特性線図を観測するための
基板1上の電極、14はI−V特性線図を観測するため
の基板2上の電極、15は電極13とカーブトレーサを
電気的に結合するためのリード線、16は電極14とカ
ーブトレーサを電気的に結合するためのリード線、図3
の17は基板1及び2が電気的結合していない状態のI
−V線図、図4の18は基板1及び2が電気的結合した
状態のI−V特性線図である。次に上記構成において、
一方の接合用基板1としてInP(pタイプ)ウェハを
用い、レジストマスクを利用したRIE(リアクティブ
・イオン・エッチング)によって凹部状の接合部6を形
成し、結果として凸部から成る電気的結合面3を生ずる
ことになり、その後、該接合部6上にSi酸化膜から成
る絶縁膜8をレジスト膜を用いたフォトリソプロセス
(図示なし)を用いて成膜し、さらに該絶縁膜8上にA
lから成る接合部材10をフォトリソプロセス(図示な
し)を用いて成膜し、その後該レジスト膜を溶剤で除去
しそして該基板1を洗浄する。他方の接合用の基板9と
してInP(nタイプ)ウェハを用い、図1にみるよう
に接合部7上にSi酸化膜から成る絶縁膜9をレジスト
膜を用いたフォトリソプロセス(図示なし)を用いて成
膜し、さらに該絶縁膜9上にAlから成る接合部材11
をフォトリソプロセス(図示なし)を用いて成膜し、そ
の後該レジスト膜を溶剤で除去し、そして基板2を洗浄
する。
(First Embodiment) FIGS. 1 and 2 best illustrate the features of the present invention. In FIG. 1, reference numeral 1 denotes a substrate for close bonding, 2 denotes a substrate for close bonding, and 3 denotes a substrate. 1
An electrical coupling surface (a tight coupling region) composed of a convex portion in
Reference numeral 4 denotes an electrical coupling surface (close contact region) formed of a flat portion of the substrate 2, reference numeral 6 denotes a bonding portion for bonding to the opposing substrate 2, and reference numeral 7 denotes a bonding portion for bonding to the opposing substrate 1. , 8 is an insulating film for electrically insulating, 9 is an insulating film for electrically insulating, 10 is a bonding member on the insulating film 8, 11 is a bonding member on the insulating film 9, and 12 is a close bonding region. 13 is an electrode on the substrate 1 for observing the IV characteristic diagram, 14 is an electrode on the substrate 2 for observing the IV characteristic diagram, and 15 is an electrode 13 and a curve tracer. 3 is a lead for electrically connecting the electrode 14 and the curve tracer, and FIG.
No. 17 indicates I in a state where the substrates 1 and 2 are not electrically coupled.
-V diagram, 18 in FIG. 4 is an IV characteristic diagram in a state where the substrates 1 and 2 are electrically coupled. Next, in the above configuration,
An InP (p-type) wafer is used as one bonding substrate 1, and a concave-shaped bonding portion 6 is formed by RIE (reactive ion etching) using a resist mask. Then, an insulating film 8 made of a Si oxide film is formed on the bonding portion 6 by using a photolithographic process (not shown) using a resist film. A
1 is formed by a photolithography process (not shown), the resist film is removed with a solvent, and the substrate 1 is washed. An InP (n-type) wafer is used as the other bonding substrate 9, and a photolithography process (not shown) using a resist film as an insulating film 9 made of a Si oxide film on the bonding portion 7 as shown in FIG. 1 is used. And a bonding member 11 made of Al on the insulating film 9.
Is formed by using a photolithography process (not shown), the resist film is removed with a solvent, and the substrate 2 is washed.

【0037】上記のプロセスで準備した基板1及び基板
2を図1にみるように相対向し、その後図2にみるよう
に荷重を印加しながら減圧下の水素気流中で熱処理す
る。該熱処理中の荷重印加によって接合部材10及び接
合部材11は互いに突き合わせ状態から、時間の経過と
共にクリープ現象によって塑性変形を進行させながら、
次第に接合していく。最終的に、電気的接合面3と電気
的接合面4が互いに接触し、そして密着するまで該塑性
変形を進行させる。該塑性変形中、図3及び図4にみる
ようなカーブトレーサーに写し出されるI−V特性線図
を観察することができる。該観察中、電気的結合面3と
電気的結合面4が非接触の場合、I−V特性線図は図3
にみるようであり、一方、該塑性変形が進行し、電気的
結合面3及び4が互いに接触し、密着した場合、I−V
特性線図は図4にみるようになる。該観察中、最もよい
特性を示すI−V特性線図がカーブトレーサーに写し出
された時点で、該荷重印加を停止する。
The substrate 1 and the substrate 2 prepared in the above process are opposed to each other as shown in FIG. 1, and then heat-treated in a hydrogen stream under reduced pressure while applying a load as shown in FIG. By applying a load during the heat treatment, the joining member 10 and the joining member 11 move from the butted state to each other, while plastic deformation progresses due to a creep phenomenon over time,
Gradually joining. Eventually, the plastic deformation proceeds until the electrical joint surfaces 3 and 4 come into contact with each other and come into close contact with each other. During the plastic deformation, an IV characteristic diagram projected on a curve tracer as shown in FIGS. 3 and 4 can be observed. During the observation, when the electric coupling surface 3 and the electric coupling surface 4 are not in contact with each other, the IV characteristic diagram is shown in FIG.
On the other hand, when the plastic deformation proceeds and the electric coupling surfaces 3 and 4 come into contact with each other and come into close contact with each other, IV
The characteristic diagram is as shown in FIG. During the observation, the application of the load is stopped when the IV characteristic diagram showing the best characteristics is displayed on the curve tracer.

【0038】電気的結合が生じる微小領域の密着接合領
域は必要以上の荷重(応力)の印加によって破壊する
か、あるいは該印加の荷重不足によって接触が不十分に
なる可能性がある。本発明ではI−V特性を観察しなが
ら荷重印加を行うので必要最小限で該印加を行うことが
できる。
There is a possibility that the close bonding region of the minute region where the electrical coupling occurs may be broken by applying a load (stress) more than necessary, or the contact may become insufficient due to the insufficient load applied. In the present invention, since the load is applied while observing the IV characteristics, the application can be performed with a minimum necessary.

【0039】上記一連の過程から、基板1と基板2は接
合部材10及び接合部材11を介して堅固に接合し、か
つ該密着結合領域でI−V特性のよい電気的結合を得る
ことが可能となった。
From the above series of processes, it is possible to firmly join the substrate 1 and the substrate 2 via the joining members 10 and 11, and to obtain an electrical connection having good IV characteristics in the close joining region. It became.

【0040】上記手法による基板1及び基板2の密着接
合した後、各種プロセス、すなわち該密着接合基板の薄
片化研磨、溶剤中への浸漬及び超音波洗浄を行った場合
においても、該I−V特性に何ら変化は生じなく、かつ
IR(赤外線カメラ)カメラによる密着接合個所にも何
ら変化は生じなかった。
After the substrate 1 and the substrate 2 are adhered to each other by the above-mentioned method, even when various processes are performed, that is, when the adhered substrate is subjected to thinning polishing, immersion in a solvent, and ultrasonic cleaning, the IV is maintained. There was no change in the characteristics, and no change occurred in the tightly joined portion by the IR (infrared camera) camera.

【0041】上記方法で素子を作製後、基板1及び基板
2との間に電圧を印加し、次第に電流を増して行ったと
ころ、発光を観察した。
After the device was manufactured by the above method, a voltage was applied between the substrate 1 and the substrate 2 and the current was gradually increased, and light emission was observed.

【0042】なお、該荷重印加による接合過程を雰囲気
中で行った場合においても、例えば、真空中、減圧中、
減圧したArガス中及び窒素ガス中等で行った場合にお
いてもよく、電気的結合部を該雰囲気で密閉することが
可能となり、良好な結果が得られた。
When the joining process by applying the load is performed in an atmosphere, for example, in a vacuum, under a reduced pressure,
It may be carried out in a reduced pressure Ar gas or nitrogen gas, etc., and the electrical connection can be sealed in the atmosphere, and good results were obtained.

【0043】また、本実施例においては絶縁膜としてS
i酸化膜を用いたが、他にAl酸化膜、Si窒化膜を用
いた場合においても可能であり、本発明の意図するとこ
ろは何ら変わるものではない。
In this embodiment, the insulating film is made of S
Although the i-oxide film is used, it is also possible to use an Al oxide film or a Si nitride film instead, and the intention of the present invention does not change at all.

【0044】さらに、本実施例においてはInP同士の
p−n接合を得たが、InP以外の材料、例えば、S
i,InP,GaAs,GaN同士、あるいはこれらの
材料の異種材料同士の組み合わせによる接合(電気的結
合)を行う場合においても可能であり、本発明の意図す
るところは何ら変わるものではない。
Furthermore, in this embodiment, a pn junction between InPs was obtained, but a material other than InP, for example, S
It is also possible to perform bonding (electrical coupling) by combining i, InP, GaAs, and GaN or a combination of different materials of these materials, and the intention of the present invention does not change at all.

【0045】(第2の実施例)図5、図6は本発明の特
徴を最もよく表わす図画であり、同図において1は密着
接合するための基板、2は密着接合するための基板、3
は基板1における凸部から成る電気的結合面(密着結合
領域)、4は基板2における平面部から成る電気的結合
面(密着結合領域)、5は密着結合領域に形成した異方
性エッチングによるエッチピット、6は相対向する基板
2と互いに接合するための接合部、7は相対向する基板
1と互いに接合するための接合部、8は電気的絶縁をす
るための絶縁膜、9は電気的絶縁をするための絶縁膜、
10は絶縁膜8上の接合部材、11は絶縁膜9上の接合
部材、12は密着接合領域の空間部、13はI−V特性
線図を観測するための基板1上の電極、14はI−V特
性線図を観測するための基板2上の電極、15は電極1
3とカーブトレーサを電気的に結合するためのリード
線、16は電極14とカーブトレーサを電気的に結合す
るためのリード線、17は基板1及び2が電気的結合し
ていない状態のI−V線図、18は基板1及び2が電気
的結合した状態のI−V特性線図である。
(Second Embodiment) FIGS. 5 and 6 are drawings showing the features of the present invention best, wherein 1 is a substrate for close bonding, 2 is a substrate for close bonding, and 3
Is an electric coupling surface (tightly bonded region) formed of a convex portion on the substrate 1, 4 is an electric coupling surface (closely bonded region) formed of a flat portion on the substrate 2, and 5 is anisotropic etching formed in the tightly bonded region. Etch pits, 6 are bonding portions for bonding to the opposing substrate 2, 7 are bonding portions for bonding to the opposing substrate 1, 8 is an insulating film for electrically insulating, and 9 is an electrical film. Insulating film for electrical insulation,
Reference numeral 10 denotes a bonding member on the insulating film 8, 11 denotes a bonding member on the insulating film 9, 12 denotes a space in a close bonding region, 13 denotes an electrode on the substrate 1 for observing an IV characteristic diagram, and 14 denotes an electrode. An electrode on the substrate 2 for observing an IV characteristic diagram;
A lead wire for electrically coupling 3 to the curve tracer, 16 is a lead wire for electrically coupling the electrode 14 to the curve tracer, and 17 is an I- in a state where the substrates 1 and 2 are not electrically coupled. A V diagram 18 is an IV characteristic diagram in a state where the substrates 1 and 2 are electrically coupled.

【0046】次に上記構成において、一方の接合用基板
1としてInP(pタイプ)ウェハを用い、レジストマ
スクを利用したRIE(リアクティブ・イオン・エッチ
ング)によって凹部状の接合部6を形成し、結果として
凸部から成る電気的結合面3を生ずることになり、その
後、該接合部6上にSi酸化膜から成る絶縁膜8をレジ
スト膜を用いたフォトリソプロセス(図示なし)を用い
て成膜し、さらに該絶縁膜8上にAlから成る接合部材
10をフォトリソプロセス(図示なし)を用いて成膜
し、その後該レジスト膜を溶剤で除去し、そして該基板
1を洗浄する。
Next, in the above configuration, an InP (p-type) wafer is used as one of the bonding substrates 1, and a concave-shaped bonding portion 6 is formed by RIE (reactive ion etching) using a resist mask. As a result, an electric coupling surface 3 consisting of a convex portion is produced. Thereafter, an insulating film 8 consisting of a Si oxide film is formed on the joining portion 6 by using a photolithography process (not shown) using a resist film. Then, a bonding member 10 made of Al is formed on the insulating film 8 by using a photolithography process (not shown). Thereafter, the resist film is removed with a solvent, and the substrate 1 is washed.

【0047】他方の接合用の基板9としてInP(nタ
イプ)ウェハを用い、図5にみるように接合部7上にS
i酸化膜から成る絶縁膜9をレジスト膜を用いたフォト
リソプロセス(図示なし)を用いて成膜し、さらに該絶
縁膜9上にAlから成る接合部材11をフォトリソプロ
セス(図示なし)を用いて成膜し、その後該レジスト膜
上から、該密着結合領域(電気的結合面4)にダイヤモ
ンド針を軽く押し込むようにして傷を付け、その後エッ
チング液中に浸漬し異方性エッチングによるエッチピッ
ト5を形成する。この場合、該傷を付けた個所で該エッ
チピットが生じ易いため、任意の位置にエッチピットを
形成可能となる。その後該レジスト膜を溶剤で除去し、
そして基板2を洗浄する。
As shown in FIG. 5, an InP (n-type) wafer is used as the other substrate 9 for bonding, and S
An insulating film 9 made of an i-oxide film is formed by a photolithographic process (not shown) using a resist film, and a bonding member 11 made of Al is formed on the insulating film 9 by a photolithographic process (not shown). A film is formed, and then a diamond needle is gently pressed into the tightly bonded region (electrical connection surface 4) from above the resist film, and then immersed in an etchant to form an etch pit 5 by anisotropic etching. To form In this case, since the etch pit is easily generated at the scratched portion, the etch pit can be formed at an arbitrary position. Thereafter, the resist film was removed with a solvent,
Then, the substrate 2 is washed.

【0048】上記のプロセスで準備した基板1及び基板
2を図1にみるように相対向し、その後図2にみるよう
に荷重を印加しながら減圧下の水素気流中で熱処理(2
00℃)する。該熱処理中の荷重印加によって接合部材
10及び接合部材11は互いに突き合わせ状態から、時
間の経過と共にクリープ現象によって塑性変形を進行さ
せながら、次第に接合していく。最終的に、電気的接合
面3と電気的接合面4が互いに接触し、そして密着する
まで該塑性変形を進行させる。該塑性変形中、図3及び
図4にみるようなカーブトレーサーに写し出されるI−
V特性線図を観察することができる。該観察中、電気的
結合面3と電気的結合面4が非接触の場合、I−V特性
線図は図3にみるようであり、一方、該塑性変形が進行
し、電気的結合面3及び4が互いに接触し、密着した場
合、I−V特性線図は図4にみるようになる。該観察
中、最もよい特性を示すI−V特性線図がカーブトレー
サーに写し出された時点で、該荷重印加を停止する。上
記一連の過程から、基板1と基板2は接合部材10及び
接合部材11を介して堅固に接合し、かつ該密着結合領
域でI−V特性のよい電気的結合を微小な電気的結合面
で可能となった。
The substrate 1 and the substrate 2 prepared by the above process are opposed to each other as shown in FIG. 1, and then subjected to a heat treatment (2) in a hydrogen stream under reduced pressure while applying a load as shown in FIG.
00 ° C). By applying a load during the heat treatment, the joining member 10 and the joining member 11 gradually join from the butted state while plastic deformation progresses due to a creep phenomenon over time. Eventually, the plastic deformation proceeds until the electrical joint surfaces 3 and 4 come into contact with each other and come into close contact with each other. During the plastic deformation, the I- which is projected on a curve tracer as shown in FIGS.
A V characteristic diagram can be observed. During the observation, when the electric coupling surface 3 and the electric coupling surface 4 are not in contact with each other, the IV characteristic diagram is as shown in FIG. 3, while the plastic deformation progresses and the electric coupling surface 3 4 and FIG. 4 come into contact with each other, and the IV characteristic diagram is as shown in FIG. During the observation, the application of the load is stopped when the IV characteristic diagram showing the best characteristics is displayed on the curve tracer. From the above series of processes, the substrate 1 and the substrate 2 are firmly joined via the joining members 10 and 11, and the electric connection having good IV characteristics is formed on the minute electric connection surface in the close connection region. It has become possible.

【0049】上記手法による基板1及び基板2の密着接
合した後、各種プロセス、すなわち該密着接合基板の薄
片化研磨、溶剤中への浸漬及び超音波洗浄を行った場合
においても、該I−V特性に何ら変化を生ずることな
く、かつIR(赤外線カメラ)カメラによる密着接合個
所にも何ら変化は生じなかった。
After the substrate 1 and the substrate 2 are adhered to each other by the above-described method, even when various processes are performed, that is, when the adhered substrate is subjected to thinning polishing, immersion in a solvent, and ultrasonic cleaning, the IV is maintained. No change occurred in the characteristics, and no change occurred in the tightly joined portion by the IR (infrared camera) camera.

【0050】上記方法で素子を作製後、基板1及び基板
2との間に電圧を印加し、次第に電流を増して行ったと
ころ、発光を観察した。
After the device was manufactured by the above-described method, a voltage was applied between the substrate 1 and the substrate 2 and the current was gradually increased, and light emission was observed.

【0051】なお、本実施例において接合部材としてA
lを用いたが、この他にも塑性変形能を有する材料であ
ればよく、例えばAu,Ga,Cu,Ti,Zn,P
b,Snであっても該Alと同様な効果を生ずる。
In this embodiment, A is used as the joining member.
1 is used, but any other material having plastic deformability may be used. For example, Au, Ga, Cu, Ti, Zn, P
Even with b and Sn, the same effect as that of the Al is produced.

【0052】また、本実施例においては、該荷重印加に
よる接合過程を低温(250℃以下の温度)で熱処理中
に行ったが、常温で行った場合においても良好な結果が
得られた。
In this embodiment, the bonding process by applying the load was performed at a low temperature (a temperature of 250 ° C. or less) during the heat treatment. However, good results were obtained when the bonding was performed at room temperature.

【0053】[0053]

【発明の効果】以上説明したように、本発明によれば、
基板上に形成した電気的結合面及び接合部を清浄化後、
電気的結合面同士及び接合部同士を互いに相対向させた
状態で、I−V特性線図を観察(観測)しながら押圧力
を印加することによって、電気的結合面同士での良好な
電気的結合を得、そして接合部同士で接合のための(引
き剥されないための)機械的強度を得ることにより基板
間の密着接合を可能にし、かつエッチピット作製による
電気的結合面積の微小化を可能にする手法であるため、 1.常温、あるいは低温での電気的結合が可能であり、
かつ接合部同士での十分な接合強度(引き剥されないた
めの強度)を得ることが可能である。 2.接合部同士のみで十分な接合強度を得ることが可能
であるため、電気的結合面の該結合面積を限りなく微小
にすることが可能である。 3.I−V特性線図を観測しながら該押圧力を印加する
ため、必要以上の該押圧力を印加せずに良好な電気的結
合を得ることが可能である。
As described above, according to the present invention,
After cleaning the electrical coupling surface and the junction formed on the substrate,
By applying a pressing force while observing (observing) the IV characteristic diagram in a state where the electric coupling surfaces are opposed to each other and the joints are opposed to each other, a good electric connection between the electric coupling surfaces is obtained. Bonding and obtaining mechanical strength for bonding between joints (to prevent peeling) enable close bonding between substrates and minimizing the electrical coupling area by making etch pits It is a method to Electrical coupling at room temperature or low temperature is possible,
In addition, it is possible to obtain a sufficient bonding strength (strength for preventing peeling) between the bonding portions. 2. Since a sufficient bonding strength can be obtained only by the bonding portions, it is possible to minimize the bonding area of the electrical coupling surface as much as possible. 3. Since the pressing force is applied while observing the IV characteristic diagram, good electrical coupling can be obtained without applying the pressing force more than necessary.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例に係る密着接合前の発光
素子構造の断面図である。
FIG. 1 is a cross-sectional view of a light emitting device structure before a close bonding according to a first embodiment of the present invention.

【図2】本発明の第1の実施例に係る密着接合法を用い
た発光素子構造の断面図である。
FIG. 2 is a cross-sectional view of a light emitting device structure using a contact bonding method according to a first embodiment of the present invention.

【図3】本発明の第1、第2の実施例に係る密着接合前
の発光素子のI−V特性線図である。
FIG. 3 is an IV characteristic diagram of a light emitting element before close contact bonding according to first and second embodiments of the present invention.

【図4】本発明の第1、第2の実施例に係る密着接合後
の発光素子のI−V特性線図である。
FIG. 4 is an IV characteristic diagram of the light emitting device after the close bonding according to the first and second embodiments of the present invention.

【図5】本発明の第2の実施例に係る密着接合前の発光
素子構造の断面図である。
FIG. 5 is a cross-sectional view of a light emitting device structure before close bonding according to a second embodiment of the present invention.

【図6】本発明の第2の実施例に係る密着接合法を用い
た発光素子構造の断面図である。
FIG. 6 is a cross-sectional view of a light emitting device structure using a contact bonding method according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 基板 3 電気的結合面 4 電気的結合面 5 エッチピット 6 接合部 7 接合部 8 絶縁膜 9 絶縁膜 10 接合部材 11 接合部材 12 空間部 13 電極 14 電極 15 リード線 16 リード線 17 I−V線図 18 I−V線図 DESCRIPTION OF SYMBOLS 1 Substrate 2 Substrate 3 Electrical coupling surface 4 Electrical coupling surface 5 Etch pit 6 Joining part 7 Joining part 8 Insulating film 9 Insulating film 10 Joining member 11 Joining member 12 Space 13 Electrode 14 Electrode 15 Lead wire 16 Lead wire 17 I -V diagram 18 IV diagram

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 同種あるいは異種材料から成る半導体基
板間の微小領域での電気的接合(以後、電気的結合と呼
ぶ)を得る方法において、電気的結合を生ずる密着接合
領域と、接合力を与えるための接着素子から成る接合領
域と、I−V特性線図をカーブトレーサーで観測しなが
ら密着接合する構成から成り、該構成が (1)該接合領域に絶縁膜を形成する過程と、 (2)該絶縁膜上に接合力を与えるための接着素子を形
成する過程と、 (3)該微小領域での該密着結合領域の電気的結合面と
なる部分に微小な点状の傷を1つあるいは複数個形成す
る過程と、 (4)該微小領域での該密着結合領域の該微小な点状の
傷をエッチング液によって異方性エッチングによるエッ
チピットに形成する過程と、 (5)両接合用基板の接合面に対して反対側の面に、I
−V特性線図観測用の電極を形成する過程と、 (6)該同種あるいは異種材料基板上の該接着素子同士
及び該密着結合領域同士がそれぞれ相対向するように整
合し、該同種あるいは異種材料基板同士に押圧力を印加
する過程と、 (7)該押圧力を印加する過程において、該電気的結合
面での電気的結合によって生ずるI−V特性をカーブト
レーサで電気的結合の状況を観察するI−V特性線図観
測過程から成る同種あるいは異種材料基板間の電気的結
合を常温乃至250℃までの低温で行うことを特徴とす
る半導体基板間の密着接合方法。
1. A method for obtaining electrical bonding (hereinafter referred to as electrical coupling) in a minute region between semiconductor substrates made of the same or different materials. A contact area formed by an adhesive element for the purpose of contact, and a structure in which adhesion is performed while observing an IV characteristic diagram with a curve tracer. The structure includes: (1) a process of forming an insulating film in the joint area; (3) forming an adhesive element for providing a bonding force on the insulating film; and (3) forming one small point-like flaw in a portion of the minute region which is to be an electrical coupling surface of the close coupling region. Or (4) forming the minute point-like flaws in the tightly-bonded area in the minute area into etch pits by anisotropic etching with an etchant; To the bonding surface of the On the surface of the side, I
Forming an electrode for observing a -V characteristic diagram; and (6) aligning the adhesive elements and the tightly-bonded regions on the same or different material substrate so that they face each other, (7) In the process of applying a pressing force between the material substrates, (7) in the process of applying the pressing force, the IV characteristic generated by the electrical coupling on the electrical coupling surface is used to determine the state of the electrical coupling using a curve tracer. A method for closely bonding semiconductor substrates, wherein electrical connection between substrates of the same or different materials is performed at a low temperature from room temperature to 250 ° C. in an IV characteristic diagram observation process for observation.
【請求項2】 該半導体基板が、Si,In P,GaA
s,GaNから選ばれた少なくとも1種であり、または
これらの半導体基板上に成膜した化合物半導体から成る
ことを特徴とする請求項1記載の半導体基板間の密着接
合法。
Wherein said semiconductor substrate, Si, I n P, GaA
2. The method according to claim 1, wherein the semiconductor substrate is at least one selected from the group consisting of s and GaN, or a compound semiconductor formed on these semiconductor substrates.
【請求項3】 電気的結合を生ずる密着結合領域が平面
状、あるいは1つあるいは複数のV状の溝から成ること
を特徴とする請求項1記載の半導体基板間の密着接合
法。
3. The method according to claim 1, wherein the tightly-bonded region in which the electrical connection is made is formed of a flat or one or a plurality of V-shaped grooves.
【請求項4】 該接合領域における接着素子同士が該押
圧力によって常温乃至250℃の低温で互いに接合し、
該同種あるいは異種材料基板間の接合力を得ることを特
徴とする特許請求範囲1記載の半導体基板間の密着接合
法。
4. The bonding elements in the bonding area are bonded to each other at a low temperature of room temperature to 250 ° C. by the pressing force,
2. The method according to claim 1, wherein the bonding strength between the substrates of the same or different materials is obtained.
【請求項5】 該接着素子が塑性変形能を有する材料か
ら成るものであることを特徴とする請求項1記載の半導
体基板間の密着接合法。
5. The method according to claim 1, wherein the adhesive element is made of a material having a plastic deformation ability.
【請求項6】 該塑性変形を有する材料が金属材料であ
ることを特徴とする請求項5記載の半導体基板間の密着
接合法。
6. The method according to claim 5, wherein the material having plastic deformation is a metal material.
【請求項7】 該金属材料がAl,Au,In,Ga,
Sn,Cu,Ti,Zn,Pbの少なくとも1種である
ことを特徴とする請求項6記載の半導体基板間の密着接
合法。
7. The method according to claim 1, wherein the metal material is Al, Au, In, Ga,
7. The method according to claim 6, wherein at least one of Sn, Cu, Ti, Zn, and Pb is used.
【請求項8】 絶縁膜がSi酸化膜、Si窒化膜、Al
酸化膜より選ばれた少なくとも1種であることを特徴と
する請求項1記載の半導体基板間の密着接合法。
8. An insulating film comprising a Si oxide film, a Si nitride film, and an Al film.
2. The method according to claim 1, wherein the method is at least one selected from oxide films.
【請求項9】 該接着素子が凸状、球状、あるいは半球
状であることを特徴とする請求項1記載の半導体基板間
の密着接合法。
9. The method according to claim 1, wherein the adhesive element is convex, spherical, or hemispherical.
【請求項10】 該押圧力印加によって該密着結合領域
(電気的結合部)を密封することを特徴とする請求項1
記載の半導体基板間の密着接合法。
10. The tightly-bonded region (electrically-coupled portion) is sealed by applying the pressing force.
The method for tightly bonding semiconductor substrates according to the above.
【請求項11】 該押圧力を実質的に酸素を含まない雰
囲気中で該押圧印加を行うことによって該密着結合領域
(電気的結合部)を雰囲気中に封止することを特徴とす
る請求項1記載の半導体基板間の密着接合法。
11. The tightly-bonded region (electrically-coupled portion) is sealed in the atmosphere by applying the pressure in an atmosphere substantially free of oxygen. 2. The method for tightly bonding semiconductor substrates according to 1.
【請求項12】 該実質的に酸素を含まない雰囲気が真
空中、減圧中、あるいは減圧した還元ガスあるいは不活
性ガス中であることを特徴とする請求項11記載の半導
体基板間の密着接合法。
12. The method according to claim 11, wherein the atmosphere substantially free of oxygen is in a vacuum, under reduced pressure, or in a reduced gas or an inert gas under reduced pressure. .
【請求項13】 該還元ガスあるいは不活性ガスが水素
ガス、アルゴンガス、窒素ガスまたはこれ等の混合物で
あることを特徴とする請求項12記載の密着接合法。
13. The method according to claim 12, wherein the reducing gas or the inert gas is hydrogen gas, argon gas, nitrogen gas or a mixture thereof.
JP14938197A 1997-06-06 1997-06-06 Method for bonding semiconductor substrates through minute area Pending JPH10341042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14938197A JPH10341042A (en) 1997-06-06 1997-06-06 Method for bonding semiconductor substrates through minute area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14938197A JPH10341042A (en) 1997-06-06 1997-06-06 Method for bonding semiconductor substrates through minute area

Publications (1)

Publication Number Publication Date
JPH10341042A true JPH10341042A (en) 1998-12-22

Family

ID=15473894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14938197A Pending JPH10341042A (en) 1997-06-06 1997-06-06 Method for bonding semiconductor substrates through minute area

Country Status (1)

Country Link
JP (1) JPH10341042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005419A (en) * 2005-06-22 2007-01-11 Canon Inc DIRECT BONDING METHOD OF GaN/GaN

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005419A (en) * 2005-06-22 2007-01-11 Canon Inc DIRECT BONDING METHOD OF GaN/GaN
JP4663420B2 (en) * 2005-06-22 2011-04-06 キヤノン株式会社 GaN / GaN direct bonding method

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