JPH10336582A - Digital-video signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale without the need for a complicated circuit for the address control of a RAM. SOLUTION: An FRAM 12 having a capacity by one SYNC block is used in units of macro blocks and two kinds of MRAM 13 and a VRAM 14 are used for RAMs which store variable length coding data for a high-frequency AC components. A reproduction 3rd step signal processing circuit 18 conducts error detection of variable length coding data by mis-correction and image defect prevention processing and an error-processing circuit 22 replaces variable length coding data of an orthogonal transform block, whose error is detected with an error code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing device in a recording and reproducing device for digitized video and audio signals.

[0002]

2. Description of the Related Art When recording or transmitting a digitized video signal, image compression using orthogonal transform and variable length coding is often used. Here, image compression of a home digital VCR will be described.

There are two types of image compression modes in a home digital VCR. A standard image compression mode (hereinafter, referred to as a standard mode) and an image compression mode (hereinafter, referred to as a standard mode) in which the code amount is further reduced to half of the standard mode code amount. High compression mode).

In the case of the standard mode, a macroblock is formed by collecting four orthogonal transform blocks of four luminance components and two orthogonal transform blocks of two color difference components, and five macroblocks are collected from positions distant from the screen. A video segment is constructed, and control is performed so that the total amount of codes obtained by performing orthogonal transform on the 30 orthogonal transform blocks in the video segment and performing variable-length encoding is substantially constant, and stores the total in five sync blocks.

In the high compression mode, the number of pixels of the luminance component is thinned to 3/4 of the standard mode, the number of pixels of the color difference component is thinned to 1/2 of the standard mode, and then the orthogonality of six adjacent luminance components is reduced. A transform block and two orthogonal transform blocks of chrominance components are collected to form a macroblock, and five macroblocks are collected from distant positions on the screen to form a video segment. Forty orthogonal transform blocks in the video segment Are controlled so that the total code amount obtained by performing the orthogonal transform on the variable-length code is substantially constant, and is stored in five sync blocks.

By collecting five macroblocks from remote positions on the screen, a macroblock of a complicated pattern requiring a large amount of code and a macroblock of a monotonous pattern requiring a small amount of code are the same. The probability of being assigned to video segments is increased, and stable image quality can be expected.

Here, the five sync blocks in the video segment correspond to five macro blocks, respectively. The sync block in the standard mode is composed of six fixed regions, and four fixed regions correspond to orthogonal transform blocks of the luminance component of the macroblock corresponding to the two fixed regions. Two fixed regions correspond to orthogonal transform blocks of the chrominance components of the macroblock corresponding to the fixed regions. Assigned for. The sync block in the high compression mode is composed of eight fixed regions, and the orthogonal transform block of the luminance component of the macroblock corresponding to the six fixed regions;
Two fixed areas are allocated for the orthogonal transform block of the chrominance component of the corresponding macroblock.

[0008] The variable-length coded data of the orthogonally transformed block that has been subjected to the orthogonal transformation and the variable length coding is first stored in order in each fixed area of the corresponding sync block. The variable length coded data stored here is called LAC.

At this time, since the code amount of each orthogonal transform block varies, there are cases where all the data can be stored in the fixed area and there is still an empty area, cases where the data can be stored exactly in the fixed area, and cases where the data cannot be completely stored in the fixed area. There are cases where it overflows. Here, the variable-length coded data that cannot be stored in the fixed area and overflows is called an HAC.

Next, the HACs are sequentially stored in the gaps of the fixed area in the other orthogonal transform block in the same sync block, which still has a free area. Here, the stored HAC is M
Call it AC.

At this time, since the code amount of each macroblock varies, there is a case where all the data can be stored in the sync block and there is still an empty area, a case where the data can be stored in the sync block, and a case where the sync block cannot be completely stored and overflows. There is a case that ends up.

Next, the overflowing HACs that cannot be stored in the sync blocks are sequentially stored in the gaps of the fixed areas of the other sync blocks in the video segment which still have free areas. Here, the stored HAC is called a VAC.

By storing the variable-length coded data in the video segment in the five sync blocks in the above-described manner, a large amount of code can be stored in the free area of the fixed area of the orthogonal transform block which does not require much code. Is stored, and stable image quality can be expected.

The process of storing the variable-length coded data in the video segment in five sync blocks as described above is called a format process.

In both the standard mode and the high compression mode, after the variable-length encoded data is stored in five sync blocks in the format processing, an error correction code for correcting or correcting an error at the time of reproduction is added and digitally modulated. Later, it is recorded on a tape.

The reproduced signal reproduced from the tape is digitally demodulated, and the error correction decoding circuit corrects or corrects a code error at the time of reproduction, and modifies each of the orthogonal transform blocks stored in the five sync blocks. Re-arrange the long encoded data in order for each orthogonal transformation block,
After performing variable length decoding and inverse orthogonal transform, the pixels of each orthogonal transform block are rearranged, and the image is restored.

The process of rearranging the variable-length coded data of each orthogonal transform block stored in the five sync blocks in order for each orthogonal transform block as described above is called a deformat process.

In the reformatting process, when all the errors of the reproduced five sync blocks are corrected, all the variable-length encoded data of the recorded orthogonal transform blocks can be rearranged in order. One sync block that does not belong to the video segment at the time of recording, such as a sync block that cannot be corrected at the time and has been replaced with a sync block corresponding to the same position of the past frame on the screen.
If one exists, it becomes impossible to rearrange all the variable-length encoded data of the orthogonal transform block recorded due to discontinuity in the variable-length encoded data, and the existence of such a sync block is ignored. Then, if the deformatting process is performed, the reproduced image is broken and the quality is greatly impaired.

Therefore, an error correction decoding circuit generates a flag (hereinafter, referred to as an error correction flag) indicating the presence of a sync block which does not belong to the video segment at the time of recording, and receives this flag in the reformatting process. Accordingly, it is necessary to perform a process of stopping the output of the variable length coded data (VAC) recorded between the sync blocks to prevent the breakdown of the image and suppress the deterioration of the quality of the reproduced video.

Japanese Patent Application Laid-Open No. 6-30357 discloses a prior art for realizing the format processing and the deformat processing.
There is a recording / reproducing apparatus disclosed in Japanese Patent Laid-Open Publication No. H11-209, pp. 1-5. In this recording / reproducing apparatus, an FRAM (190w) having a capacity of a sync block for one video segment is used as a main RAM.
HRAM (151 words × 16 bits) which uses three ord × 16 bits and stores the HAC is described as VRAM in the specification of the prior art. However, in order to distinguish it from the VRAM used in the present invention, HRAM and ) Is used, and a format process and a deformat process are realized by using a total of 13952 bits of RAM.

In this recording / reproducing apparatus, at the time of format processing, the HAC that overflows the fixed area of the FRAM is
Are stored sequentially from the front of the address, and when the HAC exceeds a certain value, the remaining HACs are stored sequentially from the back of the address. This operation is performed for five macro blocks in order.

Next, the MAC and VAC are stored in the free area of the FRAM.
, First, part or all of the HAC of the same macroblock stored from the front of the address of the HRAM for five macroblocks is stored as MAC. Next, HR is sequentially set for the five macro blocks.
The rest of the HAC (HAC not used as MAC) stored from the front of the AM address and part or all of the HAC stored from the back of the address are stored as VAC.

[0023]

However, in the format processing of the prior art as described above, when storing a MAC in an empty area of the FRAM, all the HACs stored from the head of the HRAM address can be used as the MAC. Since there is no limitation, the HAC stored from the head of the HRAM address for each macroblock is used as much as the MAC, and when storing the MAC of the next macroblock,
It is necessary to jump the HRAM address to the HAC storage location of the next macroblock.

After the operation of storing the MAC of each macroblock is completed, the operation shifts to the operation of storing the VAC. In the operation of storing the VAC, the HAC stored from the head of the HRAM address and not used as the MAC is used. , H
Since the HAC stored from the rear of the RAM address is used intermittently, more complicated HRAM address control is required.

Also, in the prior art deformatting process, when an erroneous correction occurs in the error correction decoding circuit, no measures have been taken to minimize the screen failure, so that if the erroneous correction occurs, the screen will fail. The possibilities are enormous.

[0026]

According to a first aspect of the present invention, there is provided a digital video signal processing apparatus comprising: an MRAM for storing all valid HACs from the front of an address; By using a VRAM that stores from the front, the RAM as in the prior art is used.
It provides a format processing that does not require complicated address control.

The digital video signal processing device according to the fourth aspect of the present invention uses an MRAM that stores only the MAC from the front of the address and a VRAM that stores only the VAC from the front of the address. Na RA
It also provides a deformatting process that does not require M complicated address control.

Further, the digital video signal processing apparatus according to the third and sixth aspects of the present invention uses an FRAM which requires a capacity of 3 video segments (15 macroblocks) in the prior art for each macroblock. By doing so, the capacity can be reduced to 7 macroblocks, FR
It is possible to reduce the capacity of the AM to less than half that of the prior art.

Further, according to the digital video signal processing apparatus of the present invention, when an error correction occurs in the error correction decoding circuit during the deformatting process (in this case, the error correction flag does not become true) It is intended to perform detection and processing for preventing the breakdown of the reproduced image, and to provide a deformatting process which suppresses the possibility of screen failure due to erroneous correction.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a digital video signal processing device according to an embodiment of the present invention.

In FIG. 1, 1 is a pixel data input terminal,
2 is a shuffling circuit, 3 is an orthogonal transformation circuit, 4 is a quantization circuit, 5 is a variable length encoding circuit, 6 is a recording first step signal processing circuit, 7 is a recording second step signal processing circuit, and 8 is a recording first step signal processing circuit. 3 step signal processing circuit, 9 is a recording first step RAM control circuit, 10 is a recording second step RAM control circuit, 11 is a recording third step RAM control circuit, and 2 to 11 are circuits used in the recording system. , 6 in this
To 11 are format processing circuits.

Reference numeral 12 denotes a first memory (hereinafter, referred to as FRAM) having a capacity of one sync block. Reference numeral 13 stores all valid HACs from the front of the address at the time of format processing, and stores only MAC at the time of deformat processing. A second memory (hereinafter referred to as MRAM) for storing from the front of the address,
A third memory (hereinafter referred to as VRAM) 14 stores only the HAC not used as a MAC from the front of the address at the time of the format processing, and stores only the VAC from the front of the address at the time of the deformat processing. During processing, F is used in the process up to the recording second step signal processing.
This is a fourth memory (hereinafter referred to as FPRAM) used to store the final position information of the variable length coded data stored in each fixed area of the RAM.

Reference numeral 16 denotes a reproduction first step signal processing circuit,
7 is a reproduction second step signal processing circuit, 18 is a reproduction third step signal processing circuit, 19 is a reproduction first step RAM control circuit, 20 is a reproduction second step RAM control circuit, 21
Is a reproduction third step RAM control circuit, 22 is an error processing circuit, 23 is a variable length decoding circuit, 24 is an inverse quantization circuit,
25 is an inverse orthogonal transform circuit, 26 is a deshuffling circuit, 2
Reference numeral 7 denotes a pixel data output terminal, and 16 to 26 are circuits used in the reproduction system, and 16 to 22 are deformat processing circuits.

The FRAM 12 has a capacity (38 words × 16 bi in the present embodiment) for storing formatted variable-length encoded data for one macroblock.
t) is used for seven macroblocks, that is, seven.

If the MRAM 13 requires the largest capacity to store all the valid HACs during the format processing, the two chrominance component orthogonal transform blocks of one macro block and one
In this case, the maximum code amount is allocated to one luminance component orthogonal transform block, and the remaining orthogonal transform blocks are only DC components. The required capacity is equivalent to the sum of the free areas of the fixed areas including only the DC components. This value is 146 words × 16 bits in the standard mode as shown in FIG. 9, and two macroblocks are used for replacement.

When the MRAM 13 needs the largest capacity to store only the MACs at the time of the deformat processing, the maximum size of one chrominance component orthogonal transform block in all the macroblocks in the video segment is reduced. This is the case where a code amount is allocated and the remaining orthogonal transform blocks have only DC components, and the required capacity is equivalent to the sum of the free areas of the fixed areas including only DC components. This value is 140 words × 1 in the standard mode as shown in FIG.
It becomes 6 bits, and two video segments are used for replacement.

Therefore, in order to use the MRAM 13 commonly for the format processing and the deformat processing, two capacities (146 words × 16 bits in the present embodiment) required for the formatting processing are used.

When the VRAM 14 needs the largest capacity to store only the HAC not used as the MAC during the format processing, the maximum code amount is allocated to one macroblock in the video segment. , The remaining macroblocks are only DC components, and the required capacity is equivalent to the total free space in the fixed area of the remaining macroblocks. This value is 128 words × 16 bits in the standard mode as shown in FIG. 11, and two video segments are used for replacement.

When the VRAM 14 needs the largest capacity to store only the VACs at the time of the deformat processing, the maximum code amount can be stored in one macroblock in the video segment as at the time of the format processing. Is assigned, and the remaining macroblock has only a DC component. The required capacity is equivalent to the total of the free area of the fixed area of the remaining macroblock. This value is 128 words × 16 bits in the standard mode as shown in FIG. 11 as in the case of the format processing, and two video segments are used for replacement.

Therefore, in order to use the VRAM 14 commonly in the format processing and the deformat processing, the capacity required in common in the formatting processing and the deformat processing (128 words × 16b in the present embodiment)
it).

In the format processing, the FPRAM 15 stores the FRAM in the process up to the recording second step signal processing.
Is used to store the final position information of the variable length coded data stored in each fixed area of FRAM.
3 bits for identifying the maximum address depth (the depth of the fixed area of the luminance signal in the standard mode) in each fixed area of
4 to identify the last position in a 16-bit word
Since a total of 7 bits are required for the fixed number of areas in the video segment in the high compression mode, in the present embodiment, a capacity of 40 words × 7 bits is used for video segment replacement.

Here, the FRAM at the time of format processing,
The write and read timings of the MRAM and VRAM will be described with reference to FIG.

In FIG. 12, the input is variable-length coded data input from the variable-length coding circuit 5 in FIG. 1, and is input in the order of MB0 and MB1 in macroblock units. The output is format data to be output to the error correction coding circuit 31 in FIG. 1, and is output in the order of MB0 and MB1 in macroblock units in the same manner as input. Here, for example, MB0 to MB
Four (5) macroblocks correspond to one video segment.

In FIG. 12, FRAM is used in units of macro blocks, and in this embodiment, FRAMa is used.
7 to FRAMg are used. For example, in the case of FRAMa, during the period when MB0 is input (first step), M
The LAC of B0 is written, and the MAC is written in the free area of each fixed area during the period when MB1 is input (second step). In this second step, reading and writing are performed, and reading is performed when it is necessary to connect the MAC to the same address as the already written LAC and write the LAC in advance. And MB
During the period in which 6 is input (third step), the written LAC and MAC are read. In this series of steps, the constraint period from when data is written to the FRAM to when it is read is seven macroblocks, and seven FRAs are used.
M is shifted by one macroblock.

The MRAM is also used for each macroblock, and in this embodiment, two MRAMa and MRAMb are used. For example, in the case of MRAMa, the HAC of MB0 is written during the period when MB0 is input (first step), and the period when MB1 is input (second step).
Then, the HAC is read in order to write the MAC in the free area of each fixed area of the FRAMa. Also, in this second step, H that could not be completely written to FRAMa
AC is transferred to VRAMa. In this series of steps, the constraint period from the time data is written to the MRAM to the time it is read is two macroblocks.
Are shifted by one macroblock.

The VRAM is used in units of video segments, and in this embodiment, two VRAMs, VRAMa and VRAMb, are used. For example, in the case of VRAMa, MB1 to MB
5 is input (second step), the HAC that could not be stored in the FRAMa to FRAMe is written as the MAC of MB0 to MB4, and during the period (third step) where MB6 to MB10 are input, the FRAMa to MB4 are input.
It is read in order to connect and output the VAC to an empty area of the LAC and MAC read from the FRAMe. In this series of steps, the constraint period from the time data is written to the VRAM to the time it is read is two video segments, and two VRAMs are used shifted by one video segment.

Next, the FRAM at the time of the reformatting process,
Write and read timings of the MRAM and the VRAM will be described with reference to FIG. FIG.
, The input means the error correction decoding circuit 3 in FIG.
2 is the format data input from
0 and MB1 are input in the order of macroblocks. The output is the error processing circuit 22 in FIG.
Variable-length coded data to be output to
0 and MB1 are output in macroblock units in this order. Here, for example, five macroblocks MB0 to MB4 correspond to one video segment.

In FIG. 13, FRAM is used in units of macro blocks, and in this embodiment, FRAMa is used.
7 to FRAMg are used. For example, in the case of FRAMa, during the period when MB0 is input (first step), M
The format data of B0 is written, and the MAC and VAC stored in the free area of each fixed area are separated during the period when MB1 is input (second step), and the MRAM
a and VRAMa for reading. Then, during the period in which MB6 is input (third step), only the LAC of each fixed area in which data is written is output. In this series of steps, the constraint period from the writing of data to the FRAM until the data is read is seven macroblocks, and the seven FRAMs are used shifted by one macroblock.

The MRAM is used for each video segment, and in the present embodiment, two MRAMa and MRAMb are used. For example, in the case of MRAMa, MB1 to MB
5 is input (second step), the MACs of MB0 to MB4 are written, and during the input period of MB6 to MB10 (third step), FRAMa to FR are written.
If necessary, add MAC to LAC read from AMe
Are read in order to connect and output. In this series of steps, the constraint period until data is written to and read from the MRAM is two video segments,
Two MRAMs are used shifted by one video segment.

VRAMs are also used in video segment units. In this embodiment, two VRAMs, VRAMa and VRAMb, are used. For example, in the case of VRAMa, MB1 to MB
5 is input (second step), the VAC of MB0 to MB4 is written, and during the input of MB6 to MB10 (third step), FRAMa to FR are written.
If necessary, the VAC is connected to the LAC read from the AMe and the MAC read from the MRAMa, so that the VAC is read. In this series of steps, the constraint period from when data is written to and read out to the VRAM is two video segments, and two VRAMs are used.
Are shifted by one video segment.

Next, the processing of the recording system will be described with reference to FIG. The pixel data input to the pixel data input terminal 1 is divided by the shuffling circuit 2 into orthogonal transform blocks of 8 × 8 pixels, and further combined into a macroblock composed of a plurality of adjacent orthogonal transform blocks of luminance and chrominance components. The video segment is further combined into a video segment consisting of five macroblocks extracted from dispersed positions on the screen. Next, the pixel data is orthogonally transformed by the orthogonal transformation circuit 3 in units of orthogonal transformation blocks, and the AC component other than the DC component is quantized by the quantization circuit 4. The quantized AC component is determined by a variable-length coding circuit 5 using a well-known algorithm such as a two-dimensional Huffman code (a code word is determined from a combination of a zero run of the AC component and a subsequent non-zero value, and a combination having a high probability of occurrence is determined. Allocating a short code word to a combination and assigning a long code word to a combination having a low probability of occurrence) to reduce the data amount.
8 is input.

Next, the operation of the recording first step signal processing circuit 6 will be described with reference to FIG. In the recording first step signal processing, data processing is performed in units of macroblocks, and the variable length coded data of each orthogonal transform block input from the variable length coding circuit 5 is LAC in FRAM and HAC in MR.
The work of storing each in the AM is performed.

The variable length coded data of each orthogonal transform block input from the variable length coding circuit 5 is
Are arranged in order from the MSB side in units of 16 bits, and stored in each fixed area of the FRAM via the recording first step RAM control circuit 9a. The data is stored in the FRAM every time a 16-bit LAC is prepared in the cyclic coupler 202, but before the fixed area overflows, an end codeword (hereinafter referred to as an EOB code: EOB code:
nd Of Block Code), the LAC up to the EOB code is stored in the FRAM even if the cyclic coupler 202 does not have a 16-bit LAC.

The HACs are similarly arranged in order from the MSB side in 16-bit units using the cyclic coupler 204, and are sequentially stored in the MRAM via the recording first step RAM control circuit 9b. The storage in the MRAM is performed by the cyclic coupler 204.
Is performed every time a 16-bit HAC is prepared, but when all data processing in the macroblock is completed, the cyclic coupler 20
If the 16-bit HAC is not available in 4, the HAC remaining in the cyclic coupler 204 is stored in the MRAM.

In the above processing, the information necessary for the next recording second step signal processing includes the presence or absence of a free area of each fixed area of the FRAM in the macro block, and the start address and bit of the free area if there is a free area. The position information, the final write address of the MRAM, and the bit position information are stored.

In this embodiment, although not shown, the presence / absence of a free area in each fixed area of the FRAM in the macroblock, the start address and bit position information of the free area when there is a free area, and the last address of the MRAM The write address and bit position information are held using a register.

Here, in the present embodiment, the number of clocks allocated to the transfer of the DC component and AC component of one orthogonal transform block and the EOB code from the variable length coding circuit 5 is 64 clocks. One clock is used to transfer the DC component, and 6 is used to transfer the AC component and EOB code.
Since there are three clocks, there is no period for transferring the EOB code when there are 63 AC components.
Therefore, when there are 63 AC components, the EOB code is not transferred, and the format processing circuit 28
Code is to be added. Selector 2 in FIG.
03 is a circuit for performing this processing.

The recording stored in the first step signal processing,
In the fixed area of the first orthogonal transformation block having an empty area of the FRAM, the data of the head address of the empty area is recorded from the FRAM, one word is read out via the second step RAM control circuit 10a, and valid data ( LAC) only. At this time, the selector 301 sets F
Control is performed so as to pass data read from the RAM. Next, the selector 301 reads the HAC read from the MRAM.
And read the HAC stored in the MRAM one word at a time from the MRAM via the recording second step RAM control circuit 10b.
2 is linked to a free area of valid data held in the FRAM 2 via the recording second step RAM control circuit 10c.
To the same address.

If there is an empty area at the address next to the written FRAM, the HAC read from the MRAM is used.
From the next HAC already written to the FRAM,
The second step RAM control circuit 10c is arranged in order from the MSB side in 16-bit units by using the cyclic coupler 302.
And the process is repeated until there is no more free space in the first fixed area.

Similarly, for the fixed area of the second and subsequent orthogonal transform blocks having an empty area, one word of the data of the head address of the empty area is read out from the FRAM, and only the valid data (LAC) is written to the cyclic coupler 302. The HAC held and read from the MRAM are sequentially transmitted from the next HAC already written to the FRAM to the FR controller via the cyclic coupler 302 and the recording second step RAM control circuit 10c.
It is embedded in the free area of the fixed area of AM.

In this process, between the total of the free areas in the macroblock and the total of the HAC, the HAC is naturally smaller than, equal to, or larger than the total of the free areas in the macroblock. If there are three states and the HAC is less than the total free space in the macroblock, the HACs are all stored in the free space in the fixed area of another orthogonal transform block in the same macroblock, and the MRAM All the HACs stored in
At the time when the data is stored in the AM, the recording second step signal processing ends.

If the HAC is larger than the total free area in the macro block, the HA that cannot be stored in the FRAM
C means that the HAC is
3 is sequentially arranged in units of 16 bits from the MSB side using V.3, and V is set via the recording second step RAM control circuit 10d.
Store in RAM.

In the above processing, the information necessary for the next recording third step signal processing includes the presence / absence of a free area in each fixed area of the FRAM in the video segment, and if there is a free area, the start address and bit of the free area The position information, the final write address of the VRAM, and the bit position information are stored.

In the present embodiment, although not shown, the presence / absence of a free area of each fixed area of the FRAM in the video segment and the start address and bit position information of the free area when there is a free area are stored in the FPRAM. VRA
The final write address and bit position information of M are held using a register.

Next, the operation of the recording third step signal processing circuit 8 will be described with reference to FIG. In the recording third step signal processing, data processing is performed in video segment units,
In the process up to the recording second step signal processing, the work of outputting as format data while embedding the HAC stored in the VRAM into the free area of the LAC and MAC stored in the FRAM is performed.

The LAC and MA stored in the FRAM in the recording first step signal processing and the recording second step signal processing
C is sequentially read out via the recording third step RAM control circuit 11a, and at the same time, information as to whether or not an empty area remains in each fixed area is read out from the FPRAM. V in two-step signal processing
The HACs stored in the RAM are sequentially recorded from the head address. The third step is read out via the RAM control circuit 11b, and the cyclic coupler 401 is used to rearrange the LACs and MACs read from the FRAM so that they can be connected after the MAC. , And outputs the format data to the pixel data output terminal 403 while filling the LAC and MAC empty areas read from the FRAM using the coupler 402.

The output format data is input to the error correction encoding circuit 31 shown in FIG. 1 and added with an error correction code for correcting a code error at the time of reproduction. After that, it is recorded on a tape.

Next, the processing of the reproducing system will be described with reference to FIG. Although not shown, the reproduced signal reproduced from the tape is demodulated by a digital demodulation circuit, and then corrected or corrected for a code error during reproduction by an error correction decoding circuit 32.
The data is input to the deformat processing circuit 29.

Next, the operation of the reproduction first step signal processing circuit 16 will be described with reference to FIG. In the reproduction first step signal processing, data processing is performed on a macro block basis, and the format data input from the error correction decoding circuit 32 is stored in the FRAM via the reproduction first step RAM control circuit 19a.

When the error correction decoding circuit 32 fails to correct and correct a code error, the selector 502
This is a circuit for forcibly writing an error code based on a flag sent together with the format data. The pixels of the orthogonal transformation block replaced by the error code are subjected to processing such as replacement with the pixels of the previous frame by the deshuffling circuit 26 in FIG. 1 to prevent the screen from breaking down as much as possible. However, when the error is corrected by the error correction decoding circuit 32, the flag is not true and the flag is not replaced with the error code.

Next, the operation of the reproduction second step signal processing circuit 17 will be described with reference to FIG. Also in the second reproduction signal processing, data processing is performed in units of macroblocks. In this step, the processing is divided into two processes.

In the first process, the first EOB code in each fixed area of the format data stored in the FRAM is detected in the first reproduction signal processing. When the EOB code is detected by the first process, it is known that the variable length coded data after the detected EOB code is the HAC, and the LAC and the HAC can be separated.

In the second process, the HAC separated in the first process are connected, and the EOB code is further detected. Through the first process and the second process, the first process
It is understood that the HAC is MAC until the sum of the number of EOB codes detected in the second process and the number of EOB codes detected in the second process reaches the number of fixed regions in the macroblock. HAC is VAC
Therefore, the HAC can be separated into the MAC and the VAC. In the reproduction second step signal processing, the MAC and the VAC are separated by the above procedure, and the MAC is stored in the MRAM,
The process of storing the AC in the VRAM is performed.

Hereinafter, a specific processing procedure of the first process will be described. In the first process, the format data stored in the FRAM in the reproduction first step signal processing is read out through the reproduction second step RAM control circuit 20a, and the selector 602 is read out of the data from the reproduction second step RAM control circuit 20a. Is passed through, and is held in the register 603 with a hold circuit. When the next data is input from the selector 602 to the register with a hold circuit 603, the data held in the register with a hold circuit 603 is transferred and held to the register with a hold circuit 604, and the register with the hold circuit 603 stores new data. Hold. That is, control is performed so that the latest data input from the selector 602 is held in the register with hold circuit 603, and the immediately preceding data is held in the register with hold circuit 604.

The shifter 605 receives the 16-bit data held in the register with hold circuit 604 and the 31-bit data of the 15-bit data on the MSB side held in the register with hold circuit 603, and receives the VLC detector The input to 607 is output as 16 bits on the MSB side shifted so that the MSB always becomes the head of the variable length coded data. However, in the first process, only the 8 bits on the MSB side in the 16-bit output of the shifter 605 are used (in the present embodiment, the detection of the variable-length coded data length described below can all be detected in 8 bits). .

In the first process, the coupler 606 is controlled so that the data from the shifter 605 always passes, and the 8 bits on the MSB side output from the shifter 605
Is input to the VLC detector 607.

In the VLC detector 607, the input 8bi
The main purpose of the first process is to detect the first EOB code in the variable-length coded data in each fixed area from the t-data, but the detection of the EOB code is based on the previous variable-length coded data. Since it is necessary to detect the length one by one and follow the variable-length coded data, the variable-length coded data length is also detected, and the detected variable-length coded data length is output.

In the first process, the selector 609 always sets V
The variable length coded data length output from the LC detector 607 is controlled to pass, and the cumulative adder 610 performs cumulative addition of the variable length coded data length. The result of the cumulative addition is used to read data from the FRAM, hold data in the register with hold circuit 603 and the register with hold circuit 604, and control the shift amount of the shifter 605.

The EOB code detection operation is completed when the first EOB code is detected for each fixed area, and the process proceeds to the next fixed area EOB code detection. If the EOB code cannot be detected even if the detection operation is continued up to the end of the fixed area, the process then proceeds to the next fixed area EOB code detection.

If the EOB code is not detected in all the fixed areas in the macro block in the first process, that is, if the number of detected EOB codes is 0, the variable of all the fixed areas in the macro block is changed. This indicates that the long coded data is overflowing, and the macroblock has MA
Neither C nor VAC is included. Therefore, the second process is not performed because the separation of MAC and VAC, which is the purpose of the reproduction second step signal processing, is not necessary. In other cases, the process proceeds to the second process.

Here, as information necessary in the second process, the number of fixed areas in which the EOB code can be detected and the EOB code
The position information of the next bit of the code, that is, the first bit of the HAC in the fixed area, the number of fixed areas where the EOB code could not be detected, and whether the variable-length encoded data is interrupted at the end position in the fixed area If the variable length coded data is interrupted on the way, the variable length coded data up to the middle and the bit length information are stored.

In this embodiment, the variable-length coded data interrupted in the fixed area where the EOB code could not be detected is held in the shift register 611. In addition, the EOB code could be detected. The number of fixed areas, the position information of the first bit of the HAC in the fixed area, the number of fixed areas in which the EOB code could not be detected, and whether or not the variable length coded data is interrupted in the middle at the last position in the fixed area , And the bit length information of the variable-length coded data interrupted in the middle of the fixed area are held by using other registers, though not shown.

In the second process, the following processing is performed based on the information obtained in the first process. If the number of EOB codes detected in the first process is the same as the number of fixed areas in the macro block, that is, if EOB codes are detected in all fixed areas, the variable of all the fixed areas in the macro block is changed. This indicates that the long coded data is contained in each fixed area, and it can be seen that the variable length coded data after the EOB code, that is, the HAC is all VAC. Therefore, in the second process, all of the HACs are VR
Store in AM.

When the number of EOB codes detected in the first process is other than the above, HAC is added after the variable length coded data that is interrupted in the middle of the first fixed area where the EOB code cannot be detected. The EOB code detection work is continued by connecting the HACs in the first fixed area included in this order. If the EOB code is not detected even when all the HACs in the first fixed area including the HAC are used, the HACs in the second and subsequent fixed areas including the HAC are sequentially joined, The same processing is continued.

When an EOB code is detected,
After the variable-length coded data that is interrupted in the middle of the second or subsequent fixed area where the EOB code cannot be detected,
HACs not yet used for the OB code detection operation are connected in order to continue the EOB code detection operation.

The EOB code detection is performed by checking whether the sum of the number of EOB codes detected in the first process and the number of EOB codes detected in the second process reaches the number of fixed areas in the macroblock. , Until the HAC is gone.

Through this operation, it is understood that the HAC is MAC until the sum of the number of EOB codes detected in the first process and the second process reaches the number of fixed regions in the macroblock. It can be seen that the HAC after the sum reaches the number of fixed areas in the macroblock is a VAC. Therefore, the HAC until the sum reaches the number of fixed areas in the macroblock is stored in the MRAM, and the HAC after the previous sum reaches the number of fixed areas in the macroblock is stored in the VRAM.

Hereinafter, a specific processing procedure of the second process will be described. First, the flow of data from the FRAM to the shifter 605 in the second process will be described. The data of the first address including the HAC is read out from the FRAM sequentially from the front via the reproduction second step RAM control circuit 20a, and supplied to the cyclic coupler 601.

In the cyclic coupler 601, the head of the read HAC becomes the MSB based on the positional information of the head bit of the HAC held in the first process in the fixed area, and the subsequent HAC becomes the LSB. Bits are circulated so as to be continuous on the side, and are arranged in 16-bit units sequentially from the MSB side.

In the second process, the selector 602 is controlled so that the output from the cyclic coupler 601 always passes, and the HAC arranged in units of 16 bits is supplied to the register 603 with a hold circuit. The register with hold circuit 603 holds the HAC input via the selector 602 when the HAC has been aligned in the cyclic coupler 601 at 16 bits.

The next HAC in the cyclic coupler 601 is 16 bi
When t is completed, the HAC held so far is transferred to the register with a hold circuit 604, and the HAC is newly held. That is, the relationship between the register with a hold circuit 603 and the register with a hold circuit 604 is the same as in the first process, and the register with the hold circuit 603 has the latest HAC input from the selector 602 and the register with the hold circuit 604.
Is controlled so that the previous HAC is held.

In the shifter 605, in order to supply the first data of the second process to the VLC detector 607, first, the variable-length coded data is transmitted at the final position of the first fixed area where the EOB code cannot be detected. If the variable-length coded data is interrupted on the way based on the information on whether or not the data is interrupted in the middle, the MSB side is vacated by the bit length of the variable-length coded data interrupted on the way. Register 603 with hold circuit and register 60 with hold circuit
4 shifts the input HAC. If the variable length coded data is not interrupted on the way at the last position of the first fixed area where the EOB code cannot be detected, the HAC
Is not shifted.

The output of the shifter 605 is connected to a coupler 606.
Is supplied to one input. Further, the shift register 611 supplies variable-length coded data that is interrupted at the beginning of the fixed area where the EOB code cannot be detected in the first process to the other input of the coupler 606. The coupler 606 is interrupted on the way to the variable length encoded data on the basis of information on whether the variable length encoded data is interrupted on the way at the final position of the first fixed area where the EOB code could not be detected. In this case, the variable-length encoded data supplied from the shift register 611 is interrupted, and the HAC supplied from the shifter 605 is connected to the LSB side, and the MSB side 8 bits of the connected data are output. . If the variable length coded data is not interrupted on the way, the input from the shift register 611 is ignored, and the MAC of the HAC supplied from the shifter 605 is ignored.
The SB side outputs 8 bits.

The VLC detector 607 detects the EOB code and the variable-length coded data length based on the input 8-bit data as in the first process. The only difference from the first process is that the shift Variable-length encoded data supplied from the register 611 and interrupted in the middle;
Only when the variable length coded data length obtained by concatenating the HACs supplied from the shifter 605 is output, the VLC detector 6
A process of subtracting the bit length (614 in FIG. 6) of the variable-length coded data that has been interrupted halfway using the adder 608 is performed from the variable-length coded data length output from 07.

The selector 609 operates only at this time.
Is controlled to pass the data from. Selector 60
9, the variable-length coded data length is added to the accumulator 610.
And the cumulative addition of the variable-length encoded data length is performed in the same manner as in the first process. As in the first process, the result of the accumulative addition is read out of the data from the FRAM, the register 603 with the hold circuit and the register 6
04 is used for holding the data and controlling the shift amount of the shifter 605.

On the other hand, in the second process, the sum of the EOB code detected in the second process and the EOB code detected in the first process is sequentially calculated, and the sum is calculated as the number of fixed regions in the macroblock. HAC to reach, ie M
The AC uses the cyclic coupler 612 to convert the MS into 16-bit units.
They are arranged in order from the B side and are sequentially stored in the MRAM via the reproduction second step RAM control circuit 20b. HA after the sum reaches the number of fixed areas in the macroblock
C, that is, VAC is 16 bits using the cyclic coupler 613.
The unit is arranged in order from the MSB side, and the reproduction second step RA
The data is sequentially stored in the VRAM via the M control circuit 20c.

In the above-mentioned processing, the last write address of the MAC of each macro block stored in the MRAM and b
The it position information, the final write address of the VAC stored in the VRAM, and the bit position information are not shown, but are held using a register.

Next, the operation of the reproduction third step signal processing circuit 18 will be described with reference to FIG. In the reproduction third step signal processing, data processing is performed in video segment units, and the DC component and LAC stored in the FRAM in the reproduction first step signal processing are separated into MRAM and VRAM in the reproduction second step signal processing. MAC stored
And VAC are connected and output to the error processing circuit 22.

Here, when the information known up to the present is arranged, the MAC of each macroblock is stored in the MRAM in order from the front of the address in the reproduction second step signal processing, and the boundary of the MAC for each macroblock is stored. Although not shown, it is held in a register. VR
The VAC in the video segment is stored in the AM in order from the front of the address in the reproduction second step signal processing,
Although not shown, the final write address and bit position information of the VAC are held in a register.

Therefore, in order to connect and output a DC component and a variable-length AC component (LAC, MAC, VAC) for each orthogonal transformation block, the DC component stored in the fixed area of the FRAM is first read out. Subsequently, the variable length coded data length of the LAC is detected one by one and read while tracking the variable length coded data.
When the B code is detected, the orthogonal transform block has H
Since there is no AC, the processing is stopped until the processing of the next orthogonal transformation block is started.

If the EOB code cannot be detected in the LAC, the MAC is connected after the LAC, and the detection of the variable-length coded data length and the EOB code is continued. Here, when there is no MAC, or even when the boundary of the MAC of the macroblock to which the orthogonal transform block belongs is reached, EOB
If the code cannot be detected, the VAC is further connected to continue the work of detecting the variable-length coded data length and the EOB code. Here, if there is no VAC, or if the EOB code is not detected even when the VAC reaches the final VAC write position in the video segment, the processing is stopped until the processing of the next orthogonal transformation block is started at that point. This operation is performed for all the orthogonal transform blocks in the video segment.

In the reproduction third step signal processing, the DC component of each orthogonal transform block and the variable-length AC component (LAC,
MAC, VAC) for continuous connection and output, and the RAM of each of FRAM, MRAM and VRAM
It is necessary to pre-read the data stored in the buffer and store it in the buffer. The buffers 701, 702, and 703 are used for this purpose.

The capacity of these buffers is
M from the read request to M, the read third step RAM control circuit 21a, the third read step R
It relates to the number of clock cycles required to pass through the AM control circuit 21b and the reproduction third step RAM control circuit 21c to reach the respective buffers, and is composed of a shift register of 16 bits width and several stages.

Hereinafter, a specific processing procedure of the reproduction third step signal processing will be described. DC component and LAC previously stored in the FRAM in the reproduction first step signal processing
Is stored in the read buffer 701 as necessary through the third reproduction step RAM control circuit 21a, and the MAC stored in the MRAM and the VAC stored in the VRAM in the second reproduction step signal processing are similarly stored. The reproduction third step RAM control circuit 21b and the reproduction third
The necessary data is read out via the step RAM control circuit 21c and stored in the buffers 702 and 703, respectively. Since the DC component has a fixed length, the DC component is directly supplied to the selector 714, bypassing the work of detecting the variable-length encoded data length and the EOB code.

The operation of detecting the variable length coded data length and EOB code of each orthogonal transform block will be described below. LA of each orthogonal transform block held in the buffer 701
C is connected to a register with a hold circuit 70 via a coupler 707.
8 and the held LAC is input to the MSB side 16 bits of the input 31 bits of the shifter 709.

The remaining one on the LSB side of the input of the shifter 709
5 bits is the 15 bits on the MSB side of the next LAC that is directly input via the coupler 707. Shifter 709
Bit shifts the input 31 bits so that the head of the variable length coded data is always the MSB,
16 bits are output on the side. The 8 bits on the MSB side of the 16 bits output from the shifter 709 are the VLC detector 71.
0 has been entered.

The VLC detector 710 detects the variable length coded data length and the EOB code. Cumulative adder 711
Accumulates the variable length coded data length in each orthogonal transform block input from the VLC detector 710. Hereinafter, V
The LC detector 710 sequentially detects the variable length coded data length of the LAC and the EOB code. LA in this work
When the EOB code is detected in C, the processing is stopped until the processing of the next orthogonal transformation block is started.

If the EOB code is not detected in the LAC, the MAC held in the buffer 702 is bit-circulated using the cyclic concatenator 704 so as to be continuously connected after the LAC. The LAC is connected after the LAC using the connector 707, and the detection of the variable length coded data length and the EOB code is continued. Here, if there is no MAC, or if the EOB code is not detected even when the MAC boundary of the macroblock to which the orthogonal transform block belongs is detected, the VAC stored in the buffer 703 is used.
Is cyclically connected using the cyclic coupler 705 so as to be continuously connected after the LAC or the MAC.
6. Connect after the LAC or MAC using the connector 707 to continue detection of the variable length coded data length and EOB code. Here, if there is no VAC, or if the EOB code is not detected even when the VAC reaches the final VAC write position in the video segment, the processing is stopped until the processing of the next orthogonal transformation block is started at that point.

On the other hand, the shifter 70 is provided in the mask circuit 712.
9 output 16 bits are input, and the VLC detector 7
Only the MSB side input for the variable length coded data length detected at 10 is passed, the other LSB side inputs are masked to the LOW level, and the EOB addition circuit 713 does not detect the EOB code even when all the VAC is used up. In this case, EOB is added immediately after the previously completely detected variable-length coded data.
A code is added, and the selector 714 combines the DC component with a DC component input through another path and outputs the resultant to an output terminal 715.

Next, error detection in the third reproduction signal processing will be described. In this embodiment, a pixel set of 8 × 8 pixels is regarded as one orthogonal transform block, and the orthogonal transform and quantized 63 AC components are subjected to 0-run of the AC component by using an algorithm such as a two-dimensional Huffman code. Then, a code word is generated from a combination of a non-zero value and the following value.

Therefore, in one orthogonal transform block,
When all the quantized AC components take values other than 0, the number of codewords becomes the maximum number of 63, and when a value of 63 or more is obtained (there is no EOB code following the 63rd codeword) Case)
It is clear that a code error has occurred on the way. A code error that can be detected under this condition is defined as an AC63 error.

In one orthogonal transformation block,
When the AC component at the final scan position (highest band) by a well-known zigzag scan or the like takes a value other than 0, the cumulative addition value of the value obtained by adding 1 to the coded 0 run length is 6 at the maximum.
It is clear that when a value of 3 or more is obtained, a code error occurs on the way. A code error that can be detected under this condition is a RUN63 error.

In the reproduction third step signal processing, the A
A C63 error and a RUN63 error are detected.

First, a method for detecting an AC63 error will be described. The EOB detector 717 receives the four MSBs from the shifter 709 and outputs a flag that becomes true when the input pattern matches the EOB code. 4 bits corresponds to the EOB code length in the present embodiment. The VLC counter 716 is a counter that counts the number of variable-length encoded data in the orthogonal transform block.
When the EOB detector 717 detects the EOB code of the first variable-length coded data in the orthogonal transform block, the EOB code becomes 0 when the EOB code is detected. Count up until is detected. The AC63 error detector 718 outputs AC6 when the output of the EOB detector 717 is false when the count value of the VLC counter 716 reaches 63.
3 Set the error detection flag to true.

Next, a method of detecting a RUN 63 error will be described. The RUN detector 720 includes a shifter 709
13 bits of the MSB side of the output from is input, the 0-run length of the input variable-length coded data is obtained, and a value obtained by adding 1 thereto is output. Hereinafter, a value obtained by adding 1 to 0 run length is referred to as RUN. Here, 13bi
t corresponds to the bit length required to obtain the zero run length of all the variable length coded data used in the present embodiment.

RUN output from RUN detector 720
Is input to the accumulator 721. Cumulative adder 721
Performs the cumulative addition of the RUN for each orthogonal transformation block and outputs the cumulative addition value to the comparator 722. Comparator 722
Sets the RUN63 error detection flag to true when the cumulative addition value exceeds 63.

If either or both of the two errors are detected, it means that the MAC of the macroblock to which the orthogonally-transformed block in which the error is detected can no longer be relied upon, and the error is detected. This also means that the VAC of the video segment to which the orthogonal transform block belongs is no longer reliable.

Therefore, the following two error processes are executed in the third reproduction signal process. The first error processing is for orthogonal transform blocks subsequent to the orthogonal transform block in which an error has been detected in the macroblock.
Stop output of MAC and VAC. In the second error processing, the output of the VAC is stopped for the macroblocks after the macroblock in which the error is detected in the video segment.

When the output of the MAC is stopped, the read pointer of the MRAM is forcibly set to the boundary of the MAC of the macroblock to which the orthogonal transform block belongs (all the MACs in the corresponding macroblock are exhausted). Things can be easily realized.

The output stop of the VAC can be easily realized by forcibly setting the read pointer of the VRAM to the last write position of the VAC in the video segment (all the VACs are used up).

As a result of these error processes, the output of unreliable variable-length coded data for the variable-length coded data after the orthogonal transform block in which an error has been detected in the video segment is stopped to reduce screen breakdown. However, regarding the orthogonal transform block in which an error is detected, the error detection is performed while outputting the variable-length coded data. Data has been output. The error processing circuit 22 at the next stage masks the output of the erroneous variable-length coded data.

Next, the operation of the error processing circuit 22 will be described with reference to FIG. In the error processing, data processing is performed in units of orthogonal transform blocks, and the variable-length coded data synthesized in the reproduction third step signal processing is delayed by one orthogonal transformation block using the FIFO 802. The output AC63 error detection flag and RU
The N63 error detection flag is monitored. If either or both error detection flags are true, the variable-length coded data output from the FIFO is masked by the mask circuit 803 and replaced with data such as an error code. Is output as deformed data.

The outputted deformed data is decoded by a variable length decoding circuit 23 shown in FIG. 1 according to a well-known algorithm such as a two-dimensional Huffman code, and is inversely quantized by an inverse quantization circuit 24. The pixel data is rearranged by the deshuffling circuit 26 and output from the pixel data output terminal 27.

In the embodiment of the present invention, AC
1 shows an example in which the error processing circuit 22 in FIG. 1 performs a process of masking variable-length encoded data of a corresponding orthogonal transform block based on a 63 error detection flag and a RUN 63 error detection flag and replacing the data with an error code or the like. However, when the delay circuit for one orthogonal transform block is mounted on the variable length decoding circuit 23 located at the subsequent stage of the deformat processing unit 29, the AC6
The same effect can be obtained by masking the variable-length coded data of the corresponding orthogonal transform block based on the 3 error detection flag and the RUN63 error detection flag and replacing it with data such as an error code. Although not illustrated again, in this case, the configuration is such that the error processing circuit 22 in FIG. 1 is simply deleted.

[0125]

As described above, in the digital video signal processing apparatus of the present invention, a complicated circuit is not required for controlling the address of the RAM, and the circuit scale can be reduced.
Further, the increase in the RAM capacity for storing the HAC as compared with the prior art is offset by the reduction in the FRAM capacity by using the FRAM in macroblock units, and the total RAM capacity can be reduced. The circuit scale can be further reduced. In addition, since the process of preventing the reproduction image from being broken due to the erroneous correction is performed, the quality of the reproduction image can be improved when the reproduction condition is poor or during high-speed reproduction.

Since the digital video signal processing device according to the first aspect of the present invention has the above-described configuration, the first memory, the second memory, and the third memory are each used during the format processing. Address control can be realized by simple control, and the circuit size can be reduced.

Since the digital video signal processing device according to the second aspect of the present invention has the above-described configuration, the second memory and the third memory are simply replaced during format processing. By using a single memory, writing and reading control of the memory can be realized by simple control, and the circuit scale can be further reduced as compared to the first aspect of the present invention.

Since the digital video signal processing apparatus according to the third aspect of the present invention has the above-described configuration, the first memory is set to n for the number of macroblocks in the video segment during format processing. In this case, the required first memory capacity can be greatly reduced by using n + 2 macroblock units, and the first memory, the second memory, and the third memory necessary for the format processing can be reduced.
The total required memory capacity including the above-mentioned memories can be reduced as compared with the related art, and the circuit scale can be further reduced as compared with the first and second aspects of the present invention.

Since the digital video signal processing device according to the fourth aspect of the present invention has the above-described configuration, the first memory, the second memory, and the third memory are each used during the deformatting process. Address control can be realized by simple control, and the circuit size can be reduced.

Since the digital video signal processing apparatus according to the fifth aspect of the present invention has the above-described configuration, the second memory and the third memory are required for the reformatting process.
By simply using two memories each of which is simply replaced, the writing and reading control of the memories can be realized by simple control, and the circuit scale can be further reduced as compared to the fourth aspect of the present invention.

Since the digital video signal processing device according to the sixth aspect of the present invention has the above-described configuration, the first memory stores the number of macroblocks in a video segment as n during the deformatting process. In this case, the required first memory capacity can be greatly reduced by using n + 2 macroblock units, and the first memory, the second memory, and the third memory required for the deformatting process can be reduced. The total required memory capacity can be reduced as compared with the related art, and the circuit scale can be further reduced as compared with claims 4 and 5 of the present application.

Since the digital video signal processing apparatus according to the present invention has the above-described configuration, it detects an error in the variable-length coded data due to an erroneous correction during the deformat processing, and The variable-length coded data of the detected orthogonal transform block is replaced with an error code indicating that there is an error, and the variable-length coded data of the subsequent orthogonal transform block in the macro block is arranged in a corresponding fixed area. Decodes only the variable-length coded data that is present in the video segment, and converts the variable-length coded data of the orthogonal transform block in a subsequent macroblock in the video segment into the same macroblock By decoding only the variable-length coded data located in other fixed areas in the Ken made it possible to improve the quality of the reproduced image at the time of the case and the high-speed reproduction bad.

Since the digital video signal processing apparatus according to the present invention has the above-described configuration, the deformat processing specifically includes an error in the variable-length encoded data due to an erroneous correction. It is possible to detect an AC63 error and prevent a screen breakdown, and to improve the quality of a reproduced image when reproduction conditions are poor or during high-speed reproduction.

Since the digital video signal processing apparatus according to the ninth aspect of the present invention has the above-described configuration, the deformat processing specifically includes an error in the variable-length coded data due to an erroneous correction. RUN 63 errors can be detected and screen failure can be prevented, and the quality of reproduced images can be improved when reproduction conditions are poor or during high-speed reproduction.

Since the digital video signal processing apparatus according to the tenth aspect of the present invention has the above-described configuration, in the case of the deformat processing, the error of the variable length coded data due to the erroneous correction is specifically determined as follows. It is possible to detect both the AC63 error and the RUN63 error and prevent a screen failure, and to improve the quality of a reproduced image when reproduction conditions are poor or during high-speed reproduction.

Next, the operation of the recording second step signal processing circuit 7 will be described with reference to FIG. Also in the recording second step signal processing, data processing is performed in macroblock units, and the HAC stored in the MRAM in the recording first step signal processing is transferred to the free area of the fixed area of another orthogonal transformation block in the same macroblock. We are working on storing.

[Brief description of the drawings]

FIG. 1 is an overall block diagram according to an embodiment of the present invention.

FIG. 2 is a block diagram of a recording first step signal processing circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram of a recording second step signal processing circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram of a recording third step signal processing circuit according to the embodiment of the present invention.

FIG. 5 is a block diagram of a reproduction first step signal processing circuit according to the embodiment of the present invention;

FIG. 6 is a block diagram of a reproduction second step signal processing circuit according to the embodiment of the present invention.

FIG. 7 is a block diagram of a reproduction third step signal processing circuit according to the embodiment of the present invention.

FIG. 8 is a block diagram of an error processing circuit according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram relating to the capacity of the MRAM at the time of format processing according to the embodiment of the present invention;

FIG. 10 is an explanatory diagram relating to the capacity of the MRAM at the time of deformat processing according to the embodiment of the present invention;

FIG. 11 is an explanatory diagram relating to the capacity of the VRAM according to the embodiment of the present invention;

FIG. 12 is an explanatory diagram relating to write and read timings of FRAM, MRAM, and VRAM memories at the time of format processing according to the embodiment of the present invention.

FIG. 13 is an explanatory diagram regarding write and read timings of the FRAM, the MRAM, and the VRAM during the deformat processing according to the embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 6 first recording step signal processing circuit 7 second recording step signal processing circuit 8 third recording step signal processing circuit 16 first reproduction step signal processing circuit 17 second reproduction step signal processing circuit 18 third reproduction step signal processing circuit 22 error Processing circuit 28 Format processing circuit 29 Deformat processing circuit

Claims (10)

[Claims] An orthogonal transform unit for orthogonally transforming an orthogonal transform block composed of a plurality of pixels as a unit; a quantizing unit for quantizing orthogonal components of the orthogonal transform block obtained by the orthogonal transform unit; Variable length encoding means for converting the orthogonal components of the quantized orthogonal transform block obtained by the means into variable length encoded data; and variable length encoded data of the orthogonal transform block obtained by the variable length encoding means. Means for collecting a plurality of orthogonal transform blocks to form a macroblock; means for collecting a plurality of the macroblocks to form a video segment; and code amount control means for controlling a code amount in the video segment to be substantially constant. The variable length encoded data of the orthogonal transform block in the variable length encoded video segment is transmitted to a plurality of sync blocks corresponding to macro blocks. In a digital video signal processing device that packs in a lock, a fixed-length fixed area for storing variable-length coded data of orthogonal transform blocks in the number of orthogonal transform blocks in a macro block is provided as the capacity for one sync block. The variable length encoded data of each orthogonal transform block is arranged in each fixed area of the first memory, and the variable length encoded data of the orthogonal transform block in the macro block which cannot be arranged in the fixed area is stored in the second memory. The variable-length coded data stored in the second memory is placed in a free area where the variable-length coded data is not yet placed in each fixed area of the first memory, The variable length coded data stored in the second memory that cannot be arranged in the free area of each fixed area of the orthogonal transform block of In the fixed area of the orthogonal transformation block in each macroblock in the video segment, the variable length coding stored in the third memory is stored in an empty area where the variable length coding data is not yet arranged. A digital video signal processing device characterized by arranging data. 2. The second memory according to claim 1, wherein:
The digital memory according to claim 1, wherein two memories alternated in macroblock units are used, and the third memory according to claim 1 uses two memories alternated in video segment units. Video signal processing device. 3. The first memory according to claim 1, wherein:
3. The digital video signal processing apparatus according to claim 1, wherein when the number of macroblocks in a video segment is n, n + 2 macroblocks are used. 4. An orthogonal transformation unit for performing orthogonal transformation in units of an orthogonal transformation block composed of a plurality of pixels; a quantization unit for quantizing orthogonal components of the orthogonal transformation block obtained by the orthogonal transformation unit; Variable length encoding means for converting the orthogonal components of the quantized orthogonal transform block obtained by the means into variable length encoded data; and variable length encoded data of the orthogonal transform block obtained by the variable length encoding means. Means for collecting a plurality of orthogonal transform blocks to form a macroblock; means for collecting a plurality of the macroblocks to form a video segment; and code amount control means for controlling a code amount in the video segment to be substantially constant. The variable length encoded data of the orthogonal transform block in the variable length encoded video segment is transmitted to a plurality of sync blocks corresponding to macro blocks. In a digital video signal processing device for decoding variable-length coded data packed by a digital video signal processing device for packing in a lock, the capacity of one sync block is determined by the number of orthogonal transform blocks in a macro block and the number of orthogonal transform blocks. Packed variable-length coded data is stored in a first memory having a fixed-length fixed area for storing variable-length coded data, and another orthogonal transformation block in the same macroblock is stored in each fixed area. Is stored in the second memory, and the variable-length coded data of the orthogonal transform block in another macroblock in the video segment is stored in the third memory.
And the variable length coded data corresponding to each fixed area stored in the first memory and the other fixed area in the same macro block stored in the second memory. The variable-length encoded data is decoded by joining the variable-length encoded data and the variable-length encoded data arranged in a fixed area in another macroblock in the video segment stored in the third memory. Digital video signal processing device characterized by the following. 5. The digital video signal according to claim 4, wherein each of the second memory and the third memory according to claim 4 uses two memories that are alternated in video segment units. Processing equipment. 6. The first memory according to claim 4, wherein:
6. The digital video signal processing apparatus according to claim 4, wherein when the number of macroblocks in a video segment is n, n + 2 are used. 7. An orthogonal transformation unit for performing orthogonal transformation in units of an orthogonal transformation block composed of a plurality of pixels; a quantization unit for quantizing orthogonal components of the orthogonal transformation block obtained by the orthogonal transformation unit; Variable length encoding means for converting the orthogonal components of the quantized orthogonal transform block obtained by the means into variable length encoded data; and variable length encoded data of the orthogonal transform block obtained by the variable length encoding means. Means for collecting a plurality of orthogonal transform blocks to form a macroblock; means for collecting a plurality of the macroblocks to form a video segment; and code amount control means for controlling a code amount in the video segment to be substantially constant. The variable length encoded data of the orthogonal transform block in the variable length encoded video segment is transmitted to a plurality of sync blocks corresponding to macro blocks. A digital video signal processor that decodes variable-length coded data packed by a digital video signal processor that packs in a lock. An orthogonal transform block that detects an error in the variable-length coded data due to erroneous correction and detects the error. Replace the variable-length coded data of the macroblock with the error code indicating that there is an error, and replace the variable-length coded data of the subsequent orthogonal transform block in the macro block only with the variable-length coded data located in the corresponding fixed area. Decodes the variable-length coded data of the orthogonal transform block in the subsequent macroblock in the video segment into the variable-length coded data located in the corresponding fixed area and another fixed area in the same macroblock. A digital video signal processing device characterized in that it decodes only the variable-length coded data arranged. 8. An error in variable-length coded data due to an erroneous correction according to claim 7, wherein the variable-length coded data corresponding to each fixed area arranged in each fixed area and the variable-length coded data in the same macroblock When joining variable-length coded data arranged in another fixed area and variable-length coded data arranged in a fixed area in another macroblock in a video segment, the variable length encoded data in the orthogonal transform block is connected. The number of encoded data is counted, and when the counted number reaches the maximum number of variable-length encoded data in the orthogonal transform block, it is determined whether the next variable-length encoded data is an end codeword. 8. The digital video signal processing apparatus according to claim 7, wherein if the codeword is not an end codeword, it is determined that the error is in variable-length encoded data. 9. An error in variable-length coded data due to an erroneous correction according to claim 7, wherein the variable-length coded data corresponding to each fixed area arranged in each fixed area and the variable-length coded data in the same macroblock When joining the variable-length coded data arranged in another fixed area and the variable-length coded data arranged in a fixed area in another macroblock in the video segment, the variable length coded data 0 The run length is decoded, the cumulative addition of the value obtained by adding 1 to 0 run length in the orthogonal transformation block is performed, and the result of the cumulative addition is less than or exceeds the maximum value of the cumulative addition value in the orthogonal transformation block. 8. The digital video signal processing apparatus according to claim 7, wherein the digital video signal processing apparatus determines whether the error is in the variable length coded data if the maximum value is exceeded. 10. The error of the variable-length coded data due to the erroneous correction according to claim 7 includes the error of the variable-length coded data due to the erroneous correction according to claim 8, and the error of the variable-length coded data according to claim 9. 10. The digital video signal processing device according to claim 7, wherein the error is one or both of errors of variable-length coded data due to correction.