JPH10336519A - Image-pickup element and image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate an image signal having provision for a large number of the kinds of video formats with a simple configuration, with respect to the image-pickup elements. SOLUTION: This device is provided with a connection changeover circuit 13 that gives register control signals e1-e6 to a desired register of a vertical transfer register 12, based on a wiring changeover control signal Sc, the connection changeover circuit it used to control the position of the register to give the register control signal and to control the logic level of the register control signal, then the number of horizontal lines of the image signal is changed freely in matching with a desired video format. Thus, an image-pickup element 10 that easily generates an image signal having provision for a large number of the kinds of video formats with a simple configuration is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Prior Art (FIGS. 18 to 20) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) Embodiments of Imaging Device (1-1) ) Overall configuration of image sensor (FIGS. 1 and 2) (1-1-1) HDTV method (FIGS. 3 to 6) (1-1-2) ATV-p method (FIGS. 7 to 9) 1-3) ATV-i system (FIGS. 10 and 11) (1-1-4) EDTVII-p system (FIGS. 12 and 1)
3) (1-2) Operation and Effect (2) Embodiment of Imaging Apparatus (2-1) Switch Switching Type Camera (FIG. 14) (2-2) Programmable Timing Generator Type Camera (FIG. 15) (2-3) FPGA / timing generator type camera (FIG. 16) (3) Other embodiments (FIG. 17) Effects of the invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device and an image pickup device, and more particularly to a CCD device (Charge Coupled Device).
An electric charge corresponding to the light quantity of the input optical signal is accumulated, and the electric charge is transferred and output to generate an image signal corresponding to the optical signal. It is suitable.

[0004]

2. Description of the Related Art In recent years, in the field of broadcasting, broadcasting routes have been diversified, and not only conventional terrestrial broadcasting but also satellite broadcasting and CATV (Community Antenna Television system) have been performed.
: So-called cable television broadcasting), Internet broadcasting and the like. In addition, interactive services can be provided via a line network such as the Internet. With the spread of multimedia in recent years, broadcast information is not limited to audio data and video data, but also, for example, computer graphics (hereinafter referred to as CG). Character data, code data, and the like. Furthermore, with these developments, virtual studios, virtual cameras, etc.
Video production in a virtual space where G and a real subject are mixed is also progressing, and multimedia information, virtual space representation, and the like are also being applied to the field of broadcasting and network services.

[0005] Virtual studios and virtual cameras can be constructed in very compact and inexpensive studio equipment, and are sold and developed in large quantities not only in broadcasting stations but also in fields such as universities, companies, Internet broadcasting homes, and other places in Taki. Is also applied to home world wide wave homes (www homes) as a system mainly composed of personal computers, and is expected to be deployed in mass-market, low-priced huge markets.

Further, with the spread of multimedia in recent years, various video signal formats exist, and there is a demand for a digital motion picture camera capable of outputting such various format video signals. In the field of future multimedia such as virtual cameras, fusion with computer generated CGs will be attempted, and a number of new video formats such as progressive (non-interlaced) video signals will become popular. It seems to be.

[0007] As a video format currently considered, as shown in FIG. 18, an HDTV (High Definition) is used.
ion Television) rectangular lattice type, HDTV square lattice type, ATV-p (Advanced Television progressive)
) Square grid type system, ETV-p1 (Enhanced Televisi
on progressive 1) system, ETV-p2 square lattice system, EDTVII-p (Enhanced Definition Television)
2 progressive) Rectangular grid type, EDTVII-p2
Rectangular lattice type, NTSC-D1 Rectangular lattice type, PC
-SVGA (Personal Computer Super Video Graphics)
There are various methods such as the Array method. In Japan, a rectangular lattice type pixel array is mainly pushed, and in the United States, a square lattice type pixel array is pushed mainly with priority on matching with a computer. In the field of multimedia and virtual video that integrates with CG, progressive scanning is expected to increase in the future because square grid type and progressive scanning are advantageous.

As described above, a plurality of formats have been proposed as video formats. As a CCD device for generating a video signal, as shown in FIG. 19, a video signal of any one of the formats is used. At present, the circuit configuration is fixed so as to generate the video signals, and the configuration does not correspond to a so-called multi-format that can generate video signals of a plurality of formats.

Here, the conventional CCD device shown in FIG. 19 will be specifically described. Note that this CCD element 1
For example, it is assumed that the CCD device has 1125 horizontal lines and is compatible with an interlaced scanning HDTV system. First, the CCD element 1 includes a plurality of vertical transfer units 2A to 2N provided in a number corresponding to the number of pixels in the horizontal direction (2200 in the HDTV system), and the vertical transfer units 2A to 2N.
, Sequentially receiving charges transferred in units of horizontal lines, sequentially shifting the charges in the horizontal direction and outputting the signals, and outputting a CCD output signal S1 based on the charges output from the horizontal transfer unit 3. And a buffer amplifier 4.

Each of the vertical transfer units 2A to 2N has basically the same configuration, and as shown in FIG. 19, the number (1125 in the HDTV system) of photo sensors 5A corresponding to the number of pixels in the vertical direction. ５5N. The photo sensors 5A to 5N are elements for accumulating electric charge corresponding to the light amount of the input optical signal, and lead / lead connected to each of them.
The stored charges can be read out through the out gates 6A to 6N. The overflow sensors 7A to 7N are also connected to the photo sensors 5A to 5N, respectively.
Unnecessary charges stored in A to 5N are overflowed.
It is configured to be discarded to the overflow drain 8 via the control gates 7A to 7N.

The read-out gates 6A to 6N are supplied with a gate control signal Sg at a rate of once in the field section. When the gate control signal Sg is supplied, the read-out gates 6A to 6N are read out. The gates 6A to 6N collectively transfer the electric charges accumulated in the photo sensors 5A to 5N to the register V1 or V3 of the vertical transfer register 9. Incidentally, the gate control signal Sg is
The register control signals e1 to e4, which will be described later, are not supplied through separate wiring, but are actually supplied to the register control signals e1 to e4.
Ｅe4.

The vertical transfer register 9 is a circuit in which a plurality of registers are connected in the vertical direction. The vertical transfer register 9 performs read-out based on register control signals e1 to e4 supplied from the outside.
The charges received from the gates 6A to 6N are sequentially shifted in the vertical direction. The charges transferred to the vertical transfer registers 9 of the vertical transfer units 2A to 2N in this manner are stored in the register control signal e.
The data is sequentially shifted in the vertical direction based on a predetermined transfer sequence of 1 to e4, and is thereby transferred to the horizontal transfer unit 3 in units of horizontal lines.

In the horizontal transfer section 3, the vertical transfer section 2A
2N, the charges sequentially transferred in horizontal line units are received, and the charges are sequentially shifted in the horizontal direction to output the charges to the buffer amplifier 4. Thus, the CCD output signal S1 for one field is output from the buffer amplifier 4. By repeating such processing sequentially for each field, a CCD output signal S including a charge component corresponding to an image represented by an optical signal is obtained.
1 is generated.

As described above, in the CCD device 1,
For example, in the case of the HDTV system, 1125 × 2200 photo sensors 5A to 5N are provided, and the electric charges accumulated in the photo sensors are sequentially transferred and output, thereby supporting an HDTV system video signal including 1125 × 2200 pixels. CCD
The output signal S1 is output.

By the way, the CCD generated by the CCD element 1 fixed for each video format as described above.
When a video signal of another video format is generated from the output signal S1, conventionally, a rate converter is provided after the CCD element 1, and the number of pixels is changed by changing the sampling rate by the rate converter. Has been adapted to generate a video signal of another video format.

FIG. 20 shows the principle of rate conversion by the rate converter. For example, as shown in FIG. 20A, by performing 2/3 down-rate conversion on the original data sampled at the sampling frequency fc,
When changing the original data to new data sampled at the sampling frequency fd, the rate converter
First, as shown in FIG. 20B, the original data is up-converted to the frequency of the least common multiple of the frequencies fc and fd by inserting zero data between the original sampling points. In this case, since the frequency of the least common multiple is 2fc, the rate converter performs twice oversampling. Next, as shown in FIG. 20 (C), the rate converter applies a discrete low-pass filter having pass band characteristics to the bands of frequencies 2fc, 4fc,. The harmonic component at the time of is removed, and only the data component due to oversampling is left. Next, as shown in FIG. 20 (D), the rate converter performs thinning-out processing at 1/3 intervals on the low-pass filtered data to convert the new data subjected to 2/3 down-rate conversion to the new data. Generate. Through such a series of processing, the rate converter changes the sampling rate to reduce the number of pixels,
Thus, a video signal of another video format is generated.

In the above description of the principle, zero insertion processing has been described. However, the zero insertion processing is actually omitted, and this is generally realized by a coefficient time-varying operation in a low-pass filter. Is the way.

[0018]

By the way, as described above, in the method of generating a video signal of another video format by providing a rate converter at the subsequent stage of the CCD element 1, a circuit is provided by an amount corresponding to the rate converter. In addition to the increase in scale, there is a disadvantage that complicated control processing must be performed for format conversion in the rate converter. In particular, in order to cope with a variety of video formats, the number of gates is increased and the circuit scale is further increased, and the control processing itself is increased by that much, which is further complicated.

The present invention has been made in view of the above points, and is intended to propose an image pickup device and an image pickup apparatus capable of easily generating image signals corresponding to various video formats with a simple configuration. is there.

[0020]

According to the present invention, there is provided a photo sensor which is arranged in a plurality of positions in the horizontal and vertical directions corresponding to pixels and accumulates a charge corresponding to a light amount of an input optical signal. A vertical transfer register that is provided for each vertical line and is formed by connecting a plurality of registers, and sequentially shifts the electric charges received from the photosensors located on the vertical line in the vertical direction. A connection switching circuit provided for switching the internal connection state based on a wiring switching control signal to supply a register control signal input to a desired one of the vertical transfer registers; To receive charges transferred line by line, shift the charges in the horizontal direction, and output them A horizontal transfer circuit for outputting an image signal corresponding to the optical signal, controlling the position of a register for supplying the register control signal by a wiring switching control signal, and controlling the logical level of the register control signal. An image signal having a desired number of horizontal lines is generated.

In this manner, a connection switching circuit for supplying a register control signal to a desired one of the vertical transfer registers based on the wiring switching control signal is provided, and the connection switching circuit is used to supply the register control signal using the connection switching circuit. By controlling the position and the logic level of the register control signal, the number of horizontal lines of the image signal can be freely changed in accordance with a desired video format.

In the present invention, a plurality of photo sensors are provided in the horizontal and vertical directions corresponding to the pixels and accumulate electric charges corresponding to the amounts of the input optical signals. A vertical transfer register that is formed by connecting the registers and sequentially shifts the electric charge received from the photo sensor located on the vertical line in the vertical direction, and provided for each vertical transfer register, based on a wiring switching control signal. A connection switching circuit for supplying a register control signal input by switching the internal connection state to a desired register of the vertical transfer registers, and receiving a charge transferred from each vertical transfer register in units of horizontal lines; An image signal corresponding to the optical signal is output by sequentially shifting the charge in the horizontal direction and outputting the image signal. And a horizontal transfer circuit for controlling a position of a register for supplying a register control signal by a wiring switching control signal, and controlling a logical level of the register control signal to form an image signal having a desired number of horizontal lines. An imaging device to be generated and a timing generator circuit to generate and output a register control signal and a wiring switching control signal corresponding to a desired video format based on an input mode switching signal are provided.

An image sensor capable of generating an image signal having a desired number of horizontal lines by controlling the position of the register for supplying the register control signal and controlling the logical level of the register control signal, A timing generator circuit that generates a register control signal and a wiring switching control signal corresponding to a desired video format based on the switching signal and outputs the generated signal to the imaging device is provided. Since the number of horizontal lines can be easily changed according to the video format, an image signal suitable for the video format desired by the user can be easily generated.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Embodiment of Image Sensor In this section, an embodiment of the image sensor will be described first.

(1-1) Overall Configuration of the Image Sensor In FIG. 1 in which the same reference numerals are assigned to parts corresponding to those in FIG. 19, reference numeral 10 denotes a CCD element to which the present invention is applied as a whole. (For example, 2200 pixels corresponding to the HDTV system having the maximum number of pixels), and a plurality of vertical transfer units 11A to 11N are transferred from the vertical transfer units 11A to 11N in units of horizontal lines. It comprises a horizontal transfer section 3 for sequentially receiving charges, sequentially shifting the charges in the horizontal direction, and outputting the same, and a buffer amplifier 4 for outputting a CCD output signal S10 based on the charges output from the horizontal transfer section 3. You.

Each of the vertical transfer units 11A to 11N has the same configuration. As shown in FIG. 1, each of the vertical transfer units 11A to 11N includes a photo sensor 5, a read-out gate 6, a vertical transfer register 12, and a connection switching circuit 13. I have. The photo sensor 5 is an element that accumulates electric charge corresponding to the light amount of an input optical signal. The read-out gate 6 is a circuit for reading out the electric charge stored in the photo sensor 6, and the gate control signal S is externally provided at a predetermined timing.
When g is supplied, charge is read from the photosensor 5 in response to the gate control signal Sg, and the charge is transferred to the vertical transfer register 12.

The vertical transfer register 12 has a connection switching circuit 1
3, the register control signals e1 to e6 are supplied, and the vertical transfer register 12 sequentially shifts the charges in the vertical direction in a predetermined transfer sequence based on the register control signals e1 to e6. It has been made like that. The connection switching circuit 13 is composed of, for example, a programmable cross switch circuit, and connects an output line to a desired input line based on a wiring switching control signal Sc supplied from the outside, and thereby a register received via the input line. The control signals e1 to e6 can be supplied to desired registers in the vertical transfer register 12.

The electric charges accumulated in the vertical transfer registers 12 in the vertical transfer units 11A to 11N are sequentially shifted in horizontal line units by the horizontal shift as described above.
Is forwarded to The horizontal transfer unit 3 includes vertical transfer units 11A to 11A.
The charge received from the 1N is sequentially shifted in the horizontal direction based on, for example, a two-phase control method, and the charge is output to the buffer amplifier 4. Thus, buffer amplifier 4
By sequentially outputting the supplied charges, the CCD element 10 outputs a CCD output signal S10 including a charge component (that is, an image signal component) corresponding to the image indicated by the optical signal. .

Here, the configuration of the vertical transfer units 11A to 11N will be specifically described with reference to FIG. However, since the vertical transfer units 11A to 11N have basically the same configuration, only the vertical transfer unit 11A will be described here.

As shown in FIG. 2 where parts corresponding to those in FIG. 19 are assigned the same reference numerals, the vertical transfer unit 11A has a number corresponding to the number of pixels in the vertical direction (for example, an HDT having the maximum number of pixels).
Photo sensors 5A to 5N
Is provided. The photosensors 5A to 5N are adapted to accumulate electric charges corresponding to the light amounts of the input optical signals, and the electric charges can be read out via read-out gates 6A to 6N. Actually, the overflow sensors 7A to 7N are also connected to the photosensors 5A to 5N, respectively. Unnecessary charges accumulated in the photosensors 5A to 5N are removed by the overflow control gates 7A to 5N.
A to 7N are discarded to the overflow drain 8.

The gate control signal Sg is supplied to the read-out gates 6A to 6N once every field or frame period, and the read-out gates 6A to 6N receive their gate control signals. The charge is read from the photosensor 5 in response to Sg, and is transferred to the vertical transfer register 12. In addition,
This gate control signal Sg is actually superimposed on register control signals e1 to e6 described later. Therefore, the gate control signal Sg is actually supplied to the read-out gates 6A to 6N via the vertical transfer register 12. It has become to be.

The vertical transfer register 12 is a circuit in which a plurality of registers are connected in the vertical direction. In the vertical transfer register 12, charges from the read-out gates 6A to 6N are input to odd-numbered registers of the vertical transfer register 12, and a register supplied through the connection switching circuit 13 The charges are shifted in the vertical direction based on the control signals e1 to e6. As a result, the charges transferred to the vertical transfer registers 12 of the vertical transfer units 11A to 11N are sequentially shifted in the vertical direction based on a predetermined transfer sequence by the register control signals e1 to e6. The data is transferred to the horizontal transfer unit 3.

The connection switching circuit 13 comprises, for example, a programmable cross-switch circuit, and the vertical transfer register 12
, And six input lines arranged so as to intersect with the output line, and a wiring switching control signal Sc supplied from the outside.
The input line and the output line can be connected at a desired cross point (indicated by a cross in the figure) based on. Thus, the connection switching circuit 13 can output the register control signals e1 to e6 received via the input lines to desired output lines.

Here, in the CCD element 10 having such a configuration, by executing a control procedure as described below, a CCD corresponding to various video formats can be used.
A CD output signal S10 is generated.

(1-1-1) HDTV system First, a CCD output signal S corresponding to the HDTV system having 1125 horizontal lines and the scanning system of interlaced scanning is used.
When the connection switching circuit 13 is generated, the connection state of the connection switching circuit 13 is set as shown in FIG. 3 by controlling the connection state of the connection switching circuit 13 based on the wiring switching control signal Sc. That is, assuming that n = 0, 1, 2,..., The output line connected to the (4n + 1) -th register (hereinafter, this register is referred to as a register V1) of the vertical transfer register 12 is connected to the first input line, The output line connected to the (4n + 2) -th register (hereinafter, this register is referred to as a register V2) of the vertical transfer register 12 is connected to the second input line, and the (4n + 3) -th register ( Hereinafter, an output line connected to this register is referred to as a register V3) is connected to a third input line, and (4n +
4) A register (hereinafter referred to as a register V
4) is connected to the fourth input line.

By setting such a connection state, first, the register control signal e1 is transmitted to the vertical transfer register 12
Register control signal e2 can be supplied to the register V2 of the vertical transfer register 12, and the register control signal e3 can be supplied to the register V3 of the vertical transfer register 12. The signal e4 can be supplied to the register V4 of the vertical transfer register 12.

After setting such a connection state,
By executing the control procedure as shown in FIGS. 4 to 6, a CCD output signal S10 corresponding to the HDTV system is generated. First, at time t1 shown in FIG.
Of the photo sensors 5A to 5N by supplying the register control signals e1 and e3 of the logic level "H" and the register control signals e2 and e4 of the logic level "L". The data is read out through the out gates 6A to 6N, and is transferred collectively to the registers V1 and V3 of the vertical transfer register 12.

In this case, the read-out gates 6A-
6N, upon receiving the gate control signal Sg of the logic level "H", transits to the transfer mode, reads the charges of the photo sensors 5A to 5N, and reads the registers V1, V of the vertical transfer register 12.
Transfer to 3. Each of the registers V1 to V4 of the vertical transfer register 12 is a register control signal e1 of a logical level "H".
~ E4, the potential well becomes deeper to be able to accumulate electric charge, and when the register control signals e1 to e4 of logic level "L" are received, the potential well becomes shallower to be unable to accumulate electric charge. . Therefore, at time t1
Supplies a gate control signal Sg of a logic level "H" and a register control signal e of a logic level "H".
When 1, e3 is supplied, the charges of the photo sensors 5A to 5N can be transferred to the registers V1, V3 and accumulated.

FIG. 5A shows the state of the potential well of each of the registers V1 to V4 at this time. Time point t1
, The register control signal e1 of the logic level “H”,
Since e3 is supplied, as shown in FIG.
The potential wells of the registers V1 and V3 become deeper, whereby the registers V1 and V3 are turned on and accumulate the charges transferred. In FIG. 5,
The hatched portions indicate the accumulated charges. On the other hand, as for the registers V2 and V4, since the register control signals e2 and e4 of the logic level "L" are supplied, the potential well becomes shallow, so that electric charges cannot be accumulated.

Subsequently, at time t2 shown in FIG. 4, the gate control signal Sg is switched to the logic level "L".
By switching the register control signal e2 to the logic level "H", the potential well of the register V2 is made deep to be in a state where charges can be accumulated. As a result, FIG.
As shown in the figure, when the register V2 located between the register V1 and the register V3 is turned on, the registers V1 and V
The charges accumulated in 3 are combined and averaged. By this processing, the charges of the pixels adjacent in the vertical direction are combined, and the charge component of the first field having 1125/2 horizontal lines is generated. When the horizontal transfer unit 3 takes in the electric charge, the position indicated by the triangle in the figure may be set as the sampling point.

Subsequently, after the time point t3 shown in FIG. 4, by sequentially controlling the logic levels of the register control signals e1 to e4, the vertical transfer process of the thus generated first field charge component is started. . That is, first, at time t3, the register control signal e1 is switched to the logic level "L", as shown in FIG. 5C, the potential well of the register V1 is made shallow, and the register V1 is turned off. Charge is stored only in V3. Next, at time t4 shown in FIG. 4, the register control signal e4 is switched to the logic level "H", so that the potential well of the register V4 is deepened to turn on the register V4 as shown in FIG. 5D. I do. As a result, charges are accumulated in the registers V2, V3, and V4, and as a result, the charges are shifted by one register in the vertical direction. Incidentally, in FIG. 5, the right direction indicates the vertical lower part of the vertical transfer register 12.

Subsequently, at time t5 shown in FIG. 4, the register control signal e2 is switched to the logic level "L", so that the potential well of the register V2 is made shallow as shown in FIG. It is turned off, and charges are stored only in the registers V3 and V4. Next, FIG.
By switching the register control signal e1 to the logic level "H" at time t6 shown in FIG. 5, the potential well of the register V1 is deepened to turn on the register V1 as shown in FIG. As a result, electric charges accumulate in the registers V3, V4, and V1, and as a result, as shown in FIG.
The electric charge shifts in the vertical direction by one register as compared with the state shown in (D). Similarly, the electric charge is shifted in the vertical direction by controlling the logic levels of the respective register control signals e1 to e4.

Next, in the case of the second field, the gate control signal Sg of the logic level "H" is similarly supplied, and the register control signals e1 and e3 of the logic level "H" are similarly supplied.
By supplying the register control signals e2 and e4 at the logic level "L", the charges of the photosensors 5A to 5N are read out from the read-out gate 6A as shown in FIG.
To 6N, which are transferred to the vertical transfer register 12
To the registers V1 and V3. Next, by switching the gate control signal Sg to the logical level "L" and switching the register control signal e4 to the logical level "H", the register V4 is turned on as shown in FIG. , V1 are combined and averaged. By this processing, the charges of the adjacent pixels are combined in a different combination from the first field,
A charge component of a second field having 1125/2 horizontal lines is generated. For the subsequent vertical transfer,
By controlling the logic levels of the register control signals e1 to e4, charges are shifted one register at a time.

By sequentially executing such a control procedure, in the CCD device 10, each vertical transfer unit 11
A to 11N, the electric charges are read out from the respective photo sensors 5A to 5N and transferred in the vertical direction, whereby the number of horizontal lines is reduced.
With 1125 lines, a CCD output signal S10 compatible with the interlaced scanning HDTV system is generated.

(1-1-2) ATV-p system Next, in this section, the ATV-p system in which the number of horizontal lines is 750 (= 1125 × 2/3) and the scanning system is progressive (ie, sequential scanning) The case where the CCD output signal S10 corresponding to the above is generated will be described. In the case of this system, first, the connection state of the connection switching circuit 13 is controlled based on the wiring switching control signal Sc, so that the connection switching circuit 13 is controlled.
Are set as shown in FIG. That is, n =
(6n) of the vertical transfer register 12 as 0, 1, 2,.
The output line connected to the (+1) th register (hereinafter, this register is referred to as a register V1) is connected to the first input line, and the (6n + 2) th register (hereinafter, this register is referred to as a register) of the vertical transfer register 12 is connected. V2) is connected to the second input line, and the output line connected to the (6n + 3) th register of the vertical transfer register 12 (hereinafter, this register is referred to as a register V3) is connected to the second input line. 3 (6n + 4) -th register (hereinafter, referred to as a vertical transfer register 12).
An output line connected to this register is referred to as a register V4, is connected to a fourth input line, and is connected to a (6n + 5) th register of the vertical transfer register 12 (hereinafter, this register is referred to as a register V5). The output line is connected to the fifth input line, and (6) of the vertical transfer register 12 is connected.
An output line connected to the (n + 6) -th register (hereinafter, this register is referred to as a register V6) is connected to a sixth input line.

By setting such a connection state, first, the register control signal e1 is transmitted to the vertical transfer register 12
Register control signal e2 can be supplied to the register V2 of the vertical transfer register 12, and the register control signal e3 can be supplied to the register V3 of the vertical transfer register 12. The signal e4 can be supplied to the register V4 of the vertical transfer register 12, the register control signal e5 can be supplied to the register V5 of the vertical transfer register 12, and the register control signal e6 is supplied to the register V6 of the vertical transfer register 12. To be able to do it.

After setting such a connection state,
By executing a control procedure as shown in FIGS. 8 and 9, a CCD output signal S10 corresponding to the ATV-p system is generated. First, at time t1 shown in FIG. 8, the gate control signal Sg of the logic level "H" is supplied, and the register control signals e1, e3, e5 of the logic level "H" and the register control signals e2, e4 of the logic level "L" are provided. , E6, the charges of the photosensors 5A to 5N are read out through the read-out gates 6A to 6N,
This is batch-transferred to the registers V1, V3, V5 of the vertical transfer register.

In this case, the read-out gates 6A-
6N, upon receiving the gate control signal Sg of the logic level "H", transits to the transfer mode, reads the charges of the photo sensors 5A to 5N, and reads the registers V1, V of the vertical transfer register 12.
3. Transfer to V5. When the registers V1 to V6 of the vertical transfer register 12 receive the register control signals e1 to e6 of the logic level "H", the potential wells become deeper to be able to accumulate electric charge, and the register control of the logic level "L" is performed. When the signals e1 to e6 are received, the potential well becomes shallow and becomes unable to accumulate charges. Therefore, at time t1, gate control signal Sg at logic level "H"
And the register control signals e1, e3, e5 of the logic level "H" are supplied, the photo sensors 5A to 5A
5N charges can be transferred to and stored in registers V1, V3, V5.

FIG. 9A shows the state of the potential well of each of the registers V1 to V6 at this time. Time point t1
, The register control signal e1 of the logic level “H”,
Since e3 and e5 are supplied, as shown in FIG. 9A, the potential wells of the registers V1, V3, and V5 are deepened, whereby the registers V1, V3, and V5 are turned on and transferred. The incoming charge is stored. In FIG. 9 as well, the hatched portions indicate the accumulated charges. On the other hand, regarding the registers V2, V4, and V6,
Register control signals e2, e4, e6 of logic level "L"
Is supplied, the potential well becomes shallow, and the electric charge cannot be stored.

Subsequently, at time t2 shown in FIG. 8, the gate control signal Sg is switched to the logic level "L".
By switching the register control signal e4 to the logic level "H", the potential well of the register V4 is made deeper so that electric charges can be stored. Thereby, FIG. 9 (B)
As shown in the figure, when the register V4 located between the register V3 and the register V5 is turned on, the registers V3 and V
The charges accumulated in 5 are combined and averaged. By this processing, the number of pixels in the vertical direction is increased by 2/3, and a charge component corresponding to the ATV-p system including 750 (= 1125 × 2/3) horizontal lines is generated. That is, the processing in the second stage corresponds to linear interpolation and horizontal line number conversion in a method using a conventional rate converter.

In this case, in this case, the position indicated by a triangle in the figure is a sampling point. However, the level of the point P becomes half the level of the point Q by the vertical transfer process described below. After sampling at the position indicated by the mark, the level of the point P is adjusted by doubling the level.

Subsequently, after the time point t3 shown in FIG. 8, by sequentially controlling the logic levels of the register control signals e1 to e6, the vertical transfer process of the ATV-p type charge component generated in this manner is started. I do. That is, first, at time t3, the register control signal e3 is switched to the logical level "L", so that the potential well of the register V3 is made shallow to turn off the register V3, as shown in FIG. Register V
4. Charge is stored only in V5. Next, at time t4 shown in FIG.
By switching the register control signal e2 to the logic level "H" in the step (d), the potential well of the register V2 is deepened as shown in FIG.
Is turned on. As a result, electric charges accumulate in the registers V1 and V2 and the registers V4 and V5.

Subsequently, at time t5 shown in FIG. 8, the register control signals e1 and e4 are switched to the logical level "L", so that the registers V1 and e4 are switched as shown in FIG.
The potential well of V4 is made shallow and the register V1,
V4 is turned off, and charges are stored only in the registers V2 and V5. Next, at time t6 shown in FIG. 8, the register control signals e3 and e6 are switched to the logic level "H", thereby causing the register V to be switched as shown in FIG.
3. Deepen the potential well of V6 and make the register V
3. Turn on V6. This allows register V2,
Charge accumulates in V3 and registers V5 and V6, and as a result,
As compared with the state shown in FIG. 9D, the electric charge shifts by one register in the vertical direction.

Subsequently, at time t7 shown in FIG. 8, the register control signals e2 and e5 are switched to the logic level "L", thereby causing the registers V2, e5 as shown in FIG.
V5 is turned off, and charges are stored only in the registers V3 and V6. Next, at time t8 shown in FIG. 8, the register control signals e4 and e1 are switched to the logic level "H", thereby causing the register V to be switched as shown in FIG.
4. Turn on V1. This allows register V3,
Charge accumulates in V4 and registers V6 and V1, and FIG.
The electric charge shifts by one register in the vertical direction as compared with the state shown in FIG. Hereinafter, similarly, each register control signal e
By controlling the logic levels 1 to e6, the charges are shifted in the vertical direction.

Thus, in this CCD device 10,
After converting the number of horizontal lines to 750 by combining the electric charges read from the photosensors 5A to 5N, the electric charges are sequentially transferred in the vertical direction, so that the progressive scanning is performed with the number of horizontal lines of 750. The CCD output signal S10 corresponding to the ATV-p system is generated.

(1-1-3) ATV-i system Next, in this section, a CCD corresponding to the ATV-i system in which the number of horizontal lines is 750 and the scanning system is interlaced.
The case where the output signal S10 is generated will be described. In the case of this system, the connection state of the connection switching circuit 13 is set as shown in FIG. 10 by first controlling the connection state of the connection switching circuit 13 based on the wiring switching control signal Sc. That is, as n = 0, 1, 2,..., The output line connected to the (6n + 1) -th register (hereinafter, this register is referred to as a register V1) of the vertical transfer register 12 is connected to the first input line, Vertical transfer register 1
2 (6n + 2) -th register (hereinafter, this register is referred to as a register V2).
Of the vertical transfer register 12 (6n
The output line connected to the (+3) th register (hereinafter, this register is referred to as a register V3) is connected to the third input line, and the (6n + 4) th register (hereinafter, this register is referred to as a register) of the vertical transfer register 12 V4) is connected to the fourth input line, and the output line connected to the (6n + 5) th register of the vertical transfer register 12 (hereinafter, this register is referred to as register V5) is connected to the fourth input line. 5, the (6n + 6) th register (hereinafter, referred to as a vertical transfer register 12) of the vertical transfer register 12.
An output line connected to this register is referred to as a register V6) is connected to a sixth input line.

By setting such a connection state, the register control signal e1 is first transmitted to the vertical transfer register 12
Register control signal e2 can be supplied to the register V2 of the vertical transfer register 12, and the register control signal e3 can be supplied to the register V3 of the vertical transfer register 12. The signal e4 can be supplied to the register V4 of the vertical transfer register 12, the register control signal e5 can be supplied to the register V5 of the vertical transfer register 12, and the register control signal e6 is supplied to the register V6 of the vertical transfer register 12. To be able to do it.

After setting such a connection state,
By executing the control procedure as shown in FIG.
A CCD output signal S10 corresponding to the Vi system is generated. First, as shown in FIG. 11A, by supplying a gate control signal Sg of a logic level "H" only to the read-out gates 6A, 6D,. 5D,... Are selectively transferred to the register V1 of the vertical transfer register 12. Incidentally, when the gate control signal Sg of the logic level "H" is supplied only to the read-out gates 6A, 6D,... Connected to the register V1, the gate control signal Sg is applied only to the register control signal e1. May be superimposed.

Subsequently, as shown in FIG. 11B, by supplying the register control signals e2 and e6 of the logical level "H", the register V located before and after the register V1 is supplied.
2. Turn on V6. As a result, the charges accumulated in the register V1 are changed to the registers V5 to V6, V1 to V3.
And a first field charge component having 1125/3 horizontal lines is generated. Next, FIG.
As shown in (C), the register control signal e4 is switched to the logic level "H" and the register control signal e5 is switched to the logic level "L", whereby the register V
4 is turned on and the register V5 is turned off.
As a result, the electric charges accumulated in the registers V5 to V6 and V1 to V3 are accumulated in the registers V6 and V1 to V4. As a result, the electric charges are shifted by one register in the vertical direction. Similarly, each of the register control signals e1
By controlling the logic levels of .about.e6, the charges are sequentially shifted in the vertical direction.

Next, in the case of the second field, FIG.
As shown in (D), read-out gates 6B, 6C, 6E, 6F connected to registers V3, V5,...
Supply the gate control signal Sg of the logic level “H” only to the photo sensors 5B, 5C, 5E,
.. Are selectively transferred to the registers V3 and V5 of the vertical transfer register 12. By the way, read-out signals connected to the registers V3 and V5
When the gate control signal Sg of the logic level “H” is supplied only to the gates 6B, 6C, 6E, 6F,..., The gate control signal Sg may be superimposed only on the register control signals e3 and e5.

Subsequently, as shown in FIG. 11 (E), the registers V4 and V6 are turned on by supplying the register control signals e4 and e6 of the logic level "H". As a result, the electric charges stored in the registers V3 and V5 are combined, the number of horizontal lines is reduced to half, and the number of horizontal lines is reduced to 11
A charge component of the second field consisting of 25/3 (= 1125 × 2/3 × 1/2) is generated. Next, as shown in FIG. 11F, the register control signal e2 is switched to the logical level "H" and the register control signal e3 is switched to the logical level "L".
, The register V2 is turned on and the register V3 is turned off. As a result, the charges accumulated in the registers V3 to V6 and V1
4 to V6 and V1 to V2, and as a result, the electric charge shifts by one register in the vertical direction.
Similarly, the charges are sequentially shifted in the vertical direction by controlling the logic levels of the register control signals e1 to e6.

As described above, in this CCD device 10,
By selectively transferring the charges accumulated in the photo sensors 5A to 5N to the vertical transfer register 12, a charge component of the first field is generated and transferred in the vertical direction.
Subsequently, the charges accumulated in the photosensors 5A to 5N are selectively transferred to the vertical transfer register 12 to generate a charge component of the second field. After halving the number, transfer vertically. By such processing, the CCD element 10 has a horizontal line number of 750 (= 1125
× 2/3) are used to generate a CCD output signal S10 corresponding to the interlaced scanning ATV-i system.

By the way, in the case of the first field, the point P shown in the figure is a sampling point, and in the case of the second field, the point Q shown in the figure is a sampling point. As is apparent from FIG. In the case of two fields, since the charges of the two photosensors are combined, P
The level of point Q is higher than that of point. Therefore, for the point P, the level is adjusted by doubling the level.

(1-1-4) EDTVII-p system Next, in this section, a C-type corresponding to the EDTVII-p system in which the number of horizontal lines is 525 and the scanning system is progressive is used.
The case where the CD output signal S10 is generated will be described.
In the case of this method, the connection state of the connection switching circuit 13 is first set as shown in FIG. 12 by controlling the connection state of the connection switching circuit 13 based on the wiring switching control signal Sc. That is, assuming that n = 0, 1, 2,..., The output line connected to the (4n + 1) -th register (hereinafter, this register is referred to as a register V1) of the vertical transfer register 12 is connected to the first input line, The output line connected to the (4n + 2) -th register (hereinafter, this register is referred to as a register V2) of the vertical transfer register 12 is connected to the second input line, and the (4n + 3) -th register ( Hereinafter, an output line connected to this register is referred to as a register V3) is connected to a third input line, and (4n +
4) A register (hereinafter referred to as a register V
4) is connected to the fourth input line.

By setting such a connection state, first, the register control signal e1 is transmitted to the vertical transfer register 12
Register control signal e2 can be supplied to the register V2 of the vertical transfer register 12, and the register control signal e3 can be supplied to the register V3 of the vertical transfer register 12. The signal e4 can be supplied to the register V4 of the vertical transfer register 12.

After setting such a connection state,
By executing a control procedure as shown in FIG.
A CCD output signal S10 corresponding to the TVII-p system is generated. First, as shown in FIG. 13 (A), by supplying a gate control signal Sg of a logic level “H”, charges accumulated in the photo sensors 5A, 5B,... Are stored in the registers V1 and V3 of the vertical transfer register 12. Forward. At this time, a gate control signal Sg is supplied only to a predetermined read-out gate so as to selectively transfer only 1050 horizontal lines including an effective portion out of 1125 horizontal lines corresponding to the HDTV system. . As a result, FIG.
The number of horizontal lines is converted to 1050 at the time of the first stage shown in FIG.

Subsequently, as shown in FIG. 13B, by supplying a register control signal e2 of a logic level "H", the register V2 located between the registers V1 and V3 is turned on. As a result, the electric charges stored in the registers V1 and V3 are combined and averaged. By this processing, the charges of the pixels adjacent in the vertical direction are combined, and a charge component corresponding to the EDTVII-p system including 525 (= 1050/2) horizontal lines is generated. Next, FIG.
As shown in (4), the register control signal e4 is switched to the logical level "H" and the register control signal e1 is switched to the logical level "L", whereby the register V4
Is turned on and the register V1 is turned off. As a result, the electric charges stored in the registers V1 to V3 are stored in the registers V2 to V4.
The charge shifts vertically by one register. Similarly, the electric charges are sequentially shifted in the vertical direction by controlling the logic levels of the respective register control signals e1 to e4.

As described above, in this CCD device 10,
By selectively transferring the charges accumulated in the photo sensors 5A to 5N to the vertical transfer register 12, a charge component having 1050 horizontal lines is generated, and this is combined to reduce the number of horizontal lines by half. After that, the data is vertically transferred by the vertical transfer register 12. Through such processing, the CCD element 10 generates a CCD output signal S10 corresponding to the progressive scanning EDTVII-p system having 525 horizontal lines.

(1-2) Operation and Effect In the above configuration, the CCD element 10 is provided with the connection switching circuit 13 and the connection state of the connection switching circuit 13 is switched to a desired state, whereby the vertical transfer register 12 Register control signal e1
To e6. And register control signals e1 to e6
Is controlled in accordance with the video format to be generated, thereby obtaining a CCD output signal S10 matching the video format to be generated.

In this manner, in the CCD device 10, the vertical transfer register 12 which supplies the register control signals e1 to e6 by controlling the connection state of the connection switching circuit 13 in accordance with the video format to be generated. In addition to controlling the register position, the register control signal e
By controlling the logical levels of 1 to e6, the horizontal line number conversion and the scanning method conversion can be easily performed with a simple configuration, and the video format for generating the horizontal line number and the scanning method can be used. The CCD output signal S10 corresponding to a desired video format can be generated with a simple configuration.

Incidentally, since most of the current CG images are generated by the non-interlace processing of the computer, when performing the synthesis processing with the CG images, the image generated by the non-interlace processing is better. It is advantageous. This is a very important factor in terms of providing efficient and highest image quality, and it is expected that all devices handling virtual cameras and CG images in the future will use non-interlaced processing in the mainstream. Therefore, in that sense, a CCD element in which the number of horizontal lines and the scanning method can be freely changed, such as the CCD element 10 to which the present invention is applied, will be greatly effective.

Since the CCD device 10 can perform the conversion processing in a programmable manner as described above, it is possible to generate the CCD output signal S10 corresponding to various video formats without using a rate converter as in the related art. Therefore, the CCD device can be simply and inexpensively reduced in size. Further, in the CCD element 10, the HD of the interlace scanning is used.
The progressive CCD output signal is converted from the CCD output signal of the TV system by down-rate conversion to the CCD element 1.
0, it is not necessary to perform complicated processing such as motion adaptive interpolation processing and image quality degradation such as afterimages, as compared with the case where a conversion processing is performed by providing an external rate converter as in the conventional case. There are also advantages that can be avoided.

According to the above arrangement, the connection switching circuit 13 is provided, and the connection state of the connection switching circuit 13 is controlled in accordance with the video format to be generated, and the register control signals e1 to e6 are supplied. By controlling the position and controlling the logic levels of the register control signals e1 to e6, various types of video formats can be easily configured with a simple configuration as compared with a conventional method using a rate converter. CCD output signal S1 corresponding to Matsuto
0 can be realized.

(2) Embodiment of Imaging Apparatus In this section, an embodiment in which the above-described CCD element 10 is applied to a camera as an imaging apparatus will be described.

(2-1) Switch-Switching Camera In FIG. 14, reference numeral 20 denotes a camera to which the present invention is applied as a whole, which is roughly divided into a timing generator circuit 21, a CCD drive circuit 22, and the above-mentioned multi-format camera. , A correlated double sampling circuit (CDS) 23 and a gain switching circuit 24.

The timing generator circuit 21 is a CCD
This is a circuit that generates a control signal for controlling the operation of the element 10, the correlated double sampling circuit 23, and the gain switching circuit 24. The timing generator circuit 21 has a plurality of timing generator circuits 21A to 21C for internally generating control signals corresponding to the respective video formats, and these timing generator circuits 21A to 21C respond to a mode switching signal S20 supplied from the outside. Timing generator circuits 21A-2
By selecting a desired timing generator circuit from 1C, a control signal suitable for a video format desired by the user is generated.

More specifically, the timing generator circuit 21 internally generates an HDTV control signal S21.
DTV timing generator circuit 21A, ATV-
a timing generator circuit 21B for ATV-p for generating a control signal S22 for p, a timing generator circuit 21C for EDTVII-p for generating a control signal S23 for EDTVII-p, and the like. It has a selection switch 21D for selecting a desired control signal among the control signals S21 to S23 generated by the generator circuits 21A to 21C, and an interface circuit 21E for outputting the selected control signal.

The timing generator circuit 21 has a mode switching signal S20 generated by a user operating a mode switching switch (not shown), for example.
(This mode switching signal S20 indicates a video format desired by the user), and this is supplied to the selection switch 21D and the interface circuit 21E.

The selection switch 21D receives the mode switching signal S
Based on the control signal 20, the control signal corresponding to the desired video format is selected from the control signals S21 to S23, and the selected control signal is supplied to the interface circuit 21E. Incidentally, each of the control signals S21 to S23 does not consist of one control signal, but a sampling timing signal for driving the correlated double sampling circuit 23 and a gain for controlling the operation of the gain switching circuit 24. It consists of a switching control signal, a gate control signal for driving the CCD element 10, a register control signal, and other CCD control signals (the other CCD control signals are not necessarily required for the CCD element 10). .

The interface circuit 21E converts the sampling timing signal S24 of the control signals supplied via the selection switch 21D into a correlated double sampling circuit 2
3, and the gain switching control signal S25 is supplied to the gain switching circuit 2
4 The interface circuit 21E converts the gate control signal Sg ', the register control signal e', and the other CCD control signal S26 among the supplied control signals to the CC signal.
It is supplied to the D drive circuit 22. Further, the interface circuit 21E generates a wiring switching control signal Sc corresponding to a desired video format based on the mode switching signal S20, and supplies this to the CCD drive circuit 22.

As described above, the timing generator circuit 21 outputs a control signal suitable for the video format desired by the user by performing the selecting operation based on the mode switching signal S20.

The CCD drive circuit 22 receives the gate control signal S supplied from the timing generator circuit 21.
g ', a register control signal e', and a wiring switching control signal Sc '
And a circuit for generating a control signal for actually driving the CCD element 10 based on the CCD control signal S26 and other signals. The CCD drive circuit 22 has first to
It has third drive circuits 22A to 22C, inputs the gate control signal Sg 'and the register control signal e' to the first drive circuit 22A, and sends the wiring switching control signal Sc 'to the second drive circuit 22B. Then, the other CCD control signal S26 is input to the third drive circuit 22C.

The first drive circuit 22A drives the CCD element 10 by superimposing the gate control signal Sg 'on the register control signal e' and then converting the signal into a signal having a predetermined voltage and current. A register control signal e (register control signals e1 to e6 in the example of the above-described CCD element 10) having a voltage and a current that can be obtained and having the gate control signal Sg superimposed thereon is generated, and is transmitted to the CCD element 10. Output. The second drive circuit 22B converts the wiring switching control signal Sc 'into a wiring switching control signal Sc having a voltage and a current sufficient to drive the CCD element 10,
This is output to the CCD element 10. Similarly, the third drive circuit 22C outputs the other CCD control signal S26 to C
The CCD element 10 is converted into a CCD control signal S27 having a voltage and a current sufficient to drive the CD element 10,
Output to

The CCD element 10 receives these control signals e, S
c and S27, the CCD output signal S1 that matches the video format desired by the user.
0 is generated and output to the correlated double sampling circuit 23. The correlated double sampling circuit 23 removes a noise component included in the CCD output signal S10 by sampling the CCD output signal S10 based on the sampling timing signal S24 output from the timing generator circuit 21, and removes only the image component. Is output.

The gain switching circuit 24 switches the gain for each horizontal line based on the gain switching control signal S25 synchronized with the horizontal blanking signal to amplify the image signal S28.
As a result, the signal level of the image signal S28 having a different signal level for each horizontal line can be adjusted by a charge combining process or the like in the CCD element 10. By outputting the gain-adjusted image signal from the gain switching circuit 24, the camera 20 obtains an image signal S29 that matches the video format desired by the user.

In the above configuration, the camera 20 is provided with a timing generator circuit 21 having a plurality of timing generator circuits 21A to 21C for generating a control signal corresponding to each video format.
Control signals S21 to S generated in timing generator circuits 21A to 21C based on mode switching signal S20.
23, a desired control signal is selected. As a result, a control signal suitable for the video format desired by the user can be generated. Therefore, this control signal is transmitted to the CCD drive circuit 2.
When the image signal S29 is supplied to the multi-format compatible CCD element 10 via the line 2 and supplied to the correlated double sampling circuit 23 and the gain switching circuit 24, an image signal S29 suitable for the video format desired by the user can be easily generated. I can do it.

In the camera 20, the gain switching circuit 2
4 and the gain is switched for each horizontal line to change the image signal S
28, the CCD element 10
The signal level of the image signal S28 having a different signal level for each horizontal line can be easily adjusted by the charge synthesis processing described above.

Thus, according to the above configuration, the control signals S21 to S23 corresponding to the respective video formats generated by the timing generator circuits 21A to 21C are selected based on the mode switching signal S20, and are selected according to the multiformat. Is supplied to the CCD element 10, the image signal S29 conforming to the video format desired by the user can be easily generated as long as the video format is designated by the mode switching signal S20. Thus, a camera 20 capable of easily generating an image signal S29 corresponding to various video formats with a simple configuration.
Can be realized.

(2-2) Programmable Timing Generator Type Camera In FIG. 15 in which parts corresponding to those in FIG. 14 are assigned the same reference numerals, reference numeral 30 denotes a camera to which the present invention is applied as a whole. Microprocessor 31, programmable timing generator circuit 32, CCD drive circuit 22, CCD for multi-format
Except for the microprocessor 31 and the programmable timing generator circuit 32, the switch-switching camera 20 is constituted by an element 10, a correlated double sampling circuit (CDS) 23 and a gain switching circuit 24.
It has almost the same configuration.

The programmable timing generator circuit 32 has a counter circuit therein, and controls the gate control signal Sg ′, the register control signal e ′, and the wiring switching control based on the set value set in the register of the counter circuit. Signal Sc ', other CCD control signal S26, sampling timing signal S24, and gain switching control signal S2
5 is generated.

The microprocessor 31 outputs a register control signal S31 to the programmable timing generator circuit 32 based on the mode switching signal S20 supplied from the outside, so that the microprocessor 31 matches the video format desired by the user. The set value is set in a register of the programmable timing generator circuit 32.

In the above configuration, when the mode switching signal S20 indicating the video format desired by the user is supplied, the microprocessor 31 sets the set value corresponding to the desired video format to a programmable timing generator circuit. 32 registers.
As a result, the programmable timing generator circuit 32 operates based on the set values, and the gate control signal Sg ', the register control signal e', and the wiring switching control signal S which match the desired video format.
c ', a CCD control signal S26, a sampling timing signal S24, and a gain switching control signal S25. Therefore, these control signals are transmitted to the CCD drive circuit 2.
When the image signal S29 is supplied to the multi-format compatible CCD element 10 via the line 2 and supplied to the correlated double sampling circuit 23 and the gain switching circuit 24, an image signal S29 suitable for the video format desired by the user can be easily generated. I can do it.

Thus, according to the above configuration, the programmable timing generator circuit 32 for generating a desired control signal based on the set value set in the register,
The programmable timing generator circuit 32
And a microprocessor 31 for setting a set value suitable for a video format desired by a user in a register of the user. The control signal generated by the programmable timing generator circuit 32
By supplying the data to the CD element 10, the camera 30 that can easily generate the image signal S29 corresponding to various video formats with a simple configuration can be realized.

(2-3) FPGA / Timing Generator Type Camera In FIG. 16 in which parts corresponding to those in FIG. 14 are assigned the same reference numerals, reference numeral 40 denotes a camera to which the present invention is applied as a whole. Microprocessor 41, field programmable gate array type timing generator circuit (hereinafter referred to as FPGA / TG circuit)
42, a CCD drive circuit 22, the above-mentioned multi-format compatible CCD element 10, a correlated double sampling circuit (CDS) 23, and a gain switching circuit 24. The microprocessor 41 and the FPGA / TG circuit 42 Except for this, it has substantially the same configuration as the switch-switching type camera 20 described above.

The FPGA / TG circuit 42 includes control signals (ie, a gate control signal Sg ', a register control signal e', a wiring switching control signal Sc ', other CCD control signals S26, and a sampling signal) corresponding to a video format desired by the user. Timing signal S24 and gain switching control signal S
25). The FPGA / TG circuit 42 is formed by a circuit called a field programmable gate array, which can freely change the circuit structure, thereby programming the circuit structure according to the video format desired by the user. A control signal suitable for the desired video format can be generated.

Incidentally, the field programmable gate array has a configuration in which a plurality of circuit blocks and wiring blocks are regularly arranged on a chip, and inside the circuit blocks and wiring blocks, electrical connection or non-connection of circuits is performed. There are many devices that can program the connection,
This allows the circuit structure to be freely changed by programming these devices. Such field programmable gate arrays include a write-once type in which the circuit structure can be programmed only once and a write-once type in which the circuit structure can be freely programmed any number of times.
The circuit employed in No. 2 is the latter writable type.

The microprocessor 41 is an FPGA / TG
This is a circuit for changing the circuit structure of the circuit 42 so that a control signal suitable for a video format desired by a user can be generated. A memory storing program data indicating a circuit structure corresponding to each video format is built in the microprocessor 41.
When the mode switching signal S20 is supplied from the outside, the program data of the video format desired by the user is read out based on the mode switching signal S20, and this is used as the programming signal S41.
Send to 2. As a result, the microprocessor 41
The circuit structure of the FPGA / TG circuit 42 can be changed to a structure suitable for a video format desired by the user.
The control signal of the video format can be output from the GA / TG circuit 42.

By the way, in this camera 40, for example, a computer device such as a personal computer is connected to this camera 40 so that the program data S 4
2 can be downloaded to the memory of the microprocessor 41. Therefore, even when a new video format is standardized, if the program data S42 corresponding to the video format is downloaded to the memory of the microprocessor 41, the FPGA / TG circuit 42 based on the program data S42 is downloaded. The circuit structure can be changed, and the image signal S29 adapted to the new video format can be easily generated. Therefore, in the case of the camera 40, the versatility can be further improved.

In the above arrangement, when the user supplies the mode switching signal S20 indicating the video format desired by the user, the microprocessor 41 reads out the program data corresponding to the desired video format from the internal memory, and This is referred to as a programming signal S41.
Is downloaded to the FPGA / TG circuit 42. In response, the FPGA / TG circuit 42 changes the internal circuit structure in accordance with the desired video format. Thus, the FPGA / TG circuit 42 generates a gate control signal Sg ', a register control signal e', a wiring switching control signal Sc ', other CCD control signals S26, and a sampling timing signal that match the video format desired by the user. S24 and a gain switching control signal S25 can be generated. Accordingly, these control signals are transmitted via the CCD drive circuit 22 to the multi-format compatible CCD element 1.
By supplying the signal to 0 and supplying it to the correlated double sampling circuit 23 and the gain switching circuit 24, the image signal S29 suitable for the video format desired by the user can be easily generated.

In the case of the camera 40, the FPGA
By being able to externally download program data for determining the circuit structure of the TG circuit 42,
Even if a new video format is standardized, the new video format can always be supported by downloading program data corresponding to the new video format. Therefore, it is possible to prevent the camera 40 from being unusable due to the standardization of a new video format, which can contribute to effective use of resources. Further, since the camera 40 can be prevented from being discarded, it is also advantageous in terms of environmental conservation.

Thus, according to the above configuration, the program data is downloaded to the FPGA / TG circuit 42 via the microprocessor 41, and the circuit structure of the FPGA / TG circuit 42 is adjusted according to the video format desired by the user. The control signal generated by the FPGA / TG circuit 42 is changed to a multiformat CCD.
By supplying the image signal to the element 10, the camera 40 capable of easily generating the image signal S29 corresponding to various video formats with a simple configuration can be realized.

(3) Other Embodiments In the above-described embodiment, the case where the transfer sequence shown in FIG. 11 is executed when the video format is the ATV-i system has been described. The present invention is not limited to this, and a transfer sequence as shown in FIG. 17 may be executed. That is, regarding the first field, all the charges of the photo sensors 5A to 5N are transferred to the respective registers V1, V3, V5 of the vertical transfer register 12, and the charges of the registers V1, V3, V5 are combined and transferred in order. Photo sensor 5A for 2 fields
5N may be selectively transferred to the registers V3 and V5 of the vertical transfer register 12, and the charges of the registers V3 and V5 may be combined and transferred sequentially. Incidentally, in this case, since the signal level of the first field is 1.5 times that of the second field, Q
What is necessary is just to make the signal level of a point 1.5 times, and to adjust a level.

In the above embodiment, only the conversion of the number of horizontal lines, that is, the conversion of the number of pixels in the vertical direction, has been described. The same process as the number conversion may be performed in the horizontal transfer unit 3. As another method, a method described below may be applied. In other words, since the signal is an analog signal in the horizontal direction, it is digitized using a low-pass filter and an analog digital converter, and then converted into a digital horizontal rate by a one-dimensional interpolation low-pass filter having a desired number of taps. The number of pixels may be converted. By the way, this method is
The configuration can be further simplified as compared with the case where the same processing as the horizontal line number conversion is applied.

In the above embodiment, the case where a programmable cross switch circuit is used as the connection switching circuit 13 has been described. However, the present invention is not limited to this, and other circuits such as a selector circuit may be used. May be. In short, if a connection switching circuit that can supply a register control signal input by switching an internal connection state based on a wiring switching control signal to a desired register of the vertical transfer register is provided, The same effect as in the above case can be obtained.

In the above embodiment, the vertical transfer units 11A to 11N have been described as including the photo sensors 5A to 5N. However, the present invention is not limited to this, and the vertical transfer units 11A to 11N are not limited to the photo sensors 5A to 5N. May not be included. In short, if a plurality of photo sensors are provided in the horizontal and vertical directions corresponding to the pixels and accumulate electric charges corresponding to the light amount of the input optical signal, the same effect as in the above case can be obtained. it can.

In the above-described embodiment, a case has been described in which a plurality of vertical transfer units 11A to 11N having the vertical transfer register 12 are provided. However, the present invention is not limited to this, and is provided for each vertical line. If a vertical transfer register is formed by connecting a plurality of registers and sequentially shifts the electric charge received from the photo sensor located on the vertical line in the vertical direction,
The same effect as in the above case can be obtained.

Further, in the above-described embodiment, the case where the horizontal transfer unit 3 that shifts the charges sent from the vertical transfer units 11A to 11N in the horizontal direction is provided, but the present invention is not limited to this. A horizontal transfer circuit that receives an electric charge transferred in a unit of a horizontal line from each vertical transfer register, sequentially outputs the electric charge in the horizontal direction, and outputs an image signal corresponding to an input optical signal. If provided, the same effect as in the above case can be obtained.

In the above-described embodiment, a plurality of timing generator circuits 21A to 21A for generating control signals S21 to S23 corresponding to respective video formats are provided.
C and a control signal S21 based on the mode switching signal S20.
To S23, and a timing generator having an interface circuit 21E for outputting a selected control signal S21, S22 or S23 and generating a wiring switching control signal Sc 'based on the mode switching signal S20. Although the case where the circuit 21 is provided has been described, the present invention is not limited to this, and a plurality of signal generators for generating a register control signal corresponding to each video format and a plurality of signal generators based on a mode switching signal are provided. And a timing generator circuit having a selection switch for selecting a desired register control signal among a plurality of register control signals generated by the switch and a signal generator for generating a wiring switching control signal based on a mode switching signal. if,
The same effect as in the above case can be obtained.

Further, in the above-described embodiment, the setting value of the programmable timing generator circuit 32 is set by the microprocessor 31 so that the control signals (Sg ', Sg',
e ', Sc' and S26) have been described, but the present invention is not limited to this, and the timing generator comprising a counter for generating a register control signal and a wiring switching control signal based on set values is set. Circuit,
If a register control signal and a wiring switching control signal that match the desired video format are generated by setting a set value that matches the desired video format based on the mode switching signal, the same as in the above-described case. The effect of can be obtained.

In the above-described embodiment, the microprocessor 41 downloads the program data to the FPGA / TG circuit to control the control signals (Sg ', e', S ') corresponding to the desired video format.
c 'and S26) have been described, but the present invention is not limited to this, and the timing generator circuit comprising a field programmable gate array capable of changing the internal circuit structure based on supplied program data And program data matching the desired video format based on the mode switching signal.
If the register control signal and the wiring switching control signal that match the desired video format are generated by supplying them to the programmable gate array, the same effect as in the above case can be obtained.

[0112]

As described above, according to the present invention, a connection switching circuit for supplying a register control signal to a desired one of the vertical transfer registers based on a wiring switching control signal is provided, and the connection switching circuit is used. By controlling the position of the register supplying the register control signal and controlling the logical level of the register control signal, the number of horizontal lines of the image signal can be freely changed according to a desired video format, Thus, an imaging device capable of easily generating image signals corresponding to various video formats with a simple configuration can be realized.

An image sensor capable of controlling a position of a register for supplying a register control signal and generating an image signal having a desired number of horizontal lines by controlling a logic level of the register control signal. And a timing generator circuit for generating a register control signal and a wiring switching control signal corresponding to a desired video format based on the video format and outputting the generated signal to the image pickup device. The number of horizontal lines can be easily changed according to
An image signal suitable for a video format desired by a user can be easily generated. Thus, an imaging apparatus capable of easily generating image signals corresponding to various video formats with a simple configuration can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CCD device to which the present invention is applied.

FIG. 2 is a circuit diagram illustrating a configuration of a vertical transfer unit.

FIG. 3 is a circuit diagram showing a connection state of a connection switching circuit in an HDTV system.

FIG. 4 is a signal waveform diagram showing a register control signal in the HDTV system.

FIG. 5 is a state transition diagram showing states of a vertical transfer register in the HDTV system.

FIG. 6 is a state transition diagram showing states of a vertical transfer register in the HDTV system.

FIG. 7 is a circuit diagram showing a connection state of a connection switching circuit in an ATV-p system.

FIG. 8 is a signal waveform diagram showing a register control signal in the ATV-p system.

FIG. 9 is a state transition diagram showing states of a vertical transfer register in the ATV-p system.

FIG. 10 is a circuit diagram showing a connection state of a connection switching circuit in the ATV-i system.

FIG. 11 is a state transition diagram showing states of a vertical transfer register in the ATV-i system.

FIG. 12 is a circuit diagram showing a connection state of a connection switching circuit in the EDTVII-p system.

FIG. 13 is a state transition diagram showing the state of the vertical transfer register in the EDTVII-p system.

FIG. 14 is a block diagram showing a switch-switching type camera on which the CCD element of the present invention is mounted.

FIG. 15 is a block diagram showing a programmable TG type camera on which the CCD element of the present invention is mounted.

FIG. 16 shows an FPGA-T mounting the CCD device of the present invention.
It is a block diagram which shows a G type camera.

FIG. 17 is a state transition diagram for explaining another control procedure in the ATV-i system.

FIG. 18 is a table showing various video formats.

FIG. 19 is a block diagram showing a configuration of a conventional CCD element.

FIG. 20 is a characteristic curve diagram for explaining the rate conversion principle of the rate converter.

[Explanation of symbols]

1, 10 ... CCD element, 2A-2N, 11A-11N
... Vertical transfer unit, 3 ... Horizontal transfer unit, 4 ... Buffer amplifier, 5, 5A to 5N ... Photo sensor, 6, 6A to 6
N: read-out gate, 7A to 7N: overflow control gate, 8: overflow
Drain, 9, 12 vertical transfer register, 13 connection switching circuit, 20, 30, 40 camera, 21 timing generator circuit, 22 CCD drive circuit, 23 correlated double sampling circuit , 24 ... Gain switching circuit, 31, 41 ... Microprocessor, 32 ...
... Programmable timing generator circuit, 41
…… FPGA / TG circuit.

Claims (10)

[Claims] A plurality of photosensors are provided in each of the vertical and horizontal directions to accumulate electric charges corresponding to the amount of an input optical signal, and a plurality of registers are provided for each vertical line. Vertical transfer registers for sequentially shifting the electric charges received from the photosensors located in the vertical line in the vertical direction, and provided for each of the vertical transfer registers, and the internal transfer registers are provided based on a wiring switching control signal. A connection switching circuit for supplying a register control signal input by switching the connection state to a desired register of the vertical transfer registers; receiving a charge transferred from each of the vertical transfer registers in units of horizontal lines; An image signal corresponding to the optical signal is output by sequentially shifting the charge in the horizontal direction and outputting the image signal. A horizontal transfer circuit for controlling the position of the register for supplying the register control signal by the wiring switching control signal and controlling the logical level of the register control signal to provide a desired number of horizontal lines. An image sensor for generating the image signal. 2. The connection switching circuit has six input lines and a plurality of output lines connected to each of the vertical transfer registers. Each of the connection lines is based on the wiring switching control signal. The image sensor according to claim 1, wherein the register control signal input to the input line is supplied to a desired register by connecting to the desired input line. 3. The image sensor according to claim 1, wherein the vertical transfer register converts the number of horizontal lines by combining the electric charges based on the register control signal. 4. A photo sensor which is arranged in a plurality of pixels in the horizontal and vertical directions and accumulates a charge corresponding to the light amount of an inputted optical signal, and is provided for each vertical line and connects a plurality of registers. Vertical transfer registers for sequentially shifting the electric charges received from the photosensors located in the vertical line in the vertical direction, and provided for each of the vertical transfer registers, and the internal transfer registers are provided based on a wiring switching control signal. A connection switching circuit for supplying a register control signal input by switching the connection state to a desired register of the vertical transfer registers; receiving a charge transferred from each of the vertical transfer registers in units of horizontal lines; An image signal corresponding to the optical signal is output by sequentially shifting the charge in the horizontal direction and outputting the image signal. And a horizontal transfer circuit for controlling a position of the register for supplying the register control signal by the wiring switching control signal and controlling a logical level of the register control signal to set a desired number of horizontal lines. An image sensor for generating the image signal, a timing generator circuit for generating and outputting the register control signal and the wiring switching control signal corresponding to a desired video format based on an input mode switching signal, and An imaging device comprising: 5. The connection switching circuit has six input lines and a plurality of output lines connected to each of the vertical transfer registers. The connection switching circuit switches the output lines based on the wiring switching control signal. 5. The imaging apparatus according to claim 4, wherein the register control signal input to the input line is supplied to a desired register by connecting to the desired input line. 6. The imaging device according to claim 4, wherein the vertical transfer register converts the number of horizontal lines by combining the electric charges based on the register control signal. 7. The image pickup apparatus according to claim 4, further comprising a gain switching circuit for switching a gain for each horizontal line and amplifying the image signal output from the horizontal transfer circuit. 8. The timing generator circuit includes: a plurality of signal generators for generating the register control signals corresponding to respective video formats; and a plurality of signal generators for generating the register control signals based on the mode switching signal. And a selection switch for selecting a desired register control signal among the plurality of register control signals, and a signal generator for generating the wiring switching control signal based on the mode switching signal. 5. The imaging device according to 4. 9. The timing generator circuit includes a counter for generating the register control signal and the wiring switching control signal based on a set value, and a desired video format based on the mode switching signal. 5. The image pickup apparatus according to claim 4, wherein the register control signal and the wiring switching control signal that match a desired video format are generated by setting the set value that matches the video format. 10. The timing generator circuit comprises a field programmable gate array capable of changing an internal circuit structure based on supplied program data, and a desired video format based on the mode switching signal. The above program data matched to
5. The image pickup apparatus according to claim 4, wherein the register control signal and the wiring switching control signal that match a desired video format are generated by supplying the register control signal and the wiring switching control signal to a programmable gate array.