JPH10336196A - Output conflict controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To separately prevent plural FIFOs that have output requests from remaining without being selected for a long time and to need only a small amount of hardwares. SOLUTION: This output conflict controller selects plural FIFOs 0 to 7 which make output requests every two FIFO output requests and has plural stages of output conflict circuits 2a to 2d, 3a and 3b and 4 which output one FIFO output request, and finally, the circuit 4 on the final stage outputs one FIFO output request. In such cases, a flag control part 1 which is installed between plural FIFOs and each output conflict circuit 2a to 2d performs such flag control as to fix the flag value of an FIFO that is finally selected in an output conflict circuit on the final stage to zero. When flags are the same in each output conflict circuit, an upper is preceded, and when flags are different, an FIFO of a flag one is preceded so that a flag zero may not be selected, the rest of FIFOs are successively and finally selected in the circuit 4 on the final stage, and plural FIFOs are prevented from remaining without being selected for a long time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output contention control device in a shaping device, for example, an ATM (As
(ynchronous Transfer Mode) This can be applied to a switching network, a terminal side of an ATM communication system, and the like.

[0002]

2. Description of the Related Art In general, a Subscribe Line Terminal (SLT) makes a large number of connections at the same time.
The cell performs connection admission control (CAC: Call Adm).
Usage parameter control (UPC: Usage Parameter Control) so as to satisfy the conditions allowed by the ission control.
ol). However, in the subscribe line terminal SLT, ATM cells are collected on each route by the ATM switch, so that ATM cells are concentrated on a specific route, and as a result, the virtual path (V
AT: Fast instantaneous speed exceeding the capacity of P: Virtual Path)
It may happen that M cells have to be sent. For this reason, each ATM cell is temporarily stored in a buffer memory provided for each connection, and the ATM cell is read so that the instantaneous speed of the ATM cell does not exceed a certain value (the capacity of VP). Such a function is called shaping, and a device having such a function is called a shaping device.

In this shaping apparatus, ATM cells once written in a buffer are read out according to a scheduler instruction. The scheduler outputs a read request independently for each connection, but in some cases, the scheduler may instruct a plurality of connections to request a cell read. In this case, since one cell can be output from the shaping device, a connection to output an ATM cell must be selected from a plurality of connections. This is output conflict control in the shaping device. In this output contention control, an unselected connection continues to output, so at the next cell output timing,
Further, contention control is performed.

[0004]

As one method of selecting conflicting connections in a shaping device, the FIFOs corresponding to the connections are numbered from 0 to N. Small F
There is a method of outputting cells from the IFO. In this case, there is a drawback that the number of cells selected due to contention tends to be smaller, so that there is a difference in the traffic characteristics of the cell of each connection. Next, a method of randomly selecting an output from each of the conflicting connections can be considered. In this case, the probability of each connection being selected at the time of contention is statistically equal. On the other hand, selecting at random means that when focusing on a certain connection, there is a small probability that it will not be selected forever. That is undesirable.

[0005] Next, a counter is provided for each connection and the number of times not selected by the conflict control is retained, so that the output from the one with the largest number is output (if the number is the same, the one selected at random or the one with the smaller number is output). May be selected). In this case, since the counter is configured, there is a disadvantage that the hardware scale becomes large when the bit length and the number of connections of the counter are large. With any of the methods described above, the amount of hardware in the shaping device is small,
Contention control in which a connection with a short remaining time exists cannot be realized.

[0006]

SUMMARY OF THE INVENTION An output contention control apparatus according to the present invention is arranged such that, when output requests are issued from a plurality of FIFOs, the output competition control device of the first stage responds to the output requests of the plurality of FIFOs every two output requests. Each output competing circuit makes an alternative selection, outputs an output request of one FIFO, and outputs the selected FIFO.
In response to the output request, each of the output competition circuits in the second stage makes an alternative selection for every two output requests, and outputs one FIFO output request. Performs an alternative selection, and finally, a final-stage output competition circuit outputs an output request of one FIFO. In the output competition control device, the plurality of FIFOs and each of the first-stage output competition circuits are The flag control unit provided between the first and second registers is used only when the flags of all the FIFOs are 0.
When an output request is issued from the FO, the flag is set to 1 only for the FIFO for which the output request has been issued, and a plurality of FIFOs are set.
If any one of the flags has a flag of 1,
Even if there is an output request to the FIFO, the values of the flags of all FIFOs are kept unchanged, and flag control is performed so that the value of the flag is set to 0 for the FIFO output by the final output competition circuit. The competing circuit has two FIFOs
When there is an output request from O, the output request has a high order and a low position, and when both the flags are 0 or 1, the high-order FIFO is selected and the number of the FIFO, the output request, and the flag are output. And one of the lower flags is 1
In the case of, the FIFO number and output request and the flag whose flag is 1 are output. If there is no output request from both FIFOs, the upper FIFO number and flag are output, and only one of the upper and lower output requests is output. If there is a requested FIF
It is configured to output an O number, an output request, and a flag.

In the present invention, the flag control unit sets the FI only when the flags of all the plurality of FIFOs are 0.
When an output request is issued from the FO, the flag is set to 1 only for the FIFO for which the output request has been issued, and a plurality of FIFOs are set.
If any one of the flags has a flag of 1,
The flag control is performed so that the values of the flags of all FIFOs do not change even if there is an output request to the FIFO, and the values of the flags output from the final output competition circuit are set to 0. In the output competing circuits from the last stage, when there is an output request from two FIFOs, the output request has the upper and lower positions, and when both flags are 0 or 1, the upper FIFO is selected and the corresponding FIFO is selected.
Outputs the FIFO number, output request, and flag. When one of the upper and lower flags is 1, outputs the FIFO number, output request, and flag whose flag is 1. When there is no output request from both FIFOs Outputs the number and flag of the upper FIFO, and outputs the requested FIFO number, output request, and flag when there is only one of the upper and lower output requests. When the value of the flag of the selected FIFO is set to 0 and fixed and the FIFO and another FIFO compete with each other, there is an output request, and the FIFO with the flag of 1 is given priority. Will not be selected, and will be finally selected one after another by the output competition circuit in the final stage until all remaining FIFOs that have not been finally selected are exhausted, and all FIFOs will be selected. Has been the value of the FIFO flag is selected as the flag to 1 for that there is an output request again when it is all 0, a plurality of FI
It is possible to prevent each of the FOs from being left unselected for a long time. Also, since only the flag control of the flag control unit and a plurality of output control circuits need to be prepared, the amount of hardware is small.

[0008]

FIG. 1 is a block diagram of an output conflict control device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing inputs and outputs of an output conflict circuit of the output conflict control device, and FIG. FIG. 4 is a flowchart showing the operation of the output conflict circuit of the output conflict control device, and FIG. 4 is a flowchart showing the operation of the flag control circuit of the output conflict control device. The output conflict control device according to the first embodiment shows a case where the outputs of seven FIFOs conflict. In the figure, reference numeral 1 denotes a flag control circuit for controlling flags of seven FIFOs as input information, and 2a to 2d first-stage output competition for selecting one input from two FIFOs input from the flag control circuit 1, respectively. Circuit 3a is a first stage output competition circuit 2a, 2b
The second stage output competition circuit 3b, which selects one input from the two FIFOs respectively selected by the first and second stages, is selected by the first stage output competition circuits 2c, 2d, respectively.
Another second to select one input from one FIFO
The output competing circuit of the stage is 4 and the output competing circuits 3a, 3
This is a third stage output competing circuit which is the last stage for selecting one input from the two FIFOs respectively selected by b. Each FIFO, which is input information, has a FIFO number, an output request, and a flag.

Next, the first to third stage output competition circuits 2
a to 2d, 3a to 3b, and 4 are shown in FIGS.
A description will be given based on the flowchart of FIG. Since the output competing circuits 2a to 2d, 3a to 3b, and 4 all perform the same operation, the output competing circuit 2a will be described.
For example, when two FIFOs are input to the output competition circuit 2a to compete with each other, the two competing parties are defined as a higher order and a lower order. The upper and lower determination criteria are, for example, the higher of the FIFO numbers of the FIFO. First, when there is an output request for both the high order and the low order (step S1), when both of the flags are 1 (step S2), the high order is selected, and when one of the high order flags is 1 (step S3), the high order is selected. When one of the lower flags is 1 (step S4), the lower is selected, and when both of the flags are 0, the upper is selected. As a result, if only one of the flags is 1, the FIFO with the flag of 1 is selected.

Next, when there is no output request for both the upper and lower orders, there is an output request for the upper order (step S5).
At this time, the upper order is selected. If there is no output request for the upper order and there is an output request for the lower order (step S8), the lower order is selected (step S6). If neither the upper order nor the lower order is output, the upper order is selected. Is selected. Then, the FIFO of the selected FIFO is output from the output competition circuit 2a.
The FO number and its associated output request and flag are output.

Next, the operation of the flag control circuit 1 will be described with reference to the flowchart of FIG. A FIF
If there is an output request for O (step S10),
When the flags of all FIFOs are 0 (step S11)
Sets only the flag of the FIFO for which the output request has been made to 1 (step S12). Therefore, if there are output requests for all FIFOs, all the FIFOs for
The FO flag is set to 1. When the flags of all FIFOs are not 0, that is, when the flag of one of the plurality of FIFOs is 1, the flags of all FIFOs do not change even if an output request is issued to any FIFO. Further, the value of the flag of the FIFO selected by the output contention control device is set to 0 (step S12).

Next, the operation of the output conflict control device according to the first embodiment of the present invention will be described. For example, FIFO 0
When there is an output request for all of the registers 0 to 7, the flag control circuit 1 sets all the flags of the FIFOs 0 to 7 to 1. The first stage output competition circuit 2a has FIFOs 0 and 1
, The first stage output competition circuit 2b receives FIFO 2 and 3 output requests, the first stage output competition circuit 2c receives FIFO 4 and 5 output requests, and FIFO 6 is provided in the one-stage output competition circuit 2d.
And 7 output requests are input. The first-stage output competition circuit 2a determines that the input FIFO 0 and 1 flags are both “1”, so that the higher-order FIFO 0
(In other words, the FIFO with the smaller FIFO number is defined as the higher order, so the higher order FIFO is FIFO 0) and output. Therefore, the output competition circuit 2b in the first stage uses the FIFO 2 and the output competition circuit 2c uses the FIFO 2
4 and the output competition circuit 2d outputs FIFO 6.

Next, the second stage output competing circuit 3a has a FI
FO 0 and 2 are input, and the second stage output competition circuit 3b
Are input with FIFOs 4 and 6. The output competing circuit 3a of the second stage, since both the input FIFO 0 and 2 flags are 1, the upper FIFO, FIFO
Select 0 and output. Therefore, the output competition circuit 3b in the second stage outputs FIFO4. Furthermore, FIFOs 0 and 4 are provided to the third stage output competition circuit 4 which is the last stage.
And the third stage output competition circuit 4 outputs the input F
Since the flags of IFOs 0 and 4 are both 1, FIFO 0 which is the upper FIFO is finally selected and output. Then, the FIFO that is finally selected and output
In the case of 0, the value of the flag is set to 0 by the flag control circuit 1 and fixed.

In this state, if there is an output request to all of the FIFOs 0 to 7, the output requests of the FIFOs 0 and 1 are input to the first stage output competition circuit 2a.
Since the flag of O0 is 0 and the flag of FIFO 1 is 1, flag 1 has priority and the first-stage output competition circuit 2a outputs FIFO 1. The other output competition circuits 2b to 2d in the first stage output the same FIFO as described above, FIFO1 and 2 are input to the output competition circuit 3a in the second stage, and the output competition circuit 3b in the second stage FI as before
FO 4 and 6 are input, and the second stage output competition circuit 3a
Outputs FIFO 1 and outputs the second-stage output competition circuit 3b
Outputs FIFO 4. In addition, the third stage
FIFO 1 and 4 are input to the output competition circuit 4 of the stage, and the output competition circuit 4 of the third stage
Since the flags of 1 and 4 are both 1, the upper FIFO
Is finally selected and output. Then, the flag value of the FIFO 1 finally selected and output is set to 0 by the flag control circuit 1 and fixed. In this way, the FIFO that is finally selected and output is not selected even if there is an output request, so until the remaining FIFOs are all output,
No new competing FIFOs are added.

Therefore, when the value of the flag of the FIFO finally selected by the final output competing circuit 4 is set to 0 and fixed, when the FIFO competes with another FIFO, an output request is issued. Therefore, the FIFO with the flag of 1 is prioritized, so that the FIFO is not selected, and the remaining FIFOs that have not been finally selected until now are not selected.
Are finally selected one after another by the output competing circuit 4 at the last stage until all the FIFOs are selected, and when all the FIFO flags become 0, a flag is output again for the output request. Since the selection is made to be 1, it is possible to prevent each of the plurality of FIFOs from being left unselected for a long time. The flag control unit 1
Control and a plurality of output control circuits 2a to 2d, 3a to
Since only 3b and 4 need to be prepared, there is no need to provide a counter or the like in the connection as in the related art, so that the amount of hardware is small.

For example, when output requests are issued to all of the FIFOs 0 to 7, when the flag of the FIFO 1 is 1, the flag control circuit 1 sets the flags of the FIFOs 0 to 7 regardless of which FIFO has the output request. Do not change the value.
Accordingly, the output requests of FIFO 0 and 1 are input to the first stage output competition circuit 2a, and the first stage output competition circuit 2b
, The output requests of FIFO 2 and 3 are input, the first stage output competition circuit 2c receives the output requests of FIFO 4 and 5, and the first stage output competition circuit 2d receives the FIFO request.
6 and 7 output requests are input. The first stage output competition circuit 2a sets the flag of the input FIFO 0 to 0,
Since the flag of FIFO 1 is 1, the F of flag 1
Since the IFO is prioritized, FIFO 1 is selected and output. Further, the output competition circuit 2b in the first stage selects and outputs the FIFO 2 which is the higher-order FIFO since the input flags of FIFO 2 and 3 are both 0. Therefore, the output competition circuit 2b in the first stage is F
The output competition circuit 2c outputs FIFO 4
And the output competition circuit 2d outputs FIFO 6.

Next, the second stage output competing circuit 3a has the FI
FO 1 and FO 2 are input, and the second stage output competition circuit 3b
Are input with FIFOs 4 and 6. The output competition circuit 3a of the second stage sets the input FIFO 1 flag to 1
Since the flag of FIFO 2 is 0, the flag 1
FIFO 1 is given priority, so that FIFO 1 is selected and output. Further, the output competition circuit 3b in the second stage selects and outputs the FIFO 4 which is the higher-order FIFO since both the flags of the input FIFOs 4 and 6 are 0. Further, a third stage output competition circuit 4 which is the last stage
, FIFO 1 and 4 are input, and the third-stage output competition circuit 4 sets the input FIFO 1 flag to 1 and outputs
Since the flag of FIFO 4 is 0, the F of flag 1
Since IFO has priority, FIFO 1 is selected and output.

Then, the finally selected and output F
The flag value of IFO 1 is fixed to 0 by the flag control circuit 1. Then, FIFO
Since all the flags of 0 to 7 become 0, FIFO 0
When an output request is issued to all of the registers 7 to 7, the flag control circuit 1 sets all flags of the FIFOs 0 to 7 to 1. This will return to the state described earlier. In the above description, the FIFOs 0 to 7 have one flag of 1 in a plurality of FIFOs. However, if there are a plurality of FIFOs, the plurality of FIFOs are selected by each output competing circuit on the basis of higher priority, and successively. Finally, the flag control circuit 1 sets the values of the flags to 0 one after another, and when all the flags of FIFO 0 to 7 have become 0, the flag control circuit 1
All of the flags 0 to 7 are set to 1.

[0019]

As described above, according to the present invention, only when the flags of all the plurality of FIFOs are 0, the flag control unit sets the flag only for the FIFO for which the output request was made when the output request was issued from the FIFO. Is set to 1, and if at least one of a plurality of FIFOs has a flag of 1, all FIFOs are output regardless of which FIFO is requested.
The value of the flag of O is not changed, and flag control is performed so that the value of the flag is set to 0 for the FIFO output by the output competition circuit of the final stage. In each of the output competition circuits of the first to final stages, When there are output requests from the two FIFOs, the output requests are ranked higher and lower, and when both flags are 0 or 1, the upper FIFO is selected and the number of the FIFO, the output request, and the flag are output. When one of the upper and lower flags is 1, the flag is 1.
FIFO number, output request, and flag are output, and if there is no output request from both FIFOs, the upper FIFO
Is output, and if only one of the upper and lower output requests is issued, the number of the requested FIFO, the output request, and the flag are output. When the value of the flag of the FIFO is set to 0 and fixed, when the FIFO competes with another FIFO, there is an output request and the FIFO of flag 1 is set.
Will no longer be selected because it has priority, and the remaining FIFOs that have never been finally selected
Until O is exhausted, final selection is sequentially performed by the output competing circuit at the final stage. When all FIFOs are selected and the values of the flags of the FIFOs are all set to 0, a flag is output again for an output request. Since the selection is made to be 1, there is an effect that it is possible to prevent each of the plurality of FIFOs from being left unselected for a long time. In addition, since only the flag control of the flag control unit and a plurality of output control circuits need to be prepared, there is an effect that the amount of hardware is small.

[Brief description of the drawings]

FIG. 1 is a block diagram of an output conflict control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing inputs and outputs of an output conflict circuit of the output conflict control device.

FIG. 3 is a flowchart illustrating an operation of an output conflict circuit of the output conflict control device.

FIG. 4 is a flowchart illustrating an operation of a flag control circuit of the output conflict control device.

[Explanation of symbols]

1 Flag control circuit, 2a to 2d First stage output competition circuit, 3a to 3b Second stage output competition circuit, Third stage output competition circuit (final stage output competition circuit).

Claims (1)

[Claims] When there is an output request from a plurality of FIFOs, each output competition circuit in the first stage selects one of the output requests of a plurality of FIFOs for every two output requests, and outputs one FIFO. Output request and outputs the selected FIF
In response to the output request of O, each of the output competition circuits in the second stage makes an alternative selection for every two output requests, and outputs one FIFO output request. An output contention control device in which a circuit makes a selection and an output contention circuit of a final stage finally outputs an output request of one FIFO. The plurality of FIFOs and each output contention circuit of the first stage The flag control unit provided between the first and second sets the flag to 1 only when the output request is issued from the FIFO only when the flags of all the plurality of FIFOs are 0, and sets the flag to 1 for only the FIFO for which the output request was issued. If at least one of the flags has a flag of 1, even if an output request is issued to any of the FIFOs, the values of the flags of all the FIFOs are kept unchanged, and Then, the flag control is performed so that the value of the flag is set to 0, and each of the output conflict circuits has an upper and lower position in the output request when there is an output request from two FIFOs,
When both flags are 0 or 1, the upper FIFO is selected and the FIFO number, output request and flag are output, and when one of the upper and lower flags is 1, the flag is 1
FIFO number, output request, and flag are output, and if there is no output request from both FIFOs, the upper FIFO
And a flag for outputting the requested FIFO number, output request and flag when there is only one of the upper and lower output requests. .