JPH10335651A - Mosfet and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET which functions as a device of short gate length and is less affected by the resistance of a gate electrode which causes a signal transmission delay. SOLUTION: A polysilicon 17 is deposited on the side of a structure covered with a PSG film 16 and a first PSG side wall 18, and furthermore a structure where a second BSG side wall 19 is provided is formed (F), and an empty space whose width is specified by the second side wall 19 is formed above the polysilicon 17 by etching (G). Then, a silicon 21 is deposited in the empty space to form a structure (H), and then the silicon 21 is turned to silicide, whereby a gate electrode with a silicide 23 whose width is larger than a width (gate length) on a substrate 11 side is formed (J).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOSFET (met
al-oxide-semiconducter field effect transistor) and a method for manufacturing a MOSFET, in particular, a MOSFET with a gate electrode having a silicide layer on its surface,
And its manufacturing method.

[0002]

2. Description of the Related Art In recent years, signal propagation delay due to electrode wiring resistance has become a serious problem due to miniaturization of electrode wiring accompanying high integration of LSI. For this reason, particularly in the field of MOS LSI, which has been highly integrated, a gate electrode (also called a gate electrode having a polycide structure) made of polysilicon and silicide, which is a compound of silicon and metal, has been used. A salicide process capable of simultaneously reducing the resistance of the gate electrode and the source / drain regions has attracted attention.

Hereinafter, an outline of a conventional procedure for forming a gate electrode by a salicide process will be described with reference to FIG. When silicide is formed by the salicide process, first, as shown in FIG. 6A, an element isolation region 32, a gate oxide film 33, a gate electrode polysilicon 34, a side wall are formed on a semiconductor substrate 31 made of silicon. The structure in which 35 and the like are formed is manufactured in the same procedure as when no silicide is used.

That is, after a thermal oxide film is formed on a semiconductor substrate 31, a silicon nitride (Si ₃ N ₄ ) film is formed by CVD. Next, a part of the silicon nitride film is removed by lithography and etching so that the silicon nitride remains only in a region to be an active region. Then, after ion implantation for preventing formation of a parasitic transistor, the semiconductor substrate 3 is formed using silicon nitride as a mask.
1 wet O ₂ oxidation is performed to form an element isolation region 32. Thereafter, the silicon nitride film and the oxide film are removed, and a gate oxide film 33 is formed on the semiconductor substrate 31 by thermal oxidation again.

Next, after ion implantation for threshold adjustment (channel ion implantation) is performed, a polysilicon layer is formed. Then, the polysilicon layer is patterned using a resist, and RIE (reactive ion etch) is performed.
ing) Etching is performed by an apparatus to form polysilicon 34 serving as a gate electrode. Next, a silicon oxide film or the like is deposited on the entire surface of the substrate by CVD or the like. Then, the silicon oxide film is etched back by the RIE apparatus or the like, so that the sidewall 35 is formed. In addition,
Before and after formation of the sidewall 35, ion implantation for forming the source / drain region 37 in the semiconductor substrate 31 is performed (for simplicity, the ion-implanted portion of the source / drain region is not shown).

After the structure shown in FIG. 6A is formed by such a procedure, as shown in FIG. 6B, for example, titanium (Ti) 36 is deposited on the surface of the structure. Is done.
Thereafter, the structure on which the titanium 36 is deposited is heat-treated, for example, in a nitrogen atmosphere, and silicide (TiS
i ₂ ) 38 are formed. At this time, the reaction between the silicon in the source / drain region 37 and the titanium 36 thereon causes
A silicide 38 'is also formed on the source / drain region 37. Then, titanium which did not react with silicon,
By removing titanium (TiN) reacted with nitrogen by wet etching, a structure having a gate electrode having silicide on its surface and a source / drain region (FIG. 6C) is manufactured. After this, the normal MOSF
According to the ET manufacturing process, an insulating film, a contact hole, and an aluminum wiring are formed, and a MOSFET is completed.

As described above, the use of this process does not greatly change the conventional MOSFET manufacturing procedure.
Since silicide can be formed in a self-aligned manner in a portion where silicon exists, a low-resistance gate electrode can be formed relatively easily.

However, when the gate electrode (MOSFET) is manufactured by the above-described procedure, as shown in FIG. 6C, a thin silicide 38 at both ends is formed. That is, there has been a problem that a gate electrode in which the proportion of silicide in the total cross-sectional area of the gate electrode is low is formed.

To solve this problem, Japanese Patent Laid-Open Publication No.
In the technique described in Japanese Patent No. 5823, a gate electrode (MOSFET) is manufactured by a procedure as shown in FIG.
That is, in this technique, when a structure corresponding to FIG. 6A is formed, dry etching is performed for a long time.
As shown in (A), a structure having sidewalls 35 whose height is lower than polysilicon 34 is formed. Next, as shown in FIG. 7B, titanium 3
6 is deposited. Then, silicide 3
8, 38 'are formed (FIG. 7C). Then, by removing unreacted titanium, as shown in FIG. 7D, a silicide 3 having a uniform film thickness is formed on the polysilicon 34.
8 are formed.

[0010]

The above-mentioned JP-A-7-4
According to the technique disclosed in Japanese Patent No. 5823, a gate electrode having a lower resistance can be formed as compared with a case where a silicide metal represented by titanium is simply deposited on polysilicon. However, MOSFETs using this technology
Since the manufacturing of the semiconductor device requires an overetch, the polysilicon for the gate electrode is damaged by the etching. Further, the oxide film on the source / drain region is etched, and the source / drain region below the oxide film may be damaged by the etching. Therefore, even if a low-resistance gate electrode is obtained, the characteristics of the device as a whole may be degraded.

Furthermore, the resistivity of titanium silicide increases as the width thereof (the length of the gate electrode in the channel direction indicated by an arrow 39 in FIG. 7D; hereinafter, referred to as gate length) becomes narrower. Are known. For example, a paper by Goto et al. (IEICE TRANS. ELECTRON., E77-C, P.480-485)
(1994)) reports on the gate length dependence of the sheet resistance of titanium silicide as shown in FIG. As is apparent from the figure, when the gate length is 0.5 μm or more, titanium silicide having substantially the same sheet resistance is formed. However, when the gate length is made shorter than 0.5 μm, the sheet resistance of the formed titanium silicide increases as the gate length becomes shorter. In particular, in a region where the gate length is 0.3 μm or less, the rate of increase becomes smaller. Extremely large. It is considered that such a phenomenon occurs due to the following reasons.

At the time of annealing, in titanium silicide,
A phase transition from the relatively high-resistance C49 phase to the low-resistance C54 phase occurs, and as a result, low-resistance titanium silicide is formed. However, while the particle size of the C49 phase is several hundred nm, the particle size of the C54 phase is larger than that, and is usually several μm. Therefore, when the gate length is reduced, the phase transition from the C49 phase to the C54 phase due to annealing is suppressed. Furthermore, when the gate length becomes smaller,
It is considered that the sheet resistance of silicide increases as the gate length becomes shorter because the influence of disconnection due to silicide aggregation is added.

Therefore, when a gate electrode having a short (for example, about 0.2 μm) gate length is formed using the above technique, the gate electrode contains silicide having a relatively high resistance. That is, a MOSFET having a short gate length manufactured by the above technique is affected by signal propagation delay due to the resistance value of the gate electrode.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOSFET which functions as a device having a short gate length and is less affected by signal propagation delay due to a resistance value of a gate electrode.

Another object of the present invention is to provide such an M
An object of the present invention is to provide a manufacturing method capable of easily manufacturing an OSFET.

[0016]

According to the present invention, in order to solve the above-mentioned problems, when a MOSFET having a gate electrode having a silicide layer on its surface is formed, a cross-sectional shape in a source / drain direction is changed to a silicide layer. A gate electrode in which the length in the channel direction on the layer side is longer than the length in the channel direction on the semiconductor substrate side is employed.

More specifically, for example, (a) a gate electrode having a silicide layer on its surface layer, wherein the length in the channel direction on the silicide layer side is longer than the length in the channel direction on the semiconductor substrate side. A gate electrode that is long and has a substantially constant length in the lower channel direction, which is a portion from the semiconductor substrate side to a predetermined height; and (b) a height in which the lower side surface of the gate electrode is in contact with the side surface. And (c) a part of the side surface of a portion different from the lower portion of the gate electrode, and a second sidewall whose side surface is in contact with the first sidewall. Is used to form a MOSFET.

By employing such a configuration, the width of the portion where the silicide is formed can be set independently of the gate length, so that it functions as a device having a short gate length, and furthermore, a signal based on the resistance value of the gate electrode. A MOSFET which is less affected by propagation delay can be realized.

Further, according to the first method of manufacturing a MOSFET of the present invention, when manufacturing a MOSFET having a gate electrode having a silicide layer on its surface, (i) forming a gate oxide film and silicon on a semiconductor substrate; A gate electrode structure forming step of forming a gate electrode structure by laminating a gate electrode element comprising: (ii) a first sidewall on a side surface of the gate electrode structure formed in the gate electrode structure forming step; (Iii) forming a first sidewall;
A second sidewall forming step of forming a second sidewall higher in height from the semiconductor substrate than the first sidewall on a side surface of the first sidewall formed in the first sidewall forming step; (iv A) a silicon deposition step of depositing silicon on a portion sandwiched between the second sidewalls formed in the second sidewall formation step, and a silicide formation step of forming silicide on the surface layer of silicon deposited in the silicon deposition step. Is used.

That is, in the first method for manufacturing a MOSFET according to the present invention, by using two side walls to form polysilicon serving as a gate electrode in two stages, the side on which the silicide is formed is formed. Polysilicon having a shape in which the length in the channel direction is longer than the length in the channel direction on the semiconductor substrate side is formed. Then, by forming silicide on the polysilicon having the shape, a gate electrode (MOSFET) having a short gate length and less affected by signal propagation delay due to the resistance value of the gate electrode is obtained.

According to the second method of manufacturing a MOSFET of the present invention, when manufacturing a MOSFET having a gate electrode having a silicide layer on its surface, (a) a method of forming a gate oxide film and silicon on a semiconductor substrate; Forming a gate electrode structure by laminating a gate electrode element and a first material layer that is a layer made of a first material; and (b) forming a gate electrode structure by the gate electrode structure. A first sidewall forming step of forming a first sidewall made of a first material on a side surface of the gate electrode structure;
(c) The first side wall formed in the first side wall forming step
A second side wall forming step of forming a second side wall made of a second material different from the first material on a side surface of the side wall; and (d) an etching rate for the first material is higher than that for the second material. By etching the semiconductor substrate on which the second sidewall has been formed in the second sidewall forming step under faster conditions,
A removing step of removing the first material layer and a part of the first sidewall provided on the gate electrode element, and (e) a silicon depositing step of depositing silicon on the portion from which the first material has been removed by the removing step And (f) a silicide formation step of forming silicide on the surface layer of silicon deposited in this silicon deposition step.

That is, in the second method for manufacturing a MOSFET according to the present invention, the first sidewall made of the first material is formed on the side surface of the gate electrode structure in which the first material layer is provided on the gate electrode element made of silicon. Forming the first
A second sidewall made of a second material is formed on a side surface of the sidewall. Then, by etching the semiconductor substrate on which the second sidewall and the like are formed under the condition that the etching rate for the first material is higher than the etching rate for the second material, the second electrode provided on the gate electrode element is etched. The one material layer and part of the first sidewall are removed. That is, a space that is wider than the gate electrode element and whose width is determined by the second sidewall is generated above the gate electrode element. Then, by depositing silicon in the space and forming silicide on the deposited silicon, a gate electrode having a short gate length and less affected by signal propagation delay due to the resistance value of the gate electrode is formed. .

When a MOSFET is manufactured by the second method for manufacturing a MOSFET, any combination of materials having different etching rates may be used as the first material and the second material. I can do it. For example, as the first material and the second material, respectively, P
SG and NSG may be used, and PSG and BSG may be used as the first and second materials, respectively. In addition,
When these materials are used, a step of performing etching using hydrofluoric acid can be employed as the removal step.

When the second MOSFET manufacturing method is used, it is desirable to adopt, as the silicon deposition step, a step of depositing silicon under conditions that allow silicon to selectively grow on silicon.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments. <First Embodiment> FIG. 1 shows a MOSFET according to a first embodiment.
1 shows a cross-sectional structure. As shown in FIG.
The FET includes a gate electrode composed of silicide 23 and polysilicon 24 and having a width 25 on the single crystal silicon substrate 11 side smaller than a width 27 on the silicide 23 side. Further, the MOSFET is in contact with a narrow portion below the gate electrode, and has a first height substantially equal to the height of the narrow portion.
A sidewall 18 is provided. In addition, MOSFET
Are the first sidewall 18 and the second sidewall 1 that is in contact with a part of the wide portion above the gate electrode.
9 is provided.

Hereinafter, referring to FIG. 2 and FIG.
The ET manufacturing procedure will be described. In the following, for convenience of description, formation of a source region, a drain region, and the like, or
A description of an impurity doping process performed to reduce the resistance of the gate electrode is omitted.

In manufacturing this MOSFET, first,
According to the procedure already described with reference to FIG. 6, as shown in FIG. 2A, an element isolation region 12 made of silicon oxide (SiO ₂ ) and a silicon An oxide layer 13 is formed. In this embodiment, the thickness of the silicon oxide film 13 is set to 10
nm.

Then, as shown in FIG. 2B, a polysilicon (polycrystalline silicon) film 14 and a PSG (phospho-silicon) film are formed on the element isolation region 12 and the silicon oxide film 13.
(categlass) A film 15 is formed. Note that the method for forming these films is not particularly limited, but in this embodiment, the CVD method is used.
The polysilicon film 14 and the PSG film 15 are manufactured by using (chemical vapor deposition). The thicknesses of the polysilicon film 14 and the PSG film 15 are 300
nm and 150 nm.

Then, by patterning the PSG film 15, as shown in FIG. 2C, the PSG film 16 having the same width 25 as the gate length of the gate electrode to be formed.
To form In this embodiment, the width 25 is set to 0.2 μm
And Next, the polysilicon film 14 is etched using the PSG film 16 as an etching mask, thereby forming the polysilicon 17 serving as a component of the gate electrode.
Is formed (FIG. 2D).

Next, a PSG film serving as a first sidewall is deposited. This PSG film was dry-etched using an RIE apparatus, and as shown in FIG.
6 and the first side wall 1 on the side of the polysilicon 17.
8 is formed. In this embodiment, SiH ₄ , PH ₃ ,
Depositing a PSG film by CVD using oxygen as a source gas;
By dry etching, the first 26 having a width 26 of 0.05 μm
The side wall 18 is formed.

Next, as shown in FIG.
In order to obtain a structure in which the second sidewall 19 is formed on the side surface of the sidewall 18, the first sidewall 18 is formed.
NSG (non-do
This is performed using ped silicate glass). That is, NSG
The deposition of the film is performed using ozone (O ₃ ), TEOS (tetra-ethyl-o
CV using rtho-silicate, Si (OCH ₂ CH ₃ ) ₄ )
D, the second sidewall 19 is formed by etching back the deposited NSG film.

Thereafter, the PSG film is etched by wet etching using 1% hydrofluoric acid (HF) as an etchant. As shown in FIG.
Since the etching rate of SG is higher than that of NSG, when the above processing is performed on the structure shown in FIG.
While the G film 19 is slightly etched, the PSG film 16 on the polysilicon 17 and the upper portion of the first sidewall 18 are etched. As a result, a structure having openings on both sides of the polysilicon 17 is formed as shown in FIG. Since the exposed silicon oxide film 13 on the single crystal silicon substrate 11 is also etched, the gate oxide film 20 is formed on the single crystal silicon substrate 11.
Only the silicon oxide film functioning as a film remains.

Next, selective growth of silicon is performed on the structure shown in FIG. As a result, as shown in FIG. 3H, the silicon film 2 was formed on the region where the silicon was exposed.
1 is formed. Note that single crystal silicon grows on the single crystal silicon substrate 11 and polysilicon grows on the polysilicon 17.

Thereafter, a titanium (Ti) film 22 is formed on the structure on which the silicon film 21 is formed by sputtering as shown in FIG. Then, the first short-time annealing (Rapid Thermal Anneal) is performed in nitrogen for 60 hours.
Perform at 0-700 ° C. for 30 seconds. By this short annealing, the titanium 21 reacts with the silicon 21 on the single crystal silicon substrate 11 and the gate electrode surface to form titanium silicide. Next, the titanium nitride and the unreacted titanium produced by the short-time annealing are removed using ammonia-hydrogen peroxide (a mixture of water 3, ammonia 1, and hydrogen peroxide 1). Medium, 7
By carrying out at 50 to 850 ° C. for 10 seconds, FIG.
As shown in (1), a structure including silicide films 23 and 23 'is formed on the gate electrode and the source / drain regions.

Now, as mentioned above, the width is about 0.3
When a silicide narrower than μm is formed, the resistance becomes extremely high. However, the polysilicon for the gate electrode composed of the polysilicons 17 and 21 included in the structure shown in FIG. 3J has a gate length 25 itself of 0.2 μm smaller than 0.3 μm. The width 27 on the side of the silicide 23 is approximately 0.3 (= 0.2 + 0.0) at which a silicide having a relatively low resistance can be formed.
(5 × 2) μm (in the present embodiment, the width of the first sidewall is 0.05 μm as described above). Therefore, a structure formed by depositing and annealing titanium (FIG. 3).
(J)) has a gate electrode including silicide 23 having relatively low resistance.

In other words, according to the above-described procedure, for example, a conventional gate electrode having a gate length of about 0.2 μm and having a low resistance value (less affected by signal propagation delay) is provided. A MOSFET which cannot be realized by the MOSFET structure can be easily obtained.
Since this manufacturing procedure does not require a long-time over-etching by dry etching, the source / drain region is not damaged when this manufacturing procedure is used. Further, when performing the dry etching, the gate electrode is not damaged at all because the PSG film is formed on the gate polysilicon.

<Second Embodiment> In the second embodiment, a MOSFET is manufactured by using a material different from that of the first embodiment for forming the second sidewall. Hereinafter, the structure and the manufacturing procedure of the MOSFET according to the second embodiment will be described with reference to FIG.
Since the procedure up to the formation of the first sidewall is the same as that of the first embodiment, the description will be omitted.

After the formation of the first sidewall (see FIG. 2E), in the present embodiment, the second sidewall 19 is
(Boro-silicate glass) (FIG. 5)
(F)). Then, after the formation of the second sidewall 19, etching with 1% hydrofluoric acid (HF) is performed as in the first embodiment. As shown in FIG. 4, since the etching rate of PSG with respect to HF is higher than that of BSG, this process also selectively removes the PSG film 16 on the polysilicon 17 and the upper portions of the sidewalls 18. Etching is performed to form the structure shown in FIG.

Therefore, as shown in FIGS. 6 (H) to 6 (I), thereafter, as in the first embodiment, selective growth of silicon 21, deposition of titanium film 22, and silicidation by annealing are performed. Has a gate length of approximately 0.2 μm and a gate electrode having a low resistance value.
An FET is formed.

<Modifications> The manufacturing procedure shown in each of the above embodiments can be modified in various ways. For example, combinations of materials that can be used to form the first sidewall and the second sidewall are PSG and NSG, and PSG and BS.
The combination is not limited to G, and any combination of materials that can selectively etch the first sidewall can be used. For example, the first sidewall is formed by BPSG (boro-phospho-s
ilicate glass) and the second sidewall is
It may be formed from NSG or BSG (boro-silicate glass). Note that, also in this case, hydrofluoric acid can be used as the etching solution. Further, the material of the film to be formed on the polysilicon 17 may be different from the material of the first sidewall.

Further, an oxide is used for forming the first sidewall and a nitride is used for forming the second sidewall, and the etching is performed under the condition that the oxide is selectively etched, so that FIG. ) May be formed.

Although the manufacturing process is complicated, the formation of the second sidewall can be performed using a resist pattern. In each of the embodiments, a gate electrode having titanium silicide is formed. However, the present invention is not limited to titanium, and tungsten (W), molybdenum (Mo), tantalum (Ta), platinum (Pt), cobalt (Co), Naturally, the present technology may be applied to form a gate electrode having a silicide of another metal such as nickel (Ni). Further, it goes without saying that the film thickness and the forming method of each film formed in the manufacture of the MOSFET are not limited to those described above.

[0043]

According to the MOSFET of the present invention, the gate electrode has a shorter length in the channel direction on the side of the silicide layer than the length in the channel direction on the side of the semiconductor substrate. In addition, the device functions as a device that is less affected by signal radio wave delay due to the resistance value of the gate electrode. According to the method for manufacturing a MOSFET of the present invention, the above-described MOSFET can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a manufacturing procedure of the MOSFET according to the first embodiment of the present invention.

FIG. 3 is a process chart showing a manufacturing procedure of the MOSFET according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the etch rates of various silicate glasses with 5% HF.

FIG. 5 is a process chart showing a procedure for manufacturing a MOSFET according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the structure of a conventional MOSFET having a gate electrode of a polysilicide structure.

FIG. 7 shows a MOSFE described in Japanese Patent Application Laid-Open No. 7-45823.
FIG. 4 is a process chart showing a manufacturing procedure of T.

FIG. 8 is a diagram showing the relationship between the gate length of a gate electrode and the sheet resistance of titanium silicide.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Single crystal silicon substrate 12 Element isolation region 13 Silicon oxide film 14, 17, 24 Polysilicon 18 First sidewall 19 Second sidewall 20 Gate oxide film 22 Titanium 23, 23 'Silicide

Claims (7)

[Claims] 1. A MOSFET provided with a gate electrode having a silicide layer on its surface, wherein a cross section of the gate electrode in a source / drain direction has a semiconductor substrate having a length in a channel direction on a silicide layer side. A MOSFET having a shape longer than a length in a channel direction on a side of the MOSFET. 2. A gate electrode having a silicide layer on its surface, wherein a length of the silicide layer in the channel direction is longer than a length of the semiconductor substrate in the channel direction.
And a gate electrode having a substantially constant length in a channel direction at a lower portion which is a portion from the semiconductor substrate side to a predetermined height, and the lower side surface of the gate electrode is in contact with the side surface, and the height is substantially A first sidewall having a predetermined height, a part of a side surface of a portion different from the lower portion of the gate electrode, and a second sidewall in which the side surface of the first sidewall is in contact with the side surface; A MOSFET, comprising: 3. A method of manufacturing a MOSFET having a gate electrode having a silicide layer on a surface thereof, wherein a gate for forming a gate electrode structure in which a gate oxide film and a gate electrode element made of silicon are laminated on a semiconductor substrate. An electrode structure forming step; a first sidewall forming step of forming a first sidewall on a side surface of the gate electrode structure formed in the gate electrode structure forming step; and a first sidewall forming step. A second side wall forming step of forming a second side wall having a height higher than the first side wall from the semiconductor substrate on the side surface of the formed first side wall; and a second side wall forming step. A silicon deposition step of depositing silicon in a portion sandwiched between the second sidewalls, and a deposition step in the silicon deposition step. MOS including the silicide formation step of forming a silicide surface layer of silicon
Manufacturing method of FET. 4. A method for manufacturing a MOSFET provided with a gate electrode having a silicide layer on its surface, wherein a first material is a layer made of a gate oxide element and a gate electrode element made of silicon and a first material on a semiconductor substrate. A gate electrode structure forming step of forming a gate electrode structure in which layers are stacked, and a first sidewall made of the first material on a side surface of the gate electrode structure formed in the gate electrode structure forming step. Forming a first sidewall, and forming a second sidewall made of a second material different from the first material on a side surface of the first sidewall formed in the first sidewall forming step. A sidewall forming step, wherein the etching rate for the first material is higher than the etching rate for the second material;
Removing the first material layer provided on the gate electrode element and a part of the first sidewall by etching the semiconductor substrate on which the second sidewall is formed in the sidewall forming step; A MOS including a silicon deposition step of depositing silicon on a portion where the first material has been removed by the removal step, and a silicide formation step of forming silicide on a surface layer of silicon deposited in the silicon deposition step
Manufacturing method of FET. 5. The method according to claim 4, wherein the first material and the second material are PSG and NSG, respectively, and the removing step is a step of performing etching using hydrofluoric acid. MOSF described
ET manufacturing method. 6. The method according to claim 5, wherein the first material and the second material are PSG and BSG, respectively, and the removing step is a step of performing etching using hydrofluoric acid. MOSF described
ET manufacturing method. 7. The method of manufacturing a MOSFET according to claim 4, wherein said silicon deposition step is a step of depositing silicon under conditions for selectively growing silicon.