JPH10335606A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where a memory part and a logic part are mixedly mounted, wherein optimal manufacturing conditions under which the memory part and the logic part are manufactured are realized, and a photomask cost can be lessened. SOLUTION: A memory part 2 and a logic part 3 are so arranged as be spaced from each other by an isolation region 4 and connected together with a wiring to form a semiconductor device 1. A first photomask which is used in an exposure process to form the logic part 3 shielding the memory part 2 and a second photomask which is used in a exposure process from light to form the memory part 2 shielding the logic part 3 from light are prepared. Resist is applied onto a semiconductor substrate and then subjected to an exposure process under optimal conditions using the first and the second photomask, and then the semiconductor substrate is subjected to etching, and the resist is removed from the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which a large-capacity memory such as a DRAM and a logic product such as a microprocessor or an ASIC are integrated on a semiconductor substrate, a photomask for manufacturing the semiconductor device, and the photomask. And a method of manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, general-purpose DRAMs, general-purpose synchronous DRAMs, microprocessors and ASs have been developed.
A system composed of an IC or the like is integrated on a single chip. In the following, a general-purpose DRAM or a general-purpose synchronous DRAM is referred to as a DRAM. Microprocessors and ASICs are called logic. Integrating a system including a DRAM and a logic on a single chip is referred to as mixed mounting. By integrating the DRAM and the logic on a single chip, an improvement in the data transfer speed between the DRAM and the logic and a reduction in power consumption are realized.

A conventional hybrid semiconductor device and a method of manufacturing the same will be described with reference to FIGS.
FIG. 20 shows a schematic layout of a conventional hybrid semiconductor device. The mixed semiconductor device 1 ′
It has a DRAM block 2 'and a logic block 3' other than the DRAM arranged around the DRAM block 2 '. FIG. 21 schematically shows a photomask used for exposure. This photomask is a quartz glass 1 of a predetermined size.
A chromium-based material is vapor-deposited on the light-shielding portion according to various data. The data section 107 is an area where data of the semiconductor device is arranged. The frame data 108 section is an area in which frame data for shielding the periphery of the area corresponding to the logic block 3 'is arranged. The first alignment pattern 109 is used for positioning the photomask and the exposure apparatus. The second alignment pattern 110 is used for alignment between photomasks. However, photomasks are required in the number of mask steps according to the layout data of the semiconductor device 1 '.

[0004] Frame data 108, first alignment pattern 109, second alignment pattern 11
The size 0, the quartz glass 100 are not directly related to the function of the semiconductor device 1 ′, and the size, shape, and arrangement position are defined according to the specifications of the exposure apparatus to be used. Further, since the reduced projection exposure is performed, the size of the data 107 is formed to be five times the size of the semiconductor device 1 ′.
/ 5 is subjected to reduced projection exposure. FIG. 21 shows a case where data for two chips is arranged on a photomask.
The number of chips arranged on the photomask is determined according to the performance of the exposure apparatus and the chip size.

FIG. 22 schematically shows a process flow in a process of manufacturing a mixed semiconductor device. This process flow includes a transistor forming step, a capacitance forming step, and a wiring forming step. Among these steps, the capacitance forming step is a step performed for high integration of the memory cell region, and is called a stack type and is a step peculiar to DRAM.

FIGS. 23 and 24 show cross-sectional views of typical steps of a DRAM block and a logic block, taking a first-layer wiring forming step as an example. In this process sectional view, the semiconductor substrate 201, the diffusion layer 202, the gate electrode 2
03, polycide bit line 204, capacitance electrode pair 20
5, 206, interlayer film 207, contact hole 208,
A metal 209 deposited on the entire main surface of the semiconductor substrate and a resist 210 applied on the entire main surface of the semiconductor substrate are included. The shaded portion of the photomask 304 for the wiring forming step indicates a light shielding region. As shown in FIG. 23, the exposure apparatus performs photomask 3 irradiation with light 300 having a predetermined wavelength.
Then, the resist 210 is exposed using the light emitting element 04. After exposure by the exposure device, resist development, metal etching, and resist removal are performed to form a metal wiring 211 as shown in FIG.

[0007]

In general, in order to form a fine pattern, it is necessary to focus the exposure apparatus on a register applied to a semiconductor substrate when exposing by an exposure apparatus. However, in the wiring forming step shown in FIG. 23, a large step having a height h (FIG. 23) exists between the memory cell region of the DRAM block and the other region, and DR
It was impossible to simultaneously focus the exposure on both the AM block and the logic block. For this reason, the wiring rule of the metal wiring (the metal wiring pitch L in FIG. 24) has to be made looser than the miniaturization ability defined by the performance of the exposure apparatus and the like. Therefore, this has led to a major problem that the integration degree of a logic block that uses many metal wirings cannot be increased.

In addition, variations and defects in the pattern of the photomask are directly reflected on the pattern of the semiconductor device. For this reason, very high-precision photomasks are required for large-capacity DRAMs with advanced miniaturization. In addition, there is a process that requires a special photomask such as a phase shift mask to perform miniaturization. Generally, such photomasks are very expensive. In a mixed semiconductor device, the specification of the DRAM block is limited, but the specification of the logic block differs depending on the application and customer.
Mixed semiconductor devices are products that produce a large number of products in small quantities. For this reason, in the mixed semiconductor device, it is necessary to prepare an expensive photomask for each type in all processes including the capacitance forming process, which has caused a remarkable increase in cost.

Further, since the DRAM block has a large capacity, the data constituting the layout data of the semiconductor device 101 is enormous. Therefore, the layout data is
There has been a problem that the time required for conversion to format data for a photomask manufacturing apparatus and the time required for manufacturing a photomask are increased, and the time required for a development period is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that do not increase the development cost while increasing the degree of integration of the mixed semiconductor device.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A memory block having a memory cell for writing to and reading from the memory cell, a logic block arranged at an interval from the memory block to control the memory block, the memory block and the logic And a signal line connected to the block. By providing an interval between the memory block and the logic block, the influence of the noise of the memory block on the logic block and the influence of the noise of the logic block on the memory block can be reduced.

A photomask group according to the present invention includes a first photomask for forming the memory block regardless of the size of the semiconductor device, regardless of the size of the semiconductor device, and a size of the semiconductor device. A second photomask for shading the memory block arrangement area to form the logic block, and a light shielding area for the memory block in relation to the size of the semiconductor device; The third that does not shade
A photomask. By preparing the photomask group as described above, the semiconductor device can be highly integrated, and the semiconductor device can be manufactured without increasing the development cost.

According to the method of manufacturing a semiconductor device of the present invention, after a resist is applied to a main surface of a semiconductor substrate, the resist is exposed using the first photomask, and the resist is exposed using the second photomask. Exposing the resist to light, and then developing the resist. In each of the memory block and the logic block, exposure can be performed with an optimum exposure focus.

According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: applying a resist to a main surface of a semiconductor substrate, exposing the resist using the first photomask; And then exposing the resist to light, and then developing the resist. In each of the memory block and the logic block, exposure can be performed with an optimum exposure focus.

Still another invention of a method for manufacturing a semiconductor device includes a step of exposing the resist using the first photomask and a step of exposing the resist using the second photomask. The photomask used in the process is exposed with an optimum exposure focus. In each of the memory block and the logic block, the resist is exposed at an optimum exposure focus, so that the semiconductor device can be highly integrated.

Still another invention of a method for manufacturing a semiconductor device includes a step of exposing the resist using the first photomask and a step of exposing the resist using the third photomask. The photomask used in the process is exposed with an optimum exposure focus. In each of the memory block and the logic block, the resist is exposed at an optimum exposure focus, so that the semiconductor device can be highly integrated.

Still another invention of a method of manufacturing a semiconductor device, wherein the memory block and the logic block are constituted by different pattern formation rules, wherein the step of exposing the resist using the first photomask and the step of exposing the resist are performed. In the step of exposing the resist using the photomask described above, the photomask used in each step is exposed with an optimal exposure focus. In each of the memory block and the logic block, the resist is exposed at an optimum exposure focus, so that the semiconductor device can be highly integrated.

Another invention of a photomask group is characterized in that at least one of the first photomask and the second photomask, in which the signal line is formed, has a predetermined width of the signal line. And a portion wider than the width obtained by adding the mask alignment accuracy of the photomask and the second photomask. By configuring the photomask as described above,
A signal line having a desired width can be formed.

Still another invention of a photomask group includes a boundary line between a region of the first photomask that blocks light except for the memory block, and a boundary line of a region of the second photomask that blocks light from the memory block. Are not the same.
By configuring the photomask as described above, a short circuit between signal lines can be prevented.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. << Embodiment 1 >> A semiconductor device and a manufacturing apparatus thereof according to Embodiment 1 of the present invention will be described with reference to FIGS. <Structure> FIG. 1 schematically shows a layout of a semiconductor device according to the first embodiment. Mixed semiconductor device 1
Are the DRAM block 2, the logic block 3, and the D
It has a separation band 4 having a predetermined width for separating the RAM block 2 and the logic block 3, and a metal wiring 5 connecting the DRAM block 2 and the logic block 3. The chip size of the semiconductor device 1 is Lx in the X direction and Ly in the Y direction. The DRAM block 2 includes a memory cell array having a predetermined capacity, a decoder, a sense amplifier, and a control circuit therefor.

FIG. 2 schematically shows a terminal specification diagram of the DRAM block 2. The DRAM block 2 includes a power supply, a ground, an address signal, an input signal, an output signal (hereinafter, the input signal and the output signal are collectively referred to as an I / O signal), a DR
The configuration is controlled by an AM control signal. These signals are input from the logic block 3 via the metal wiring 5 and output via the metal wiring 5. For example, 128
Bit output configuration In the case of 16 Mbit DRAM, DRAM
Block 2 has 17 address signal terminals and 128
Approximately 150 terminals including terminals for I / O signals are provided. In this case, 150 metal wires 5 are provided. The process of manufacturing this semiconductor device is the same as the conventional process shown in FIG. DRAM block 2
Is a configuration formed by a transistor forming step, a capacitance forming step, and a wiring forming step. The logic block 3 has a configuration formed by a transistor forming step and a wiring forming step.

<Photomask> As photomasks, there are a photomask for patterning the logic block 3 and a photomask for patterning the DRAM block 2. Details of these photomasks will be described below. . FIG. 3 schematically shows a photomask (hereinafter, referred to as a logic mask) for forming a pattern of the logic block 3. In this logic mask, data for two chips is arranged on a quartz glass 100 having a predetermined size. Have been. The DRAM block unit 101
This is an area where data for shielding the area corresponding to the DRAM block 3, the separation band 4, and the metal wiring 5 is arranged. The logic block unit 102 is an area where logic block data is arranged. Frame data section 106
Is an area where frame data for shielding the area corresponding to the periphery of the logic block 2 is arranged. The first alignment pattern 103 is used for aligning the logic mask with the exposure apparatus. The second alignment pattern 104 is used for alignment between logic masks.

Further, the DRAM block unit 101 will be described. The area inside the broken line 101a is the area corresponding to the DRAM block 3, and the area outside the broken line 101a is the area corresponding to the separation band 4 and the metal wiring 5.
The third alignment pattern 105 is used for masking a logic mask on a DRAM block. Note that the broken line 101a is shown for the sake of explanation, and does not mean that a dotted line pattern exists in the logic mask. The same applies to FIGS. 5 and 19. The frame data section 106, the first alignment pattern 103, and the second alignment pattern 104 are arranged according to the same arrangement rule as the conventional example (FIG. 21). The number of logic masks is required by the number of mask steps in the transistor formation step and the wiring formation step.

FIG. 4 schematically shows a photomask (hereinafter referred to as a DRAM mask) for forming a pattern in the DRAM block 2. In this DRAM mask, data for one chip is arranged on quartz glass 100 of a predetermined size. The DRAM block 107 is a DRAM
This is an area in which data for a block is arranged. In the DRAM mask used in the metal process, the separation band portion 108 is a region where wiring data for connecting the DRAM block and the logic block is arranged. However, the separation band portion 108 is formed by a DRA used in a process other than the metal process.
In the M mask, according to the rules on the process and the device,
Light-shielded or transmitted data is arranged. The frame data section 106a is an area in which frame data that shields an area corresponding to the periphery of the separation band 4 is arranged. The first alignment pattern 103a is used for aligning a DRAM mask with an exposure apparatus. The second alignment pattern 104a is used for alignment between DRAM masks. The third alignment pattern 105a corresponds to the third alignment pattern 105 of the logic mask, and is used for masking the logic block with the DRAM mask. The frame data section 106a, the first alignment pattern 103a, and the second alignment pattern 104a are arranged according to the same arrangement rule as in the conventional example (FIG. 21). The number of DRAM masks is required as many as the number of mask steps in the transistor forming step, the wiring forming step, and the capacitance forming step.

FIG. 5 shows that the logic block 102a
A photomask in which data for a logic block is not arranged (hereinafter, referred to as a logic auxiliary mask) is shown. The configuration other than the logic block unit 102a is as follows.
This is the same as the logic mask. The logic auxiliary mask is
It is used to remove the deposited layer in the logic block region from the deposited layers deposited in each step in the capacitance forming step. The logic auxiliary mask can be shared by one logic auxiliary mask in each capacitance forming step.

<Manufacturing Method> A method of manufacturing a semiconductor device using the photomasks of FIGS. 3 to 5 will be described below. [Transistor forming step and wiring forming step] The transistor forming step and the wiring forming step will be described. FIG. 6 shows manufacturing steps for a transistor forming step and a wiring forming step. In this manufacturing process, a logic mask and a DRAM mask are used. A resist is applied to the entire main surface of the semiconductor substrate (step S061). The alignment between the logic mask and the exposure apparatus is the first of the logic masks.
Is performed by the same method as the conventional method using the alignment pattern 103 of FIG. The alignment of the logic block is performed by the second alignment pattern 10 of the logic mask.
4 is performed. The alignment of the logic block is corrected using the third alignment pattern 105 of the logic mask as needed. The resist applied to the entire main surface of the semiconductor substrate is exposed using a logic mask at a pitch of Lx in the X direction and (2 × Ly) in the Y direction (step S062).

The alignment between the DRAM mask and the exposure apparatus is performed by the first alignment pattern 10 of the DRAM mask.
3a, using the same method as in the prior art. DRA
The alignment of the M blocks is performed using the second alignment pattern 104a of the DRAM mask. Note that the alignment of the DRAM block is corrected using the third alignment pattern 105a of the DRAM mask as needed. The resist applied on the entire main surface of the semiconductor substrate is exposed using a DRAM mask at a pitch of the chip size of the semiconductor device, that is, at a pitch of Lx in the X direction and a pitch of Ly in the Y direction (step S063). In addition, only the alignment of the DRAM block in the first mask process,
The determination is performed based on the information on the relative positional relationship of the DRAM block 2 with respect to the logic block 3 that is known at the design stage of the semiconductor device 1. Resist development (step S064), etching (step S065), and resist removal (step S064)
066) is performed to form a resist pattern.

The above-described transistor forming step and wiring forming step will be described focusing on exposure performed using a logic mask and a DRAM mask, taking a first-layer wiring forming step as an example. 7, 8, and 9 show cross-sectional views of a first layer wiring process at typical locations of a DRAM block and a logic block. This process sectional view includes a semiconductor substrate 201, a diffusion layer 202, a gate electrode 203, a polycide bit line 204, a pair of capacitance electrodes 205 and 20.
6, interlayer film 207, contact hole 208, metal 209 deposited on the entire main surface of the semiconductor substrate, resist 210 applied on the entire main surface of the semiconductor substrate, metal wiring 21
1 is included. Logic mask 30 for metal process
1 and the shaded portion of the DRAM mask 302 indicate a light shielding area.

As shown in FIG. 7, the exposure apparatus exposes a resist 210 with light 300 having a predetermined wavelength using a logic mask 301. Here, since the logic block is formed only of a region having a small step between the transistor and the wiring, the exposure focus of the exposure apparatus is set to the logic block having a small step. Therefore, a finer wiring pattern (metal wiring pitch L1 in FIG. 7) can be formed as compared with the related art. Note that the DRAM block is not exposed. As shown in FIG. 8, the exposure apparatus exposes a resist 210 with light 300 having a predetermined wavelength using a DRAM mask 302. In the DRAM block 2, a region having a high step to form a capacitance and a region having a low step to form a transistor such as a sense amplifier and a wiring are mixed. Therefore, DRA
The wiring pattern of the M block (the metal wiring pitch L in FIG. 8)
2) is the same wiring pattern as before. The logic block 3 is not exposed because it is outside the exposure area of the DRAM mask. Thereafter, resist development, metal etching, and resist removal are performed to form a metal wiring 211 as shown in FIG.

[Capacitance Forming Step] The capacitance forming step will be described. FIG. 10 shows a manufacturing process for the capacitance forming process. In this manufacturing process, a logic auxiliary mask and a DRAM mask are used. A resist is applied to the entire main surface of the semiconductor substrate (step S10).
1). The alignment between the logic mask and the exposure apparatus is performed using the first alignment pattern 103 of the logic mask in the same manner as in the related art. The alignment of the logic block is performed using the second alignment pattern 104 of the logic auxiliary mask. The alignment of the logic block is corrected using the third alignment pattern 105 of the logic auxiliary mask as needed. The resist applied on the entire main surface of the semiconductor substrate is exposed at a pitch of Lx in the X direction and (2 × Ly) in the Y direction using a logic auxiliary mask (step S102).

The alignment between the DRAM mask and the exposure apparatus is performed by the first alignment pattern 10 of the DRAM mask.
3a, using the same method as in the prior art. DRA
The alignment of the M blocks is performed using the second alignment pattern 104a of the DRAM mask. Note that the alignment of the logic block is corrected using the third alignment pattern 105a of the DRAM mask as necessary. The resist applied to the entire main surface of the semiconductor substrate is exposed using a DRAM mask at a pitch of the chip size of the semiconductor device, that is, at a pitch of Lx in the X direction and a pitch of Ly in the Y direction (step S103). Resist development (Step S104), etching (Step S105), and resist removal (Step S106) are performed to form a resist pattern.

The above-described capacitance forming process will be described mainly on exposure performed using a logic auxiliary mask and a DRAM mask, taking formation of a polycide bit line as an example. 11, 12, and 13 show process cross-sectional views of forming a polycide bit line at typical locations of a DRAM block and a logic block. This process sectional view includes a semiconductor substrate 201, a diffusion layer 202, and a gate electrode 20.
3. Polycide 20 entirely deposited on the main surface of the semiconductor substrate
4a, resist 21 applied to the entire main surface of the semiconductor substrate
0, and a polycide bit line 204. The shaded portions of the logic auxiliary mask 303 and the DRAM mask 302a indicate light-shielding regions. As shown in FIG. 11, the exposure apparatus exposes the resist 210 with light 300 having a predetermined wavelength using the logic auxiliary mask 303.
However, the DRAM block 2 is not exposed. FIG.
As shown in the figure, the exposure apparatus is a DRA for the polycide process.
The resist 210 is exposed to light 300 having a predetermined wavelength using the M mask 14. However, the logic block is D
Since it is outside the exposure area of the RAM mask, it is not exposed.
Thereafter, resist development, polycide etching, and resist removal are performed to form a polycide bit line 204 as shown in FIG.

[Wiring Method] The wiring method of the metal wiring 5 connecting the DRAM block 2 and the logic block 3 will be described with reference to FIGS. FIG. 14 shows a DRAM
The respective shapes near the boundary region between the mask and the logic mask are shown. The DRAM mask has linear wiring patterns Da1 and Db1 having a certain width. The logic mask has linear wiring patterns La1 and Lb1 having a fixed width.

Hereinafter, the shape of the wiring formed using the DRAM mask and the logic mask shown in FIG. 14 will be described. DRAM for alignment position of logic mask
If the alignment position of the mask is not shifted, wiring a and b
Are formed as linear wirings having a desired width (FIG. 15A). However, logic mask and DRA
The following problems occur depending on the positional relationship of the M mask. When the alignment position of the DRAM mask is shifted by a distance X in the right direction in FIG. 14 with respect to the alignment position of the logic mask, the wirings a and b cannot have a desired width in the boundary region (see FIG. b)). The alignment position of the DRAM mask with respect to the alignment position of the logic mask
In FIG. 14, when the distance Y is shifted upward, a region not exposed in the logic mask process and the DRAM mask process occurs in the boundary region, and the wires a and b are short-circuited (FIG. 15C). DRA for alignment position of logic mask
When the alignment position of the M mask is shifted downward by a distance Y in FIG. 14, exposure is performed twice in the logic mask step and the DRAM mask step near the boundary area other than the wiring section on the logic block side. For this reason, the wirings a and b cannot have a predetermined width near the boundary region (FIG. 15D). As described above, when the DRAM mask and the logic mask shown in FIG. 14 are used, a desired wiring cannot be formed with the current mask alignment accuracy. In addition,
When the accuracy of mask alignment is improved, D shown in FIG.
Even if a RAM mask and a logic mask are used, a desired wiring can be formed.

The shapes of the DRAM mask and the logic mask for solving the above problem will be described with reference to FIGS. The DRAM mask has a length (Y1 + Y
Area 2) includes wiring patterns Da2 and Db2 having a portion having a width (2 × X1) wider than a desired wiring width and a portion having a desired wiring width. Light-shielded area of DRAM mask (that is, frame data 106a of DRAM mask)
Is retracted by a distance Y2 from the boundary line. The logic mask has linear wiring patterns La2 and Lb2 having a fixed width as in the case of FIG.

DRA for the alignment position of the logic mask
When the alignment position of the M mask is not shifted, the wirings a and b are formed as wirings each having a desired wiring width (FIG. 17A). When the alignment position of the DRAM mask is shifted rightward in FIG. 16 by a distance X (X1 or less) with respect to the alignment position of the logic mask, the wirings a and b
Can secure a desired wiring width even in the boundary region (FIG. 17B). When the alignment position of the DRAM mask is shifted upward by a distance Y (Y2 or less) in FIG. 16 with respect to the alignment position of the logic mask, the wirings a and b are short-circuited as shown in FIG. No (FIG. 17 (c)). When the alignment position of the DRAM mask is shifted downward Y (Y1 or less) in FIG. 16 with respect to the alignment position of the logic mask, there is no area exposed twice in the logic mask process and the DRAM mask process, and the wiring a And b can secure a desired wiring width (FIG. 17D). Therefore, in the semiconductor device, the logic mask, and the DRAM mask, if the widths of X1, Y2 and the separation band are set to δ or more and Y1 is set to (δ + the minimum line width of the wiring) or more, the logic mask and the DRAM of FIG.
The problem in the case of using a mask can be solved.
In addition, δ indicates a mask misalignment of the DRAM mask relative to the logic mask.

The alignment of the DRAM block 2 is D
This is performed only in the DRAM block 2 using the second alignment pattern 104b of the RAM mask. For this reason,
The deviation of the mask alignment between the layers of the DRAM block 2 is very small. Usually, the misalignment of the mask is
It is 0.1 μm to 0.2 μm or less. The alignment of the logic block 3 is performed only by the logic block 3 using the second alignment pattern 104 of the logic mask 3. For this reason, the misalignment of the mask between the layers of the logic block 3 is very small. Normal,
The misalignment of the mask is 0.1 μm to 0.2 μm or less. The alignment of the DRAM block 2 with respect to the logic block 3 is performed in the first step.
Is performed based on the information on the relative positional relationship of the DRAM block 2 with respect to. In this case, the misalignment of the mask
It depends on the mechanical accuracy of the exposure apparatus and is larger than the misalignment of the mask between the layers. Usually, the deviation of mask alignment due to the mechanical accuracy of the exposure apparatus is about 1 μm.

DRAM block 2 and logic block 3
Are connected by a metal wiring 5, and in other areas, a separation band 4 is provided, and a DRAM block 2 and a logic block 3 are provided.
Are separated. For this reason, regarding the mutual relationship between the DRAM block 2 and the logic block 3, only the connection of the metal wiring 5 may be considered. If the length of one side of the DRAM block 2 is 5 mm, 150 metal wires 5 may be arranged at a pitch of about 30 μm. Since the misalignment of the mask is about 1 μm or less, FIG.
The values of X1, Y1 and Y2 in the DRAM mask of
The value can be set with a sufficient margin without increasing the size of the semiconductor device 1 almost.

As described above, by preparing a photomask group of the DRAM mask, the logic mask, and the logic auxiliary mask, the DRAM block 2 and the logic block 3 can be exposed and formed under optimum exposure conditions. Therefore, the degree of integration of the semiconductor device can be increased. By fabricating a DRAM mask and a logic mask as shown in FIG. 16, a metal wiring 5 having a predetermined width can be formed. In addition, a short circuit of each metal wiring 5 can be prevented.

Embodiment 2 A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIGS.
FIG. 18 schematically illustrates a layout of the semiconductor device according to the second embodiment. The mixed semiconductor device 1a has a D
RAM block 2a, logic block 3a, DR
It has a separation band 4a having a predetermined width for separating the AM block 2a and the logic block 3a, and a metal wiring 5a for connecting the DRAM block 2a and the logic block 3a. Here, the logic block 3a differs from the semiconductor device 1 in the first embodiment in the content of the logic. For this reason, the sizes of the semiconductor device 1 in the first embodiment and the semiconductor device 1a in the second embodiment are different.

A photomask used for exposing the semiconductor device 1a shown in FIG. 18 will be described. FIG. 19 schematically shows a logic mask for pattern-forming the logic block 3a. In the logic mask, data for one chip is arranged on a quartz glass 100 of a predetermined size. The description of the logic mask in FIG. 3 is omitted except for the arrangement of data of one chip, except for the data of one chip. The logic auxiliary mask is shown in FIG.
In the logic mask of FIG.
2 is a photomask in which data for a logic block is not arranged. The photomasks required for manufacturing the semiconductor device 1a are the same number of logic masks and one logic auxiliary mask as the number of mask steps in the transistor formation step and the wiring formation step. The DRAM mask is
The one used for manufacturing the semiconductor device 1 can be used. If the information on the relative positional relationship of the DRAM block with respect to the logic block is changed in the mask alignment of the DRAM block, the semiconductor device 1a can be manufactured by the manufacturing method described in the first embodiment. As described above, since the DRAM mask and the logic mask in the mask steps other than the transistor forming step and the wiring forming step can be shared, development costs and manufacturing costs can be reduced.

The semiconductor device according to the first and second embodiments is provided with a separator separating the logic block and the DRAM block. Therefore, it is possible to reduce the influence of noise generated in the logic block on the DRAM block. Similarly, the effect of noise generated in the DRAM block on the logic block can be reduced. If no separation band is provided between the logic block and the DRAM block, the DRAM block has a higher level difference than the logic block. Therefore, exposure must be performed in consideration of the level difference at the boundary between the DRAM block and the DRAM block. However, by providing the separation band, the resist can be exposed to each of the DRAM block and the logic block under optimal exposure conditions without considering the steps. By providing the separation band, the alignment between the logic block and the DRAM block only needs to consider the connection of the metal wiring, and the alignment between the logic block and the DRAM block becomes easy. The area of the separation band can also be used as an arrangement area of the alignment pattern.

In the above embodiment, a DRAM mask and a logic mask were prepared for all mask steps. However, for example, a DRAM mask and a logic mask may be prepared only in a part of a mask process such as a capacitance forming process or a wiring forming process. In the above embodiment, one DRA is connected to one semiconductor device.
Although the case where M blocks are arranged, the case where two or more DRAM blocks are arranged in a semiconductor device may be adopted.
In the above embodiment, after the exposure using the logic mask, the exposure is performed using the DRAM mask. However, after the exposure using the DRAM mask, the exposure is performed using the logic mask. Is also good. In the above embodiment, a region wider than the wiring width is provided on the DRAM mask side in order to form the wiring. However, a region wider than the wiring width may be provided on the logic mask. Alternatively, a region wider than the wiring width may be provided in the DRAM mask and the logic mask.

In the above embodiment, the second alignment pattern of the DRAM mask is arranged in a region corresponding to the separation band. However, the second alignment pattern of the DRAM mask may be arranged in a region corresponding to the DRAM block so that the width of the separation band is not limited by the second alignment pattern. In the above embodiment, the separation band is arranged on the DRAM block side. However, the separation band may be arranged on the logic block side.
It may be arranged on the RAM block side and the logic block side. Further, for example, a pattern for process monitoring or the like may be arranged in the region of the separation band. The above embodiment is a semiconductor device in which a stacked DRAM and a logic are mixed. However, a semiconductor device mixed with a trench type DRAM may be used, and a flash type EEPROM may be used.
The semiconductor device may be a semiconductor device mixed with an M, an ultraviolet-erasable EPROM, a ferroelectric memory, or the like.

[0045]

As described above, according to the present invention, the DRAM
Mask, logic mask, logic auxiliary mask 3
By using different types of photomasks, it is possible to expose each of the DRAM block and the logic block under optimal exposure conditions. Therefore, high integration of both the DRAM block and the logic block is possible. Further, even when a DRAM block and a logic block designed according to different design rules are mixed, the exposure conditions for forming the pattern can be optimized, and a mixed semiconductor device with a high degree of integration can be manufactured. Further, according to the present invention, the DRAM mask can be shared, and the number of photomasks and logic auxiliary masks (1
Only) may be manufactured for each semiconductor device. Therefore, a significant cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a layout of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a terminal specification diagram of the DRAM block in FIG. 1;

FIG. 3 is a diagram illustrating a logic mask according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a DRAM mask according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a logic auxiliary mask according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a transistor forming step and a wiring forming step in Embodiment 1 of the present invention.

FIG. 7 is a sectional view schematically showing a wiring forming step according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing a wiring forming step according to the first embodiment of the present invention.

FIG. 9 is a sectional view schematically showing a wiring forming step according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a capacitance forming step according to the first embodiment of the present invention.

FIG. 11 is a sectional view schematically showing a capacitance forming step according to the first embodiment of the present invention.

FIG. 12 is a sectional view schematically showing a capacitance forming step according to the first embodiment of the present invention.

FIG. 13 is a sectional view schematically showing a capacitance forming step according to the first embodiment of the present invention.

FIG. 14 is a diagram illustrating a wiring forming D according to the first embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating an example of a RAM mask and a logic mask.

FIG. 15 is a view showing a wiring formed by the DRAM mask and the logic mask shown in FIG. 14;

FIG. 16 is a diagram illustrating a wiring forming D according to the first embodiment of the present invention.
FIG. 4 is a schematic diagram showing another example of a RAM mask and a logic mask.

FIG. 17 is a diagram showing a wiring formed by the DRAM mask and the logic mask shown in FIG. 16;

FIG. 18 is a schematic diagram illustrating a layout of a semiconductor device according to a second embodiment of the present invention.

FIG. 19 is a diagram showing a logic mask according to the second embodiment of the present invention.

FIG. 20 is a schematic view showing a layout of a conventional semiconductor device.

FIG. 21 is a diagram showing a photomask of a conventional semiconductor device.

FIG. 22 is a view showing a manufacturing process of the semiconductor device;

FIG. 23 is a sectional view schematically showing a conventional metal wiring step.

FIG. 24 is a cross-sectional view schematically showing a conventional metal wiring process.

[Explanation of symbols]

 1, 1a, 1 'Semiconductor device 2, 2a, 2' DRAM block 3, 3a, 3 'Logic block 4, 4a, 4' Separator band 5, 5a, 5 'Metal wiring 100 Quartz glass 101, 107 DRAM block section 102 , 102a Logic block section 103, 103a First alignment pattern 104, 104a Second alignment pattern 105, 105a Third alignment pattern 106, 106a Frame data section 108 Separator band section 201 Semiconductor substrate 202 Diffusion layer 203 Gate electrode 204 Poly Side bit lines 205, 206 Capacitance electrode 207 Interlayer film 208 Contact hole 209 Metal 210 Resist 211 Metal wiring 301 Logic mask 302, 302a DRAM mask 303 Logic auxiliary mask 304 Photo mask 300 light

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Claims (9)

[Claims] A memory block that has a memory cell and performs writing to and reading from the memory cell; a logic block disposed at an interval from the memory block to control the memory block; A semiconductor device comprising: a memory block; and a signal line connected to the logic block. 2. A first photomask for forming the memory block irrespective of the size of the semiconductor device, irrespective of the size of the semiconductor device, and a first photomask for forming the memory block irrespective of the size of the semiconductor device. A second photomask for forming the logic block by shielding the arrangement area from light; and a third photomask which does not shield the arrangement area of the logic block and does not shield the arrangement area of the logic block in relation to the size of the semiconductor device. The photomask group for semiconductor manufacturing according to claim 1, comprising: a photomask. 3. A method of manufacturing a semiconductor device using a group of photomasks according to claim 2, wherein after applying a resist to a main surface of a semiconductor substrate, the resist is applied using the first photomask. Exposing;
Exposing the resist using the second photomask and developing the resist after two steps. 4. A method of manufacturing a semiconductor device using a group of photomasks according to claim 2, wherein after applying a resist to a main surface of a semiconductor substrate, the resist is applied using the first photomask. Exposing;
Exposing the resist using the third photomask and developing the resist after two steps. 5. An exposing step of exposing the resist using the first photomask and an exposing step of the resist using the second photomask are optimal for the photomask used in each step. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the exposure is performed at a proper exposure focus. 6. In the step of exposing the resist using the first photomask and the step of exposing the resist using the third photomask, the photomask used in each step is optimized. The method for manufacturing a semiconductor device according to claim 4, wherein exposure is performed at a proper exposure focus. 7. A step of exposing the resist using the first photomask and exposing the resist using the second photomask, wherein the memory block and the logic block are configured according to different pattern formation rules. 4. The method according to claim 3, wherein, in the step (b), a photomask used in each step is exposed at an optimum exposure focus. 5. 8. The first photomask and the second photomask, wherein at least one of the signal line forming regions has a predetermined width of the signal line and the first photomask and the second photomask have a predetermined width. The photomask group according to claim 2, wherein the photomask group has a portion wider than a width obtained by adding the mask alignment accuracy of the photomask. 9. A boundary line of a region of the first photomask that blocks light except for the memory block and a boundary line of a region of the second photomask that blocks light of the memory block are not the same. The group of photomasks according to claim 8, wherein: