JPH10335587A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which outputs plural similar or inverted signals, by allowing waveform distortions of plural outputs under effect of parasitic element sticking to wirings in a PKG(package) and on a semiconductor substrate to be almost identical. SOLUTION: A semiconductor device comprises plural circuits outputting similar or inverted signals formed on a semiconductor substrate 301. Plural wirings 103, 201, 117, 109, 202, and 118 from the output on the semiconductor substrate of a circuit to the output terminal of a package are allocated in almost axis or point symmetry about the package or the semiconductor substrate. The power source wiring from the package terminal to the circuit for supplying a power source voltage to the circuit is allocated in almost axis or point symmetry about the package or the semiconductor substrate 301. The plural wirings on a mounting substrate from the package output to a target element to which the signal is transferred are configured in axis or point symmetry about the package.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitably used for a semiconductor device which outputs a plurality of similar or inverted signals for performing high-speed or large-current switching.

[0002]

2. Description of the Related Art FIG. 7A shows a mounting state diagram of an integrated circuit, and FIG. 7B shows an equivalent circuit diagram including a parasitic element. FIG.
In (a), PMs 1 and 2 of an output stage for outputting a signal
OSFET and NMOSFET, 3 is a wiring on a semiconductor substrate, 4 is a bonding pad, 5 is a chip including an integrated circuit, 6 is a bonding wire between the chip and a lead frame, 7 is a lead frame, 8 is an external wiring of the integrated circuit, 9 is a load, 10 is a package including an integrated circuit (PK
G).

In FIG. 7B, reference numerals 11 and 12 denote inductance and resistance parasitic on wiring on a semiconductor substrate;
Reference numerals 13 and 14 denote inductance and resistance parasitic on the bonding wire, reference numerals 15 and 16 denote inductance and resistance parasitic on the lead frame, and reference numerals 17 and 18 denote inductance and resistance parasitic on the external wiring.

The operation at the time of switching with the capacitive load 23 will be examined with reference to FIG. 7C in which the equivalent circuit of FIG. Here, 19 is a power supply, 20 is a switch indicating a PMOSFET which is turned on at the time of rising, and inductance 21 is inductances 11, 13, 15, and 17.
, The resistor 22 is composed of the resistors 12, 14, 16, 18 and the PMO
This is the sum with the ON resistance of SFET1.

[0005] Assuming that the charge is q in the circuit of FIG.

L (d ² q / dt ² ) + R (dq / dt) + q / c = V _cc (1) The solution is q _s = CV _cc (2) The solution is P instead of d / dt Then, when the characteristic equation is obtained, LP ² + RP + 1 / C = 0 (3) When the two solutions of the equation (3) are P ₁ and P ₂ , P ₁ , P ₂ = − (R / 2L) ± (1 / 2L) ) · √ (R ² − (4L / C)) (4) This solution is divided into three cases according to the sizes of R, L, and C.

1) R ² -4L / C = 0 P ₁ = P ₂ = − (R / 2L) ≡−α (5) 2) R ² -4L / C> 0 P ₁ , P ₂ = − (R / 2L) ± (1 / 2L ) · √ (R 2 - (4L / C)) ≡-α ± δ (6) 3) R 2 -4L / C <0 P 1, P 2 = - (R / 2L ) for ± j (1 / 2L) · √ ((4L / C) -R 2) ≡-α ± jβ (7) above 1), the transient term q _f

[0008]

(Equation 1) So the general solution is

[0009]

(Equation 2) Assuming that t = 0, q = 0, and i = 0 as initial conditions, K
Been obtained is _1, K ₂ constants

[0010]

(Equation 3) Therefore, the voltage V _load generated at the _load is as shown in equation (12).

[0011]

(Equation 4) In the case of 2), the transient term q _f is obtained by using P ₁ and P ₂ in the equation (6).

[0012]

(Equation 5) Thus the general solution for charge q and current i is

[0013]

(Equation 6) Using the initial conditions of q = 0 and i = 0 at t = 0, K ₁ ,
K ₁ = K ₂ is been determined _{(P 2 C · V cc)} / (P 1 -P 2) = - (α + δ) / (2δ) · C · V cc (16) K 2 = - (P 1 C · V _cc ) / (P ₁ −P ₂ ) = (α−δ) / (2δ) · C · V _cc (17) Substituting these into equation (14)

[0014]

(Equation 7) In the case of 3), the transient term q _f is calculated by using P ₁ and P ₂ in equation (7).

[0015]

(Equation 8) When a general solution is obtained under the same initial conditions as in 2),

[0016]

(Equation 9) Becomes

FIG. 8 is a schematic diagram of the waveform of V _load in the cases 1) to 3). FIG. 8A shows the above 1) (R ² -4L / C
= 0), and FIG. 8 (b) shows the waveform in the above 2) (R ² -4).
L / C> 0), and FIG.
² shows a waveform in the case of -4L / C <0). The above 1) shown in FIG. 8A becomes a critical point and converges fastest.
The above 2) shown in (b) converges gently, and FIG.
3) described above results in damped vibration. As described above, LCR
, The voltage generated at the load changes greatly.

Such an effect of the parasitic element becomes remarkable at the time of high-speed operation and switching of a large current because the back electromotive force due to the parasitic inductance becomes L · (di / dt). Since the effect of the parasitic cannot be reduced to zero, the output waveform overshoots or becomes dull due to the values of L, C, and R and deviates from the ideal waveform.

[0019]

However, FIG.
Since the values of the parasitic inductance and the parasitic resistance in (b) vary depending on the shape such as the length and width of the wiring, a similar waveform or an inverted waveform such as a shift register driving pulse or a CCD driving pulse is required. When a signal is supplied to a device, simply by arranging and wiring a plurality of output circuits on a semiconductor substrate, even if the configuration of the plurality of output circuits is the same, the waveform transmitted to the drive target is not limited to the semiconductor substrate. There is a drawback that delay, duty, rise time, fall time, and the like are different due to the difference in the shape of the wiring, the bonding wire, and the lead frame. For this reason, there arises a problem that a device to be driven malfunctions or characteristics are deteriorated.

It is an object of the present invention to provide a wiring and a P on a semiconductor substrate.
It is an object of the present invention to provide a semiconductor device in which waveforms of a plurality of outputs have substantially the same distortion due to the influence of a parasitic element attached to a wiring in a KG (package) and output a plurality of similar or inverted signals.

Another object of the present invention is to provide a circuit type in which the fluctuation of the power supply voltage due to the influence of the parasitic element attached to the wiring on the semiconductor substrate and the wiring in the PKG is substantially the same, and the output voltage depends on the power supply voltage. Another object is to provide a semiconductor device that outputs a plurality of similar or inverted signals.

A further object of the present invention is to provide a semiconductor device which makes the waveform distortion of a plurality of outputs substantially the same due to the influence of a parasitic element on a mounting board on which a PKG is mounted, and outputs a plurality of similar or inverted signals. The purpose is to:

[0023]

In order to achieve the above object,
According to a first aspect of the present invention, there is provided a semiconductor device including a circuit for outputting a plurality of similar or inverted signals formed on a semiconductor substrate, wherein a plurality of circuits from an output of the circuit on the semiconductor substrate to an output terminal of the package are provided. Are arranged in a substantially line or point symmetrical shape with respect to the package or the semiconductor substrate.

According to a second aspect of the present invention, there is provided a semiconductor device including a circuit formed on a semiconductor substrate and outputting a plurality of similar or inverted signals, wherein a terminal of a package for supplying a power supply voltage to the circuit is provided. The power supply wiring from the power supply to the circuit is arranged in a substantially line or point symmetric shape with respect to the package or the semiconductor substrate.

The semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein a power supply wiring from a terminal of the package for supplying a power supply voltage to the circuit to the circuit is connected to the package or the package. The semiconductor device is characterized by being arranged in a line or point symmetrical shape with respect to the semiconductor substrate.

Further, the semiconductor device of the fourth invention of the present application is:
In the semiconductor device according to the first aspect of the present invention, a plurality of wirings on a mounting board from an output terminal of the package to an element to which the signal is transmitted are formed in a shape substantially line or point symmetric with respect to the package. It is characterized by having done.

The "plurality of wirings" include bonding pads, bonding wires, package output terminals, etc., in addition to circuit output wirings. And the output terminals of the package need not be symmetrical. The above-mentioned “power supply wiring” includes, in addition to the wiring on the substrate, bonding pads, bonding wires, package terminals, and the like. Some of the components of these wirings, for example, bonding wires and package terminals are symmetrical. It is not necessary.

The term "substantially line or point symmetry" includes not only a line or point symmetry state but also a line or point symmetry state.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first embodiment of the present invention, output wirings of a plurality of output circuits on a semiconductor substrate, bonding pads, bonding wires, and lead frames (terminals of a package) corresponding to the outputs are provided on the semiconductor substrate. Or PK
G is arranged almost line-wise or point-symmetrically with respect to a highly symmetrical point such as a center point, a diagonal line, or a center line of each side.

In the above configuration, symmetrically arranging and wiring means that the inductance and resistance parasitic to the wiring on the semiconductor substrate and the wiring in the PKG are substantially the same between a plurality of outputs without fine adjustment, and a plurality of output waveforms are obtained. Act to make the strains equal.

According to the second embodiment of the present invention, power supply wirings of a plurality of output circuits on a semiconductor substrate and bonding pads, bonding wires, and lead frames corresponding to the power supply wirings are further added to the configuration of the first embodiment. They are arranged almost line or point symmetrically with respect to a highly symmetric point such as a center point, a diagonal line, or a center line of each side of the semiconductor substrate or PKG.

In the above configuration, symmetrically arranging the power supply wiring means that the inductance and resistance parasitic on the power supply wiring on the semiconductor substrate and the power supply wiring in the PKG are substantially the same between a plurality of outputs without fine adjustment. In addition, even if the power supply voltage waveforms of the plurality of output circuits are made equal, and even if the output type depends on the power supply voltage, the circuit operates so that the output waveforms have the same distortion.

According to a third embodiment of the present invention, output wirings of a plurality of output circuits on a mounting board on which a PKG is further mounted on the configuration of the first embodiment are connected to a semiconductor substrate or a PKG.
It is arranged almost line-wise or point-symmetrically with respect to a highly symmetrical point such as a center point, a diagonal line, or a center line of each side.

By symmetrically arranging and wiring in the above configuration, the inductance and resistance parasitic on the wiring on the mounting board on which the PKG is mounted can be made substantially the same between a plurality of outputs without fine adjustment, and a plurality of output waveforms can be obtained. It works so that distortion may be equivalent.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1 is an equivalent circuit diagram showing a mounting state of a first embodiment of a semiconductor device according to the present invention. In FIG. 1, reference numerals 101 and 108 denote PMs forming two output circuits.
OSFETs 102 and 107 are also NMOSFETs. 103 and 109 are output wirings of the respective output circuits, 106 and 112 are wirings of control lines for controlling the output circuits, 104 and 111 are high-voltage power supply wirings (hereinafter referred to as power supply wirings) of the output circuits, and 105 and 110 are outputs. The low voltage side power supply wiring of the circuit (here, GND wiring; hereinafter referred to as GND wiring), 113 and 114 are bonding pads corresponding to two outputs, 201 and 202 are bonding wires, 117 and 118 are lead frames and packages (P
KG) 116. Reference numeral 115 denotes another circuit other than the output circuit. Reference numeral 301 denotes a semiconductor chip on which an output circuit and the like are integrated, and 302 denotes a horizontal center line of the PKG and the semiconductor substrate.

FIG. 2 is a layout diagram of the semiconductor device. 2, the same reference numerals are given to the components corresponding to those in FIG. 1, and the description will be omitted. In FIG. 2, 4
01 is a PMOSFET 101 and an NMOSFET 102
Gate electrodes 402 and 403 are PMOSFET 101
404, 405 are NMOFE
The drain / source region of T102, 406 is a contact hole, and 407 is a P-well region. Reference numeral 411 denotes the gate electrodes of the NMOSFET 107 and the PMOSFET 108, 412 and 413 denote the drain / source regions of the NMOSFET 107, and 414 and 415 denote the PMOFET 10
8 shows a drain / source region.

As shown in FIGS. 1 and 2, the output wirings 103 and 109 of the two output circuits and the bonding wire 2
01, 202, and lead frames 117, 118 are PKG
Are symmetrically arranged with respect to the center line 302 within an error range of each manufacturing process. That is, the width, length, and shape of the wiring (or bonding wire) are substantially the same. Therefore, the parasitic inductance and resistance of the output wiring of the output circuit are not only lumped values, but also
A value closer to the actual distribution constant is also equal. Therefore, the impedance of the load seen from the two output circuits becomes equal, and the waveform seen at the output of the PKG is similar or inverted between the two outputs even if distorted by the influence of the parasitic element. It is very difficult, if not impossible, to match the values of the parasitic elements to the same value in an unsymmetrical arrangement.However, according to this method, the patterns can be made equivalent without considering the size of the parasitic elements. By doing so, the purpose can be achieved.

Here, an output circuit using a CMOS has been exemplified. However, the present invention is not limited to a CMOS and is not limited to a CMOS.
It is needless to say that the same effect can be obtained for an output circuit that requires a plurality of similar or inverted waveforms using lar), Bi-CMOS, or a compound semiconductor. Although an example in which wiring symmetrical with respect to the center line of the PKG is used is shown here, the present invention is not limited to the case where the width, length, shape, and the like of the wiring can be made the same, and is not limited to line symmetry, and a point with respect to the PKG center may be used. It may be a symmetrical arrangement or an arrangement of a combination of these. Since it is important to make the effect of the parasitic device attached to the wiring the same, the arrangement of the devices constituting the output stage does not necessarily have to be symmetric. Furthermore, the case of two output circuits has been described here, but the number of output circuits is not necessarily limited to two. For example, output circuits may be provided at four corners of the chip symmetrically with respect to the center of the chip, or one of them may not be used if unnecessary. In another example, a total of four output circuits provided symmetrically with respect to the center line of a horizontal chip are provided at the left and right ends of the chip, and four more output circuits are provided at positions rotated by 90 degrees. It can also be configured.

Although a plurality of output wirings can be arranged in parallel with each other on the semiconductor substrate, the parasitic elements on the semiconductor substrate can be equalized. However, the lead frame of the PKG is generally symmetrical with respect to the center. Therefore, in this method, arranging the bonding pads at equivalent positions greatly restricts the layout.
It is desirable to reduce the effect of the parasitic element caused by the above.

The present invention is more effective when the objects to be driven by the plurality of output circuits have substantially the same impedance. This is because no matter how much the parasitic elements caused by the wiring are equal, the waveform will be different if the subsequent load is greatly different. <Second Embodiment> In the above-described first embodiment, the parasitic element attached to the output wiring has been noted. However, considering the source of the current flowing to the output, it is a power supply or a GND wiring, and is a high-speed or large current. When switching is performed, the power supply and the GND wiring are affected by the parasitic element similarly to the output, and the power supply voltage fluctuates. As is remarkable in the case of the CMOS output as in the first embodiment or the open collector output of a resistive load, the output waveform often depends on the fluctuation of the power supply voltage or GND. For this reason, even if the effects of the parasitic elements on the output wiring are equalized, a difference may occur between a plurality of obtained waveforms due to a voltage fluctuation of the power supply or the GND wiring at the time of switching due to the effect of the parasitic elements.

Therefore, in the present embodiment, the effect of the parasitic element is equalized not only for the output of the output circuit but also for the power supply and the GND wiring so as to eliminate the difference in the waveform between a plurality of outputs.

FIG. 3 shows a second embodiment of the present invention. FIG.
The same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. In FIG. 3, 119 and 121 are bonding pads of two outputs arranged in parallel with bonding pads 113 and 114, 123 and 125 and 127 and 129 are bonding pads corresponding to GND wirings 105 and 111 of two output circuits, respectively. 131, 133 and 135, 1
37 denotes power supply wirings 104 and 11 for two output circuits, respectively.
0 is a bonding pad corresponding to “0”. 201 to 2
12, bonding wires 117, 118, 120, 122, 124, 12 corresponding to the respective wirings;
6,128,130,132,134,136,138
Is a lead frame (a pin when viewed from outside the PKG) corresponding to each wiring.

FIG. 4 is a layout diagram of the semiconductor device. In FIG. 4, the same reference numerals are given to constituent members corresponding to FIG. 2, and description thereof will be omitted.

In this embodiment, the horizontal center line 302 of the PKG is used.
Power supply for output circuit, GND
The wiring, the bonding wires corresponding thereto, and the lead frame are also arranged so as to be axisymmetric. Therefore, not only the output wiring of the output circuit, but also the power supply wiring and the GND wiring, the parasitic inductance and the resistance are almost equal to not only the values viewed as lumped constants but also the values viewed as distributed constants which are closer to the actual values. . Therefore, the load, the power supply, and the impedance of GND as seen from the output circuit are equal between the two circuits, and the power supply voltage and GND of the two output circuits are equal.
The fluctuation of the potential due to the parasitic element becomes equal, and even if the output is of an output type depending on the power supply voltage or the GND potential,
Similar or inverted output waveforms can be obtained as in the first embodiment.

In this example, the GND wirings 105 and 111 are separated between the two output circuits, but the same result can be obtained even if they are commonly connected in the semiconductor chip. At this time (as long as symmetry is maintained), the number of bonding pads may be one or two or more.

When the power supply wirings are back to back and the power supply wirings are connected in common, the same effect can be obtained even if the power supply wirings are connected in common. In this example, a plurality of lead frames and wire bonding corresponding to output, power supply, and GND are connected in parallel. This is because the absolute values of the parasitic resistance and the inductance are reduced so that the influence is reduced when the symmetry is broken even by a slight amount due to a manufacturing error. Of course, the effect is higher if the number is increased. Further, here, the output circuit using CMOS is illustrated, but CM
Bi-CMO not only for OS but also for bipolar
It is needless to say that the same effect can be obtained for an output circuit requiring a plurality of similar or inverted waveforms using S or a compound semiconductor. Although an example in which wiring symmetrical with respect to the center line of the PKG is used is shown here, the present invention is not limited to the case where the width, length, shape, and the like of the wiring can be made the same, and is not limited to line symmetry, and a point with respect to the PKG center may be used. They may be arranged symmetrically or in a combination of these. <Third Embodiment> In the first and second embodiments described above, a parasitic element up to the PKG pin is considered so that a waveform similar or inverted to a plurality of outputs can be obtained at the level of an integrated circuit alone. However, in most cases, the integrated circuit is actually mounted on a mounting board such as a printed board. When driving other ICs and the like on the mounting board, there are extra parasitic inductances and resistances caused by the board wirings corresponding to 17 and 18 in FIG. 7 (b). The output waveform may differ. In this embodiment, the symmetrical arrangement of not only the inside of the PKG but also the output wiring on the mounting substrate allows the symmetrical IC to transmit signals from a plurality of output circuits on the semiconductor substrate.
The parasitic elements described above are made equal to eliminate the difference in waveform between a plurality of outputs.

FIG. 5 shows a third embodiment of the present invention. FIG.
The same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. Here, for the sake of simplicity, the description will be made in the case of two output circuits. In FIG. 5, 141 and 142 are wirings of two outputs on a mounting board, 143 is a device to which a signal is transmitted, and 139 and 140 are pins to which a signal is input.

FIG. 6 is a layout diagram of the semiconductor device. In FIG. 6, the same reference numerals are given to constituent members corresponding to FIG. 2, and description thereof will be omitted. Reference numeral 408 denotes a mounting board.

In this case, the output wiring 10 of the two output circuits
3, 109, bonding wires 201, 202, lead frames 117, 118, and wiring 1 on mounting board
Reference numerals 41 and 142 are wired symmetrically with respect to the center line 302 of the PKG within an error range of each manufacturing process. That is, the width, length, and shape of the wiring (or bonding wire) are substantially the same. For this reason, the parasitic inductance and resistance of the output wiring of the output circuit are substantially equal to not only the value seen as a lumped parameter but also the value seen as a distributed parameter that is closer to the actual value. Therefore, the impedance of the load seen from the two output circuits becomes equal, and the waveform seen at the input of the symmetric device 143 transmitting the signal has a similar waveform between the two outputs even if distorted by the influence of the parasitic element. Is obtained.

[0050]

As described above, according to the present invention,
Parasitic elements attached to the output wiring of a plurality of similar or inverted signals inside the semiconductor substrate can be made substantially equal to each other, so that similar waveforms can be obtained at the output terminals of the integrated circuit, and the effect of the parasitic elements can be obtained. Therefore, it is possible to prevent a device having a symmetrical signal transmission from malfunctioning due to a difference in waveform and a decrease in performance.

According to the present invention, parasitic elements attached to the output wiring, the power supply wiring, and the GND wiring of the output circuit for outputting a plurality of similar or inverted signals inside the semiconductor substrate are substantially equal among the plurality of output circuits. Therefore, even if the output waveform is a circuit type that depends on the power supply voltage or the voltage level of GND, a similar waveform can be obtained at the output terminal of the integrated circuit, and signal transmission due to a difference in waveform due to the effect of a parasitic element. Malfunction of the symmetric device and performance degradation can be prevented.

Further, according to the present invention, the parasitic element attached to the output wiring of the output circuit for outputting a plurality of similar or inverted signals inside the semiconductor substrate can be made substantially equivalent to the parasitic element attached to the wiring on the mounting board. Therefore, a similar or inverted input waveform can be obtained at the input terminal of the symmetric device for transmitting a signal, thereby preventing malfunction of the device for symmetrical signal transmission due to a difference in waveform due to the effect of a parasitic element and deterioration of performance. it can.

[Brief description of the drawings]

FIG. 1 is a mounting state diagram illustrating a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a layout diagram of the semiconductor device shown in FIG. 1;

FIG. 3 is a mounting state diagram for explaining a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a layout diagram of the semiconductor device shown in FIG. 3;

FIG. 5 is a mounting state diagram illustrating a third embodiment of the semiconductor device of the present invention.

FIG. 6 is a layout diagram of the semiconductor device shown in FIG. 5;

FIG. 7A is a mounting state diagram illustrating a conventional example, and FIG.
3A is an equivalent circuit diagram including the parasitic element of FIG. 3A, and FIG. 3C is an equivalent circuit diagram in the case of a capacitive load.

FIG. 8 is a diagram illustrating a difference in a rising waveform of the RCL series circuit due to a difference in a parameter.

[Explanation of symbols]

101, 108, 1 PMOSFET 102, 107, 2 NMOSFET 103, 109, 3 Output wiring on semiconductor substrate 104, 111 Power supply wiring on semiconductor substrate 105, 110 GND wiring on semiconductor substrate 106, 112 Control for controlling output circuit Of wiring on semiconductor substrate 113,114,119,121,123,125,1
27,129,131,133,135,137,4
Bonding pad on semiconductor substrate 115 Other circuits other than output circuit 116, 10 Package 117, 118, 120, 122, 124, 126, 1
28, 130, 132, 134, 136, 138, 7
Lead frame and package pins 201 to 212, 6 Bonding wires 301, 5 Semiconductor chip 302 PKG center lines 141, 142, 8 Wiring on mounting board 139, 140 Pins to which signals are input 143, 9 Targets to which signals are transmitted Devices 11, 13, 15, 17, 21 Parasitic inductance 12, 14, 16, 18, 22 Parasitic resistance 19 Power supply 20 Switch 23 Load capacitance

Claims (4)

[Claims] 1. A semiconductor device including a circuit formed on a semiconductor substrate and outputting a plurality of similar or inverted signals, wherein a plurality of wirings from an output of the circuit on the semiconductor substrate to an output terminal of a package are provided. A semiconductor device, wherein the semiconductor device is arranged in a substantially line or point symmetric shape with respect to a package or the semiconductor substrate. 2. A semiconductor device including a circuit formed on a semiconductor substrate and outputting a plurality of similar or inverted signals, comprising: a power supply line from a terminal of a package for supplying a power supply voltage to the circuit to the circuit; A semiconductor device, wherein the semiconductor device is arranged in a substantially line or point symmetric shape with respect to a package or the semiconductor substrate. 3. A power supply line from a terminal of the package, which supplies a power supply voltage to the circuit, to the circuit, is arranged in a substantially line or point symmetric shape with respect to the package or the semiconductor substrate. The semiconductor device according to claim 1, wherein: 4. A plurality of wirings on a mounting board from an output terminal of the package to an element to which the signal is transmitted are formed in a substantially line or point symmetric shape with respect to the package. The semiconductor device according to claim 1, wherein: