JPH10335443A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming an element isolation region using a trench, which can reduce dishing after polishing, by reducing a step difference before growth of a CVD oxide film to reduce a step difference in the oxide film. SOLUTION: A SiN film 3 is formed on a silicon substrate 1 through an underlying oxide film 2. Next, with use of a resist mask 4, holes are made in parts of a broad element isolation region 5 joined to an element formation region 6 and at several positions therebetween, and the SiN film 2 and underlying oxide film 3 are dry-etched. After removal of the resist, a thin oxide film 7 is selectively formed in the element isolation region 5. Next, a resist mask 9 is formed so that the broad element isolation region 5 and a narrow element isolation region 8 are opened. With use of the mask 9, the SiN film 2, oxide film 3 and silicon substrate 1 of the narrow and broad element isolation regions 8 and 5 are dry-etched. After formation of a CVD oxide film, the film is polished down to a surface of the SiN film 2 by a CMP method. Thereafter, the SiN film 2 is removed and the entire surface of the silicon oxide film 3 is removed down to the silicon substrate 1 of the region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region using a trench.

[0002]

2. Description of the Related Art In recent years, high-speed and high-integration LSIs have been developed, and various element isolation methods have been required. Among them, conventionally, in a transistor which is isolated by burying an insulating film in a trench (groove) portion, a trench shallower than an isolation trench is formed, and BPSG is deposited and melted inside the trench to form a deep trench. The inside is filled, BPSG is etched back to the depth of a shallow trench, and thereafter, a CVD oxide film is grown in both trenches, and the substrate surface is polished or etched back to planarize the substrate surface.

A method for forming a device isolation region using a conventional trench described in Japanese Patent Application Laid-Open No. 5-114646 will be described below with reference to FIG.

First, a shallow trench 21 and a deep trench 22 are formed on a silicon substrate 20 (FIG. 4A). Next, BPSG 23 is grown (FIG. 4B).
The BPSG 23 is melted and filled in the trenches 21 and 22 (FIG. 4C).

Next, the BPSG 23 is etched back to the depth of the shallow trench 21 (FIG. 4D), and a CVD oxide film 24 is grown to a thickness not less than the depth of the shallow trench 21. Embed both (Fig. 4
(E)). Thereafter, the substrate surface is etched back or polished to flatten it (FIG. 4F). Thereafter, element isolation is performed by a normal process.

[0006]

In a conventional device isolation forming method using a trench, in a shallow device isolation region, a silicon substrate must be dug more than a film thickness necessary for enabling device isolation. CV filling trench
When the D oxide film is grown, the step on the uppermost surface of the oxide film is approximately equal to the step on the dug silicon substrate. Also,
At the time of polishing, it is better to form some kind of polishing stopper on the activated region in order to protect the activated region from damage due to polishing, so that the step is further increased. If polishing is performed in the state of the large step, in a wide region of the shallow trench, there is a problem that an oxide film in the region is excessively ground (dishing).

According to the present invention, a step before growing a CVD oxide film is reduced, thereby reducing the step of the oxide film.
An object of the present invention is to provide a method for forming element isolation using a trench, which can reduce dishing after polishing.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein a first element isolation region having at least a first area and an area larger than the first element isolation region are formed on the same semiconductor substrate. A semiconductor device in which a second element isolation region having a large second area is formed;
The element isolation region includes an insulating film embedded in one groove formed in the semiconductor substrate. The second element isolation region includes an insulating film embedded in a plurality of grooves formed in the semiconductor substrate. And a selective oxide film formed in the other region.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, an oxide film formed in the same step is buried in the groove of the first element isolation region and the groove of the second element isolation region. 2. The semiconductor device according to claim 1, wherein:

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming an oxidation-resistant film on the semiconductor substrate,
In the region to be the second element isolation region, the oxidation-resistant film on the semiconductor substrate including a portion in contact with the element region is opened at a plurality of positions, and the semiconductor substrate exposed portion of the opening region is selectively oxidized to selectively oxidize. After forming the film, the oxidation-resistant film in the region to be the first element isolation region and the region to be the second element isolation region is removed, and the semiconductor substrate is etched using the oxidation-resistant film and the selective oxidation film as a mask. Then, a groove is formed in the region to be the first element isolation region and the region to be the second element isolation region, and then the first element isolation region and the second element isolation region are buried by filling an insulating film in the groove. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed.

Further, according to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, after forming the groove, an insulating film is formed on the entire surface of the semiconductor substrate to form the insulating film in the groove. A method for manufacturing a semiconductor device according to claim 3, characterized in that:

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a structural sectional view of a semiconductor substrate after an element isolation region according to one embodiment of the present invention is formed, and FIG. 2 is a manufacturing process diagram of a first half of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a manufacturing process diagram of the latter half of the semiconductor device according to the embodiment of the present invention. 1 to 3, reference numeral 1 denotes a silicon substrate, 2 denotes an oxidation-resistant film and a SiN film (for example, a film thickness of about 500）) as a CMP polishing stopper, 3 denotes a base oxide film (about 10 数 film thickness), and 4 and 9 denote A resist mask, 5 is a wide element isolation region, 6 is an element formation region, 7 is a selective oxide film, 8 is a narrow element isolation region, and 10a and 10b are CVD oxide films.

According to the present invention, as shown in FIG. 1, a wide device isolation region 5 is composed of a plurality of trenches in which a CVD oxide film 10b is buried and a selective oxide film 7, and a narrow device isolation region is a CVD device. It has a single trench portion in which oxide film 10a is buried.

Hereinafter, the manufacturing process of the present invention will be described with reference to FIGS.

First, an SiN film 2 is formed on a silicon substrate 1 with a base oxide film 3 interposed therebetween (FIG. 2A).

Next, the resist mask 4 is used to open a part of the wide element isolation region 5 which is in contact with the element formation region 6 and several places therebetween, and dry-etch the SiN film 2 and the base oxide film 3. The etching conditions at this time are, for example, a flow rate of CF ₄ of 100 sccm and a pressure of 50 mT so that the selection ratio of SiN / Si is about 1.5.
orr, field strength 80 Gauss, RF power 40
Dry etching is performed at 0W. At this time, patterning is performed so that the line width of the resist on the wide element isolation region is substantially equal to the line width of the narrow element isolation region (for example, 0.5 μm) (FIG. 2B).

Next, after removing the resist mask 4, SiN
Using the film 2 as an oxidation resistant film, a selective oxidation film 7 (for example, having a thickness of about 1000 °) is selectively formed in the wide element isolation region 5 by thermal oxidation. Next, a resist is applied, and a wide element isolation region 5 and a narrow element isolation region 8 are formed by a photolithography process.
A resist mask 9 having an opening is formed (FIG. 2).
(C)).

Next, the SiN film 2, the oxide film 3, and the silicon substrate 1 in the narrow element isolation region 8 and the wide element isolation region 5 are dry-etched using a resist mask 9. The etching conditions of the silicon substrate 1 at this time are, for example, a HBr flow rate of 50 sccm and an O ₂ flow rate of 6 s so that the selection ratio of the silicon / silicon oxide film is about 80.
ccm, pressure 0.90Pa, coil current in 40
A, out 20A, RF etching at 1500 W source, and 70 W bias for dry etching. At this time, the wide element isolation region is selectively etched only at locations other than the thin oxide film 7. Further, the depth of the groove to be formed is set to a depth (for example, about 3000 °) that enables element isolation (FIG. 2).
(D)).

Next, after the resist mask 9 is removed, C
The VD oxide film 10 is formed, for example, at about 3500 ° (FIG.
(A)).

Next, the CVD oxide film 10 is polished by the CMP method until the surface of the SiN film 2 serving as a CMP polishing stopper is exposed (FIG. 3B). At this time, in the later etching step of the silicon oxide films 3 and 10, it is desirable to reduce the thickness of the SiN film 2 by etching the SiN film 2 to some extent in order to further flatten the surface of the silicon substrate 1. .

Thereafter, the phosphoric acid is added with phosphoric acid at about 150 ° C. for 5 minutes.
The SiN film 2 is removed by wet etching for 0 minutes (FIG. 3 (c)), and the entire surface of the silicon oxide films 3 and 10 up to the silicon substrate 1 in the element formation region 6 by wet etching using hydrofluoric acid or CMP. Removal is performed to expose the surface of the silicon substrate 1 in the element formation region 6. At this time, the narrow element isolation region 8 and the wide element isolation region 5 have C
VD oxide films 10a and 10b are filled (FIG. 3
(D)).

Thereafter, an element is formed in an element forming region surrounded by the element isolation region of the trench by a usual process.

[0024]

As described above in detail, by using the present invention, the variation in the wafer surface at the time of depositing an oxide film burying the element isolation region and the dishing after the planarization by the CMP method can be achieved as compared with the conventional method. By forming a trench that is several places deeper with the edge portion of a wide element isolation region, sufficient isolation characteristics can be obtained and the parasitic capacitance can be reduced.

Further, by filling the same oxide film in the groove of the element isolation region, the reliability of the isolation characteristics can be further improved.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a first half of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the latter half of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a view showing a process of forming an element using a conventional trench.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 SiN film 3 base oxide film 4, 9 resist mask 5 wide element isolation region 6 element formation region 7 selective oxide film 8 narrow element isolation region 10, 10a, 10b CVD oxide film

Claims (4)

[Claims] 1. A semiconductor device in which a first element isolation region having at least a first area and a second element isolation region having a second area larger than the first element isolation region are formed on the same semiconductor substrate. The first element isolation region includes an insulating film buried in one groove formed in the semiconductor substrate, and the second element isolation region includes an insulating film buried in a plurality of grooves formed in the semiconductor substrate. And a selective oxide film formed in a region other than the trench. 2. The semiconductor device according to claim 1, wherein an oxide film formed in the same step is buried in the groove of the first element isolation region and the groove of the second element isolation region. . 3. An oxidation-resistant film is formed on the semiconductor substrate,
In a region to be the second element isolation region, the oxidation-resistant film on the semiconductor substrate including a portion in contact with the element region is opened at a plurality of locations, and the semiconductor substrate exposed portion of the opening region is selectively oxidized,
After forming the selective oxidation film, the oxidation-resistant film in the region to be the first element isolation region and the region to be the second element isolation region is removed, and the semiconductor substrate is formed by using the oxidation-resistant film and the selective oxidation film as a mask. Is etched to form a groove in the region to be the first element isolation region and the region to be the second element isolation region, and thereafter, the first element isolation region and the second element isolation region are buried with an insulating film in the groove. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a region is formed. 4. The method for manufacturing a semiconductor device according to claim 3, wherein after forming the groove, the insulating film is formed in the groove by forming an insulating film on the entire surface of the semiconductor substrate.