JPH10333021A - Focus detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely execute monitor photometry without complicating the constitution of a sensor and to make the sensor compact in a phase difference detection type focus detector provided with the plural pairs of line sensors having a monitor part used for deciding a photoelectric current integration time. SOLUTION: This detector is provided with a 4th island having a monitor part photodiode(MPD) only at a standard part and a 1st to a 3rd islands having the MPD both at the standard part and a reference part. By making the magnitude of the output of the MPD 91a of the 4th island almost two times of the outputs of the MPDs 81a and 81b of the 1st to the 3rd islands, the magnitude of the output of the monitor part of the 4th island is made almost identical to the outputs of the whole monitor parts of the 1st to the 3rd islands. Thus, the precise monitor photometry is executed without complicating the constitution of a sensor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a focus detection device for performing focus detection by a phase difference detection method using a plurality of paired line sensors.

[0002]

2. Description of the Related Art Conventionally, in a focus detection apparatus, a subject image is separately formed on a predetermined focal plane by a phase difference detection system, that is, by subject light passing through two regions on both sides of an optical axis on a lens. Is formed, 2
Since the respective images are displaced due to the parallax of the subject in the two regions, there is a method in which the focus is detected by a method of calculating the amount of defocus of the lens by detecting the amount of the shift. In such a focus detection device, a cross-shaped line sensor in which two line sensor pairs forming a reference portion and a reference portion are arranged in a horizontal direction and a vertical direction so that each line sensor pair is orthogonal at a center portion. It has been known. This cross-shaped line sensor is a kind of an image sensor, and a monitor photodiode (which is disposed along the PD of the reference portion and the reference portion to determine the photocurrent integration time of the photodiode for the pixel (referred to as PD). MPD) is used.

[0003]

However, in the cross-shaped line sensor, the MPD line of one of the two line sensor pairs in the horizontal direction and the vertical direction (the MPD lines of the reference portion and the reference portion are not connected). Line connecting
Is divided by the MPD line and the PD line of the other line sensor pair (lines connecting the PDs of the respective units). To connect this split MPD line,
It is necessary to connect the MPD lines in a multilayer structure or to detour around the line sensor to connect the MPD lines at the intersections. However, any connection method complicates the configuration of the cross-shaped line sensor, This was a factor that hindered the miniaturization of line sensors. Some cross-shaped line sensors are provided with an MPD only at the reference portion (see, for example, Japanese Patent Application Laid-Open No. 62-212611). Photometry becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to accurately perform monitor photometry without complicating the structure of a sensor and to reduce the size of the sensor. It is an object of the present invention to provide a focus detection device that can be achieved.

[0005]

In order to achieve the above object, the invention according to the first aspect comprises a plurality of pairs of line sensors having a monitor unit used for determining a photocurrent integration time. In the focus detection device that performs focus detection by the phase difference detection method, the plurality of line sensor pairs include a first line sensor pair having a monitor unit in only one of the reference unit and the reference unit, and a reference unit and a reference unit. A second line sensor pair having a monitor unit in both of the units,
The magnitude of the output of the monitor unit of the first line sensor pair
Is approximately twice the output of the monitor unit of the pair of line sensors.

In the above configuration, the magnitude of the output of the monitor unit of the first pair of line sensors having the monitor unit in only one of the reference unit and the reference unit is different from the configuration in which the monitor unit is provided in both the reference unit and the reference unit. In this case, the output becomes substantially the same as the output of the entire monitor unit, and accurate monitor photometry can be performed.

According to a second aspect of the present invention, there is provided the focus detecting device according to the first aspect, wherein the area of the monitor photodiode of the first line sensor pair is reduced by the reference portion of the second line sensor pair. By making the area of the monitor photodiode of the reference section approximately twice as large, the magnitude of the output of the monitor section of the first line sensor pair is made about twice the output of the monitor section of the second line sensor pair. is there.

In the above configuration, the area of the photodiode of the monitor section of the first line sensor pair is made approximately twice as large as the area of the photodiode of the monitor section of the reference section or reference section of the second line sensor pair. The amount of charge accumulated in the monitor photodiode of the first line sensor pair is substantially the same as the total value of the amount of charge accumulated in the monitor photodiode of the reference portion and the reference portion of the second line sensor pair. Accordingly, the magnitude of the output of the monitor of the first pair of line sensors becomes substantially the same as the output of the entire monitor of the second pair of line sensors.

According to a third aspect of the present invention, there is provided the focus detection device according to the first aspect, wherein the amplification factor of the monitor section output amplifier of the first line sensor pair is monitored by the second line sensor pair. The magnitude of the output of the monitor unit of the first pair of line sensors is approximately twice as large as the output of the monitor unit of the second pair of line sensors by making the gain of the unit output amplifier approximately twice as large.

In the above configuration, the amount of electric charge stored in the first line sensor pair having the monitor section only in one of the reference section and the reference section is equal to the amount of electric charge stored in the second line sensor having the monitor section in both the reference section and the reference section. Although the charge amount of the line sensor pair is reduced to half, the gain of the monitor output amplifier of the first line sensor pair is substantially twice the gain of the monitor output amplifier of the second line sensor pair. The magnitude of the monitor output of the first line sensor pair is substantially the same as the magnitude of the monitor output of the second line sensor pair.

According to a fourth aspect of the present invention, there is provided the focus detecting device according to the first aspect, wherein the capacitance of the capacitor of the charge-voltage converter of the monitor of the first line sensor pair is changed to the second line sensor. By making the capacitance of the capacitor of the charge-voltage conversion unit of the pair of monitor units approximately half, the magnitude of the output of the monitor unit of the first line sensor pair is reduced to approximately the value of the output of the monitor unit of the second line sensor pair. It is doubled.

In the above configuration, the amount of electric charge stored in the first line sensor pair having the monitor section only in one of the reference section and the reference section is equal to the amount of the electric charge accumulated in the second line sensor having the monitor section in both the reference section and the reference section. Although the charge amount of the line sensor pair is reduced to half, the capacitance of the monitor charge-to-voltage converter of the first line sensor pair is approximately two times the capacitance of the monitor charge-to-voltage converter of the second line sensor pair. From the relational expression of V (voltage) = Q (charge amount) / C (capacitor capacitance), the magnitude of the output of the monitor unit of the first line sensor pair is equal to the monitor of the second line sensor pair. It is almost the same size as the unit output.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a focus detecting device according to an embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 2 is a perspective view of an optical system included in the focus detection device according to the present embodiment. The optical system of the focus detection device 1 includes a photographing lens 2 of a camera, a field mask 3 having a cross-shaped opening in the center and a vertically long opening on the left and right sides, a condenser lens 4, an aperture mask 5 having a shape corresponding to the field mask 3, Separator lens 6
The image sensor 10 includes a line sensor having the same shape as the opening of the field mask 3. The light beam reflected from the subject passes through the photographing lens 2 and forms an image on the field mask 3. Only the image formed on the opening of the field mask 3 is re-imaged on the line sensor of the image sensor 10 by the condenser lens 4, the aperture mask 5 and the separator lens 6.

FIG. 2 is a block diagram of a control system of the focus detection device 1. The focus detection device 1 performs focus detection by a phase difference detection method. The focus detection device 1 is provided with a microcomputer 20 that controls the image sensor 10, performs calculations related to focus detection, and controls lens driving. The microcomputer 20 includes an image sensor 10 comprising a CCD, a lens data output unit 30 for outputting data relating to the lens such as a lens extension amount according to the type of lens, a display circuit 40 for displaying a focus detection state and the like, and a lens. A lens driving unit 60 driven by the motor 50 and an encoder 70 for monitoring the amount of rotation of the motor 50 are connected. When detecting the start signal of the distance measurement operation, the microcomputer 20 sends a mode selection signal 1 (MD1), a mode selection signal 2 (MD2), a mode selection signal 3 (MD3), and a clear signal from the sensor control unit 27 to the CCD operation control unit 13. Gate control signal (IC
G), the image sensor 10 is driven by outputting each signal of the shift gate control signal (SHM) to perform photocurrent integration. At this time, the integration time control unit 11 controls the MPD provided along the PD of each island (in this case, a line sensor pair) on the image sensor 10.
The integration time is controlled based on the output voltage or the like. When the integration is completed, the microcomputer 20 sets the analog signal processing unit 12
The image information output from each line sensor pair of the image sensor 10 is sequentially fetched into the A / D conversion unit 21 through the interface, and the image information is converted into digital data and output to the RAM 22.

Next, the microcomputer 20 outputs the image information stored in the RAM 22 to the focus detection unit 23, calculates a defocus amount (defocus amount) based on the image information, and then calculates a defocus amount. The defocus amount correction calculation is performed, and based on the result, the display circuit 40 displays an in-focus state or the like. The lens drive control unit 25 of the microcomputer 20 converts the defocus amount into a lens extension amount based on the lens data output from the lens data output unit 30, and outputs the motor amount via the lens drive unit 60 according to the lens extension amount. 50 is driven. At this time, the lens drive control unit 2
5 is a motor 5 based on an output value from the encoder 70.
The lens drive is performed while checking the drive amount of 0. Note that the sensor control unit 27 sends an A / D signal from the analog signal processing unit 12.
When outputting image information to the conversion unit 21, the timer circuit 26
By transmitting a clock pulse (CP) signal to the CCD clock generation unit 14 using the
2, a synchronization signal for setting the data output timing is sent. At this time, the CCD operation control section 13 sends a synchronization signal to the A / D conversion section 21 to determine the timing of data reception.

FIG. 3 is an arrangement diagram of the islands in the image sensor 10. Each of the first to third islands includes a monitoring photodiode (MPD) 8
1a, 81b, pixel photodiode arrays (PD arrays) 82a, 82b, charge storage units (ST) 83a, 8
3b and a shift register (SR) 84. In the first to third islands, SR84
Are not separated between the reference portion and the reference portion, and the reference portion and the reference portion are provided with MPDs 81a and 81b, respectively. These MPDs 81a and 81b are connected by an MPD line, and A monitor section is formed. On the other hand, regarding the fourth island, the SR 94a and 94b of the reference portion and the reference portion are separated by the SR84 of the second island and the MPD line, and the MPD 91a of the monitor portion is provided only in the reference portion.

The reason that the MPD 91a of the monitor section is only in the reference section is that the fourth island also has an MPD in both the reference section and the reference section and is connected by an MPD line. It is necessary to connect the MPD lines by using a multi-layer structure or by circumventing the island. However, whichever method is adopted, the structure becomes complicated, and a limitation in miniaturizing the image sensor 10 is required. It is because it becomes. Instead, the area (width) of the MPD 91a at the reference portion of the fourth island is twice as large as those of the other MPDs 81a and 81b, and the amount of accumulated charges is twice that of the other MPDs 81a and 81b. In focus detection by the phase difference detection method, the amount of light received by the reference portion and the reference portion is substantially equal in principle, based on the principle that the subject image in the same area is divided into two and received by the reference portion and the reference portion. For this reason, the charge accumulation amount of the monitor portion of the fourth island is determined by providing the MPD 91a only in the reference portion and making the amount of accumulated charge twice that of the other MPDs 81a and 81b. Is substantially the same as the total value of the charge accumulation amount of the monitor unit in the configuration having As a result, the output voltage of the monitor unit 91a of the fourth island becomes substantially the same as the output voltage when the monitor unit of the fourth island also has a monitor unit in the reference unit as in the other islands. 91a has substantially the same sensitivity as the monitor units of the other islands.

The sensor control means 13A shown in FIG.
The sensor control unit 27 and the CCD operation control unit 1 shown in FIG.
SH, SH2, IC on each island
By transmitting the G, BG, and CP signals, the entire image sensor 10 is controlled. Further, the selection means 13B
A part of the CD operation control unit 13 and the sensor control unit 13
In accordance with the instruction from A, an island from which analog data is transmitted to the microcomputer 20 is selected.

According to the cross-shaped line sensor having the above structure, the fourth island in the vertical direction is provided only in the reference portion by the MPD 9.
1a, the MPD line at the intersection is made to have a multilayer structure,
There is no need to connect the D line. The second island in the horizontal direction, which requires accurate monitor photometry, has MPDs 81a and 81b in both the reference portion and the reference portion.
Using this, accurate monitor photometry can be performed. For this reason, it is possible to accurately perform monitor photometry in the horizontal direction and the vertical direction without complicating the configuration of the image sensor 10, and to reduce the size of the image sensor 10.

FIG. 4 is a sensor configuration diagram of one of the first to third islands. The MPD 81a, the PD array 82a, the integration control gate 85, and the SR 84 are provided in the reference portion, and the MPD 81 is provided in the reference portion.
b, PD array 82b, integration control gate 85,
The SRs 84 are respectively arranged in parallel. The MPDs 81a and 81b provided in the reference portion and the reference portion are connected to each other by an MPD line, and the SR84 is also integrated in the reference portion and the reference portion. further,
Each gate of the integration control gate 85 is also connected by each line connecting the reference section and the reference section. PD
In the array, a photodiode and a capacitor for integrating the output photocurrent are elements for one pixel, and such elements are arranged in an array. The PD arrays 82a and 82b of the reference section and the reference section respectively have
A light-shielded pixel (OPD: black dot portion) 82 made of aluminum that generates dark-time charges used for output dark-time output compensation
c and 82d are provided.

The MPD provided in the reference part and the reference part
81a and 81b are a charge-voltage converter 81c, a buffer 8
The monitor section 81 is formed together with 1d. MPD81a, 8
The charge accumulated in the buffer 1b is converted into a voltage by the charge-voltage converter 81c, and then stored in the buffer 81d.
It is output from the GCOS terminal. The output from the AGCOS terminal is output to the integration time control unit 11 (see FIG. 2), and is used for appropriately controlling the integration levels of the PD arrays 82a and 82b.

The integration control gate 85 includes a barrier gate 85a, STs 83a and 83b, a clear gate 85b, and a shift gate 85c. S
R84 is connected to a charge-voltage converter 86 that converts the charge output from the SR84 into a voltage to obtain a photoelectric conversion output. Further, a voltage conversion unit 88 is provided for removing a fluctuation of the power supply voltage from the photoelectric conversion output of the charge-voltage conversion unit 86. The voltage conversion unit 88 includes an aluminum light-shielded drift signal compensation photodiode (MD). And this M
A reference voltage, which is a dark output obtained from the output of D, is output from the DOS terminal via the buffer 89.

Next, with reference to FIG. 4 and FIG. 2, the photocurrent integration processing of the first to third islands will be described. The application of the integration clear pulse from the ICG terminal shown in FIG. 4 to the clear gate 85b initializes the integration circuit and then starts photocurrent integration. Then, the charges photoelectrically converted by the PD arrays 82a and 82b are accumulated in the STs 83a and 83b via the barrier gate 85a. Also, the output from the AGCOS terminal increases with the start of integration, and when the output reaches a predetermined level, the integration time control unit 11 sets the PD arrays 82a, 82b
End integration of. When the integration is completed, the sensor control unit 2
In response to the SHM signal indicating the start of reading from No. 7, by applying a shift pulse from the SH terminal to the shift gate 85c, the charges accumulated in the STs 83a and 83b are transferred in parallel to the SR 84. The charge of the SR 84 is voltage-converted by the charge-to-voltage converter 86, and then, as a photoelectric conversion output, from the OS terminal via the buffer 87 to the analog signal processor 1.
2 is output. This output is output to the CCD clock generator 1
4 is performed in accordance with the clock pulse generated from step 4.

FIG. 5 is a sensor configuration diagram of the fourth island. In the sensor of the fourth island, the MPD 91a is arranged only at the reference portion, and the SRs 94a and 94b are separated at the reference portion and the reference portion. Further, the lines of the integration control gates 95a and 95b are also separated at the reference portion and the reference portion. The sensor of the fourth island has such a configuration because the reference portion and the reference portion of the fourth island are separated by each line connecting the reference portion and the reference portion of the second island and the SR84. is there. Regarding the MPD 91a of the reference portion of the fourth island, the area (width) is set to the MPDs 81a and 81 of the other islands.
b, and the amount of accumulated electric charge is changed to another MPD 81.
By doubling a and 81b, the sensitivity is substantially the same as that of the monitor unit of another island having the MPD in both the reference unit and the reference unit.

The charge accumulated in the ST 93a of the reference portion of the fourth island is the same as the charge accumulated in the reference portions ST 83a, 83b of the other islands, and the SHM at the start of reading from the sensor control portion 27. By applying a shift pulse to the shift gate 95e corresponding to the signal, ST
93a is transferred in parallel to the SR 94a and voltage-converted by the charge-to-voltage converter 96. Then, the photoelectric conversion output is sent from the OS4 terminal to the analog signal processor 1 via the buffer 97.
2 is output. On the other hand, the charge accumulated in ST93b of the reference portion of the fourth island is changed by applying a shift pulse from the SH2 terminal to the shift gate 95f in synchronization with the end signal of the reading of the charge of the reference portion.
From the OS4 terminal via the buffer 97, after being transferred in parallel to the SR 94b and subjected to voltage conversion by the charge-voltage converter 96 following the output of the reference unit.
Output to

The photoelectric conversion outputs from the first to fourth islands shown in FIGS. 4 and 5 are received by the analog signal processing unit 12 and then subjected to dark output compensation inside the analog signal processing unit 12. You. This dark-time output compensation is performed through a clamp that uses the dark-time output as the reference voltage (by matching the upper or lower end of the output voltage waveform to the dark output voltage). The clamp using the dark output as a reference voltage is the first clamp.
The output from the third island is clamped by using the output value of the light-shielded pixel OPD 82c detected by the reference unit as a reference voltage, while the output from the fourth island is clamped by the reference unit and the reference unit. Are clamped separately in the reference portion and the reference portion using the output values of the light-shielded pixels OPDs 92c and 92d detected in each of the reference portions as reference voltages.
This is because, as described above, in the fourth island, since the reference portion and the reference portion are separated from each other in terms of circuit, the dark output noise of the reference portion and the reference portion is different due to a difference in sensor manufacturing and the like.
Since the dark output level of the reference portion and the reference portion may be different, if the entire island including the reference portion is clamped based on the output value of the light-shielded pixel detected by the reference portion, accurate dark output compensation is performed. This is because there are things that you cannot do.

FIG. 6 is a timing chart of control signals between the image sensor 10 and the microcomputer 20 from the start of integration until the operation of reading photoelectric conversion outputs of four islands is performed. After outputting the SHM signal for starting each island readout, the sensor control unit 27 sets the reference voltage to the dark output of the light-shielded pixel by setting the ICG signal to Hi while outputting the light-shielded pixel. Perform the operation of clamping. This clamping operation is performed for the first to third islands before the output of the effective pixel of the reference portion of each island.
The output of the light-shielded pixel OPD92d of the reference portion is performed as a reference voltage, and the fourth island is not only output of an effective pixel of the reference portion but also output of an effective pixel of the reference portion. The output is used as a reference voltage.

The flow of control signals between the image sensor 10 and the microcomputer 20 from the start of integration until the operation of reading photoelectric conversion outputs of the four islands and the operation of the image sensor 10 and the microcomputer 20 will be described below.
As shown in FIG. 6, the sensor control unit 27 of the microcomputer 20 repeats the rising and falling of the SHM signal twice during the period of the integration start ICG signal Hi, thereby obtaining the CC signal.
A clear pulse is applied from the D operation control unit 13 to the SH and SH2 terminals of each island to initialize the integration circuit. In addition, at the timing of the rise and fall of the SHM,
An integration mode is set according to a combination of Hi and Lo of the MD2 signal and the MD3 signal. This integration mode includes P
There is a mode in which electric charges are accumulated only by the D array, and a mode in which electric charges are accumulated by the PD array and ST (accumulation unit).
During the integration, the CCD operation control unit 13 of the image sensor 10 notifies the microcomputer 20 of the integration by setting the ADT signal to be notified to the A / D conversion unit 21 of the microcomputer 20 to Hi, and the monitor unit 81 Alternatively, when the output voltage from 91 has reached a predetermined value or when the integration time has reached a predetermined time, the ADT signal is set to Lo to notify the microcomputer 20 that the integration has been completed.

Next, the microcomputer 20 outputs the MD2 signal, MD
In synchronization with the output of the three signals, the digital data such as the integration end order of each island is transferred to the ADT from the CCD operation control unit 13.
Read by signal. Regarding the type of digital data read from the ADT signal, the MD2 signal and MD3 signal
This is performed by a combination of i and Lo.

The microcomputer 20 switches from the integration mode to the data dump mode by setting the MD1 signal to Hi. Then, the microcomputer 20 starts up the SHM signal,
By performing the fall, reading of the output of each island is started, and the read island is designated by a combination of Hi and Lo of the MD2 signal and the MD3 signal when the SHM signal is rising. In the case of the present embodiment, Lo and Lo are a first island, Lo and Hi are a second island, Hi and Lo are a third island, and Hi and Lo are a third island.
The fourth island is read by Hi. After starting to read the output of each island, the image sensor 1
0, while synchronizing with the ADT signal sent to the microcomputer 20, the analog signal processing unit 12 of the image sensor 10
, Analog data (photoelectric conversion output from each island) to the A / D converter 21 of the microcomputer 20 is output via the Vout output terminal. At this time, the data from each light-shielded pixel (OPD) is output before the effective pixel output of each island. At this time, the rising and falling of the ICG signal is performed, so that the internal The circuit performs an operation of clamping using the output (dark output) from each light-shielded pixel (OPD) as a reference voltage. This clamping operation is performed for the first to third islands before the output of the reference portion effective pixel of each island before the light shielding pixel OPD of the reference portion.
The output of the reference portion valid pixel is performed by using the output of the reference portion effective pixel for the fourth island before the output of the reference portion valid pixel before the output of the reference portion valid pixel. Also, the light-shielded pixel O
This is performed using the output of the PD 92d as a reference voltage.

After this clamping operation, the effective pixel data of each island is output. In FIG. 6, the output of one pixel of the PD array is Vout between one rising and falling of the ADT signal in the data dump mode.
Output from the output terminal. In each island, the first three pixels are light-shielded pixels OPD, and the effective pixels start from the fourth. For example, in the case of the first island, CC
The output of the effective pixel is started from the time when the D operation control unit 13 sends the fourth ADT signal shown in FIG. The rise and fall of some ADT signals between the reference portion effective pixel and the reference portion effective pixel of each island causes the output of the idle feed pixel. In addition, the MD2 signal is set to Hi at the time of outputting an effective pixel. This is because the analog output signal from the actual Vout output terminal is switched between the pixel output and other information, and from the microcomputer 20 to the image sensor 10 by the MD2 signal. This is because it is necessary to instruct output of an effective pixel. Other information includes the temperature output and the monitor unit 8
There are output voltages from the pixels 1 and 91, and these pieces of information can be extracted at timings other than when valid pixels are output.

FIGS. 7 and 8 are circuit diagrams of the analog signal processing unit 12. FIG. The details of the analog signal processing unit 12 that outputs as analog data to the A / D conversion unit 21 of the microcomputer 20 after performing processing such as dark output compensation on the photoelectric conversion output of each island will be described with reference to FIGS. 7 and 8. Will be explained. First, in FIG. 7, the photoelectric conversion output OS of each island
1, OS2, OS3, and OS4 are connected to terminals 101,
The signals are stored in the buffer circuit 200 through 102, 103, and 201 and are selectively supplied to the positive input terminal of the differential amplifier 75 by analog switches SW1, SW2, SW3, and SW4 that are sequentially turned on.

Here, the buffer circuit 200 is connected to the terminal 10
Capacitors C17, C18, C19, C20 connected between 1, 102, 103, 201 and a ground point, and terminals 104, 105, 106, 202 to which a power supply voltage is applied
And the switching transistors 107, 108, 109, and 203 connected between the
111, 112, and 204. Buffers Analog switches SW1, SW2, SW3, connected to the output side of buffers 110, 111, 112, 204
SW4 and the switching transistors 107, 1
08, 109 and 203 are formed of MOS transistors, though not particularly limited thereto.

The analog switches SW1, SW2, S
W3 and SW4, photoelectric conversion outputs OS1 and OS repeatedly output sequentially and given to the differential amplifier 75
2, OS3, OS4, the differential amplifier 75 removes the fluctuation of the power supply voltage Vcc. The differential amplifier 75 is provided mainly for performing drift signal compensation for removing the fluctuation of the power supply voltage. In the differential amplifier 75, the difference between the photoelectric conversion output supplied to the positive input terminal and the drift signal compensation reference voltage DOS from the DOS terminal supplied to the negative input terminal is obtained, and as a result, the photoelectric conversion is performed. The fluctuation of the power supply voltage can be removed from the output.

As described above, the power supply voltage Vc
The photoelectric conversion output from which the variation of c has been removed is subjected to clamping (dark output compensation) using the output of the light-shielded pixel OPD as a reference voltage by the differential amplifier 76 at the next stage. This dark output compensation is performed by using the light-shielded pixel OPD 82c (see FIG. 4) or the OPD
The dark output voltage sampled by the transistor Q18 is held by the capacitor C15 with the output of the output 92c (see FIG. 5) being timed by the input signal from the φOB terminal. This is realized by applying the photoelectric conversion output output from the differential amplifier 75 to the negative input terminal side in addition to the input terminal. As described above, this dark-time output compensation is performed for the first to third islands before the output of the reference portion effective pixel of each island.
Is performed using the output of the reference portion as the reference voltage. For the fourth island, the output of the light-shielded pixel OPD92c of the reference portion is performed using the reference voltage before the output of the reference portion effective pixel.
Before the output of the reference portion effective pixel, the light shielding pixel OPD of the reference portion is output.
This is performed using the output of 92d as a reference voltage.

As described above, the photoelectric conversion output subjected to the dark output compensation is supplied from the terminal 116 to the terminal 11 shown in FIG.
6 is sampled and held by the sample and hold circuit 117. The sample hold circuit 117 includes a transistor Q17, a capacitor C14, and a buffer 118.

The output of the sample-and-hold circuit 117 is used for a contrast control process in the next contrast control circuit 120. When the contrast is low, for example, when the contrast is low, the contrast control circuit 120 increases the contrast by amplifying the photoelectric conversion output with reference to the average level of the photoelectric conversion output. , The signal can be amplified with reference to a predetermined dark reference voltage Vref corresponding to the dark output.

Therefore, a reference voltage serving as a reference level for amplification is applied to the negative input terminal of the differential amplifier 77. The reference voltage supply circuit 130 that supplies the reference voltage includes an average value holding circuit 121 and a dark output reference voltage holding circuit 122. The average value holding circuit 121 outputs the first output signal compensated for darkness.
By inputting the output values of the fourth to fourth islands from the output value of the differential amplifier 77 via the buffer 132, the first island
Then, the average value of the output values of the fourth to fourth islands is calculated and held. This average value holding circuit 121 includes first, second,
The first and fourth islands provided corresponding to the third and fourth islands, respectively.
Second, third, and fourth average value holding circuits 123, 124, 1
25,220. The first average value holding circuit 123 includes a switch transistor Q11, a buffer 126, a capacitor C11, and a switch transistor Q12. The second average value holding circuit 124 includes a switch transistor Q13, a buffer 127, a capacitor C12, and a switch transistor Q14. The third average value holding circuit 125 includes a switch transistor Q15, a buffer 128, a capacitor C13, and a switch transistor Q16. Further, the fourth average value holding circuit 220 includes a switch transistor Q221 and a buffer 2
22, a capacitor C224, and a switch transistor Q223. On the other hand, the dark-time output reference voltage holding circuit 122 includes a terminal 129 to which a dark-time output reference voltage Vref, which is the same voltage as the dark-time output voltage, is provided, and a switch transistor Q10.

Switch transistors Q10, Q12, Q
Only one of the switches 14, Q16, and Q223 is turned on to output the voltage on the input side of the switch transistor. The output voltage of this switch transistor is applied to the negative input terminal of the differential amplifier 77 via the buffer 131. Also, the positive input terminal of the differential amplifier 77 is
The photoelectric conversion output of each island is the sample and hold circuit 1.
17 via a buffer 118.

The contrast control circuit 120 has an average value holding circuit 121 and a dark output reference voltage holding circuit 122. For example, when the contrast is low, the average value of the photoelectric conversion output of each island is used as the reference voltage. The contrast is increased by amplifying the photoelectric conversion output, and when the contrast is high, the photoelectric conversion output is amplified by using a predetermined dark reference voltage Vref corresponding to the dark output as a reference voltage. It is possible to lower the contrast. Then, the amplified photoelectric conversion output of each island is output to the Vout output terminal 135 via the buffer 134.

FIG. 9 is a sensor configuration diagram of a fourth island according to the second embodiment. In this embodiment, the MPD
91a has the same size as the MPDs 81a and 81b (FIG. 4) of the other islands. Instead, the monitor unit 91 includes the charge-voltage converter 9 corresponding to the output amplifier.
By setting the gain (GAIN) of the buffer 1c and the buffer 91c to approximately twice the gain of the charge-voltage converter 81c and the buffer 81d corresponding to the output amplifier of the monitor 81 (FIG. 4) of another island. The sensitivity is substantially the same as the monitor units 81 of other islands having MPDs in both the unit and the reference unit. That is, if the same amount of light is incident on the fourth island as on the other islands, the MP
The amount of charge stored in the monitor unit 91 of the fourth island having the D91a is the MPD 81 in both the reference unit and the reference unit.
Although the amount of charge stored in the monitor unit 81 of the other island having the a and 81b becomes half, the amplification factor of the output amplifier of the monitor unit 91 of the fourth island is increased by the amplification factor of the output amplifier of the monitor unit 81 of the other island. Because the rate is almost twice,
The output voltage from the monitor unit 91 of the island becomes substantially the same as the output voltage from another island.

FIG. 10 is a sensor configuration diagram of a fourth island according to the third embodiment. In this embodiment, MP
D91a has the same size as the MPDs 81a and 81b (FIG. 4) of the other islands. Instead, the monitoring unit 91 sets the capacitor capacitance of the charge-voltage conversion unit 91b to approximately one half of the capacitor capacitance C ′ of the charge-voltage conversion unit 81c of the monitoring unit 81 (FIG. 4) of another island ( 1
/ 2) By setting C ′, the sensitivity is substantially the same as that of the monitor unit 81 of another island having the MPDs 81a and 81b in both the reference unit and the reference unit. That is, if the same amount of light is incident on the fourth island as on the other islands,
The charge amount stored in the monitor unit 91 of the fourth island having the MPD 91a only in the reference portion is half of the charge amount stored in the monitor portions 81 of the other islands having the MPDs 81a and 81b in both the reference portion and the reference portion. However, since the capacitance of the charge-voltage converter 91b of the monitor 91 of the fourth island is approximately one half of the capacitance of the monitor 81 of the other island, V (voltage) = Q (charge amount) From the relational expression of) / C (capacitor capacitance), the output voltage from the monitor unit 91 of the fourth island is substantially the same as the output voltage from the other islands.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, in a general subject, the contrast in the horizontal direction is higher than the contrast in the vertical direction. Therefore, for the horizontal island, the MPD is provided in both the reference portion and the reference portion, and the vertical island is provided. Although the MPD is provided only in the reference portion for the island in the direction, the MPD is provided only in the reference portion for the island in the horizontal direction in order to perform focus detection for a subject having a higher contrast in the vertical direction. May be configured such that MPDs are provided in both the reference portion and the reference portion.

[0044]

As described above, according to the focus detecting device according to the first or second aspect of the present invention, one of the pair of line sensors of the plurality of line sensor pairs has either the reference portion or the reference portion. Since only one of the monitor units is provided and its output is approximately twice as large as the monitor units of the other line sensor pairs, the sensitivity of this monitor unit is different from that of the other line sensor pairs. In other words, even when a plurality of line sensor pairs cross each other, it is not necessary to adopt a configuration in which the monitor unit has a multilayer structure at the crossing portion or bypasses the line sensor. For this reason, the monitor photometry in the horizontal and vertical directions can be accurately performed without complicating the configuration of the sensor, and the size of the sensor can be reduced.

According to the focus detecting device of the third or fourth aspect, the area of the monitor photodiode of the second line sensor pair can be reduced.
The size of the monitor can be further reduced.

[Brief description of the drawings]

FIG. 1 is a perspective view of an optical system constituting a focus detection device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a control system of the focus detection device.

FIG. 3 is a layout diagram of islands in an image sensor of the focus detection device.

FIG. 4 is a sensor configuration diagram of first to third islands of the image sensor.

FIG. 5 is a sensor configuration diagram of a fourth island of the image sensor.

FIG. 6 is a timing chart of a control signal between the image sensor and the microcomputer.

FIG. 7 is a circuit diagram of an analog signal processing unit in the image sensor.

FIG. 8 is a circuit diagram of an analog signal processing unit in the image sensor.

FIG. 9 is a sensor configuration diagram of a fourth island according to the second embodiment.

FIG. 10 is a sensor configuration diagram of a fourth island according to the third embodiment.

[Explanation of symbols]

Reference Signs List 1 focus detection device 81 monitor section (monitor section of second line sensor pair) 81a monitor section photodiode (MPD) 81b reference section monitor section photodiode (MPD) 81c charge-voltage converter 81d buffer (monitor section) Output amplifier) 82a Photodiode array (line sensor of reference section) 82b Photodiode array (line sensor of reference section) 91 Monitor section (monitor section of first line sensor pair) 91a Monitor section photodiode (MPD) of reference section 91c Charge-to-voltage converter 91d Buffer (monitor output amplifier) 92a Photodiode array (line sensor for reference) 92b Photodiode array (line sensor for reference)

Claims (4)

[Claims] 1. A focus detection device comprising: a plurality of line sensor pairs having a monitor unit used for determining a photocurrent integration time; and performing focus detection by a phase difference detection method using the line sensor pairs. Are constituted by a first line sensor pair having a monitor section in only one of the reference section and the reference section, and a second line sensor pair having a monitor section in both the reference section and the reference section. The magnitude of the output of the monitor unit of the first line sensor pair is
A focus detection device wherein the output of the monitor unit of the second line sensor pair is substantially doubled. 2. The area of the monitor photodiode of the first line sensor pair is substantially equal to the area of the monitor photodiode of the reference or reference section of the second line sensor pair.
2. The size of the output of the monitor unit of the first pair of line sensors is approximately twice as large as the output of the monitor unit of the second pair of line sensors by doubling. Focus detection device. 3. An amplification factor of a monitor output amplifier of the first line sensor pair is made approximately twice as large as an amplification factor of a monitor output amplifier of the second line sensor pair.
The magnitude of the output of the monitor unit of the first line sensor pair is
2. The focus detection device according to claim 1, wherein the output of the monitor unit of the second line sensor pair is substantially doubled. 4. The capacitance of the charge-voltage converter of the monitor of the first line sensor pair is reduced to approximately one half of the capacitance of the charge-voltage converter of the monitor of the second line sensor pair. The focus detection according to claim 1, wherein the magnitude of the output of the monitor unit of the first pair of line sensors is made approximately twice as large as the output of the monitor unit of the second pair of line sensors. apparatus.