JPH1032792A - Signal processor and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the deterioration of the recognition work efficiency of a picture and sound by synchronizing first and second encoding data only by means of the detection of second encoding data and transmitting them. SOLUTION: An FIFO memory 23 accumulates an audio stream D2 and the input of a video stream D1 is detected by a signal S2 transmitted when the video stream D1 is accumulated in the half of the FIFO memory 22. Then, a CPU 14 control the starting of the reading/decoding processings of the video stream D1 and the audio stream D2, based on the timing of the signal S1 counted after detection. Thus, data are supplied to a video decoder 24 and an audio decoder 25 in a state where the video stream D1 and the audio stream D2 are synchronized and by data quantity which makes VBV delay to a minimum. Thus, the picture is synchronized with sound and they are outputted without delay.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Technical Field to which the Invention pertains Related Art Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 5) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus and a signal processing method, and more particularly to a signal processing apparatus and a signal processing method for a multiplexing apparatus that encodes and multiplexes a video signal and an audio signal. It is.

[0003]

2. Description of the Related Art Conventionally, in this type of multiplexing apparatus,
A video signal, an audio signal, a caption signal, and the like are encoded to generate a stream of data (hereinafter, referred to as an elementary stream) encoded by each data element such as video, audio, and caption. Each elementary stream is multiplexed with another digital signal sequence to form a bit data flow (hereinafter, referred to as a transport stream) as a transmission form in which each elementary stream is contained within a predetermined frequency band. It has been made to be. Note that the above-described subtitle signal is for displaying multilingual dialogues, subtitles, and the like, which are attached to a screen in a movie or the like.

[0004]

In the above-described multiplexing apparatus, it is necessary to confirm whether or not the image data, the audio data and the additional data have been encoded as intended by using a monitor or the like. desirable. That is, if any loss occurs in each elementary stream generated by the encoding process, it is obvious that loss occurs in the transport stream generated by the subsequent multiplexing process. . Incidentally, it is needless to say that the transport stream formed by the multiplexing is more preferably confirmed in the same manner. By performing such confirmation, it is possible to know in which processing step data loss has occurred. For this reason,
Each of the elementary streams generated in the encoding process is input to a monitor device, which is decoded and output from a monitor screen and a speaker to check whether or not each encoded data has any loss. A method is conceivable.

However, when encoding image data or audio data, the time required for the encoding process differs depending on the data amount of each data. For example, if the encoding process is started at the same timing, Is a state in which the image data has not yet completed the encoding process even though the encoding process has been completed and can be output to the decoder side. In this case, if each encoded data is transmitted to the monitor device at the timing when the audio data has completed the encoding process, only the audio is output and nothing is displayed on the screen.

Accordingly, when each of the data encoded as described above is supplied to a monitor device to check an image, a sound, or the like, an image is generated by a unique delay generated when each data is encoded. In addition, the image and the sound are shifted from each other without synchronizing the sound (so-called Lip Sync). Such a deviation of the lip-sync causes a user who looks at the image and the sound output from the monitor device to perform a check operation to feel uncomfortable. As a human sensation, when the image and the voice match and are synchronized, it is easy to recognize and confirm both data simultaneously. However, if there is a difference between the image and the sound, the visual and auditory senses are individually recognized, so that the user's sense is confused and it is difficult to confirm. For this reason, such a difference between the image and the sound lowers the efficiency of the confirmation operation by the user.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a signal processing apparatus and a signal processing method capable of avoiding a reduction in the efficiency of image and sound confirmation.

[0008]

According to the present invention, there is provided a storage unit for storing first encoded data output from a first encoding unit, and a second encoding unit. Detecting means for detecting second encoded data which requires more time for encoding processing than first encoded data output from the means, and converting the first encoded data according to a detection result of the detecting means. Control means for starting reading.

The first encoded data is stored and the second encoded data is stored in the second encoded data.
The first coded data is detected, and the reading of the first coded data is started at the timing when the second coded data is detected, so that the first coded data is detected only by detecting the second coded data. And the second encoded data can be transmitted in synchronization.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a multiplexing device as a whole, which is roughly classified into an encoding unit 2, a multiplexing unit 3, and a control unit 4.
It is composed of The multiplexing device 1 inputs image data and audio data provided from an external device (not shown) and additional data such as a caption signal to the encoding unit 2. The encoding unit 2 includes a video encoder 5, an audio encoder 6, and a subtitle encoder 7. Image data supplied from an external device to the multiplexer 1 is supplied to the video encoder 5, and audio data is supplied to the audio encoder 6.
Then, additional data is input to the subtitle encoder 7.

The video encoder 5 encodes the image data and converts the obtained video stream into a data size counting interface (hereinafter referred to as a data size IF) 8A and a FIFO (First In First Out) memory 9
Send to A. Also, the audio encoder 6 encodes the audio data, and sends out the obtained audio stream to the data size IF8B and the FIFO memory 9B. Further, the subtitle encoder 7 encodes the additional data, and converts the obtained subtitle stream into a data size I.
The data is transmitted to the F8C and the FIFO memory 9C. Note that the FIFO memories 9A to 9C are so-called buffer memories, and buffer video streams, audio streams, and subtitle streams.

The multiplexing unit 3 stores and stores the video stream supplied from the encoding unit 2 in the FIFO memory 9A, the audio stream in the FIFO memory 9B, and the subtitle stream in the FIFO memory 9C. The switch circuit 10 switches the connection between each terminal on the input side and the terminal on the output side in accordance with a control signal given from the control unit 4, whereby the FIFO memory 9 is switched.
A video stream, audio stream or subtitle stream which is read from A, 9B, 9C and input to each terminal on the input side is selected and multiplexed, and transmitted to the switch circuit 11. Further, the switch circuit 11 switches the connection between each input-side terminal and the output-side terminal in accordance with a control signal given from the control unit 4, so that each elementary stream or control unit given from the switch circuit 10 is switched. 4 is selected and multiplexed, and the transport stream obtained by the multiplexing is output via the FIFO memory 12. The transport stream transmitted from the switch circuit 11 is a SCSI (Small Computer).
The system interface is also supplied to an interface 13 and can be recorded on a recording device such as a hard disk drive connected via the SCSI interface 13.

The control unit 4 has data sizes IF8A to 8C,
CPU (Central Processing Unit) 14, RAM (Ran
dom Access Memory) 15 and 16, Ethernet (Eth)
er-net) An interface 17 and a serial interface 18 are provided. Data size IF8
A counts the data size of the video stream provided from the video encoder 5. Data size IF8
B counts the data size of the audio stream provided from the audio encoder 6. Further, the data size IF 8C counts the data size of the subtitle stream provided from the subtitle encoder 7.
Each data size counted in this manner is stored in the CPU bus 19.
Is supplied to the CPU 14 via the. Further, the Ethernet interface 17 is a LAN (Loca) such as an Ethernet.
lArea Network) (not shown), receives additional data for subtitles, and supplies it to the CPU 14 via the CPU bus 19. Further, the serial interface 18 accepts, for example, additional data in a serial format input from a computer and supplies it to the CPU 14 via the CPU bus 19.

The CPU 14 is, for example, a microprocessor,
RO for storing a processing procedure program for multiplexing processing
M and their peripheral circuits. CPU1
4 temporarily stores the data size of each elementary stream supplied from the data size IFs 8A to 8C in the RAM 15, and based on the data size and the program stored in the ROM, the order in which each elementary stream is multiplexed, Multiplexing procedures such as timing adjustment for scheduling and scheduling. CPU
14 controls the switching of the switch circuits 10 and 11 via the CPU bus 19 according to the processing procedure thus planned. Further, the CPU 14 stores the additional data input from the Ethernet interface 17 or the serial interface 18 in the RAM 15, performs predetermined processing on the additional data, and outputs header information multiplexed to the header portion of each elementary stream. Generate. CPU
14 reads out the generated header information from the RAM 15 and sends it to the switch circuit 11.

Next, the procedure of such a multiplexing process is described as CP
A description will be given based on the processing procedure of U14. As shown in FIG. 2, the CPU 14 starts the procedure in step SP1. C
The PU 14 has the data size IF8A in step SP2.
The data size of the video stream, audio stream, and subtitle stream supplied from 〜8C is received and temporarily stored in the RAM 15. Then CPU1
Reference numeral 4 denotes a step SP3, which plans a processing procedure for the multiplexing process based on the data size of each elementary stream. Specifically, as described above, the order of multiplexing each elementary stream, timing adjustment for multiplexing, scheduling, and the like are set.

At step SP4, the CPU 14 determines whether or not the elementary stream to be output at that time is a video stream. Here, the CPU 14
If the multiplexing plan set in P3 indicates that a video stream is to be output at that time, the process proceeds to step SP5, and if it does not indicate that a video stream is to be output at that time, the process proceeds to step SP6. If the CPU 14 determines that the video stream is to be output, it switches the connection so as to select the FIFO memory 9A by controlling the switch circuit 10 in step SP5.

At step SP6, the CPU 14 determines whether the elementary stream to be output at that time is an audio stream. Here CPU1
Step 4 proceeds to step SP7 if the multiplexing plan set in SP3 indicates that an audio stream is to be output at that time, and proceeds to step SP8 if it does not indicate to output an audio stream at that time. . If the CPU 14 determines that the audio stream is to be output, the process proceeds to step SP7 where the switch circuit 10 is output.
To switch the connection so as to select the FIFO memory 9B. If the elementary stream to be output is not a video stream or an audio stream, the CPU 14 selects the output of the subtitle stream in step SP8. That is, the CPU 14 controls the switch circuit 10 to switch the connection so as to select the FIFO memory 9C.

At step SP9, the CPU 14 determines whether or not to add header information to the elementary stream sent to the switch circuit 11 via the switch circuit 10. The CPU 14 proceeds to step SP10 if the multiplexing plan set in SP3 indicates that header information is to be added at that time, and if not, it indicates step SP1 if it does not indicate to add header information at that time.
Proceed to 1. If the CPU 14 determines to add the header information, the CPU 14 controls the switch circuit 11 to switch the connection so as to select the input terminal on the RAM 15 side in step SP9. Here, the RAM 15 is previously stored in the Ethernet interface 17 or the serial interface 18.
And additional data such as subtitles input via the PC. The CPU 14 sends the header information generated by processing the additional data to the switch circuit 11 and multiplexes it into a transport stream.

On the other hand, if the CPU 14 determines that the header information is not added, the connection is switched so as to select the input terminal of the switch circuit 10 by controlling the switch circuit 11 in step SP11. The CPU 14 controls the switch circuit 10 to selectively transmit each elementary stream, and controls the switch circuit 11 to add header information to convert each elementary stream and header information into one transport stream. Multiplex. After transmitting the header information or the elementary stream from the switch circuit 11, the CPU 14 determines whether or not all the multiplexing processes of the elementary stream have been completed in step SP12. CPU1
Step 4 is a step SP1 if all the multiplexing processes are completed.
Proceed to 3 to end the procedure. On the other hand, if the multiplexing process has not been completed, the process returns to step SP2 to continue the multiplexing process.

The multiplexing apparatus 1 selects a video stream, an audio stream or a subtitle stream in accordance with such a processing procedure, and multiplexes each elementary stream read out by repeating such selection continuously in a time-division manner. And send it out,
A transport stream in which each elementary stream is multiplexed into one is formed and output.

In FIG. 3, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, reference numeral 20 denotes a monitor as a whole, and a video encoder 5 (FIG. 1) and an audio encoder 6 of the multiplexer 1 (FIG. 1). (FIG. 1). The monitor device 20 inputs the video stream D1 obtained by encoding by the video encoder 5 and the audio stream D2 obtained by encoding by the audio encoder 6 to the signal processing unit 21.

The signal processing section 21 is a FIFO which is a detecting means.
It comprises a memory 22, a FIFO memory 23 as storage means, and a CPU 14 as control means. The video stream D1 input to the signal processing unit 21 is supplied to a FIFO memory 22. The audio stream D2 input to the signal processing unit 21 is supplied to the FIFO memory 23. At this time, the video encoder 5 sends a frame signal (hereinafter, referred to as V-Syn) to the CPU 14 as a control unit, which indicates a boundary between image frames of the video stream D1.
c1) is supplied.

A predetermined data storage amount is set in the FIFO memory 22 in advance. The supplied video stream D1 is stored and stored. When the video stream D1 has been stored to half of the total storage capacity, the DecOK signal is output. S2 is sent to the CPU 14. Incidentally, the memory used as the FIFO memory 22 has a function of outputting a signal called a half flag conventionally, and outputs this half flag when the data storage amount has become half of the total capacity. The signal processing unit 21 sets this half flag to Dec.
Used as the OK signal S2.

While counting the V-Sync signal S1 supplied from the video encoder 5, the CPU 14
It waits for the DecOK signal S2 sent from the FO memory 22. When the DecOK signal S2 is given, the CPU 14 determines that a video stream of a desired and sufficient data amount has been buffered in the FIFO memory 22. At this time, the CPU 14 waits for the next input timing of the V-Sync signal S1 counted at the time when the DecOK signal S2 is input. In this way, when the V-Sync signal S1 at the next timing is input, the CPU 14 sets the FIFO memories 22 and 23 and the video decoder 24
And a control signal S3 to the audio decoder 25.

For example, in the MPEG system, a predetermined image frame (so-called I-picture) is used as a reference, and frames before and after the image frame (so-called B-picture and P-picture) are extracted and compressed only in a difference portion from the image frame. Therefore, the decoding process cannot be performed unless a plurality of image frames including a predetermined image frame are aligned. Therefore, the video decoder 24
A memory (not shown) for storing the supplied elementary stream is provided in the audio decoder 25, and the decoding process is started after a predetermined amount of data is accumulated in the memory. The delay from when the data is supplied to when the decoding process is actually started is called a VBV (Video Buffering Verifire) delay. The monitor device 20 includes such a video decoder 24
A sufficient amount for supplying the above-mentioned predetermined amount of data to the memory in the audio decoder 25 is set as a desired amount, and when the desired amount is secured in the FIFO memories 22 and 23, the video stream D1 and the audio stream By transmitting D2, generation of VBV delay is minimized.

Further, as shown in FIG.
2 to the DecOK signal S2 given to the CPU 14 and V-Sy indicating the boundary of each video stream for each frame.
The nc signal S1 is not always transmitted at the same timing. Therefore, when the supply of the video stream D1 to the video decoder 24 is started at the timing when the DecOK signal S2 is transmitted, a video frame that is decoded in an incomplete state occurs. That is, the FIFO memory 22 sends out the DecOK signal S2 when the video stream D1 is accumulated up to Ds / 2, which is half of the total storage capacity Ds. In addition, the video encoder 5 uses the VS to indicate the boundary of each frame in the video stream D1.
The SYNC signal S1 is transmitted. Here, A1 and A2 indicate the ranges of the first frame and the second frame of the video data encoded by the video encoder 5, respectively.

However, it is conceivable that the video stream D1 stored in the FIFO memory 22 stores only the data amount indicated by ds as the data of the frame A2 when the DecOK signal S2 is transmitted. When the decoding process is started by supplying the video stream D1 in which an insufficient amount of data is accumulated as one image frame to the video decoder 24, the monitor device 2
0 can only display frame A2 as an incomplete image. Specifically, a portion where the image frame is displayed only halfway and the amount of data is insufficient is cut off. Such loss of image frames is more remarkable in a video stream having a larger amount of data per frame. For example, when storing a video stream in which one frame of image data is sufficiently large compared to half the storage capacity of the FIFO memory 22, the FIFO memory 22 stores DecOK before storing the data amount of one frame for most image frames. It sends out the signal S2. For this reason Dec
When the reading and decoding processing of the accumulated video stream D1 is started with the OK signal S2 as a trigger, most of the image frames can perform only the incomplete display as described above.

When the next V-Sync signal S1 to which the DecOK signal S2 has been sent is given to the CPU 14, the monitor device 20 triggers the reading and decoding of the stored elementary stream by using this signal as a trigger. In this way, the video stream D1 is supplied to the video decoder 24 in a state where the data amount for at least one frame is secured, thereby preventing incomplete image display. In addition,
Such a synchronization process based on the control signal S3 may be performed only once at the time of reading data and starting the decoding process.
Further, the monitor device 20 outputs the V-Sync signal S1
By transmitting the control signal S3 at a timing based on the OK signal S2, a complicated calculation process or the like for synchronizing each elementary stream is not required, and the load on the CPU 14 is reduced.

Video decoder 2 as image signal decoding means
4 is given the control signal S3 when the control signal S3 is given.
3, the video stream D1 read from the FIFO memory 22 is input, and the decoding process is started. The video decoder 24 supplies the video data D3 obtained by the decoding process to the image display unit 26. Similarly, when receiving the control signal S3, the audio decoder 25 serving as the audio signal decoding means inputs the audio stream D2 read from the FIFO memory 23 in response to the control signal S3, and starts decoding. The audio decoder 25 supplies the audio data D4 obtained by the decoding process to the audio output unit 27. The image display unit 26 and the audio output unit 27, which are output means, are thus provided with the video decoder 24 and the audio decoder 25.
Image display and audio output based on the video data D3 and the audio data D4 supplied from.

Next, the monitor device 20 sets the video stream D
A signal processing method for synchronizing and outputting the audio stream D1 and the audio stream D2 will be described according to a processing procedure of the CPU 14 described below. As shown in FIG. 5, the CPU 14 starts the procedure at step SP1. In step SP2, the CPU 14 clears the count of the V-Sync signal S1 to zero. Next, in step SP3, the CPU 14 counts each time the V-Sync signal S1 is given from the video encoder 5. Here, the video streams D1 and the audio streams D2 are supplied to the FIFO memories 22 and 23, respectively, and are sequentially stored and accumulated.

Subsequently, the CPU 14 proceeds to step SP4.
It detects whether or not the DecOK signal S2 has been input from the FIFO memory 22. The CPU 14 outputs the DecOK signal S2
When it is detected that is not input, V-Sync
The counting of the signal S1 is continued (SP2). On the other hand, De
When it is detected that the cOK signal S2 has been input, the process proceeds to the next step. When the DecOK signal S2 is input, the CPU 14 waits for the next count of the V-Sync signal S1 in step SP5. When the next count of the V-Sync signal S1 is detected, the CPU 14 proceeds to step SP.
At step 6, the control signal S3 is output to read the video stream D1 and the audio stream D2 stored in the FIFO memories 22 and 23, and the decoding process of the video decoder 24 and the audio decoder 25 is started. After outputting the control signal S3, the CPU 14 ends the procedure at step SP7.

In the above configuration, the monitor device 20
Generally, the audio stream D2 whose encoding process is completed first is buffered. Thereafter, the monitor device 20 detects that the encoding process of the video stream D1 is completed by the DecOK signal S2, and starts the reading and decoding processes at this timing to synchronize the two. As a result, without detecting the amount of data stored in the audio stream D2, it is possible to easily synchronize the two just by detecting the input of the video stream D1 for which encoding processing has been completed. Lip sync of audio data obtained by decoding image data and audio stream D2 to be obtained can be obtained.

The monitor device 20 is provided with a FIFO memory 2
The half flag provided as an existing function in
The ecOK signal S2 is used to detect the input of the video stream D1 that has been subjected to the encoding process based on whether or not the ecOK signal S2 has been transmitted. Therefore, the input of the video stream D1 can be easily performed without adding a new configuration. Can be detected.

Further, the monitor device 20 outputs a V-Sync signal S indicating a boundary between image frames of the video stream D1.
1 is counted by the CPU 14, and the DecOK signal S
2, the reading and decoding processing of the video stream D1 is started at the timing of the V-Sync signal S1 counted after the input of the video stream D1 is detected, so that the data of one frame is surely obtained. At the secured stage, the video stream D1 can be decoded.

According to the above configuration, the FIFO memory 23
The audio stream D2 is stored by the
The input of the video stream D1 is detected by the DecOK signal S2 sent when the video stream D1 is stored in the O memory 22 up to half, and based on the timing of the V-Sync signal S1 counted after the detection,
The CPU 14 controls reading and decoding of the video stream D1 and the audio stream D2 to start. As a result, the video stream D1 and the audio stream D2 can be supplied to the video decoder 23 and the audio decoder 24 in a synchronized state and with a data amount capable of minimizing the VBV delay, respectively.
Furthermore, the video stream D1 can be decoded at least at the stage when the data amount for one frame is ensured. In this way, the image and the sound can be synchronized and output without delay, and a reliable image display can be realized.

In the above embodiment, the video stream as the second encoded data and the audio stream as the first encoded data are sequentially written,
Under the control of the CPU 14 as a control means, F sequentially reads out the elementary streams in the order in which they are written.
Although the case where the IFO memories 22 and 23 are used has been described, the present invention is not limited to this.
In addition, various memory means may be applied.

In the above embodiment, the video stream D1 and the audio stream D2 are read from the FIFO memory 22 as the detecting means and the FIFO memory 23 as the storing means, and the decoding processing by the video decoder 24 and the audio decoder 25 is performed. As a trigger for controlling the start by the CPU 14 as a control means, F
The DecOK signal S2 sent from the FIFO memory 22 is used, and this DecOK signal S2 is used as the FIFO memory 2
However, the present invention is not limited to this. For example, a full flag indicating that the entire storage capacity has been stored may be used, and a desired amount of video stream is stored in the memory. The same effect as that of the embodiment can be obtained even if other signals are used as long as the signals notify that the signals have been transmitted.

Further, in the above-described embodiment, the case where the CPU 14 which is the control means of the multiplexer 1 is shared as the control means of the monitor device 20 to which the signal processing device is applied, but the present invention is not limited to this. Alternatively, a separate CPU may be provided for each of the multiplexing device and the monitor device.

[0040]

As described above, according to the present invention, the storage means for storing the first encoded data output from the first encoding processing means and the output from the second encoding processing means are provided. Detecting means for detecting second coded data which requires more time for the coding process than the first coded data, and control means for starting reading of the first coded data in accordance with the detection result of the detecting means Is provided, the first encoded data is stored, the second encoded data is detected, and the reading of the first encoded data is started at the timing when the second encoded data is detected. Thus, the first and second encoded data can be transmitted in synchronization only by detecting the second encoded data, thereby avoiding a reduction in the efficiency of the image and audio confirmation work. The signal processing device and the signal processing method It can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a multiplexing device.

FIG. 2 is a flowchart provided to explain a multiplexing processing procedure of each elementary stream.

FIG. 3 is a block diagram showing an embodiment of a monitor device to which the signal processing device according to the present invention is applied.

FIG. 4 is a schematic diagram for explaining a phase shift of a DecOK signal with respect to a V-Sync signal and a correction thereof;

FIG. 5 is a flowchart for explaining a processing procedure of a signal processing method according to an embodiment.

[Explanation of symbols]

1 multiplexing device, 2 coding unit, 3 multiplexing unit,
4 ... Control unit, 5 ... Video encoder, 6 ... Audio encoder, 7 ... Subtitle encoder, 8
A, 8B, 8C: Data size IF, 9A, 9B, 9
C, 12, 22, 23 ... FIFO memory, 10, 11
... Switch circuit, 13 SCSI interface, 14 CPU, 15, 16 RAM, 17
Ethernet interface, 18 Serial interface, 19 CPU bus, 20 Monitor device, 21 Signal processing unit, 24 Video decoder, 2
5 Audio decoder 26 Image display 27
... Audio output unit.

Claims (6)

[Claims] A first encoding means for outputting the first encoded data;
Storage means for storing the encoded data of the second encoding processing means, and detection for detecting the second encoded data which requires a longer time for the encoding processing than the first encoded data output from the second encoding processing means. Means, and control means for starting reading of the first encoded data in accordance with the detection result of the detection means, wherein the first and second encoded data are output at synchronized timing. Signal processing device. 2. The method according to claim 1, wherein the detecting means is a memory for storing the second coded data. When the data amount of the stored second coded data reaches a predetermined data amount, the second detecting means stores the second coded data. 2. The signal processing device according to claim 1, wherein a detection signal indicating that said encoded data is detected is sent to said control means. 3. The control means detects an image frame boundary of the second encoded data composed of video data, and detects a timing after the detection of the second encoded data by the detection means. Reading the first encoded data at a timing when the image frame boundary is detected.
The signal processing device according to claim 1. 4. The method according to claim 1, further comprising the step of: storing the first encoded data to be inputted; detecting second encoded data which requires more time for encoding processing than the first encoded data; A signal processing method for outputting the first and second encoded data at a synchronized timing by starting to read the first encoded data in response thereto. 5. The signal processing method according to claim 1, wherein the second encoded data is stored, and when the data amount of the second encoded data reaches a predetermined data amount, the second encoded data is stored in the second encoded data. The signal processing method according to claim 4, wherein the detection is performed. 6. The signal processing method according to claim 1, wherein: after the timing at which the second encoded data is detected, at the timing at which an image frame boundary of the second encoded data comprising video data is detected. 5. The signal processing method according to claim 4, wherein the encoded data is read.