JPH1032786A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a non-use area by efficiently using a memory for signal processing at a digital VTR. SOLUTION: At the time of ordinary recording and reproducing, reproduced data are decoded by encoding and recording signals while using three frame banks 0, 1 and 2. At the time of search, the encoded data reproduced during the period of frame 1 are written as shown by dotted lines and data written after one track are written back after their errors are corrected. Parallelly with this operation, encoded data are read out of the bank 2 and decoded. During the period of the next frame 2, decoding is performed concerning the bank 1 and writing and error correction are performed concerning the bank 2. Therefore, the bank 0 is made excess, this bank can be effectively used for other processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal processing apparatus which performs processing such as encoding and decoding of image data and the like which is particularly suitable for use in recording and reproducing with a VTR or the like.

[0002]

2. Description of the Related Art Hitherto, various devices have been proposed for encoding various data having an enormous amount of data to reduce the amount of data so that the data can be transmitted at a relatively low transmission rate. For example, a digital VTR that records image data on a recording medium such as a magnetic tape also has
Input data of about 24 Mbps is reduced to 1/5 of 25 Mbps
Standards have been established for recording data on a magnetic tape after being compressed to about s and reproducing the data. In a digital VTR based on such a standard, input data is DCT-transformed and then quantized, and the quantized data is subjected to variable-length encoding to compress the data. Is varied according to various parameters, and rate control is performed so that the data amount after variable-length coding becomes constant.

In addition, input data is compressed using predictive coding with motion compensation between frames (fields), and this predictive coded data is further compressed using DCT, quantization and variable length coding as described above. The MPEG standard is being enacted, and a CD-RO compatible with this standard has been established.
Various devices such as M have also been developed.

FIG. 6 is a diagram for explaining the MPEG encoding method. In the figure, the direction of prediction in encoding is indicated by an arrow. FIG. 7 shows MPEG (Moving Picture Exp).
ertGroup) Encoding in encoding method (encoding)
FIG. 9 is an explanatory diagram showing an order of image data by processing, arrangement on a medium, and decoding (decoding) processing.

As shown in FIG. 6, in the MPEG encoding method, a GOP (Group of Pictu
re). The GOP includes at least one intra-coded image I. Intra-coded image I is DCT
One frame of image data is encoded by (discrete cosine transform). One frame of image data for each predetermined a frame from the intra-coded image I is converted into a forward prediction coded image P. Further, the image data of each frame between the intra-coded image I or the first forward predictive coded image P1 and the second forward predictive coded image P2 is bidirectional using forward and backward image data. The image is converted to a bidirectionally coded image B by predictive coding.

As shown in FIG. 7, first, an intra-coded image I is encoded. The intra-coded image I is encoded only by information in the frame, and does not include prediction in the time direction. Next, a forward prediction coded image P is created,
After the intra-coded image I or the forward predicted coded image P, the coding process of the bidirectional predicted coded image B is performed. The forward predictive coded image P and the bidirectional predictive coded image B utilize correlation with other image data. As described above, due to the prediction method of each image data, the bidirectionally predicted coded image B is the intra-coded image I or the forward predicted coded image P
Is recorded on the recording medium after, and is restored to the original order at the time of decoding.

[0007] Since the intra-coded image I is encoded only by information in the frame, it can be decoded only by the single encoded data. On the other hand, the forward prediction coded image P and the bidirectional prediction coded image B are coded using the correlation with other image data, and cannot be decoded only by the single coded data. ing.

As described above, the MPEG encoding / decoding apparatus performs forward or bidirectional prediction.
A storage means is required to make a comparison between the predicted image and the encoded image. In a conventional encoding / decoding device using the above various devices, a plurality of independent memories are used. That is, for example, in the case of a digital VTR, a video memory for temporarily storing input image data, a track memory for storing encoded data after the encoding process is completed, and the like are necessary. The memories were provided individually. In the apparatus based on the MPEG standard, a plurality of independent memories such as an input buffer and a reference buffer for motion compensation are provided.

In the above-described devices, a plurality of memories are individually provided and independently controlled, so that the cost must be increased. For this reason, there has been a proposal to use a single storage device for a plurality of encoding / decoding processes.

[0010]

However, in a signal processing device in which a single storage device is used for a plurality of encoding / decoding processes, an area on a memory accessed by each processing means is previously determined. Due to the decision, not all of the storage cells on the memory are always used. Further, depending on the mode of the signal processing device, there is a problem that an unused portion may appear in a wide range on the memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a multi-functional signal processing device which reduces a non-use area on a memory without increasing costs. I do.

[0012]

According to the first aspect of the present invention, there are provided a plurality of processing means for performing a plurality of different processes in a predetermined data unit, and a plurality of processing means provided in common with each of the processing means for inputting the data in the predetermined unit. Storage means for outputting, and control means for performing access control between each of the processing means and the storage means, wherein the control means is capable of accessing each of the processing means in accordance with the processing of each of the processing means. The capacity of the storage means is dynamically changed.

According to a sixth aspect of the present invention, in a signal processing apparatus used in a recording / reproducing apparatus for recording / reproducing coded image data, an input signal is encoded at the time of recording and the encoded image data reproduced at the time of reproduction is decoded. Encoding / decoding processing means for converting, and first, second, and third storage means used for the encoding / decoding processing at the time of recording / reproducing;
Control means for controlling the encoding / decoding processing means and the first and second storage means at the time of a search, wherein the control means includes means for controlling the reproduction of the encoded image data during a first frame period. Is written in the first storage means, and the encoded data written in the second storage means is decoded. In the next second period, the writing and the writing for the first and second storage means are performed. The decoding process is performed in a manner opposite to the first frame period.

[0014]

According to the first aspect of the present invention, the use area of the storage means changes according to the signal processing, and the storage means is used effectively.

According to the sixth aspect of the present invention, three storage means are used during normal recording / reproduction, but only two storage means are used during a search. It can be used for processing, and the storage means is used effectively.

[0016]

FIG. 1 is a block diagram showing a basic configuration according to an embodiment of the present invention applied to a digital VTR. In the present embodiment, as shown in FIG. 1, various processing blocks are controlled by internal / external CPUs, each accesses a memory at a desired timing, and the memory control unit arbitrates those access requests. , Are configured to guarantee the operation of the processing block. Each processing block in FIG. 1 can perform real-time processing of SD-compatible image data. In the present embodiment, such processing units are arranged in parallel, and image data is time-divisionally allocated to each processing block. It is configured to supply and process.

In FIG. 1, reference numeral 1 denotes a data input / output (hereinafter, I / O) for inputting / outputting input data from a camera (not shown), output data to an EVF, and line input / output data.
O) block, 3 input data from camera, E
Y / for output data to VF and line input / output data
Image data input / output block for processing such as C separation, 5
Is an audio processing block that processes audio signals, 7 is an encoding / decoding block that performs variable-length encoding / decoding using discrete cosine transform on image data, and 9 is the addition or error correction of an error correction code. An error correction block 11 for converting the data coded by the coding / decoding block 7 into a tape format at the time of recording, or a coded data input / output (I / O) for performing a data format conversion at the time of reproduction The block 13 is an address conversion circuit for converting an access request to the memory 17 of each processing block, which will be described later, into an address on an actual memory. Memory interface, 1
Reference numeral 7 denotes a memory capable of high-speed input / output such as an SDRAM.

Reference numeral 19 denotes a system control CPU for comprehensively controlling each processing block. Reference numeral 21 denotes a servo CPU 23 to be described later and the system control CPU 19
An interface 23 for exchanging commands with the CPU 23, a servo CPU 23 for performing control such as a tape speed control (not shown), and a data 25 input / output by the coded data I / O block 11 during recording / reproduction. An electromagnetic conversion processing block 27 for performing the electromagnetic conversion processing described above, a frequency oscillator 27 for supplying a clock signal as a timing signal to each processing block, and a clock signal 29 output from the frequency oscillator 27 to an appropriate frequency for each processing block. A frequency multiplier for multiplying and distributing a clock signal to each processing block, 31 is a reference clock generator for generating a reference clock used when the image data I / O block 3 inputs and outputs an image signal, and 33 is a memory Still image input / output (I / I) for inputting / outputting still image data stored in
O) Block, CBS1 is a first CPU bus for supplying a command from the servo CPU 23 to each processing block, and CBS2 is a second CPU for supplying a command from the system control CPU 19 to each processing block.
It is a bus.

Next, the operation will be described. The processing unit includes, as shown in FIG.
I for processing output data to VF and line input / output data
/ O block 1, image data input / output block 3 for performing processing such as Y / C separation on the data, audio processing block 5, and variable-length encoding / decoding using discrete cosine transform for image data. An encoding / decoding block 7 to be performed, an error correction block 9, an encoded data input / output block 11 for converting the encoded data into a tape format at the time of recording or performing a deformatting process at the time of reproduction, and an electromagnetic at the time of recording / reproduction. It is roughly composed of an electromagnetic conversion processing block 25 for performing a conversion process, and each of these blocks exchanges data with an external memory 17 via an address conversion circuit 13 and a memory interface 15.

The operation of these processing blocks is performed by a system control CPU 19 which controls internal electric system processing.
From the external servo CPU 23 to the CPU bus CBS2.
Controlled by a predetermined command supplied via the BS1, the interface 21, and the CBS2, each processing block arranged in parallel is subjected to time division processing.

The memory 17 is, for example, an SDRAM (Synchronous-DRAM) capable of performing burst transfer of data in synchronization with a rising edge of a clock. In addition, a clock of, for example, 27.5 MHz is supplied from the external frequency oscillator 27 having no jitter to the frequency multiplier 29 in the unit, and the frequency multiplier 67.5M is generated therefrom.
Hz is supplied as a reference clock.

Each memory space of such a memory 17 is:
A video memory (VM) area having a capacity for one frame, and a track memory (TM) area also having a capacity for storing encoded data for one frame. Can be set to a writing mode and a reading mode for each frame, and each of the processing blocks exchanges data with the VM area or the TM area according to the processing mode.

Next, the address space of the memory 17 accessed by each block will be described with reference to FIG. 2, the same numbers as those in FIG. 1 indicate the same functions. As shown in FIG. 2, the image data input / output block 3 is exclusively V
The encoding / decoding block 7 transmits / receives data to / from the M area via the sense amplifier, and transmits / receives data to / from both the VM area and the TM area via the sense amplifier. During the encoding operation, data is read from the VM area and subjected to the encoding process, and then written into the TM area. At the time of the decoding operation, the data is read from the TM area, decoded, and then written into the VM area. The audio processing block 5, the error correction block 9, and the coded data I / O block 11 exclusively exchange data with the TM area.

In the TM area, image data (Y, Cr, Cb) before being encoded is written in pixel units, and this image data (in the case of NTSC, 7 horizontal lines per frame).
20 pixels x 480 pixels vertically) is 5 blocks in the horizontal direction x
The blocks are allocated to 10 blocks in the vertical direction, that is, 50 super macroblocks (hereinafter, referred to as SMBs), and each SMB is a macroblock (hereinafter, referred to as MB) including 4 DCT blocks of luminance data and 1 DCT block of chrominance data.
Are collected in 27 blocks. Note that each DCT
A block consists of 8 × 8 pixels. In the case of the NTSC system, one frame of image data having the number of pixels as described above is encoded and then recorded over 10 tracks on the magnetic tape (12 tracks in the case of the PAL system). In the previous image data, 5 SMB data aligned in the horizontal direction as described above is recorded on 11 tracks. Therefore, addresses for accessing this VM area include h, v, track number Tr, and track number corresponding to the horizontal and vertical directions of each pixel, respectively.
It is desirable to use the SMB number in each track, the MB number in each SMB, and the DCT number in each macroblock.

On the other hand, in the TM area, encoded pixel data and error correction codes are distributed and recorded on the above-described 10 tracks (12 tracks in the case of PAL), and are recorded in areas corresponding to each track. Is recorded with 149 sync blocks (hereinafter referred to as SB). Each SB of the image data is synchronized data (hereinafter SY) indicating the head of the SB.
), ID data (hereinafter, referred to as ID) indicating each address and attribute of the signal, valid (image) data, and parity. Therefore, as addresses when accessing the TM area, the track number Tr, the sync block number in each Tr (hereinafter, referred to as SB), and the symbol number in each SB (hereinafter, referred to as SMB).
It is desirable to use

Access of each processing block to the memory 17 as described above is arbitrated and controlled by the address conversion circuit 13. That is, the address conversion circuit 13 receives a command for designating the type of various modes such as the reproduction mode or the recording mode from the internal CPUs 19 and 23 via the CBS 2 or directly transmits a predetermined bit of the address of each processing block. The above-mentioned mode is transmitted, and the scheduling regarding the priority of data transfer is performed according to the above information, and the communication between each processing block and the memory 17 is performed according to an access request (hereinafter, referred to as Req) from each processing block. Arbitration of data transfer between

The above-mentioned command sets the operation mode set by each switch of the apparatus main body to the internal or external CPU.
Is determined by detecting the signal, and corresponds to various operation modes such as an encoding mode, a decoding mode, and a special reproduction mode in a VTR.

On the other hand, each processing block is supplied with a required clock, and operates in synchronization with the clock. These clocks include: Synchronization signals Hsync, V extracted from the input signal
A first clock (13.5 MHz in the present embodiment) supplied to the image data input / output block 3 and synchronized with an input signal based on a sync and an internal reference clock.
z)

2. Second clock (67.5 MHz in the present embodiment) supplied to encoding / decoding block 7, error correction block 9, address conversion circuit 13, memory interface 15, and memory 17

3. A third clock (41.85 MHz in the present embodiment) for recording / reproducing on / from a recording medium with a clock supplied to the encoded data input / output block 11 from the electromagnetic conversion processing block and synchronized with the rotation of the drum.
There is. Each processing block performs a processing operation according to each of the supplied clocks.

Next, access to the memory during normal recording and reproduction will be described with reference to FIGS. 3 (a) and 3 (b). FIGS. 3A and 3B are diagrams showing the access timing of each processing block to the memory 17 in the above configuration. The horizontal axis indicates the processing time, and the vertical axis indicates the address of the TM area (three frames). FIG. 3A shows the state of FIG.
(B) shows the timing at the time of recording. The hatched area indicated by a indicates the access of the encoding / decoding block 7, and the broken line indicates the encoded data input / output block 11
Indicates access. The black area indicated by b indicates access to the error correction block 9.

First, the case of reproduction, that is, the case of FIG. 3A will be described. During the time of frame 1, the coded data input / output block 11 uses the track 0 of the bank 0 in the TM area.
, Data is sequentially written as indicated by a broken line, and data for 10 tracks is written in a time corresponding to one frame. At this time, the error correction block 9
Reads data sequentially from a region written by the encoded data input / output block 11 with a time (1/10 frame) corresponding to one track behind the encoded data input / output block 11 as shown by b, and corrects the error. Later, the data after error correction is written back to the same address. The above operation of the error correction block 9 is called write-back.

On the other hand, the encoding / decoding block 7 has the TM
Regarding the bank 2 that is not accessed by the encoded data input / output block 11 in the area, first, decoding is performed in the even track area, and after decoding all, decoding is performed in the odd area.

During the time of the next frame 2, the coded data input / output block 11 and the error correction block 9 take ba.
nk1 and the encoding / decoding block 7
nk0 is accessed and the same processing as the above processing is performed.
For the time of the subsequent frame 3, the coded data input / output block 11 and the error correction block 9
k2, and the encoding / decoding block 7
By accessing k1, the same processing as the above operation is performed.

Next, the case of recording, that is, the case of FIG. 3B will be described. First, during the time of frame 1, the encoding / decoding block 7 sequentially decodes the even-numbered track area of the bank 2 in the TM area, and decodes the odd-numbered area after completing all. The coded data input / output block 11 executes the bank1 in parallel with the processing with the coding / decoding block 7.
Are sequentially read from the track 0 and output to the electromagnetic conversion processing block 25. At this time, the error correction block 9
Adds an error correction code to the area accessed by the encoded data input / output block 11 one track time (1/10 frame) earlier.

During the time of the next frame 2, the coded data input / output block 11 and the error correction block 9 take ba.
nk1 and the encoding / decoding block 7
nk0 is accessed and the same processing as the above processing is performed.
For the time of the subsequent frame 3, the coded data input / output block 11 and the error correction block 9
k2, and the encoding / decoding block 7
By accessing k1, the same processing as the above operation is performed.

Next, an access operation at the time of a search will be described with reference to FIG. FIG. 4 is a diagram showing the access timing to the memory at the time of the search. At the time of search, it has a two-frame configuration. As in FIG. 3, the horizontal axis indicates the processing time, and the vertical axis indicates the address of the TM area (two-frame configuration). FIG.
In the figure, the shaded area indicated by a indicates access of the encoding / decoding block 7 and the broken line indicates access of the encoded data input / output block 11. The black area indicated by b indicates access to the error correction block 9.

At the time of frame 1 during the search, the coded data input / output block 11
Data is sequentially written from an address corresponding to track 0 of nk1, and data for 10 tracks is written in a time corresponding to one frame. At this time, the error correction block 9
Reads data sequentially from a region written by the encoded data input / output block 11 with a delay (1/10 frame) corresponding to that of the encoded data input / output block 11, and performs write back after error correction.

On the other hand, the encoding / decoding block 7
Regarding the bank 2 that is not accessed by the encoded data input / output block 11 in the area, first, decoding is performed in the even track area, and after decoding all, decoding is performed in the odd area.

During the time of the next frame 2, the coded data input / output block 11 and the error correction block 9 take ba.
nk2 and the encoding / decoding block 7
nk1 is accessed, and the same processing as the above processing is performed.

According to the above operation, bank0 becomes an unnecessary area. In the search mode, the system control CPU 19 sends a bank instruction to the still image I / O block 33.
0 access is allowed. Still image I / O block 3
Reference numeral 3 denotes a bank operation for transferring a still image recorded in advance at the time of recording by the arbitration operation of the system control CPU 19 to the bank.
After being stored in 0, it is output to the outside. By the above operation, a still image can be output in the background by efficiently accumulating and outputting the still image to the bank0 during the search.

Next, the present invention relates to an ATV using MPEG-2.
A second embodiment applied to a (Advanced Television) decoder will be described with reference to the drawings. 5, 101 is an input terminal, 103 is a data input circuit, 1
05 is a system decoder, 107 is a video coder, 10
9 is an audio decoder, 111 is a video output circuit, 1
13 is an audio output circuit, 115 is an address conversion circuit, 117 is a memory interface circuit, and 119 is S
A memory such as a DRAM, 121 is a system controller, 123 is an audio output terminal, 125 is a video output terminal, and 127 is a system bus.

In the MPEG-2 system, a coded image signal, audio signal, or other bit string is called an elementary stream. A PES (Packetized Elementary Stream) packet is defined as a structure for carrying an elementary stream. This is the PES header followed by the PES
It has a structure followed by a payload. In MPEG-2, a set of elementary streams having a common time base is called a program. Two formats are defined for encoding in the MPEG-2 system. One is a transport stream, and the other is a program stream.

The definitions of both the transport stream and the program stream include a necessary and sufficient grammar regarding the synchronization of decoding and reproduction of video and audio. A program stream is formed by combining one or more PES packets having a common time base into a single bit string. A transport stream combines one or more programs with one or more timebases into a single bitstream.

Next, the operation will be described. Input terminal 10
1 to an MPEG-2 bit stream are input.
The input bit stream is temporarily stored in the memory 119 by the data input circuit 103 via the address conversion circuit 115 and the memory interface 117. First, the system data of the bit stream stored in the memory 119 is decoded by the system decoder 105.

The system data includes PSI (Program
Specific information) includes information for demultiplexing a program, various header information, time base information for synchronizing video and audio, and the like. As described above, in the MPEG-2 transport stream, a plurality of programs are transmitted as a single bit string. Therefore, it is necessary to separate these programs. The PSI contains a program, which is information necessary to separate these programs.
Association Table (Program Association Ta)
ble) and the program map table (Program Ma
p Table).

Based on the above system data, the system controller 121 identifies video data, audio data, other system data, and the like from the data stored in the memory 119. The identified video data and audio data are decoded by the video decoder 107 and the audio decoder 109, respectively.
The other identified system data is decoded by the system decoder 105 and sent to the system controller 121.

The above-described system data includes time stamp information used for synchronizing video and audio. Based on the time stamp information, the system controller 121 causes the video output circuit 111 and the audio output circuit 113 to synchronize the audio and the video, and to output them to the output terminals 123 and 125. As the memory 119 in the present embodiment, for example, an SDRAM that can perform burst transfer of data in synchronization with a rising edge of a clock is used.

As described above, the transport stream is obtained by combining the elementary streams into packets. In the decoder of the invention, the transport stream is recombined into PES packets. The recombined PES packet contains a PES header. There is a 1-bit ES rate flag in the PES header. When this flag is set to 1, there is an ES rate field in the PES header. The ES rate field is a 24-bit field by adding a marker bit.
The rate of receiving bytes of ES packets is 50 bytes /
It is described in seconds.

When the system decoder 105 decodes the ES rate, the system decoder 105 calculates a virtual rate Ref from this value. The system decoder 105 calculates a buffer size BSn for decoding, and secures a buffer area in the memory 119.

These values are calculated according to the following equations. Reff = ES rate × 188/184 BSn = Ref × 4 + BSn (dec) where BSn is a video buffering verifier for video and an audio frame size for audio.

The video buffering verifier (hereinafter referred to as VBV) is detected from the data by decoding the recomposed video PES packet. The VBV is, for example, in the case of MPEG-2, a vbv buffer size value (10) in the sequence header () that is present in the video stream recombined from the PES packet.
bits) and vbv buffer siz in sequence extension ()
It is found in the data string to be decoded by e extension (8bits). vbv buffer size value is vbv bu
Lower 10 bits of ffer size, vbv buffer size exte
nsion is the upper 8 bits of vbv buffersize. The minimum value BSmin of VBV is represented by the above vbv buffer size as follows. BSmin = 16 × 1024 × vbv buffer size

In the decoder of the present invention, the above ES
rate, and vbv buffer size value, vbv buffer siz
A buffer area is dynamically secured in the memory 119 based on the value of e extension. In the decoder according to the present invention, the surplus area generated by the dynamic reservation of the memory 119 as described above can be allocated to the simple decoding of another program.

As described above, the MPEG-2 Transpor
In tStream, a plurality of programs are transmitted as a single bit string. Therefore, even when decoding a single bit string, multiple different Progra
m may be present. The memory 119 not assigning this different Program to the program currently being decoded
Decoding is performed by using the area in. In this case, memory 1
If there are few free areas in 19, only I pictures of different programs may be decoded. Also, in the same bit string, undecoded Program
When there are a plurality of programs, the program having the largest number of accesses in the past may be simply decoded in the surplus area of the memory 119.

By the above operation, in the decoder of the present invention, the access response time until another Progarm is displayed and the channel hopping response time can be significantly reduced.

As described above, according to the present embodiment,
Since the capacity of the memory can be dynamically secured, it is possible to prevent an unnecessary area from being generated in the memory.

[0057]

As described above, according to the present invention,
Without increasing the cost, the non-use range on the memory can be reduced according to the content of the processing, and the memory can be used effectively, and a multifunctional signal processing device can be provided.

In particular, with the configuration of claim 6, two of the three storage means are used at the time of search, so that the other one can be used for other processing, and the storage capacity is effectively used. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment in which the present invention is applied to a digital VTR.

FIG. 2 is a configuration diagram illustrating an address space of a memory.

FIG. 3 is a timing chart showing access timing to a memory during recording and reproduction.

FIG. 4 is a timing chart showing access timing to a memory at the time of a search.

FIG. 5 is a block diagram showing a second embodiment in which the present invention is applied to an ATV.

FIG. 6 is a configuration diagram showing an MPEG encoding method.

FIG. 7 is a configuration diagram showing the order of image data for encoding processing, arrangement on a recording medium, and decoding processing in MPEG encoding.

[Explanation of symbols]

 5 Audio Processing Block 7 Encoding / Decoding Block 9 Error Correction Block 11 Encoded Data Input / Output Block 13 Address Conversion Circuit 17 Memory 19 System Control CPU 105 System Decoder 107 Video Decoder 109 Audio Decoder 115 Address Conversion Circuit 119 Memory 121 System Controller

Claims (8)

[Claims] A plurality of processing means for performing a plurality of different processes in a predetermined data unit; a storage means provided in common with each of the processing means for inputting / outputting the data in the predetermined unit; Control means for performing access control with respect to the storage means, wherein the control means dynamically changes the capacity of the storage means which can be accessed by each processing means according to the processing of each processing means. Characteristic signal processing device. 2. The signal processing apparatus according to claim 1, further comprising an image encoding / decoding processing unit using discrete cosine transform as one of the plurality of processing units. 3. As one of the plurality of processing means, coded data obtained by time-division multiplexing intra-coded image data and inter-coded data is provided, and from the coded data to intra-coded data. 2. The signal processing apparatus according to claim 1, further comprising: encoded data reconstructing means for reconstructing the intra-picture encoded data by selecting the image data. 4. The encoded data obtained by time-division multiplexing the intra-coded image data and the inter-coded data is M
4. The signal processing apparatus according to claim 3, wherein the data is PEG coded data. 5. The encoded data obtained by time-division multiplexing the intra-coded image data and the inter-coded data is A
The signal processing device according to claim 3, wherein the signal processing device is TV encoded data. 6. A signal processing apparatus used in a recording / reproducing apparatus for recording / reproducing coded image data, wherein the encoding / decoding for encoding an input signal at the time of recording and decoding the coded image data reproduced at the time of reproduction. Encoding / decoding processing means; first, second, and third storage means used for the encoding / decoding processing at the time of recording / reproducing; and encoding / decoding processing means at the time of search, and the first and second storage means. And control means for controlling the storage means, wherein the control means writes the reproduced coded image data in the first storage period to the first storage unit and writes the reproduced encoded image data to the second storage unit. Decoding the encoded data thus obtained, and performing the writing and decoding processes on the first and second storage means in the next second period in reverse to the first frame period. Characteristic signal Management apparatus. 7. An error correction of the coded image data written in said first and second storage means at the time of said search, and the corrected coded image data is written back to said first and second storage means. 7. The signal processing device according to claim 6, further comprising an error correction unit. 8. The signal processing apparatus according to claim 6, wherein said third storage means is used for other processing during said search.