JPH10327573A - Semiconductor stack of power conversion device - Google Patents

Semiconductor stack of power conversion device

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Publication number
JPH10327573A
JPH10327573A JP13266797A JP13266797A JPH10327573A JP H10327573 A JPH10327573 A JP H10327573A JP 13266797 A JP13266797 A JP 13266797A JP 13266797 A JP13266797 A JP 13266797A JP H10327573 A JPH10327573 A JP H10327573A
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Japan
Prior art keywords
terminal layer
semiconductor
current
semiconductor element
parallel
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP13266797A
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Japanese (ja)
Inventor
Seiitsu Kin
Hiroshi Yamamoto
弘 山本
世逸 金
Original Assignee
Fuji Electric Co Ltd
富士電機株式会社
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Application filed by Fuji Electric Co Ltd, 富士電機株式会社 filed Critical Fuji Electric Co Ltd
Priority to JP13266797A priority Critical patent/JPH10327573A/en
Publication of JPH10327573A publication Critical patent/JPH10327573A/en
Application status is Pending legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To reduce current unbalance between semiconductor devices in the semiconductor stack of a power conversion device. SOLUTION: A wiring board 3 is constituted as a three-layered structure consisting of an alternating-current terminal layer U, a positive-pole terminal layer P, and a negative-pole terminal layer N. These layers are arranged in proximity to one another and in parallel with one another, in such a manner that the direction of currents flowing from the positive-pole terminal layer P to the alternating-current terminal layer U is opposite to the direction of the currents flowing from the alternating-current terminal layer U to the negative-pole terminal layer N. Thereby the field interferences of the semiconductor devices with each other is eliminated, and a current unbalance is reduced. Number 2 in the figure refers to a base on which the semiconductor devices 1 are to be mounted.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】この発明は、無停電電源装置(UPSとも略記する)の電力変換装置などに用いて好適な半導体スタックに関する。 TECHNICAL FIELD The present invention relates to a suitable semiconductor stack using a like power converter of uninterruptible power supply (also UPS abbreviated).

【0002】 [0002]

【従来の技術】図6に従来の半導体スタックの回路構成例を、図7にその構造例を示す。 An example of a circuit configuration of a conventional semiconductor stack 6 shows the structure example in Fig. すなわち、ここでは合計8個の半導体素子1が冷却体のベース面2に取り付けられており、上下2個の半導体素子によって1つの上下アームを構成し、4アームを並列接続してある。 That is, where a total of eight semiconductor element 1 is mounted on the base surface 2 of the cooling body, by the upper and lower two semiconductor elements constitute one of the upper and lower arms, are connected in parallel 4 arms. 構造的には図7に示すように、大電流配線用基板3を半導体素子1の端子に固定することにより、4アーム並列接続を実現している。 Structurally, as shown in FIG. 7, by fixing the high-current wiring board 3 to the terminal of the semiconductor element 1 realizes a 4-arm parallel connection.

【0003】図8は図7の側面図である。 [0003] FIG. 8 is a side view of FIG. 7. この図8から明らかなように、交流端子としてのU層(U相)を半導体素子側に、正端子層(P相)を上アーム側に、また負端子層(N相)を下アーム側にそれぞれ配置している。 As apparent from FIG. 8, U layer of the alternating current terminals (U-phase) on the semiconductor element side, the positive terminal layer (P-phase) to the upper arm side and the negative terminal layer (N-phase) lower arm side They are arranged respectively on.
なお、図示はしていないが、各層間には絶縁のためのシートが挟み込んである。 Although not illustrated, between the respective layers Aru sandwiched sheet for insulation. 符号4は電解コンデンサを示す。 Reference numeral 4 denotes an electrolytic capacitor. また、U相端子は電力変換装置が整流器の場合には入力端子、インバータの場合には出力端子となるが、いずれにしても交流端子である。 Further, U-phase terminal is an input terminal in the case of a power converter a rectifier, although the output terminal in the case of an inverter, an AC Anyway terminal.

【0004】 [0004]

【発明が解決しようとする課題】図9(a)に上アーム素子の1つがスイッチングしたときの電流の流れる方向を示し、図9(b)に下アーム素子の1つがスイッチングしたときの電流の流れる方向をそれぞれ示す。 One of the upper arm element 9 INVENTION Problems to Solved] (a) indicate the direction of flow of the current when switching, one of the lower arm element 9 (b) of the current when switching It shows the direction of flow, respectively. これらの図から、大電流配線用基板3では破線部分に磁界が発生し、これが図7,図8のような4素子タイプのものでは磁界の相互干渉により、各アーム間に流れる電流のバランスが悪くなり、1つの素子に電流集中するという問題が生じる。 From these figures, a large current magnetic field is generated in the wiring board 3, the broken line portion, which is 7, the mutual interference of the magnetic field than 4 those elements type, such as FIG. 8, the balance of current flowing between each arm worse, a problem that the current concentrates on one element occurs.

【0005】図10は半導体素子を冷却するためのヒートパイプ冷却体の従来例を示す概要図である。 [0005] FIG. 10 is a schematic diagram showing a conventional example of the heat pipe heat sink for cooling the semiconductor element. 同(a) The same (a)
は平面図、同(b)は側面図である。 It is a plan view, and (b) is a side view. 図示のように、半導体素子1を取り付けるベース面2と、ベース面2に挿入されたヒートパイプ5および放熱用フィン6等から構成される。 As shown, the base surface 2 for mounting the semiconductor element 1, and a heat pipe 5 and the radiating fins 6, etc. that is inserted into the base surface 2. このような構成において、半導体素子1が発熱してベース面2に熱が伝達されると、ヒートパイプ5 In such a configuration, when the semiconductor element 1 the heat is transmitted to the base surface 2 by heating the heat pipe 5
内の液が蒸発し、放熱用フィン6側に移動する。 Liquid inner evaporates and moves to the heat radiating fin 6 side. 放熱用フィン6側で液が冷却されると液が凝固しベース面2側に移動する、といった具合で熱の移動が行なわれる。 When the liquid in the heat radiating fins 6 side is cooled liquid moves solidified base surface 2 side, heat transfer is performed at so on.

【0006】図10のように構成するメリットとしては、ベース面2で局部的熱集中が起きても全体的に熱が分散することが挙げられる。 [0006] As the merit configured as shown in FIG. 10, the overall heat even occur locally heat concentration in the base surface 2 and the like to be distributed. このため、上述のごとき1 For this reason, such as the above-mentioned 1
つの素子に電流集中し、発熱が集中することを緩和させるために上記のようなヒートパイプ冷却体を採用している。 One of then current concentration in the element, heat generation is employed a heat pipe cooling body as described above in order to relieve to focus. ただ、このようなヒートパイプ冷却体では、ベース面と放熱用フィン部がヒートパイプを介して連結されているため、コンパクトさに欠けるという問題がある。 However, in such a heat pipe heat sink, since the radiating fins and the base surface is connected via the heat pipe, there is a problem of lacking compactness. したがって、この発明の課題は、各アーム間に流れる電流にアンバランスを生じないようにすること、さらには、 Accordingly, an object of the present invention is possible to prevent the occurrence of unbalanced current flowing between the arms, and further,
局部熱集中を分散し半導体素子冷却体のコンパクト化を図ることにある。 Dispersed local heat concentration in be made compact semiconductor element cooling body.

【0007】 [0007]

【課題を解決するための手段】このような課題を解決すべく、請求項1の発明では、複数の半導体素子と、これらを並列接続するための正端子層,負端子層および交流端子層からなる配線基板と、前記半導体素子を冷却するための冷却体とからなる電力変換装置の半導体スタックにおいて、前記配線基板の正端子層,負端子層および交流端子層を互いに平行にかつ近接して積層し、交流端子層と正端子層,負端子層間を流れる電流方向がそれぞれ互いに逆となるようにしている。 To solve SUMMARY OF THE INVENTION The above problems, in the invention of claim 1, a plurality of semiconductor devices, the positive terminal layer for parallel connecting these, from the negative terminal layer and the AC terminal layer a wiring substrate comprising, laminated the semiconductor stack of the power converter comprising a cooling body for cooling the semiconductor element, the positive terminal layer of the wiring substrate, in parallel with and close to each other the negative terminal layer and the AC terminal layer and, the AC terminal layer and the positive terminal layer, the current direction flowing through the negative terminal interlayer so that respectively opposite to each other. この請求項1の発明では、前記交流端子層を2分割し、両者をコア結合とすることができる(請求項3の発明)。 In the invention of claim 1, wherein the AC terminal layer 2 is divided, it is possible to both the core binding (the invention of claim 3).

【0008】請求項2の発明では、複数の半導体素子と、これらを並列接続するための正端子板,負端子板および交流端子板からなる配線基板と、前記半導体素子を冷却するための冷却体とからなる電力変換装置の半導体スタックにおいて、前記冷却体を、半導体素子が取り付けられるベース面の、半導体素子が並列接続される並びの方向に沿ってヒートパイプを挿入し、かつ、前記ベース面の裏側に放熱用フィンを配置している。 [0008] In the present invention of claim 2, a plurality of semiconductor devices, the positive terminal plate for parallel connection of these, the wiring board consisting of a negative terminal plate and the AC terminal plate, a cooling body for cooling the semiconductor element in the semiconductor stack of the power converter comprising a, the cooling body, the base surface of the semiconductor element is mounted, the semiconductor element is inserted a heat pipe along the direction of arrangement being connected in parallel, and the base surface and a radiating fin disposed on the back side.

【0009】 [0009]

【発明の実施の形態】図1はこの発明の第1の実施の形態を示す外観図である。 Figure 1 DETAILED DESCRIPTION OF THE INVENTION is an external view showing a first embodiment of the present invention. ここでは、16個の半導体素子1が冷却体のベース面2に取り付けられ、上下2個の半導体素子からなる1アームを8個並列接続して構成している。 Here, 16 of the semiconductor element 1 is mounted on the base surface 2 of the cooling body constitutes a first arm consisting of two upper and lower semiconductor element 8 connected in parallel. 図2に図1の側面図を示す。 Figure 2 shows a side view of FIG. 図2から明らかなように、ここでは、U相を下側に、N相を中側に、P相を上側にした3層構造とし、各層は互いに平行で近接して配置した点が特徴である。 As apparent from FIG. 2, where, in the lower U-phase, the middle side N phase, a three-layer structure in which the P phase on the upper side, each layer is a point which is arranged close and parallel to each other in characteristics is there. また、各層間には絶縁のためのシートが挟み込んである。 Further, between the respective layers Aru sandwiched sheet for insulation.

【0010】図3(a)に、図1において下アーム素子の1つがスイッチングしたときの電流の流れる方向を示し、図3(b)に上アーム素子の1つがスイッチングしたときの電流の流れる方向を示す。 [0010] FIG. 3 (a), one of the lower arm device in FIG. 1 indicate the direction of flow of the current when switching the direction of flow one of the upper arm device in FIG. 3 (b) of current when switching It is shown. 図3からも明らかなように、各層が平行に近接して配置されていることから、下アーム素子または上アーム素子の1つがスイッチングしたときに、配線基板3を流れる電流は(a)または(b)のように互いに逆方向になるため、電流によって発生する磁界がキャンセルされる。 As is apparent from FIG. 3, since the layers are arranged close in parallel, when one of the lower arm element or upper arm element and switching, the current flowing through the wiring board 3 (a) or ( to become in opposite directions as b), the magnetic field generated by the current is canceled. その結果、半導体素子1が複数並列接続されていても、各アーム間の磁界による相互干渉が無くなるため、各アーム間に流れる電流バランスが良くなり、1つの半導体素子に電流集中することが抑制される。 As a result, even if the semiconductor element 1 has a plurality of parallel-connected, since the mutual interference by the magnetic field between each arm is eliminated, the better the current balance flowing between each arm, it is prevented that current concentration on a single semiconductor element that.

【0011】図4はこの発明の第2の実施の形態を示す外観図である。 [0011] FIG. 4 is an external view showing a second embodiment of the present invention. これは、半導体素子の冷却装置を示すもので、半導体素子1を取り付けるベース面2と、このベース面2に対して半導体素子1が並列接続されている並び方向に沿ってヒートパイプ5を挿入して構成されている。 This shows a cooling apparatus for a semiconductor element, a base surface 2 for mounting the semiconductor device 1, the semiconductor element 1 is inserted a heat pipe 5 along the arrangement direction are connected in parallel to the base surface 2 It is configured Te. また、ベース面2の裏側には、放熱のためのフィン6が設けられている。 Further, on the back side of the base surface 2, the fins 6 are provided for heat radiation. このように、半導体素子1が並列接続の並び方向に沿ってヒートパイプ5を挿入されているため、一部の半導体素子に局部発熱が発生しても、半導体素子の並び方向に熱が分散され、半導体素子の電流アンバランスを緩和させるという効果が得られる。 Since the semiconductor element 1 is inserted a heat pipe 5 along the direction of arrangement of the parallel connection, even if local heat generation occurs in a portion of a semiconductor device, heat is distributed in the arrangement direction of the semiconductor element , the effect of relieving the current unbalance of the semiconductor device can be obtained.

【0012】特に、半導体素子が絶縁ゲート型バイポーラトランジスタ(IGBT)素子の場合、その一部に電流が集中し加熱されるとその電気抵抗値が下がり、さらに電流が集中するという悪循環が生じるので、上記のような熱の分散は有効である。 [0012] Particularly, when the semiconductor element is an insulated gate bipolar transistor (IGBT) devices, that a part current is heated concentrate decreases the electric resistance value, the more current is vicious cycle concentrates occur, dispersion of heat as described above is effective. また、図10に示す従来例とは異なり、ベース面のすぐ裏側に放熱フィンを配置するようにしているので、発熱部と放熱部どほぼ一体となりコンパクト化が可能となる利点もある。 Further, unlike the conventional example shown in FIG. 10, since to arrange the radiating fins immediately on the back side of the base surface, etc. heat radiating portion and the heat-generating unit is also an advantage that it is possible to substantially compact come together.

【0013】図5はこの発明の第3の実施の形態を示す外観図である。 [0013] FIG. 5 is an external view showing a third embodiment of the present invention. 基本的な構成は図1と同じであるが、U The basic structure is the same as Figure 1, U
層部分を図示のように2分割し、各端子までの基板を電流方向が逆となるように配置し、これらをコア7によって磁気結合したものである。 The layer portion is divided into two as shown, the substrate is placed to each terminal such that the current direction is reversed, it is obtained by magnetically coupling them with core 7. この例も図1の場合と同じく、各アーム間の磁界の干渉が少ないので、電流アンバランスの要因として残るのは、半導体素子内部のインピーダンスの差と、各端子(U端子,P端子,N端子)と半導体素子間の配線距離の違いによるインピーダンスの差である。 This example also as in the case of FIG. 1, the interference of the magnetic field is small between the arms, the left as a factor of the current imbalance, the difference in impedance in the semiconductor device, the terminals (U terminal, P terminal, N terminal) and which is the difference in impedance due to difference in the wiring length between the semiconductor elements. ただ、コア7による磁気結合により2分割されたそれぞれの相に流れる電流が等しくなるから、図1 However, since the current flowing through the respective phase which is bisected by the magnetic coupling by the core 7 is equal, FIG. 1
に示すものに比べて上記配線距離が1/2程度に短くなることから、さらに電流アンバランスが小さくなる。 The wiring distance from becoming short as 1/2, further current imbalance is small as compared with that shown in. その結果、1部の半導体素子の加熱も小さくなるので、冷却体を小さくできるという利点がある。 As a result, the smaller the heating of the semiconductor element 1 part, there is an advantage that the cooling body can be reduced.

【0014】 [0014]

【発明の効果】この発明によれば、配線基板の正端子層,負端子層および交流端子層を互いに平行にかつ接近して積層し、交流端子層と正端子層,負端子層間を流れる電流方向が互いに逆となるようにすることで、各半導体素子の電流アンバランスを小さくする。 Effects of the Invention According to the present invention, the positive terminal layer of the wiring substrate, the negative terminal layer and the AC terminal layer laminated in parallel with and close to each other, the AC terminal layer and the positive terminal layer, the current flowing through the negative terminal interlayer by such directions are opposite to each other, to reduce the current imbalance of the semiconductor elements. また、上記のような構成において交流端子層を2分割し、両者をコア結合することで、電流アンバランスをさらに小さくし、 Also, the AC terminals layer in the above structure is divided into two, both of them by core binding, and further reduce the current imbalance,
熱集中を回避することができるという利点が得られる。 Advantage that it is possible to avoid heat concentration can be obtained.
半導体素子が取り付けられるベース面の、半導体素子が並列接続される並びの方向に沿ってヒートパイプを挿入し、かつ、前記ベース面の裏側に放熱用フィンを配置することで、局部熱集中が分散されコンパクト化が可能になる、などの利点が得られる。 The base surface of the semiconductor element is mounted, by inserting the heat pipe semiconductor element along the direction of arrangement being connected in parallel, and, by disposing the radiation fins on the back side of the base surface, a local heat concentration dispersion by allowing compact, it has advantages such as obtained.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】この発明の第1の実施の形態を示す外観図である。 1 is an external view showing a first embodiment of the present invention.

【図2】図1の側面図である。 Is a side view of FIG. 1;

【図3】この発明における電流経路説明図である。 3 is a current path diagram in the present invention.

【図4】この発明の第2の実施の形態を示す外観図である。 4 is an external view showing a second embodiment of the present invention.

【図5】この発明の第3の実施の形態を示す外観図である。 5 is an external view showing a third embodiment of the present invention.

【図6】半導体スタックの従来例を示す回路図である。 6 is a circuit diagram showing a conventional example of a semiconductor stack.

【図7】半導体スタックの従来例を示す構成図である。 7 is a block diagram showing a conventional example of a semiconductor stack.

【図8】図7の側面図である。 FIG. 8 is a side view of FIG. 7.

【図9】図7の場合の電流経路説明図である。 9 is a current path diagram in the case of FIG.

【図10】冷却体の従来例を示す概要図である。 10 is a schematic diagram showing a conventional example of a cooling body.

【符号の説明】 DESCRIPTION OF SYMBOLS

1…半導体素子、2…ベース面、3…配線基板、4…電解コンデンサ、5…ヒートパイプ、6…放熱フィン、7 1 ... semiconductor device, 2 ... base surface, 3 ... wiring board, 4 ... electrolytic capacitor, 5 ... heat pipes, 6 ... heat radiating fins, 7
…コア。 …core.

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 複数の半導体素子と、これらを並列接続するための正端子層,負端子層および交流端子層からなる配線基板と、前記半導体素子を冷却するための冷却体とからなる電力変換装置の半導体スタックにおいて、 前記配線基板の正端子層,負端子層および交流端子層を互いに平行にかつ近接して積層し、交流端子層と正端子層,負端子層間を流れる電流方向がそれぞれ互いに逆となるようにしたことを特徴とする電力変換装置の半導体スタック。 And 1. A plurality of semiconductor devices, the positive terminal layer for connecting these parallel, power conversion consisting of a wiring board comprising a negative terminal layer and the AC terminal layer, the cooling body for cooling said semiconductor element the semiconductor stack device, the positive terminal layer of the wiring board, laminated in parallel to and close to each other the negative terminal layer and the AC terminal layer, AC terminal layer and the positive terminal layer, together current direction flowing through the negative terminal layers respectively the semiconductor stack of the power converter being characterized in that as the reverse.
  2. 【請求項2】 複数の半導体素子と、これらを並列接続するための正端子板,負端子板および交流端子板からなる配線基板と、前記半導体素子を冷却するための冷却体とからなる電力変換装置の半導体スタックにおいて、 前記冷却体を、半導体素子が取り付けられるベース面の、半導体素子が並列接続される並びの方向に沿ってヒートパイプを挿入し、かつ、前記ベース面の裏側に放熱用フィンを配置したことを特徴とする電力変換装置の半導体スタック。 2. A plurality of semiconductor devices, the positive terminal plate for parallel connection of these power conversion comprising a wiring board composed of the negative terminal plate and the AC terminal plate, a cooling body for cooling said semiconductor element the semiconductor stack device, the cooling body, the base surface of the semiconductor element is mounted, by inserting the heat pipe semiconductor element along the direction of arrangement being connected in parallel, and heat radiation fins on the back side of the base surface the semiconductor stack of the power converter, characterized in that a.
  3. 【請求項3】 前記交流端子層を2分割し、両者をコア結合したことを特徴とする請求項1に記載の電力変換装置の半導体スタック。 3. A semiconductor stack of the power converter according to claim 1, characterized in that said AC terminal layer 2 is divided, and both were core binding.
JP13266797A 1997-05-23 1997-05-23 Semiconductor stack of power conversion device Pending JPH10327573A (en)

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002186265A (en) * 2000-12-18 2002-06-28 Fuji Electric Co Ltd Power converter
WO2013059446A1 (en) * 2011-10-18 2013-04-25 Arctic Sand Technologies, Inc. Power converters with integrated capacitors
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US9742266B2 (en) 2013-09-16 2017-08-22 Arctic Sand Technologies, Inc. Charge pump timing control
US9041459B2 (en) 2013-09-16 2015-05-26 Arctic Sand Technologies, Inc. Partial adiabatic conversion
US10162376B2 (en) 2013-09-16 2018-12-25 Psemi Corporation Charge pump with temporally-varying adiabaticity
US9658635B2 (en) 2013-09-16 2017-05-23 Arctic Sand Technologies, Inc. Charge pump with temporally-varying adiabaticity
US9825545B2 (en) 2013-10-29 2017-11-21 Massachusetts Institute Of Technology Switched-capacitor split drive transformer power conversion circuit
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