JPH10327573A - Semiconductor stack of power conversion device - Google Patents

Semiconductor stack of power conversion device

Info

Publication number
JPH10327573A
JPH10327573A JP13266797A JP13266797A JPH10327573A JP H10327573 A JPH10327573 A JP H10327573A JP 13266797 A JP13266797 A JP 13266797A JP 13266797 A JP13266797 A JP 13266797A JP H10327573 A JPH10327573 A JP H10327573A
Authority
JP
Japan
Prior art keywords
terminal layer
semiconductor
semiconductor elements
current
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13266797A
Other languages
Japanese (ja)
Inventor
Seiitsu Kin
世逸 金
Hiroshi Yamamoto
弘 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP13266797A priority Critical patent/JPH10327573A/en
Publication of JPH10327573A publication Critical patent/JPH10327573A/en
Pending legal-status Critical Current

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  • Power Conversion In General (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce current unbalance between semiconductor devices in the semiconductor stack of a power conversion device. SOLUTION: A wiring board 3 is constituted as a three-layered structure consisting of an alternating-current terminal layer U, a positive-pole terminal layer P, and a negative-pole terminal layer N. These layers are arranged in proximity to one another and in parallel with one another, in such a manner that the direction of currents flowing from the positive-pole terminal layer P to the alternating-current terminal layer U is opposite to the direction of the currents flowing from the alternating-current terminal layer U to the negative-pole terminal layer N. Thereby the field interferences of the semiconductor devices with each other is eliminated, and a current unbalance is reduced. Number 2 in the figure refers to a base on which the semiconductor devices 1 are to be mounted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、無停電電源装置
(UPSとも略記する)の電力変換装置などに用いて好
適な半導体スタックに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor stack suitable for use in a power converter of an uninterruptible power supply (UPS).

【0002】[0002]

【従来の技術】図6に従来の半導体スタックの回路構成
例を、図7にその構造例を示す。すなわち、ここでは合
計8個の半導体素子1が冷却体のベース面2に取り付け
られており、上下2個の半導体素子によって1つの上下
アームを構成し、4アームを並列接続してある。構造的
には図7に示すように、大電流配線用基板3を半導体素
子1の端子に固定することにより、4アーム並列接続を
実現している。
2. Description of the Related Art FIG. 6 shows an example of a circuit configuration of a conventional semiconductor stack, and FIG. 7 shows an example of the structure. That is, here, a total of eight semiconductor elements 1 are mounted on the base surface 2 of the cooling body, and one upper and lower arm is constituted by two upper and lower semiconductor elements, and four arms are connected in parallel. Structurally, as shown in FIG. 7, by fixing the large current wiring substrate 3 to the terminal of the semiconductor element 1, four-arm parallel connection is realized.

【0003】図8は図7の側面図である。この図8から
明らかなように、交流端子としてのU層(U相)を半導
体素子側に、正端子層(P相)を上アーム側に、また負
端子層(N相)を下アーム側にそれぞれ配置している。
なお、図示はしていないが、各層間には絶縁のためのシ
ートが挟み込んである。符号4は電解コンデンサを示
す。また、U相端子は電力変換装置が整流器の場合には
入力端子、インバータの場合には出力端子となるが、い
ずれにしても交流端子である。
FIG. 8 is a side view of FIG. As is apparent from FIG. 8, the U layer (U phase) as an AC terminal is on the semiconductor element side, the positive terminal layer (P phase) is on the upper arm side, and the negative terminal layer (N phase) is on the lower arm side. Are arranged respectively.
Although not shown, a sheet for insulation is interposed between the respective layers. Reference numeral 4 indicates an electrolytic capacitor. The U-phase terminal is an input terminal when the power converter is a rectifier, and an output terminal when the power converter is an inverter. In any case, the U-phase terminal is an AC terminal.

【0004】[0004]

【発明が解決しようとする課題】図9(a)に上アーム
素子の1つがスイッチングしたときの電流の流れる方向
を示し、図9(b)に下アーム素子の1つがスイッチン
グしたときの電流の流れる方向をそれぞれ示す。これら
の図から、大電流配線用基板3では破線部分に磁界が発
生し、これが図7,図8のような4素子タイプのもので
は磁界の相互干渉により、各アーム間に流れる電流のバ
ランスが悪くなり、1つの素子に電流集中するという問
題が生じる。
FIG. 9 (a) shows the direction of current flow when one of the upper arm elements is switched, and FIG. 9 (b) shows the current flow when one of the lower arm elements is switched. The flow direction is shown. From these figures, a magnetic field is generated at the broken line portion in the large current wiring board 3, and in the four-element type shown in FIGS. 7 and 8, the balance of the current flowing between the arms is caused by the mutual interference of the magnetic fields. As a result, there is a problem that current concentrates on one element.

【0005】図10は半導体素子を冷却するためのヒー
トパイプ冷却体の従来例を示す概要図である。同(a)
は平面図、同(b)は側面図である。図示のように、半
導体素子1を取り付けるベース面2と、ベース面2に挿
入されたヒートパイプ5および放熱用フィン6等から構
成される。このような構成において、半導体素子1が発
熱してベース面2に熱が伝達されると、ヒートパイプ5
内の液が蒸発し、放熱用フィン6側に移動する。放熱用
フィン6側で液が冷却されると液が凝固しベース面2側
に移動する、といった具合で熱の移動が行なわれる。
FIG. 10 is a schematic diagram showing a conventional example of a heat pipe cooling body for cooling a semiconductor element. (A)
Is a plan view, and (b) is a side view. As shown in the figure, a base surface 2 on which the semiconductor element 1 is mounted, a heat pipe 5 inserted into the base surface 2 and radiating fins 6 are provided. In such a configuration, when the semiconductor element 1 generates heat and the heat is transmitted to the base surface 2, the heat pipe 5
The liquid inside evaporates and moves to the heat radiation fin 6 side. When the liquid is cooled on the heat dissipating fin 6 side, the liquid is solidified and moves to the base surface 2 side, so that heat is transferred.

【0006】図10のように構成するメリットとして
は、ベース面2で局部的熱集中が起きても全体的に熱が
分散することが挙げられる。このため、上述のごとき1
つの素子に電流集中し、発熱が集中することを緩和させ
るために上記のようなヒートパイプ冷却体を採用してい
る。ただ、このようなヒートパイプ冷却体では、ベース
面と放熱用フィン部がヒートパイプを介して連結されて
いるため、コンパクトさに欠けるという問題がある。し
たがって、この発明の課題は、各アーム間に流れる電流
にアンバランスを生じないようにすること、さらには、
局部熱集中を分散し半導体素子冷却体のコンパクト化を
図ることにある。
An advantage of the configuration shown in FIG. 10 is that even if local heat concentration occurs on the base surface 2, heat is dispersed as a whole. Therefore, as described above, 1
The above-described heat pipe cooling body is employed to reduce the concentration of current and the concentration of heat in one element. However, in such a heat pipe cooling body, there is a problem in that the heat sink fins are not compact because the base surface and the radiating fins are connected via the heat pipe. Therefore, an object of the present invention is to prevent imbalance in the current flowing between the arms,
It is an object of the present invention to disperse local heat concentration and to make a semiconductor element cooling body compact.

【0007】[0007]

【課題を解決するための手段】このような課題を解決す
べく、請求項1の発明では、複数の半導体素子と、これ
らを並列接続するための正端子層,負端子層および交流
端子層からなる配線基板と、前記半導体素子を冷却する
ための冷却体とからなる電力変換装置の半導体スタック
において、前記配線基板の正端子層,負端子層および交
流端子層を互いに平行にかつ近接して積層し、交流端子
層と正端子層,負端子層間を流れる電流方向がそれぞれ
互いに逆となるようにしている。この請求項1の発明で
は、前記交流端子層を2分割し、両者をコア結合とする
ことができる(請求項3の発明)。
In order to solve such a problem, according to the present invention, a plurality of semiconductor elements and a positive terminal layer, a negative terminal layer, and an AC terminal layer for connecting them in parallel are provided. A positive terminal layer, a negative terminal layer, and an AC terminal layer of the wiring substrate are stacked in parallel with and close to each other in a semiconductor stack of a power conversion device including a wiring substrate formed of a wiring board and a cooling body for cooling the semiconductor element. The directions of the currents flowing between the AC terminal layer, the positive terminal layer, and the negative terminal layer are opposite to each other. According to the first aspect of the present invention, the AC terminal layer can be divided into two parts, and the two can be core-coupled (the third aspect of the invention).

【0008】請求項2の発明では、複数の半導体素子
と、これらを並列接続するための正端子板,負端子板お
よび交流端子板からなる配線基板と、前記半導体素子を
冷却するための冷却体とからなる電力変換装置の半導体
スタックにおいて、前記冷却体を、半導体素子が取り付
けられるベース面の、半導体素子が並列接続される並び
の方向に沿ってヒートパイプを挿入し、かつ、前記ベー
ス面の裏側に放熱用フィンを配置している。
According to a second aspect of the present invention, a plurality of semiconductor elements, a wiring board including a positive terminal plate, a negative terminal plate, and an AC terminal plate for connecting them in parallel, and a cooling body for cooling the semiconductor elements In the semiconductor stack of the power conversion device, the heat sink is inserted along a direction in which the semiconductor elements are connected in parallel with each other on the base surface on which the semiconductor elements are mounted, and Radiation fins are arranged on the back side.

【0009】[0009]

【発明の実施の形態】図1はこの発明の第1の実施の形
態を示す外観図である。ここでは、16個の半導体素子
1が冷却体のベース面2に取り付けられ、上下2個の半
導体素子からなる1アームを8個並列接続して構成して
いる。図2に図1の側面図を示す。図2から明らかなよ
うに、ここでは、U相を下側に、N相を中側に、P相を
上側にした3層構造とし、各層は互いに平行で近接して
配置した点が特徴である。また、各層間には絶縁のため
のシートが挟み込んである。
FIG. 1 is an external view showing a first embodiment of the present invention. Here, 16 semiconductor elements 1 are attached to the base surface 2 of the cooling body, and eight 1-arms composed of two upper and lower semiconductor elements are connected in parallel. FIG. 2 shows a side view of FIG. As is clear from FIG. 2, here, the U-phase is on the lower side, the N-phase is on the inner side, and the P-phase is on the upper side. is there. Further, a sheet for insulation is interposed between the respective layers.

【0010】図3(a)に、図1において下アーム素子
の1つがスイッチングしたときの電流の流れる方向を示
し、図3(b)に上アーム素子の1つがスイッチングし
たときの電流の流れる方向を示す。図3からも明らかな
ように、各層が平行に近接して配置されていることか
ら、下アーム素子または上アーム素子の1つがスイッチ
ングしたときに、配線基板3を流れる電流は(a)また
は(b)のように互いに逆方向になるため、電流によっ
て発生する磁界がキャンセルされる。その結果、半導体
素子1が複数並列接続されていても、各アーム間の磁界
による相互干渉が無くなるため、各アーム間に流れる電
流バランスが良くなり、1つの半導体素子に電流集中す
ることが抑制される。
FIG. 3 (a) shows the direction of current flow when one of the lower arm elements in FIG. 1 switches, and FIG. 3 (b) shows the direction of current flow when one of the upper arm elements switches. Is shown. As is clear from FIG. 3, since each layer is arranged in parallel and close to each other, when one of the lower arm element or the upper arm element switches, the current flowing through the wiring board 3 is (a) or ( Since the directions are opposite to each other as in b), the magnetic field generated by the current is canceled. As a result, even when a plurality of semiconductor elements 1 are connected in parallel, mutual interference due to the magnetic field between the arms is eliminated, so that the current balance flowing between the arms is improved, and current concentration on one semiconductor element is suppressed. You.

【0011】図4はこの発明の第2の実施の形態を示す
外観図である。これは、半導体素子の冷却装置を示すも
ので、半導体素子1を取り付けるベース面2と、このベ
ース面2に対して半導体素子1が並列接続されている並
び方向に沿ってヒートパイプ5を挿入して構成されてい
る。また、ベース面2の裏側には、放熱のためのフィン
6が設けられている。このように、半導体素子1が並列
接続の並び方向に沿ってヒートパイプ5を挿入されてい
るため、一部の半導体素子に局部発熱が発生しても、半
導体素子の並び方向に熱が分散され、半導体素子の電流
アンバランスを緩和させるという効果が得られる。
FIG. 4 is an external view showing a second embodiment of the present invention. This shows a cooling device for a semiconductor element, in which a heat pipe 5 is inserted along a base surface 2 on which a semiconductor element 1 is mounted and a direction in which the semiconductor element 1 is connected in parallel to the base surface 2. It is configured. Further, on the back side of the base surface 2, fins 6 for heat radiation are provided. As described above, since the heat pipes 5 are inserted along the direction in which the semiconductor elements 1 are connected in parallel, even if local heat is generated in some of the semiconductor elements, the heat is dispersed in the direction in which the semiconductor elements are arranged. This has the effect of reducing the current imbalance of the semiconductor element.

【0012】特に、半導体素子が絶縁ゲート型バイポー
ラトランジスタ(IGBT)素子の場合、その一部に電
流が集中し加熱されるとその電気抵抗値が下がり、さら
に電流が集中するという悪循環が生じるので、上記のよ
うな熱の分散は有効である。また、図10に示す従来例
とは異なり、ベース面のすぐ裏側に放熱フィンを配置す
るようにしているので、発熱部と放熱部どほぼ一体とな
りコンパクト化が可能となる利点もある。
In particular, when the semiconductor element is an insulated gate bipolar transistor (IGBT) element, the current concentrates on a part of the element, and when heated, the electric resistance decreases, and the current further concentrates. Heat dispersion as described above is effective. Further, unlike the conventional example shown in FIG. 10, since the heat radiation fins are arranged immediately behind the base surface, there is also an advantage that the heat generation part and the heat radiation part are almost integrated and the size can be reduced.

【0013】図5はこの発明の第3の実施の形態を示す
外観図である。基本的な構成は図1と同じであるが、U
層部分を図示のように2分割し、各端子までの基板を電
流方向が逆となるように配置し、これらをコア7によっ
て磁気結合したものである。この例も図1の場合と同じ
く、各アーム間の磁界の干渉が少ないので、電流アンバ
ランスの要因として残るのは、半導体素子内部のインピ
ーダンスの差と、各端子(U端子,P端子,N端子)と
半導体素子間の配線距離の違いによるインピーダンスの
差である。ただ、コア7による磁気結合により2分割さ
れたそれぞれの相に流れる電流が等しくなるから、図1
に示すものに比べて上記配線距離が1/2程度に短くな
ることから、さらに電流アンバランスが小さくなる。そ
の結果、1部の半導体素子の加熱も小さくなるので、冷
却体を小さくできるという利点がある。
FIG. 5 is an external view showing a third embodiment of the present invention. The basic configuration is the same as in FIG.
The layer portion is divided into two parts as shown in the figure, the substrates up to the respective terminals are arranged so that the current directions are opposite, and these are magnetically coupled by the core 7. Also in this example, as in the case of FIG. 1, the interference of the magnetic field between the arms is small, so that the factors that cause the current imbalance are the difference in the impedance inside the semiconductor element and each terminal (U terminal, P terminal, N terminal). This is the difference in impedance due to the difference in wiring distance between the terminal and the semiconductor element. However, since the current flowing in each of the two divided phases by the magnetic coupling by the core 7 becomes equal, FIG.
Since the wiring distance is reduced to about 1 / as compared with that shown in FIG. 1, the current imbalance is further reduced. As a result, the heating of a part of the semiconductor element is also reduced, so that there is an advantage that the cooling body can be reduced.

【0014】[0014]

【発明の効果】この発明によれば、配線基板の正端子
層,負端子層および交流端子層を互いに平行にかつ接近
して積層し、交流端子層と正端子層,負端子層間を流れ
る電流方向が互いに逆となるようにすることで、各半導
体素子の電流アンバランスを小さくする。また、上記の
ような構成において交流端子層を2分割し、両者をコア
結合することで、電流アンバランスをさらに小さくし、
熱集中を回避することができるという利点が得られる。
半導体素子が取り付けられるベース面の、半導体素子が
並列接続される並びの方向に沿ってヒートパイプを挿入
し、かつ、前記ベース面の裏側に放熱用フィンを配置す
ることで、局部熱集中が分散されコンパクト化が可能に
なる、などの利点が得られる。
According to the present invention, the positive terminal layer, the negative terminal layer, and the AC terminal layer of the wiring board are laminated in parallel and close to each other, and the current flowing between the AC terminal layer, the positive terminal layer, and the negative terminal layer. By setting the directions to be opposite to each other, the current imbalance of each semiconductor element is reduced. In addition, in the above configuration, the AC terminal layer is divided into two parts, and the two are core-coupled to further reduce the current imbalance.
The advantage is that heat concentration can be avoided.
By disposing a heat pipe along the direction in which the semiconductor elements are connected in parallel on the base surface on which the semiconductor elements are mounted, and disposing radiating fins behind the base surface, local heat concentration is dispersed. This makes it possible to achieve compactness and the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1の実施の形態を示す外観図であ
る。
FIG. 1 is an external view showing a first embodiment of the present invention.

【図2】図1の側面図である。FIG. 2 is a side view of FIG.

【図3】この発明における電流経路説明図である。FIG. 3 is an explanatory diagram of a current path in the present invention.

【図4】この発明の第2の実施の形態を示す外観図であ
る。
FIG. 4 is an external view showing a second embodiment of the present invention.

【図5】この発明の第3の実施の形態を示す外観図であ
る。
FIG. 5 is an external view showing a third embodiment of the present invention.

【図6】半導体スタックの従来例を示す回路図である。FIG. 6 is a circuit diagram showing a conventional example of a semiconductor stack.

【図7】半導体スタックの従来例を示す構成図である。FIG. 7 is a configuration diagram showing a conventional example of a semiconductor stack.

【図8】図7の側面図である。FIG. 8 is a side view of FIG. 7;

【図9】図7の場合の電流経路説明図である。9 is an explanatory diagram of a current path in the case of FIG. 7;

【図10】冷却体の従来例を示す概要図である。FIG. 10 is a schematic diagram showing a conventional example of a cooling body.

【符号の説明】[Explanation of symbols]

1…半導体素子、2…ベース面、3…配線基板、4…電
解コンデンサ、5…ヒートパイプ、6…放熱フィン、7
…コア。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Base surface, 3 ... Wiring board, 4 ... Electrolytic capacitor, 5 ... Heat pipe, 6 ... Radiation fin, 7
…core.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の半導体素子と、これらを並列接続
するための正端子層,負端子層および交流端子層からな
る配線基板と、前記半導体素子を冷却するための冷却体
とからなる電力変換装置の半導体スタックにおいて、 前記配線基板の正端子層,負端子層および交流端子層を
互いに平行にかつ近接して積層し、交流端子層と正端子
層,負端子層間を流れる電流方向がそれぞれ互いに逆と
なるようにしたことを特徴とする電力変換装置の半導体
スタック。
1. A power conversion system comprising: a plurality of semiconductor elements; a wiring board including a positive terminal layer, a negative terminal layer, and an AC terminal layer for connecting the semiconductor elements in parallel; and a cooling body for cooling the semiconductor elements. In the semiconductor stack of the device, the positive terminal layer, the negative terminal layer, and the AC terminal layer of the wiring board are laminated in parallel and close to each other, and the current directions flowing between the AC terminal layer, the positive terminal layer, and the negative terminal layer are mutually different. A semiconductor stack for a power converter, wherein the semiconductor stack is configured to be reversed.
【請求項2】 複数の半導体素子と、これらを並列接続
するための正端子板,負端子板および交流端子板からな
る配線基板と、前記半導体素子を冷却するための冷却体
とからなる電力変換装置の半導体スタックにおいて、 前記冷却体を、半導体素子が取り付けられるベース面
の、半導体素子が並列接続される並びの方向に沿ってヒ
ートパイプを挿入し、かつ、前記ベース面の裏側に放熱
用フィンを配置したことを特徴とする電力変換装置の半
導体スタック。
2. A power converter comprising: a plurality of semiconductor elements; a wiring board including a positive terminal plate, a negative terminal plate, and an AC terminal plate for connecting the semiconductor elements in parallel; and a cooling body for cooling the semiconductor elements. In the semiconductor stack of the device, a heat pipe is inserted into the cooling body along a direction in which the semiconductor elements are connected in parallel on a base surface on which the semiconductor elements are mounted, and a radiating fin is provided on the back side of the base surface. A semiconductor stack of a power conversion device, comprising:
【請求項3】 前記交流端子層を2分割し、両者をコア
結合したことを特徴とする請求項1に記載の電力変換装
置の半導体スタック。
3. The semiconductor stack for a power conversion device according to claim 1, wherein said AC terminal layer is divided into two parts and both are core-coupled.
JP13266797A 1997-05-23 1997-05-23 Semiconductor stack of power conversion device Pending JPH10327573A (en)

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