JPH10326894A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a small chip area and small ON loss. SOLUTION: In a semiconductor region (dielectric strength layer 1003) of a 1st conductivity type as a current path between a semiconductor region (base contact region 1016) of a 2nd conduction type and a high-density semiconductor region (drain contact region 4) of the 1st conduction type, a conductive region (embedded electrode 5) separated by an insulating film 3 from the semiconductor region 1003 of the 1st conductivity type is provided to form a narrow drain region which is narrower than the semiconductor region of the 1st conductivity type partially in the longitudinal and lateral directions, thereby terminating a drain electric field to the conductive region. Thus, the drain electric field is made not to reach a source side, so that no high voltage is applied to the dielectric strength layer nearby the base region for reducing the distance between a drain lead-out region and the base region, resulting in the reducible chip region. Further, the impurity density of the dielectric strength layer nearby the source can be made high, and the thickness of the dielectric strength layer can be made thin, so that the ON loss can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage type semiconductor device.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional semiconductor device. This is an example in which a horizontal UMOS is formed using the technique disclosed in Japanese Patent Application Laid-Open No. 63-173371. In this conventional example, a P-type substrate (10
01) An N-type buried layer (1002) is formed on the surface,
An N breakdown voltage layer (1003) is formed on the upper surface to form a substrate. Then, it is connected to the buried layer (1002) to form a lead region (1004) and is connected to the drain electrode (1011) on the substrate surface. There is also a gate electrode (1008) connected to the gate polysilicon (1007) formed on the substrate surface side, and a source region (1006) formed around the gate electrode (1006) and a base contact region (1016). A source electrode (1009) connected to (1005) is formed on the substrate surface. A gate insulating film (101) is provided between the gate polysilicon (1007) and the source region (1006).
7) is formed.

In this configuration, the factors that determine the withstand voltage of the semiconductor device are the impurity concentration of the N withstand voltage layer (1003), the distance from the base region (1005) to the buried layer (1002), and the factors derived from the base region (1005). This is the distance to the region (1004). Normally, when trying to increase the breakdown voltage of this semiconductor device, the N breakdown voltage layer (1003) is made to have a low concentration (that is, high resistance), and the base region (1005)
From the buried layer (1002) and the extraction region (10
04) is increased (that is, the resistance is increased) to obtain a desired breakdown voltage. At this time, the extraction area (100
The distance in the horizontal direction between 4) and the base region (1005) needs to be at least larger than the thickness of the N breakdown voltage layer (1003) below the base region (1005).

[0004]

As described above, if the withstand voltage is increased, the extraction region (100
It is necessary to increase the distance between 4) and the base region (1005), which causes a problem that the size of the semiconductor device increases. Further, it is necessary to increase the breakdown voltage of the breakdown voltage layer. As a result, there is a problem that the resistance between terminals of the semiconductor device increases, and the power loss of the semiconductor device when used as a switching device increases.

More specifically, for example, when a semiconductor device with a withstand voltage of 300 V is to be formed, the impurity concentration of the N withstand voltage layer (1003) is as high as 1 × 10 ¹⁵ cm to ³ or less, that is, 5 Ω · cm or more in specific resistance. Must be resistance. The thickness of the N breakdown voltage layer (1003) needs to be 19 μm or more, and the extraction region (1004) and the base region (1010)
05) also depends on the breakdown voltage.
005) It needs to be longer than the thickness of the lower breakdown voltage layer.
Further, since the lead region (1004) also needs to be formed by deep diffusion, the lead region (1004)
Also increases in the lateral direction due to lateral diffusion. As a result, when the size of the semiconductor device shown in FIG. 6 is, for example, formed by the 1 μm rule, the lateral dimension is 9 μm in the base region width including two gate polysilicons, and the distance from the base region end to the extraction region end. Is 19 μm or more, and the width of the extraction region is 46 μm, which is 74 μm or more in total. According to our calculation, the on-resistance Rsp normalized by the area is about 20Ω · c
m ² or more. As described above, in the conventional device, if the breakdown voltage is increased, the size of the semiconductor device increases, and the ON loss increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and has as its object to provide a semiconductor device having a small chip area and a small on-loss.

[0007]

In order to achieve the above object, the present invention has a structure as described in the claims. That is, in the present invention, a semiconductor of the first conductivity type serving as a current path between a semiconductor region of the second conductivity type (eg, a base contact region) and a high-concentration semiconductor region (eg, a drain contact region) of the first conductivity type. By providing a conductive region separated from the first conductivity type semiconductor region by an insulating film in the region, a narrow drain region in which the first conductivity type semiconductor region is locally narrowed in the vertical and horizontal directions is formed. It is configured to terminate the drain electric field to the conductive region.
In addition, a plurality of conductive regions surrounded by the above-described insulating film are continuously provided to further reduce the chip area.

In the present invention, by preventing the drain electric field from reaching the source side (base region side), a high voltage is not applied to the breakdown voltage layer near the base region so that the distance between the drain extraction region and the base region is reduced. Therefore, the chip area can be reduced. Further, since the impurity concentration of the breakdown voltage layer near the source can be increased (low resistance) and the thickness of the breakdown voltage layer can be reduced,
ON loss can be reduced.

In a structure in which a plurality of conductive regions surrounded by an insulating film are continuously provided, even if the distance for terminating the drain electric field to the conductive region is sufficiently long, the reduced withstand voltage layer is formed in the vertical and horizontal directions. , The chip area can be reduced.

[0010]

According to the present invention, since the distance between the drain extraction region and the base region can be reduced, the chip area is reduced, and the yield is thereby improved, and the chip cost is greatly reduced. You. Further, since the impurity concentration of the breakdown voltage layer near the source can be made high (low resistance) and the thickness of the breakdown voltage layer can be reduced, the effect of reducing on-loss can be obtained.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a sectional view showing a first embodiment of the present invention, and has a structure corresponding to, for example, claim 1, claim 2, or claim 8. In the drawings showing each embodiment to be described later, the same or equivalent parts as those in FIG. 6 and FIG. 1 are denoted by the same symbols as those in FIG. 6 and FIG. .

As shown in FIG. 1, in the first embodiment, a buried insulating film (2) is formed on the upper surface of a semiconductor substrate (1), and an N-type breakdown voltage layer (1003) is formed on a part of the upper surface. Is formed. Here, the semiconductor substrate (1) is not limited to a semiconductor substrate as long as it is a conductive substrate. Also, a P-type base region (103) is formed on the surface inside the breakdown voltage layer (1003).
05), a gate insulating film (1017) and a gate polysilicon (1017) penetrating through the base region (1005).
07), a second insulating film (3) and an N + -type drain contact (4) are formed adjacent thereto, and further, the second insulating film (3) is formed to a predetermined depth from the surface. ) Surrounded by, for example, impurity-doped poly-Si
Embedded electrode (5) is formed adjacent to the drain contact region (4). Further, an N + type source region (1006) and a P + type base contact region (1016) are formed on the surface inside the base region (1005).

Further, although not shown, a P-type minority carrier lead-out region is formed in contact with the second insulating film (3) at a predetermined position in front of the paper or in a depth direction.

The above-described structure is characterized in that a portion sandwiched between two embedded electrodes (5) surrounded by the second insulating film (3) is vertically oriented and the second insulating film (3). ), A portion sandwiched between the buried electrode (5) surrounded by the semiconductor substrate 1 with the buried insulating film (2) interposed therebetween in a laterally limited narrow range from the drain contact region (4) to the base. This means that a drain region is formed as a current path toward the breakdown voltage layer (1003) below the region. The embedded electrode (5) and the semiconductor substrate 1
Is grounded.

With the above structure, the structure shown in FIG. 1 has a structure in which a narrow drain region serving as a current path is formed in a vertical direction and a horizontal direction in a drain region of a MOS transistor having a so-called UMOS structure.

Although the gate electrode, source electrode, and drain electrode as shown in FIG. 6 are not shown in FIG.
It can be considered that it is formed similarly to

Next, the operation of the first embodiment will be described. In the structure of FIG. 1, the semiconductor substrate (1) and the buried electrode (5) are grounded, and a high voltage, for example, 300 V is applied to the drain contact region (4). Then, the source region (1006) and the base contact region (1016) of the MOS transistor are also grounded. At this time, if the gate polysilicon (1007) is grounded, the MOS transistor is turned off. If the gate polysilicon (1007) is set to a positive voltage and a voltage equal to or higher than a predetermined threshold (for example, 5V), the MOS transistor is turned off. ON to form a drain contact region (4) and a source region (100
Current flows during 6) and the drain contact region (4)
Also drops.

Next, gate polysilicon (1007)
Is equal to or lower than the ground or the threshold, that is,
Consider the case where the S transistor is off. At this time, a drain electric field is generated by the drain voltage applied to the drain contact region (4). All lines of electric force due to the drain electric field terminate in the oxide film sandwiching the narrow drain region. At this time, the narrow drain region is all depleted.
Therefore, no high drain electric field is applied to the periphery of the base region (1005), and the peripheral potential of the base region (1005) hardly increases despite the device being turned off.
At this time, the minority carriers generated in the vicinity of the second insulating film (3) are extracted from the minority carrier extraction region (not shown), so that the element characteristics are not adversely affected.

As a result, despite the high breakdown voltage, for example, a 300 V semiconductor device, the breakdown voltage layer (100
3) can be designed as a low withstand voltage, for example, a 20 V system, the impurity concentration can be reduced to 5 × 10 ¹⁶ cm ³ (that is, 0.15 Ω · cm), and the impurity concentration under the base region (1005) can be reduced. The thickness of the pressure-resistant layer (1003) is 0.6 μ
m.

Further, the distance from the base region (1005) to the second insulating film (3) may be approximately the same as the thickness of the breakdown voltage layer (1003) below the base region (1005), so that the gap is at most 1 μm. I just need. For example, when designed according to the 1 μm rule, the width of the base region is 9 μm, and the width from the end of the base region to the end of the second insulating film (3) is about 1 μm.

Further, since the narrow region sandwiched by the insulating films is formed so as to be shared in the depth direction and the lateral direction, the lateral dimension can be reduced. That is, even if the distance from the end of the second insulating film (3) to the drain contact region (4) is about 10 μm, the current path passes from the horizontal direction to the vertical direction sandwiched between the two insulating films (3). Therefore, it can be considered by adding the vertical direction (the thickness of the breakdown voltage layer 1003) to the horizontal direction.
As a result, even in the case of a semiconductor device of, for example, 300 V, the lateral dimension may be about 20 μm. Therefore, the chip area is reduced, and the yield is thereby improved, and the chip cost is significantly reduced.

In particular, when the required effective length of the narrow drain region sandwiched between the insulating films is approximately the same as or slightly longer than the depth of the breakdown voltage layer (1003), the lateral narrow drain length is effectively shortened. it can. Specifically, when the effective length of the narrow drain region is substantially the same as the depth of the breakdown voltage layer (1003), only the narrow drain region in the depth direction is depleted, and the electric field is reduced by the second insulating film (3). It is also possible to terminate with only two adjacent grounded buried electrodes (5), in which case the laterally narrow drain region length L is: L = second insulating film (3 ) × 2 + the minimum thickness of the buried electrode (5), which is at most several μm or less.

In the first embodiment, the gate mechanism of the MOS transistor is a trench gate (UMOS).
However, it is apparent that the same effect can be obtained in the case of LDMOS.

Further, by changing the polarity of the drain contact region (4) from N + type to P + type to form an IGBT (insulated gate bipolar transistor), the device O
At N, the resistance of the narrow drain region can be reduced by the effect of the so-called conductivity modulation. Therefore, in the embodiment of the present invention, the increase in resistance due to the narrowing of the current path when the narrow drain region is formed is solved. It is obvious. Also, since only a narrow drain region is required for the portion where conductivity modulation is performed, the amount of holes to be injected is small compared to a general IGBT, so that the device is turned off.
There is also an effect that the switching delay time at the time of the above is reduced. As described above, when the IGBT is used, the effect of the present invention is further enhanced.

(Second Embodiment) FIG. 2 is a sectional view showing a second embodiment of the present invention, and has a structure corresponding to, for example, claim 4 or claim 6. As shown in FIG. 2, in the second embodiment, a first embedded electrode (6) having a plurality of upward projections is formed on the upper surface of a semiconductor substrate (1). Electrically continuous. A buried insulating film (7) is formed on the upper surface. An N-type breakdown voltage layer (1003) is formed on a part thereof. Here, the semiconductor substrate (1) is not limited to a semiconductor substrate as long as it is a conductive substrate. Further, a P-type base region (100) is formed on the surface inside the breakdown voltage layer (1003).
5) and the gate insulating film (1017) and the gate polysilicon (1) penetrating through the base region (1005).
007) is formed, and a second insulating film (3) and an N + -type drain contact region (4) are formed adjacent to them.

An extraction region (1004) is formed under the drain contact region (4), and is further surrounded by a second insulating film (3) from the surface to a predetermined depth. 2 embedded electrodes (5)
Are formed with the drain contact region (4) interposed therebetween. The second buried electrode (5) forms a plurality of protrusions toward the lower side, and the protrusions are alternated with the first buried electrode (6) having a plurality of protrusions upward, and A narrow drain region (a narrow region sandwiched between insulating films) is formed in the direction and the depth direction. Further, inside the base region (1005), an N + type source region (10
06) and a P + type base contact region (101
6) is formed.

Further, although not shown, a P-type minority carrier lead-out region is formed in contact with the second insulating film (3) at a predetermined position in front of the paper or in a depth direction.

The gate electrode, source electrode and drain electrode as shown in FIG. 6 are not shown.

The characteristic feature of the above structure is that the buried insulating film (7) comprising upper and lower protrusions arranged alternately and adjacently and the second insulating film (3) form the drain contact region ( The current path from 4) to the breakdown voltage layer (1003) below the base region is formed continuously as a narrow drain region narrowed in the lateral direction and the depth direction.

As a result, the configuration shown in FIG.
In the drain region of the MOS transistor having the OS structure, the current flow path is formed through the buried insulating film (7) and the second insulating film (3) to form the first buried electrode (6) and the second buried electrode (5). ) And the drain region are continuously sandwiched in the horizontal and depth directions to form a long zigzag narrow drain region.

Next, the operation of the second embodiment will be described. In the structure of FIG. 2, the semiconductor substrate (1) and the first buried electrode (6) are grounded, and a high voltage, for example, 300 V is applied to the drain contact region (4). Then, the source region (1006) and the base contact region (1016) of the MOS transistor are also grounded. At this time, if the gate polysilicon (1007) is grounded, the MOS transistor is turned off, and if the gate polysilicon (1007) is set to a positive voltage and a predetermined threshold voltage or more (for example, 5V), the MOS transistor is turned on. To form a drain contact region (4) and a source region (100
Current flows during 6) and the drain contact region (4)
Also drops.

Next, gate polysilicon (1007)
Is equal to or lower than the ground or the threshold, that is,
Consider the case where the S transistor is off. At this time, a drain electric field is generated by the drain voltage applied to the drain contact region (4). All lines of electric force due to the drain electric field terminate in the oxide film sandwiching the narrow drain region. At this time, the narrow drain region is all depleted.
Therefore, no high drain electric field is applied to the periphery of the base region (1005), and the peripheral potential of the base region (1005) hardly increases despite the device being turned off.
At this time, minority carriers generated in the vicinity of the second insulating film (3) are extracted from the minority carrier extraction region (not shown), and thus do not adversely affect device characteristics.

As a result, despite the high breakdown voltage, for example, a 300 V semiconductor device, the breakdown voltage layer (100
3) can be designed as a low withstand voltage, for example, a 20 V system, the impurity concentration can be reduced to 5 × 10 ¹⁶ cm ³ (that is, 0.15 Ω · cm), and the impurity concentration under the base region (1005) can be reduced. The thickness of the pressure-resistant layer (1003) is 0.6 μ
m. Further, the distance from the base region (1005) to the second insulating film (3) may be about the same as the thickness of the breakdown voltage layer (1003) below the base region (1005), and therefore, it is sufficient to leave an interval of at most 1 μm.

For example, when designed according to the 1 μm rule, the width of the base region is 9 μm, and the width from the end of the base region to the end of the second insulating film (3) is about 1 μm. Further, since the narrow drain region is formed so as to be shared by a plurality of depth directions and a plurality of horizontal directions, the length of the narrow drain region in the horizontal direction is further reduced. Conventionally, the distance from the end of the base region (1005) to the lead-out region was set to be close to 20 μm. However, this distance can be reduced to 10 μm or less at most, and the horizontal dimension which was 74 μm or more as a whole becomes 64 μm and 10 μm. Can be reduced. As a result, the lateral dimension is reduced, and the chip area is reduced. Further, the yield is thereby improved, and the chip cost is significantly reduced. In particular, when the effective length of the necessary narrow drain region is several times longer than the depth of the breakdown voltage layer (1003), the lateral dimension can be effectively shortened by the present invention.

Although the second embodiment has exemplified the case where the gate mechanism of the MOS transistor is a trench gate (UMOS), it is apparent that the same effect can be obtained in the case of an LDMOS. Further, when the polarity of the drain contact region (4) is changed from N + type to P + type to make it an IGBT, when the device is turned on, the resistance of the narrow drain region can be reduced by the effect of so-called conductivity modulation. Thus, it is apparent that an increase in resistance due to a narrow current path when a narrow drain region is formed is solved. Further, the portion to be subjected to the conductivity modulation may be only the narrow drain region. Therefore, the amount of holes to be injected is smaller than that of a general IGBT, so that the switching delay time when the device is turned off is reduced. As described above, when the IGBT is used, the effect of the present invention is increased.

(Third Embodiment) FIG. 3 is a view showing a third embodiment of the present invention, and has a structure corresponding to, for example, claim 3, claim 6, or claim 8. As shown in FIG. 3, in the third embodiment, a first embedded electrode (6) having a plurality of upward projections is formed on an upper surface of a semiconductor substrate (1), and a first embedded electrode is formed on the upper surface thereof. An insulating film (7) is formed. An N-type breakdown voltage layer (1003) is formed on a part thereof. Here, the semiconductor substrate (1) is not limited to a semiconductor substrate as long as it is a conductive substrate. In addition, a P-type base region (1005) is formed on the surface inside the breakdown voltage layer (1003), and a base region (100
5), a gate insulating film (1017) and a gate polysilicon (1007) are formed, and a second insulating film (3) and an N + type drain contact region (4) are formed adjacent thereto. A second buried electrode (5) made of, for example, poly-Si doped with an impurity, surrounded by a second insulating film (3) from the surface to a predetermined depth.
Are formed adjacent to each other with the drain contact region (4) interposed therebetween. The second buried electrode (5) forms a plurality of protrusions toward the lower side, and the protrusions are alternated with the first buried electrode (6) having a plurality of protrusions upward, and A narrow drain region (a narrow region sandwiched between insulating films) in the direction and depth direction is formed. Further, an N + type source region (1006) and a P + type base contact region (1) are formed on the surface inside the base region (1005).
016) is formed.

Further, although not shown, a P-type minority carrier lead-out region is formed in contact with the second insulating film (3) at a predetermined position in front of the paper or in a depth direction. Note that the gate electrode, the source electrode, and the like as shown in FIG.
The illustration of the drain electrode is omitted.

The above structure is characterized in that the embedded electrodes (5) surrounded by the second insulating film (3) are vertically arranged so as to be adjacent to each other in the depth direction and alternately. The withstand voltage layer (1003) below the base region from the drain contact region (4) in the lateral direction and the depth direction by the second insulating film (3) composed of the portion and the buried insulating film (7).
That is, a narrow drain region in which the current path is narrowed is formed. The difference from the second embodiment is that
The point is that a narrow drain region is formed in the depth direction also in the insulating films formed adjacent to each other with the drain contact region (4) interposed therebetween.

As a result, the configuration shown in FIG.
In the drain region of the MOS transistor having the OS structure, the current flow path is formed in the lateral direction, the depth direction, and the second insulating film through the buried insulating film and the second insulating film. The structure is such that a continuous narrow drain region is formed in the depth direction between adjacent buried electrodes.

Next, the operation of the third embodiment will be described. In the structure of FIG. 3, the semiconductor substrate (1) and the first
Of the buried electrode (6) is grounded, and a high voltage, for example, 300 V is applied to the drain contact region (4). Then, the source region (1006) and the base contact region (1016) of the MOS transistor are also grounded. At this time, if the gate polysilicon (1007) is grounded, the MOS transistor is turned off. If the gate polysilicon (1007) is set to a positive voltage and a voltage equal to or higher than a predetermined threshold (for example, 5V), the MOS transistor is turned off. ON to form a drain contact region (4) and a source region (100
Current flows during 6) and the drain contact region (4)
Also drops.

Next, gate polysilicon (1007)
Is equal to or lower than the ground or the threshold, that is,
Consider the case where the S transistor is off. At this time, a drain electric field is generated by the drain voltage applied to the drain contact region (4). All lines of electric force due to the drain electric field terminate in the oxide film sandwiching the narrow drain region. At this time, the narrow drain region is all depleted.
Therefore, no high drain electric field is applied to the periphery of the base region (1005), and the peripheral potential of the base region (1005) hardly increases despite the device being turned off.
At this time, the minority carriers generated in the vicinity of the second insulating film (3) are extracted from the minority carrier extraction region (not shown), and do not adversely affect the element characteristics.

As a result, despite the high breakdown voltage, for example, a 300 V semiconductor device, the breakdown voltage layer (100
3) can be designed as a low withstand voltage, for example, a 20 V system, and the impurity concentration can be reduced to 5 × 10 ¹⁶ cm ³ (that is, 0.15 Ω · cm) and the base region (1
005) The thickness of the lower breakdown voltage layer (1003) is 0.6 μm
, Can be made extremely thin. Further, the distance from the base region to the second insulating film (3) is also increased.
5) Since the thickness may be approximately the same as the thickness of the lower pressure-resistant layer (1003), an interval of at most 1 μm is sufficient. For example, 1μ
When designed according to the m rule, the width of the base region is 9 μm, and the width from the end of the base region to the end of the second insulating film (3) is about 1 μm.

Further, since the narrow drain region is formed so as to be shared by a plurality of depth directions and a plurality of horizontal directions, the length of the narrow drain region in the horizontal direction is shortened. As a result, the lateral dimension is reduced, and the chip area is reduced. Further, the yield is thereby improved, and the chip cost is significantly reduced.

In particular, when the required effective length of the narrow drain region is several times longer than the depth of the breakdown voltage layer (1003),
According to the present invention, a narrow drain length in the horizontal direction can be effectively shortened.

Further, in this embodiment, the case where the gate mechanism of the MOS transistor is a trench gate (UMOS) has been exemplified, but it is apparent that the same effect can be obtained also in the case of the LDMOS.

When the polarity of the drain contact region (4) is changed from N + type to P + type to make it an IGBT, when the device is turned on, the resistance of the narrow drain region can be reduced by the effect of so-called conductivity modulation. It is apparent that the embodiment solves the increase in resistance due to the narrow current path when a narrow drain region is formed. Further, the portion to be subjected to the conductivity modulation may be only the narrow drain region. Therefore, the amount of holes to be injected is a general IGB
Since only a small amount is required as compared with T, there is also an effect that the switching delay time when the device is turned off is reduced. As described above, when the IGBT is used, the effect of the present invention is increased.

(Fourth Embodiment) FIGS. 4A and 4B are views showing a fourth embodiment of the present invention, wherein FIG.
(B) is a sectional view. This configuration corresponds to, for example, claim 5 or claim 8. As shown in FIG. 4, in the fourth embodiment, a buried insulating film (2) is formed on the upper surface of a semiconductor substrate (1). An N-type breakdown voltage layer (1003) is formed on a part thereof. Here, the semiconductor substrate (1) is not limited to a semiconductor substrate as long as it is a conductive substrate. In addition, a P-type base region (1005) is formed on the surface inside the breakdown voltage layer (1003), and a base region (100
5), a gate insulating film (1017) and a gate polysilicon (1007) are formed, and a second insulating film (3) and an N + type drain contact region (4) are formed adjacent thereto. A second buried electrode (5) made of, for example, poly-Si doped with an impurity, surrounded by a second insulating film (3) from the surface to a predetermined depth.
Are formed with the drain contact region (4) interposed therebetween. In the case of FIG. 4, the second insulating film (3) has reached the buried insulating film (2).

Further, an N + type source region (1006) and a P + type base contact region (1016) are formed on the surface inside the base region (1005). Further, although not shown, a P-type minority carrier extraction region is formed in contact with the second insulating film (3) at a predetermined position in front of the paper surface or at a predetermined position in the depth direction. The illustration of the gate electrode, source electrode, and drain electrode as shown in FIG. 6 is omitted.

The base region (1005) and the drain contact region (4) are formed in a straight line facing each other as shown in the plan view of FIG. Similarly, a gate insulating film (1017), polysilicon for gate (1007), and an N + type source region (1006) and a P + type base contact region (1016) on the surface inside the base region (1005). They are arranged in a stripe shape in a plane. Also, the second insulating film (3)
A plurality of buried electrodes (5) are formed linearly along the drain contact region (4) and covered with the second insulating film (3). The second insulating film (3) is formed from the front side of the substrate and reaches the buried insulating film (2). A plurality of adjacent second insulating films (3) are continuously formed in a comb-tooth shape every other so as not to come into contact with each other in a plane.

What is characteristic of the above structure is that the second insulating films (3) arranged alternately adjacent to each other have a depth equivalent to a withstand voltage layer so that the withstand voltage from the drain contact region (4) can be reduced. A narrow drain region in which a current path to the layer (1003) is narrowed is formed to be long in a zigzag and lateral direction in a plane.

As a result, the configuration of FIG.
In the drain region of the MOS transistor having the S structure,
The current path has a structure in which a narrow drain region limited by a plurality of buried electrodes (5) surrounded by a second insulating film (3) is formed long.

Next, the operation of the fourth embodiment will be described. In the structure of FIG. 4, the semiconductor substrate (1) is grounded,
A high voltage, for example, 30 is applied to the drain contact region (4).
0 V is applied. Then, the source region (1006) of the MOS transistor and the base contact region (101)
6) is also grounded. At this time, the gate polysilicon (1
007) is grounded, the MOS transistor is turned off. If the gate polysilicon (1007) is set to a positive voltage and a voltage higher than a predetermined threshold (for example, 5V), the MOS transistor is turned off.
The transistor turns on, a current flows between the drain contact region (4) and the source region (1006), and the potential of the drain contact region (4) also decreases.

Next, gate polysilicon (1007)
Is equal to or lower than the ground or the threshold, that is,
Consider the case where the S transistor is off. At this time, a drain electric field is generated by the drain voltage applied to the drain contact region (4). All lines of electric force due to the drain electric field terminate in the oxide film sandwiching the narrow drain region. At this time, the narrow drain region is all depleted.
Therefore, no high drain electric field is applied to the periphery of the base region (1005), and the peripheral potential of the base region (1005) hardly increases despite the device being turned off.
At this time, minority carriers generated in the vicinity of the second insulating film are extracted from the minority carrier extraction region (not shown), so that the device characteristics are not adversely affected.

As a result, despite the high breakdown voltage, for example, a 300 V semiconductor device, the breakdown voltage layer (100
3) can be designed as a low withstand voltage, for example, a 20 V system, and the impurity concentration can be reduced to 5 × 10 ¹⁶ cm ³ (that is, 0.15 Ω · cm) and the base region (1
005) The thickness of the lower breakdown voltage layer (1003) is 0.6 μm
, Can be made extremely thin. Further, the distance from the base region (1005) to the second insulating film (3) may be about the same as the thickness of the breakdown voltage layer (1003) below the base region (1005), and therefore, it is sufficient to leave an interval of at most 1 μm. For example, when designed according to the 1 μm rule, the width of the base region is 9 μm, and the width from the end of the base region to the end of the second insulating film (3) is about 1 μm.

Further, since the narrow drain region is formed by sharing a plurality of stripes, the length of the narrow drain region in the horizontal direction is reduced. As a result, the lateral dimension is reduced, and the chip area is reduced. Further, the yield is thereby improved, and the chip cost is significantly reduced. In particular, when the effective length of the necessary narrow drain region is several times longer than the depth of the breakdown voltage layer (1003), the lateral dimension can be effectively shortened by the present invention.

In this embodiment, since the second insulating film (3) is formed from the front surface side of the substrate, there is also an advantage that the manufacturing process can be simplified as compared with the third embodiment.

Further, in this embodiment, the case where the gate mechanism of the MOS transistor is a trench gate (UMOS) has been exemplified, but it is apparent that the same effect can be obtained also in the case of the LDMOS.

Further, if the polarity of the drain contact region (4) is changed from N + type to P + type to make it an IGBT, when the device is turned on, the resistance of the narrow drain region can be reduced by the effect of so-called conductivity modulation. It is apparent that the embodiment solves the problem that the current path is narrowed and the resistance is increased when a narrow drain region is formed.
Further, the portion to be subjected to the conductivity modulation may be only the narrow drain region. Therefore, the amount of holes to be injected is smaller than that of a general IGBT.
There is also an effect that the switching delay time at the time of F is reduced. As described above, when the IGBT is used, the effect of the present invention is increased.

(Fifth Embodiment) FIG. 5 is a sectional view showing a fifth embodiment of the present invention. As shown in FIG. 5, in the fifth embodiment, an N-type breakdown voltage layer (1003) is formed on a part of the upper surface of a P-type semiconductor substrate (10). Withstand voltage layer (10
03) P-type base region (1005) on the surface inside,
Further, the gate insulating film (1017) and the polysilicon for gate (1007) penetrate the base region (1005).
Are formed adjacent thereto, a second insulating film (3) and an N + -type drain contact (4) are formed. Further, the second insulating film (3) is formed from the surface to a predetermined depth. A buried electrode (5) of, for example, poly-Si doped with impurities is formed to surround the drain contact region (4). Further, inside the base region (1005), an N + type source region (10
06) and a P + type base contact region (101
6) is formed.

Further, although not shown, a P-type minority carrier lead-out region is formed in contact with the second insulating film (3) at a predetermined position in front of the paper or in a depth direction.

What is characteristic of the above structure is that two adjacent grounded buried electrodes (5) surrounded by a second insulating film (3) vertically extend the second insulating film (3). A narrow drain region from the drain contact region (4) to the breakdown voltage layer (1003) is formed laterally by the grounded buried electrode (5) and the grounded semiconductor substrate (1) surrounded by 3). That is.

As a result, the configuration of FIG.
In the drain region of the MOS transistor having the S structure,
Two adjacent grounded buried electrodes (5) surrounded by a second insulating film (3); and a grounded buried electrode (5) surrounded by a second insulating film (3). With the semiconductor substrate (1) being grounded, a narrow region from the drain contact region (4) to the breakdown voltage layer (1003) is formed in the vertical and horizontal directions.

The difference between the present embodiment and FIG. 1 is that in FIG. 5, a normal P-type bulk wafer is used as a substrate without using an SOI substrate. FIG.
, The gate electrode, the source electrode, and the drain electrode are not shown.

Next, the operation of the fifth embodiment will be described. In the structure of FIG. 5, the semiconductor substrate (1) is grounded,
A high voltage, for example, 30
0 V is applied. Then, the source region (1006) of the MOS transistor and the base contact region (101)
6) is also grounded. At this time, the gate polysilicon (1
007) is grounded, the MOS transistor is turned off. If the gate polysilicon (1007) is set to a positive voltage and a voltage higher than a predetermined threshold (for example, 5V), the MOS transistor is turned off.
The transistor turns on, a current flows between the drain contact region (4) and the source region (1006), and the potential of the drain contact region (4) also decreases.

Next, gate polysilicon (1007)
Is equal to or lower than the ground or the threshold, that is,
Consider the case where the S transistor is off. At this time, a drain electric field is generated by the drain voltage applied to the drain contact region (4). All lines of electric force due to the drain electric field terminate in the oxide film sandwiching the narrow drain region. At this time, the narrow drain region is all depleted.
Therefore, no high drain electric field is applied to the periphery of the base region (1005), and the peripheral potential of the base region (1005) hardly increases despite the device being turned off.
At this time, minority carriers generated in the vicinity of the insulating film are extracted from the minority carrier extraction region (not shown), so that the element characteristics are not adversely affected.

As a result, despite the high breakdown voltage, for example, a 300 V semiconductor device, the breakdown voltage layer (100
3) can be designed as a low withstand voltage, for example, a 20 V system, the impurity concentration can be reduced to 5 × 10 ¹⁶ cm ³ (that is, 0.15 Ω · cm), and the impurity concentration under the base region (1005) can be reduced. The thickness of the pressure-resistant layer (1003) is 0.6 μ
m. Further, the distance from the base region (1005) to the second insulating film (3) may be about the same as the thickness of the breakdown voltage layer (1003) below the base region (1005), and therefore, it is sufficient to leave an interval of at most 1 μm. For example, when designed according to the 1 μm rule, the width of the base region is 9 μm, and the width from the end of the base region to the end of the second insulating film (3) is about 1 μm.

Further, since the narrow region sandwiched between the insulating films is formed so as to be shared in the depth direction and the lateral direction, the lateral dimension can be reduced. That is, even if the distance from the end of the second insulating film (3) to the drain contact region (4) is about 10 μm, the current path passes from the horizontal direction to the vertical direction sandwiched between the two insulating films (3). Therefore, it can be considered by adding the vertical direction (the thickness of the breakdown voltage layer 1003) to the horizontal direction.
As a result, even in the case of a semiconductor device of, for example, 300 V, the lateral dimension may be about 20 μm. Therefore, the chip area is reduced, and the yield is thereby improved, and the chip cost is significantly reduced.

In particular, when the required effective length of the narrow drain region sandwiched between the insulating films is about the same as or slightly longer than the depth of the breakdown voltage layer (1003), the lateral narrow drain length is effectively shortened. it can. Specifically, when the effective length of the narrow drain region is substantially the same as the depth of the breakdown voltage layer (1003), only the narrow drain region in the depth direction is depleted, and the electric field is reduced by the second insulating film (3). It is also possible to terminate with only two adjacent grounded buried electrodes (5), in which case the laterally narrow drain region length L is: L = second insulating film (3 ) × 2 + the minimum thickness of the buried electrode (5), which is at most several μm or less.

In the present embodiment, as described above, since a narrow drain region can be formed with a normal P-type bulk wafer without using an SOI substrate, there is also an effect that the manufacturing cost is further reduced.

Further, in this embodiment, the case where the gate mechanism of the MOS transistor is a trench gate (UMOS) is exemplified, but it is apparent that the same effect can be obtained also in the case of the LDMOS.

Further, since the polarity of the drain contact region (4) is changed from N + type to P + type to be IGBT, the resistance of the narrow drain region can be reduced by the so-called conductivity modulation effect when the device is ON. In this embodiment, it is apparent that the increase in resistance due to the narrow current path when a narrow drain region is formed is solved. Further, the portion to be subjected to the conductivity modulation may be only the narrow drain region. Therefore, the amount of holes to be injected is smaller than that of a general IGBT, so that the switching delay time when the device is turned off is reduced. As described above, when the IGBT is used, the effect of the present invention is increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device in the present invention.

FIG. 2 is a cross-sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 3 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIGS. 4A and 4B are diagrams showing a fourth embodiment of the semiconductor device according to the present invention, wherein FIG. 4A is a plan view and FIG.

FIG. 5 is a sectional view showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 buried insulating film 3 second insulating film 4 drain contact 5 buried electrode 6 first buried electrode 7 buried insulating film 10 p-type semiconductor substrate 1001 substrate 1002 buried layer 1003 ... withstand voltage layer 1004 ... lead region 1005 ... base region 1006 ... source region 1007 ... gate polysilicon 1008 ... gate electrode 1009 ... source electrode 1010 ... trench type lead region 1011 ... drain electrode 1012 ... p-substrate 1013 ... n-substrate 1014 ... P base area 1015 ... N + area

Claims (8)

[Claims] A conductive substrate, a buried insulating film formed on the conductive substrate, and a first buried insulating film formed on the buried insulating film.
A semiconductor region of the second conductivity type and a high-concentration semiconductor region of the first conductivity type are formed at a predetermined interval on a part of the substrate having the semiconductor region of the conductivity type. A conductive region surrounded by an insulating film is formed at a predetermined portion between the second conductive type semiconductor region and the first conductive type high concentration semiconductor region, and is opposite to the first conductive type high concentration semiconductor region. A conductive region surrounded by a similar insulating film is also formed on the side, and the high-concentration semiconductor region of the first conductivity type has a shape sandwiched between two conductive regions surrounded by the insulating film. Below the first-conductivity-type high-concentration semiconductor region, the width of the first-conductivity-type semiconductor region serving as a path between the second-conductivity-type semiconductor region and the first-conductivity-type high-concentration semiconductor region is A semiconductor device characterized by being limited. 2. The semiconductor device according to claim 1, wherein the insulating film is formed from a surface side of the substrate to a predetermined depth of the semiconductor region of the first conductivity type, and the semiconductor region of the first conductivity type is surrounded by the conductive region surrounded by the insulating film. 2. The semiconductor device according to claim 1, wherein a region having a limited thickness is formed on a bottom surface side of the first conductivity type semiconductor region. 3. The semiconductor device according to claim 1, wherein a plurality of conductive regions surrounded by the insulating film are formed so as to limit a width of the semiconductor region of the first conductivity type in a lateral direction. Semiconductor device. 4. A conductive substrate, a buried insulating film formed on the conductive substrate, and a first buried insulating film formed on the buried insulating film.
A semiconductor region of the second conductivity type and a high-concentration semiconductor region of the first conductivity type are formed at a predetermined interval on a part of the substrate having the semiconductor region of the conductivity type. A plurality of conductive regions surrounded by an insulating film are formed between the second conductive type semiconductor region and the first conductive type high-concentration semiconductor region, and a second conductive region surrounded by the plurality of insulating films forms a second conductive region. A semiconductor device, wherein a width of a first conductivity type semiconductor region serving as a path between a conductivity type semiconductor region and the first conductivity type high-concentration semiconductor region is limited. 5. A semiconductor device according to claim 1, wherein said second conductivity type semiconductor region and said first conductivity type high-concentration semiconductor region are formed in a straight line so as to face each other in a plane, and said conductive region surrounded by said insulating film is First
A plurality of conductive films are formed linearly along the high-concentration semiconductor region, and are successively formed in a comb-like shape so that adjacent insulating films do not contact each other in a plane. The semiconductor device according to claim 3 or 4, wherein 6. The semiconductor device according to claim 1, wherein said insulating film is formed from a surface side of said substrate to a predetermined depth of said first conductivity type semiconductor region, and said first conductivity type semiconductor region is surrounded by said insulating film. A first portion in which a region whose thickness is limited is formed on the bottom surface side of the semiconductor region of the first conductivity type;
The insulating film is formed continuously with the buried insulating film;
A second portion in which the conductive substrate and the conductive region are formed electrically continuously, and a region where the thickness of the semiconductor region of the first conductivity type is limited is formed on the front surface side of the substrate; And the first part and the second part are
The semiconductor device according to claim 1, wherein the semiconductor region of the first conductivity type is alternately and continuously arranged from the high-concentration semiconductor region of the first conductivity type to the semiconductor region of the second conductivity type with the semiconductor region of the first conductivity type interposed therebetween. The semiconductor device according to claim 3 or 4. 7. The semiconductor device according to claim 1, wherein the conductive substrate is a semiconductor region of the second conductivity type, and the buried insulating film and the conductive region covered with the buried insulating film do not exist. The semiconductor loading described in. 8. The semiconductor device according to claim 1, wherein the high-concentration semiconductor region of the first conductivity type is of a second conductivity type.
The semiconductor device according to any one of the above.