JPH1032553A - Poh termination processor in sdh transmission system and its processing method and pointer poh termination processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce an equipment scale and a power consumption by applying POH termination arithmetic processing to a multiplex signal sent by an SDH(synchronous digital hierarchy) without demultiplexing the signal to each channel as a serial signal. SOLUTION: This system is provided with a POH(a path overhead) termination arithmetic processing section 1 applying POH termination arithmetic processing to a multiplex signal in the SDH transmission system in common to each channel, a storage section 2 for freely reading and writing the arithmetic operation result by the POH termination arithmetic processing section 1 for each channel. In the case of applying the POH termination arithmetic processing to the signal, storage information as to a corresponding channel stored in the storage section 2 is used, the POH termination arithmetic processing section 1 conducts the POH termination arithmetic processing and stores the obtained result of POH termination arithmetic processing to a storage area of a corresponding channel of the storage section 2. Thus, the multiplex signal is not demultiplexed and the POH termination arithmetic processing is applied to the signal as a serial signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Contents) Technical Field to which the Invention pertains Prior Art Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Embodiments of the Invention (A) Outline of SDH Transmission System (FIG. 2) (B) Overview of POH termination processing (FIGS. 11 to 27) (B1) Termination processing of J1 and J2 bytes (FIGS. 11 to 1)
3) (B2) Termination processing of B3 byte (FIGS. 14 to 16) (B3) Termination processing of C2 byte (FIGS. 17 and 18) (B4) Termination processing of G1 byte (FIGS. 19 and 20) (B5) V5 byte termination processing (FIGS. 21 to 25) (B6) Performance monitor (PM) function (FIG. 26,
(C) Description of POH termination device (FIGS. 28 to 122) (C1) Description of overall configuration of POH termination device (FIGS. 28 to 122)
(C2) Description of timing generation unit (FIGS. 41 to 59) (C3) Description of J1 / J2 byte end processing unit (FIG. 60 to FIG. 60)
(FIG. 82) (C4) Description of B3 / V5 byte end processing unit (FIG. 83 to FIG.
(FIG. 100) (C5) Description of C2 / V5 byte end processing unit (FIG. 101)
(C6) Description of G1 / V5 byte end processing unit (FIG. 110)
-D122) (D) Other effects of the invention

[0002]

The present invention relates to an SDH (Synchrono).
The present invention relates to a POH (path overhead) termination processing device, a POH termination processing method, and a pointer / POH termination processing device in a us Digital Hierarchy) transmission method.

[0003]

2. Description of the Related Art In SDH transmission technology, two lines, a working line and a protection line, are usually set between transmission terminal equipments, and the receiving station checks the quality of the communication lines of the working line and the protection line. In this case, the communication line is appropriately switched from the regular line to the spare line according to the degree of quality deterioration of the regular line.

[0004] For this reason, the transmission terminal equipment uses a frame format of a multiplexed signal (considering the case of an STM-1 frame) transmitted by the SDH transmission method and the STM-1 frame format.
-1 TUs multiplexed (mapped) in one frame
The line quality is confirmed based on TU format signals such as 3, TU-2, and TU-12. Specifically, the TU-multiplexed in the received STM-1 frame is
3, a PIP in a TU-2 or TU-12 signal, a BIP (Bit Interleaved PB) for path error monitoring.
arity) operation and various other POH termination processes to detect degradation of the line quality,
A control signal for line switching is generated in TU-2 and TU-12 format units.

[0005] Incidentally, the TU is included in the STM-1 frame.
-3, mapping is performed for a maximum of 21 channels for the TU2, and mapping for a maximum of 63 channels for the TU12. Therefore, the above POH termination processing is also performed independently by the number of channels corresponding to the signal size of the TU format signal. Need to be done (in parallel). For this reason,
Normally, in the transmission terminal equipment, H1, H1,
The head position of the VC-4 format is detected from the pointer value of the H2 byte, and the head position and the TU-3, TU-
2, TU-12 multiplex setting information (mapping setting information)
The TU format signal multiplexed on the VC-4 is separated on the basis of
OH termination processing is being performed.

Therefore, when all signals multiplexed in the STM-1 frame are TU-12, it is necessary to perform POH termination processing for TU-12 for 63 channels.
POH termination processing circuit (PO
H termination processing device).

[0007]

However, as described above, in the conventional SDH transmission technology, a TU format signal is separated from an STM-1 frame and POH termination processing for each TU format signal is performed in parallel. In addition, the transmission terminal station apparatus needs to provide a maximum of 63 POH termination processing apparatuses having the same configuration, and there is a problem that the apparatus scale and power consumption are greatly increased.

The present invention has been made in view of the above-mentioned problems, and performs a POH termination calculation process on a multiplexed signal transmitted by the SDH transmission system without separating it for each channel and keeping the serial. It is an object of the present invention to provide a POH termination processing device, a POH termination processing method, and a pointer / POH termination processing device in the SDH transmission system, which can greatly reduce the device scale and power consumption.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the POH termination processing apparatus shown in FIG. 1, a signal in which a plurality of channel information transmitted by the SDH transmission method is multiplexed is multiplexed. Is subjected to POH termination processing, and a common POH termination computation processing section 1 is stored for each channel on which the POH termination computation processing is performed on the multiplexed signal, and the calculation result of the POH termination computation processing section 1 is stored for each channel. It has a storage unit 2 that can be read and written freely.

The POH termination processing apparatus shown in FIG. 1 uses the POH termination information by using the storage information of the corresponding channel stored in the storage unit 2 when performing the POH termination calculation processing on the multiplexed signal. The POH termination operation processing is performed in the operation processing unit 1 and the obtained POH termination operation result is stored in the storage area of the corresponding channel in the storage unit 2, so that the multiplexed signal is not separated for each channel and the POH termination The terminal operation processing is performed.

Thus, in the above-described POH termination processing device, the multiplexed signal is not separated for each channel, and the
The OH termination arithmetic processing can be performed, so that it is not necessary to provide a circuit for the POH termination arithmetic processing for each channel in the multiplexed signal. The POH termination processing device described above uses the POH termination processing unit 1
At the time of the OH termination arithmetic processing, a latch unit is provided for temporarily storing storage information about the corresponding channel read from the storage unit 2 and POH byte data to be processed in the multiplexed signal. The storage unit 2 latches the storage information held in the storage unit 2 and the POH byte data to be processed in the multiplexed signal at the timing of detecting the POH. Since it is supplied to the terminal operation processing unit 1, P
The OH terminal operation processing unit 1 operates only when necessary (claim 2).

By the way, the above-mentioned POH terminal operation processing unit 1
May be configured as a J1 and J2 byte serial termination processing unit that serially terminates J1 and J2 bytes included in the multiplexed signal. In this case, the storage unit 2
The calculation results of the J1 and J2 byte serial termination processing units are stored for each channel, and storage information is supplied to the J1 and J2 byte serial termination processing units.

As a result, in the present POH termination device,
J1 byte (considering STM-1 frame as multiplexed signal, included in POH of VC (Virtual Container) -3), and has a lower-order group signal size different from that of the multiplexed signal including J1 byte. The J2 byte termination processing included in the POH of the multiplexed signal can be serially performed by the J1 and J2 byte serial termination processing units common to each channel.

For this reason, the above-mentioned J1, J2 byte serial termination processing unit is specifically configured to include the following units. A multi-frame pattern serial detector that serially detects multi-frame patterns of J1 byte and J2 byte. A multi-frame pattern number serial control unit that serially controls the number of multi-frames of J1 byte and J2 byte.

LOM (Loss) of J1 byte and J2 byte
LOM serial detector that detects the serial (of multiframe) serially.・ J1 byte and J2 byte CRC (Cyclic Redundanc)
A CRC serial detector that detects y Check) serially.・ J1 byte and J2 byte TIM (Trace Indicator)
TIM serial detection unit that detects Mismatch in serial.

In this case, the storage unit 2 stores each operation of the multi-frame pattern serial detection unit, the multi-frame pattern number serial control unit, the LOM serial detection unit, the CRC serial detection unit, and the TIM serial detection unit. The result is stored for each channel, and the stored information is supplied to the multi-frame pattern serial detection unit, the multi-frame pattern number serial control unit, the LOM serial detection unit, the CRC serial detection unit, and the TIM serial detection unit. You.

Thus, in the present POH termination processing apparatus,
Various types of alarm information such as LOM, CRC, and TIM can be serially obtained by a J1 and J2 byte serial termination processing unit common to each channel. Also, the POH termination arithmetic processing unit 1 shown in FIG. 1 performs BIP (B
it Interleaved Parity (BIP Performance Monitor) of B3 byte and V5 byte
May be configured as a B3, V5 byte serial termination processing unit that performs the termination processing of each in serial. In this case,
The storage unit 2 stores the operation result of the B3, V5 byte serial termination processing unit for each channel,
It is configured to supply stored information to a 3, V5 byte serial termination processing unit.

As a result, in the present POH termination processing apparatus,
BIP termination (operation) processing for B3 bytes (considered to be an STM-1 frame as a multiplexed signal and included in the POH of VC-3), and a signal size of a low-order group different from the multiplexed signal including the B3 bytes. Multiplex signal PO
BIP termination processing for the V5 byte included in H
This can be performed serially by the B3, V5 byte serial termination processing unit common to each channel.

For this reason, specifically, the B3, V5 byte serial termination processing section includes the following sections.・ BIP8 (Bit Interleaved Parit)
y-8) A BIP8 operation serial processing unit that performs the operation serially. -BIP2 (Bit Interleaved Parit) for multiplexed signals
y-2) A BIP2 operation serial processing unit that performs the operation serially.

A BIP error selection section for selecting a BIP error signal output from the BIP8 operation serial processing section and the BIP2 operation serial processing section. BI that serially performs an addition operation of BIPPM based on the BIP error signal selected by the BIP error selection unit
PPM serial adder. Then, in this case, the storage unit 2 stores the BIPP
It is configured to store each operation result in the M serial addition unit for each channel and to supply storage information to the BIPPM serial addition unit.

As a result, in the present POH termination processing apparatus,
Normally, a B3 error that should be detected by POH termination processing for each channel having a different signal size can be serially detected by a B3, V5 byte serial termination processing unit common to each channel. In addition,
The B3, V5 byte serial termination processing unit may include the following units.

A BIP8 arithmetic serial processing unit for serially performing a BIP8 arithmetic operation on a multiplexed signal; a first BIPPM serial adding unit for serially performing an addition arithmetic of the BIPPM based on a BIP error signal from the BIP8 arithmetic serial processing unit. A BIP2 arithmetic serial processing unit that serially performs BIP2 arithmetic on multiplexed signals;

· BI from the BIP2 operation serial processing unit
A second BIPPM serial addition unit that serially performs an addition operation of BIPPM based on the P error signal; In this case, the storage unit 2 stores the first BI
A first storage unit capable of storing the operation results of the PPM serial addition unit for each channel and supplying storage information to the first BIPPM serial addition unit;
The second BIPPM serial addition unit is configured to store each operation result in the PPM serial addition unit for each channel, and to supply a storage information to the second BIPPM serial addition unit.

That is, the B3, V5 byte serial termination processing unit performs the BIP error signal (BI) by the BIP8 serial termination processing and the BIP2 serial termination processing, respectively.
After independently obtaining PPM), each BIPPM is selectively output. Thereby, the BIPPM can be obtained serially with a simple configuration,
This is very effective when there is no particular need to share the storage unit 2 for holding M for all signal sizes (claim 7).

Further, the POH termination arithmetic processing unit 1 shown in FIG. 1 serially performs termination processing of C2 byte and V5 byte UNEQ (unequipped) included in the multiplexed signal.
The storage unit 2 may be configured as an EQ serial termination processing unit. In this case, the storage unit 2 stores the calculation result of the UNEQ serial termination processing unit for each channel, and
It is configured to supply stored information to the serial termination processing unit.

As a result, in the present POH termination processing apparatus,
UNEQ for C2 bytes (considered STM-1 frame as multiplexed signal, included in POH of VC-3)
Termination processing and UNEQ termination processing for V5 bytes included in the POH of a multiplexed signal having a signal size of a low-order group different from the multiplexed signal including the C2 byte are performed by a UNEQ serial termination processing unit common to each channel. It can be performed serially (as described above in claim 8).

For this reason, specifically, the above-mentioned UNEQ serial termination processing unit is configured to include the following units. A C2UNEQ display serial detection unit that serially detects whether the C2 byte is in the UNEQ display. A V5UNEQ display serial detection unit that serially detects whether the V5 byte is in the UNEQ display.

C2UNEQ display serial detector and V
UNEQ output from 5UNEQ display serial detector
UNEQ display selection section for selecting a display detection signal. A UNEQ serial detector that serially displays C2 bytes and V5 bytes of UNEQ display based on the UNEQ display detection signal selected by the UNEQ display selector. In this case, the storage unit 2 is configured to store each detection result of the UNEQ serial detection unit for each channel and to supply storage information to the UNEQ serial detection unit.

As a result, in the present POH termination processing apparatus,
Normally, the UNEQ display to be performed by the POH termination processing for each channel having a different signal size can be performed serially in the UNEQ serial termination processing unit common to each channel (claim 9). This UNE
The Q serial termination processing unit may be configured to include the following units.

A C2UNEQ display serial detector for serially detecting whether or not the C2 byte is in the UNEQ display.・ UNEQ from C2UNEQ display serial detection unit
A first UNEQ serial detector for serially displaying a C2 byte UNEQ display based on the display detection signal; A V5UNEQ display serial detection unit that serially detects whether the V5 byte is in the UNEQ display.

Based on the UNEQ display detection signal from the V5UNEQ display serial detector, a V5 byte UN
A second UNEQ serial detector that performs EQ display serially. A UNEQ display selection section for selecting the UNEQ display output from the first UNEQ serial detection section and the second UNEQ serial detection section; In this case, the storage unit 2 shown in FIG.
Each detection result of the Q serial detection unit is stored for each channel, and a first storage unit capable of supplying storage information to the first UNEQ serial detection unit, and each detection result of the second UNEQ serial detection unit is stored for each channel. And the second
A second storage unit capable of supplying storage information to the UNEQ serial detection unit is provided.

That is, the above-mentioned UNEQ serial termination processing unit performs the UNEQ display processing of C2 bytes and the UNE of V5 bytes.
After the NEQ display processing is performed independently and serially, each UNEQ display is selectively output. This makes it possible to serially display the UNEQ display with a simple configuration, which is very effective when there is no particular need to share the storage unit 2 for holding the UNEQ display for all signal sizes. (The above is the claim 1
0).

Further, the POH termination operation processing unit shown in FIG. 1 performs the processing of the S2 byte and the V5 byte included in the multiplexed signal.
It may be configured as an SLM serial termination processing unit that performs termination processing of LM (Signal Lavel Mismatch) in serial.
In this case, the storage unit 2 stores the operation result of the SLM serial termination processing unit for each channel,
It is configured to supply stored information to the M serial termination processing unit.

As a result, in the present POH termination processing apparatus,
The SLM termination processing for the C2 byte and the SLM termination processing for the V5 byte can be serially performed by the SLM serial termination processing unit common to each channel. Therefore, specifically, the above-described SLM
The serial termination processing unit includes the following units.

A C2 mismatch serial detection unit for serially detecting that the C2 byte has detected a mismatch. A V5 mismatch serial detector that serially detects that a V5 byte has mismatched. A mismatch detection selection section for selecting a mismatch detection signal output from the C2 mismatch serial detection section and the V5 mismatch serial detection section.

An SLM serial detection section for serially detecting C2 byte and V5 byte SLMs based on the mismatch detection signal selected by the mismatch detection selection section. In this case, the storage unit 2 stores each detection result of the SLM serial detection unit for each channel,
It is configured to supply stored information to the M serial detection unit.

Thus, in the present POH termination processing apparatus,
Normally, SLM detection to be performed by POH termination processing for each channel having a different signal size can be performed serially in an SLM serial termination processing unit common to each channel. The SLM serial termination processing unit may include the following units.

A C2 mismatch serial detector that serially detects that the C2 byte has detected a mismatch. A first SLM serial detector that serially detects a C2 byte SLM based on a mismatch detection signal from the C2 mismatch serial detector; A V5 mismatch serial detector that serially detects that a V5 byte has mismatched.

A second SLM serial detector for serially detecting a V5 byte SLM based on a mismatch detection signal from the V5 mismatch serial detector; SLM for selecting the SLM output from the first and second SLM serial detectors
Selection section. In this case, the storage unit 2 stores each detection result of the first SLM serial detection unit for each channel, and supplies a storage information to the first SLM serial detection unit, and a second SLM serial detection unit. Each detection result of the detection unit is stored for each channel, and a second storage unit capable of supplying storage information to the second SLM serial detection unit is provided.

That is, the above-described SLM serial termination processing unit performs a C2 byte SLM detection process, a V5 byte SLM
After performing the detection process independently and serially,
Each SLM is selectively output. Thus, SLM detection can be performed serially with a simple configuration, which is very effective when there is no particular need to share the storage unit 2 for holding the SLM for all signal sizes ( Thus, claim 13).

Further, the POH termination arithmetic processing unit shown in FIG. 1 performs the processing of the G1 byte and V5 byte F
EBE (Far End Block Error) termination processing and G
1-byte and 5-byte FEBEPM (FEBE Performanc
e Moniter) FEB which performs termination processing of each serially
In this case, the storage unit 2 stores the operation result of the FEBE serial termination processing unit for each channel, and also stores the result of the FEBE termination processing.
It is configured to supply stored information to the serial termination processing unit.

As a result, in the present POH termination processing apparatus,
FEBE for G1 byte (included in POH of VC-3, considering STM-1 frame as multiplexed signal)
And FEBEPM termination processing, and FEBE for the V5 byte included in the POH of the multiplex signal having a signal size of a lower-order group different from the multiplex signal including the G1 byte.
FEBEPM termination processing can be serially performed by a FEBE serial termination processing unit common to each channel.

For this reason, specifically, the above-mentioned FEBE serial termination processing section comprises the following sections. G1F that performs FEBE detection of G1 byte serially
EBE serial detector. V5F that performs FEBE detection of V5 byte serially
EBE serial detector.

An FEBE selector for selecting the FEBE detection signal output from the G1FEBE serial detector and the V1FEBE serial detector. A FEBEPM serial adder that serially performs FEBEPM addition based on the FEBE detection signal selected by the FEBE selector. In this case, the storage unit 2 is configured to store the addition result of the FEBPM serial addition unit for each channel and to supply storage information to the FEBPM serial addition unit.

Thus, in the present POH termination processing apparatus,
Normally, FEBE and FEBEPM termination processing to be performed by POH termination processing for each channel having a different signal size can be performed serially in a FEBE serial termination processing unit common to each channel. Note that the FEBE serial termination processing unit may be configured to include the following units.

A G1FEBE serial detection unit for serially detecting the FEBE of the G1 byte. A first FEBEPM serial adder that serially performs FEBEPM addition based on the FEBE detection signal from the G1FEBE serial detector; V5F that performs FEBE detection of V5 byte serially
EBE serial detector.

A second FEBEPM serial adder that serially performs an FEBEPM addition operation based on the FEBE detection signal from the V5FEBE serial detector. -The first FEBEPM serial adder and the second FE
A FEBEPM selection unit that selects the FEBEPM output from the BEPM serial addition unit. In this case, the storage unit 2 is configured to store the addition result of the FEBPM serial addition unit for each channel and to supply storage information to the FEBPM serial addition unit.

That is, the above-mentioned FEBE serial termination processing unit detects the FEBE for the G1 byte and
After the EPM addition operation, the FEBE detection for the V5 byte, and the FEBEPM addition operation are performed independently and serially, each FEBEPM is selectively output. As a result, F
EBE and FEBEPM can be detected serially, and this is very effective when there is no particular need to use a common storage unit 2 for holding FEBEPM for all signal sizes. 16).

Further, the POH termination arithmetic processing unit 1 shown in FIG. 1 is configured as a FERF serial termination processing unit that serially terminates G1 byte and V5 byte FERF (Far End Receive Failure) contained in the multiplexed signal. In this case, the storage unit 2 is configured to store the operation result of the FERF serial termination processing unit for each channel and to supply storage information to the FERF serial termination processing unit.

As a result, in the present POH termination processing apparatus,
The FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte can be performed serially by the FERF serial termination processing unit common to each channel. Therefore, specifically, the above-mentioned FERF serial termination processing unit is configured to include the following units.

A G1 FERF display serial detector that serially detects that the G1 byte indicates FERF. A V5FERF display serial detector that serially detects that the V5 byte indicates FERF. -G1FERF display serial detector and V5FE
A FERF display detection selection unit that selects a FERF display detection signal output from the RF display serial detection unit;

Based on the FERF display detection signal selected by the FERF display detection selector, the G1 byte and V
FERF serial detection unit that performs 5-byte FERF detection in serial. In this case, the storage unit 2 stores each detection result of the FERF serial detection unit for each channel,
It is configured to supply stored information to the ERF serial detector.

Thus, in the present POH termination processing apparatus,
Normally, FERF termination processing to be performed by POH termination processing for each channel having a different signal size can be performed serially in a FERF serial termination processing unit common to each channel. The FERF serial termination unit may include the following units.

A G1 FERF display serial detector that serially detects that the G1 byte indicates FERF. A first FERF serial detector that serially performs the FERF detection of the G1 byte based on the FERF display detection signal from the G1 FERF display serial detector;

A V5FERF display serial detection unit that serially detects that the V5 byte indicates FERF. A second FERF serial detector that serially detects the V5 byte FERF based on the FERF display detection signal from the V5 FERF display serial detector;

A FERF display selector for selecting the FERF display output from the first FERF serial detector and the second FERF serial detector. In this case, the storage unit 2 stores each detection result of the first FERF serial detection unit for each channel, and can supply storage information to the first FERF serial detection unit, and a second FERF serial detection unit. Each detection result in the detection unit is stored for each channel, and the second FER
A second storage unit capable of supplying storage information to the F serial detection unit is provided.

That is, the above-mentioned FEBE serial termination processing unit performs the FERF detection and display processing for the G1 byte and the FERF detection and display processing for the V5 byte independently and serially, and then performs each FERF.
Is selected and output. Thus, FERF can be displayed serially with a simple configuration, which is very effective when there is no particular need to share the storage unit 2 for holding FERF for all signal sizes. (The above is claim 19).

Further, the POH termination processing device shown in FIG. 1 performs processing in the POH termination arithmetic processing unit 1 based on a timing signal indicating the position of the J1 byte and the V5 byte of the multiplex signal and the type information of the multiplex signal. A POH timing signal serial generation unit for serially generating a POH timing signal for POH is provided, so that a POH timing signal required for the POH termination arithmetic processing unit 1 can be serially generated in common for each channel ( Claim 2
0).

Therefore, specifically, the above-described POH timing signal serial generation unit is configured to include the following units. Upon receiving a timing signal indicating the position of the J1 byte and the V5 byte of the multiplex signal, the SPE (Synchronous Payload Env.
elope) A count value initialization unit that initializes a count value.

A count value addition control unit for performing addition control of the SPE count value based on a signal from the count value initialization unit. A writable and readable storage unit capable of holding the SPE count addition value in the count value addition control unit for each channel and supplying the held data for each channel to the count value initialization unit.

A POH timing signal generation section for generating a POH timing signal for processing in the POH termination calculation processing section 1 based on the signal from the count value initialization section and the type information of the multiplexed signal. In the present POH termination device configured as described above,
In the OH timing signal serial generation unit, information on the start position (J1 byte, V5 byte) of the SPE in the multiplexed signal is stored in the storage unit for each channel.
By successively updating, a POH timing signal for processing in the POH termination arithmetic processing unit 1 can be serially generated by a POH timing signal serial generation unit common to each channel. 21) Further, the POH termination processing device shown in FIG. 1 is provided with an address creation unit for generating address information for identifying each channel of the multiplex signal, so that the storage unit 2
Information for each channel can be generated by an address generation unit common to each channel, so that it is not necessary to provide a circuit for generating address information for the storage unit 2 by the number of corresponding channels. There is no need to perform special processing for identifying each channel in the terminal operation processing unit 1 (claim 22).

The POH termination device shown in FIG.
The POH terminal operation processing unit 1 may be configured to include the following units. A J1 and J2 byte serial termination processing unit that serially terminates J1 and J2 bytes included in the multiplexed signal. .BI of B3 byte and V5 byte included in the multiplex signal
P termination processing and BIP of B3 byte and V5 byte
B3, V5 byte serial termination processing unit that performs termination processing of PMs in serial.

C2 byte and V5 included in the multiplex signal
A UNEQ / SLM serial termination processing unit that performs termination processing of byte UNEQ serially and performs termination processing of the C2 byte and V5 byte SLM in serial. .FE of G1 byte and V5 byte included in the multiplex signal
BE termination processing and F of G1 byte and V5 byte
A FEBE / FERF serial termination unit for serially performing the termination processing of the EBEPM and serially performing the termination processing of the FERF of the G1 byte and the V5 byte.

In this case, the storage unit 2 stores the above J
The calculation results in the 1, J2 byte serial termination processing unit, the B3, V5 byte serial termination processing unit, the UNEQ / SLM serial termination processing unit, and the FEBE / FERF serial termination processing unit are stored for each channel.
It is configured to supply storage information to a 1, J2 byte serial termination processing unit, a B3, V5 byte serial termination processing unit, a UNEQ / SLM serial termination processing unit, and a FEBE / FERF serial termination processing unit.

In the POH termination processor configured as described above, termination processing is performed on the J1 and J2 bytes for detecting a multi-frame pattern of a multiplex signal, and on the B3 and V5 bytes for obtaining a BIP (BIPPM) from the multiplex signal. C for obtaining termination processing, UNEQ, SLM
2, V5 byte termination processing, FEBE (FEBE
Termination processing on G1 and V5 bytes for obtaining PM) and termination processing on G1 and V5 bytes for obtaining FERF can be performed serially in common for each channel.

It should be noted that the pointer / POH termination processing device of the present invention performs pointer processing and P-processing on a signal in which a plurality of pieces of channel information transmitted by the SDH transmission method are multiplexed.
In the pointer / POH termination processing device that performs OH termination processing, a serial pointer processing unit that performs pointer processing without separating the multiplexed signal for each channel and serially, and that performs serial processing without separating the multiplexed signal for each channel. It is characterized by comprising a serial POH termination processing unit for performing POH termination processing.

Thus, in the above-described pointer / POH termination processing device, both pointer processing and POH termination processing for a multiplexed signal transmitted by the SDH transmission method are performed.
Each of them can be performed serially without separating the multiplexed signal for each channel.

[0068]

Embodiments of the present invention will be described below with reference to the drawings. (A) Outline of SDH transmission system As is well known, SDH is a standard and standardized standard for the purpose of unifying interfaces for effectively multiplexing high-speed services and existing low-speed services around the world. The data transmission speed (bit rate) to be
A data transmission rate (155 Mbps) with a basic rate (multiplexing unit) of 5 Mbps (accurately, 155.52 Mbps)
By unifying and multiplexing ps × n: n = 1, 4, 16, 64), various types of data including existing low-speed data (low-order group information) can be multiplexed. It can flexibly respond to new services in the future.

Specifically, in this SDH, virtual
A virtual “box” called a container (VC) is defined, some low-order group information is put into this “box” to form high-order group information, and some of these “boxes” are collected to form a larger “box”. By taking a method such as putting it in a box,
Various types of information having different transmission speeds are finally transmitted in one large "box".

For example, as shown in FIG. 2, the basic multiplexing unit of SDH is STM-1 (Synchronous Transfer Mode L).
evel 1) This is called a frame, and this STM-1 frame has one AU-4 added with a management pointer [AU (Administrative Unit) pointer] for indicating a VC-4 accommodation position and frequency synchronization described later. The VC-4 frame accommodates 138 Mbps sequence data called C (Container) -4 for one channel (channel) or TUG (Tributary Unit Group) -3 for three channels. It has become.

Further, this TUG-3 frame includes:
TU (Tributary Unit) -3 (34Mbps series) is 1c
h or 7 channels of TUG-2 (6Mbps series)
TUX-2 is multiplexed into one channel or TU-12 is multiplexed into three channels. The TU-3 adds a path overhead (POH: transfer destination information) to a 34 Mbps sequence frame called C-3 to form a VC-3.
This is a frame to which a TU pointer for frequency synchronization is added.

TU-2 is a frame in which POH is added to a C-2 (6 Mbps sequence) frame to form VC-2, and a TU pointer is added to this VC-2.
U-12 adds a POH to a C-12 (2 Mbps sequence) frame to form a VC-12, and this VC-12 has a T
This is a frame to which a U pointer is added. Therefore, STM
-1 in one frame of -1 signal, 3c at maximum
h and TU-2 are multiplexed for a maximum of 21 channels, and TU-12 are multiplexed for a maximum of 63 channels.

Here, the above STM-1, TU-
3, TU-2 and TU-12 frame formats will be described. Hereinafter, the above-mentioned TU-3, TU
−2, TU-12, etc. are simply TU3, TU2, TU
12 and so on. STM-1 Frame Format FIG. 3 is a diagram showing the frame format of the STM-1. As shown in FIG. 3, the STM-1 frame has 9 rows (rows) × 270 columns (column = BYTE). The first 9 rows × 9 columns are composed of a section overhead (SOH) 231 and an AU (AU4) pointer 232, and the next 9 rows × 261 columns are a payload (SPE) containing multiplexed information. : Synchronous Payload Envel
ope) 233.

Then, the section overhead 231
Consists of various operation and maintenance information such as A1 and A2 bytes indicating the frame synchronization pattern of the STM-1 frame and B1 bytes for monitoring a code error. The AU4 pointer 232 stores the VC (VC4: VC4: H1 byte (H1 # 1 to H1 # 3 byte) and H2 byte (H2 # 1) indicating the accommodation position (head address)
To H2 # 3 bytes), H3 bytes (H3 # 1 to H3 # 3)
Bytes).

However, usually, the H1 byte (H1
# 1 byte), the actual AU4 pointer value is stored in the H2 byte (H2 # 1 byte), and the H1 # 2 byte, H2 #
Fixed values are stored in the 2 bytes, H1 # 3 bytes, and H2 # 3 bytes as dependent pointers (CI: Concatination Indication). Then, for example, as shown in FIG. 3, the offset pointer value indicating the address of the first byte of VC4 starts at address 0 after the H3 # 3 byte and is H1 # 1.
Since it is specified that the byte before ends at address 782, if the AU4 pointer value is "0", STM-1 and VC
4, indicating that VC4 is sequentially accommodated immediately after the H3 byte (H3 # 3 byte).

On the other hand, if the AU4 pointer value is a value other than "0", the frame phases of STM-1 and VC4 do not match, and for example, as shown in FIG. This indicates that the VC 4 is accommodated so as to be located at an address shifted from address 0 by an amount corresponding to the phase shift. Normally, the offset pointer value of AU4 is defined as every 3 bytes, so if one pointer value changes, the frame phase of VC4 changes by 3 bytes.

The H3 byte (H3 # 1 to H3 # 3)
# 3 byte) and 3 bytes following this H3 byte (# 1 to # 3)
# 3 bytes) are frequency adjusting bytes called negative (negative) stuff bytes and positive (positive) stuff bytes, respectively. The transmission frame (STM-1)
When there is a small difference between the clock frequency of the multiplexed information (VC4) and the clock frequency of the multiplexed information (VC4), the frequency is adjusted by using these positive / negative stuff bytes (by performing stuff control). It is possible to prevent loss of transfer information by absorbing a clock frequency difference and a phase change of a transmission frame.

TU3 Frame Format Next, FIG. 5 is a diagram showing the above TU3 frame format. As shown in FIG.
Expressed as a two-dimensional byte array of 9 rows × 86 columns (BYTE), of the first 9 rows × 1 columns, the H1 byte and H2 byte are VCs in the payload 233 (VC3: see FIG. 6).
Is a TU (TU3) pointer for indicating the accommodation position and frequency synchronization, and the H3 byte and the subsequent 1 byte (offset pointer value “0”) (rightward on the paper) are used for frequency (frame phase) adjustment. Negative stuff byte and positive stuff byte. Note that the remaining 6 rows other than the H1 to H3 bytes in the first 9 rows × 1 column are used.
Row x 1 column is fixed stuff byte (Fixed Stuff)
It is.

As shown in FIG. 5, the offset pointer value indicating the address of the first byte of VC4 is H3
Since it is specified that the byte after the byte starts at address 0 and the byte before the H3 byte ends at address 764, if the TU3 pointer value is "0", the frame phases of TU3 and VC3 match, and VC3 is the H3 byte. Immediately after the address (address 0).

On the other hand, if the TU3 pointer value is a value other than "0", the frame phases of TU3 and VC3 do not match, and for example, as shown in FIG.
VC1 is sequentially accommodated so that (1 byte) is located at an address shifted from address 0 by an amount corresponding to the phase shift. In FIG. 6, the 9-row × 1-column portion including the J1 byte indicated by reference numeral 235 is called a VC3 path overhead (VC3-POH), and is a VC3 path assembly point (multiplexed) defined as a path. Process) and stored until the decomposition point (separation process) after the information is transmitted. By monitoring this VC3-POH 235, the state of the transmission information, such as a code error, is monitored end-to-end. I can do it.

For this reason, the VC3-POH 235 stores the B3 byte, the C2 byte, and the G1 byte in addition to the J1 byte.
It has a format including bytes, F2 bytes, H4 bytes, and Z3 to Z5 bytes. The function of each of the above bytes is shown below. (1) J1 byte: This is called a path trace signal. By repeatedly transmitting a fixed pattern signal, the receiving side checks whether the connection with the transmitting side is normally continued (path continuity check). Used to do (monitor)
Is done.

(2) B3 byte: Used for monitoring a path error, a calculation result by a calculation process called BIP (BiP) 8 described later is inserted as a B3 byte of the next frame. (3) C2 byte: A byte (signal label) for indicating the mapping structure of VC3, and as described later, VC2
3 is set with various information such as UNEQ display indicating that a payload is not accommodated.

(4) G1 byte: A byte used to indicate the status of a path, a function (FEBE) for returning the error monitoring result of the received path to the transmission side of the VC3, and a termination state of the path to the transmission side. Returned game alarm display function (FER
F). (5) F2 byte: For the user channel, this byte can be used freely by the network operator.

(6) Bytes Z3 to Z5: Bytes prepared internationally as spares. In the present embodiment,
The J1 byte, the B3 byte, the C2 byte, and the G1 byte are monitored (terminated) by the POH termination processing described later. TU2 Frame Format FIG. 7 is a diagram showing a TU2 frame format. As shown in FIG. 7, a TU2 frame has four rows ×
Expressed as a two-dimensional byte array of 108 columns (BYTE), of the first 4 rows × 1 column, V1 byte and V2 byte are VC2
(See FIG. 8) TU for accommodation position indication and frequency synchronization
The (TU2) pointer is a pointer, and the V3 byte and the subsequent one byte (rightward on the paper) are a negative stuff byte and a positive stuff byte for frequency (frame phase) adjustment, respectively. The V4 byte is a reserved byte internationally reserved for future use.
Currently not used.

As shown in FIG. 7, the offset pointer value indicating the address of the first byte of VC2 is V2
Since it is defined that the byte after the byte starts at the address 0 and the byte before the V2 byte ends at the address 427, if the TU2 pointer value is "0", the frame phases of the TU2 and VC2 also match in this case. It indicates that VC2 is sequentially accommodated immediately after the V2 byte (address 0).

On the other hand, if the TU2 pointer value is a value other than "0", the frame phases of TU2 and VC2 do not match, and for example, as shown in FIG.
5 bytes) is stored at an address shifted from address 0 by an amount corresponding to the phase shift. By the way, in FIG.
The portion of 4 rows x 1 column including 5 bytes is called a path overhead (VC2-POH) of VC2.
By monitoring the VC2-POH 236, it is possible to monitor the state of the transmission information such as a code error from end to end.

For this reason, the VC2-POH 236 includes J2 byte, Z6 byte, Z7 byte in addition to the above V5 byte.
It has a format that includes bytes. Since the function of each byte is the same as that of the VC2-POH 236, the path overhead of the VC 12 will be described together in the following description of the TU12 frame format.

TU12 Frame Format FIG. 9 is a diagram showing a frame format of the above-mentioned TU12. As shown in FIG.
It is represented by a two-dimensional byte array of row × 36 columns (BYTE). As in the TU2 frame format, V1 byte and V2 byte of the first 4 rows × 1 column are VC.
12 (see FIG. 10) are a TU (TU12) pointer for indicating the accommodation position and synchronizing the frequency, and the V3 byte and the subsequent 1 byte (rightward on the paper) are negative for frequency (frame phase) adjustment, respectively. They are stuff bytes and positive stuff bytes. This TU12
Is also a reserved byte internationally reserved for future use.

Then, as shown in FIG.
The offset pointer value indicating the address of the first byte of
After 2 bytes, it starts at address 0 and before V2 byte is 139
If the TU12 pointer value is "0", the frame phases of the TU12 and the VC12 match, and the VC12 is sequentially accommodated immediately after the V2 byte (address 0). To indicate that

On the other hand, if the TU12 pointer value is a value other than "0", the frame phases of the TU12 and the VC12 do not match, and for example, as shown in FIG. This indicates that the VC 12 is accommodated so as to be located at an address shifted from address 0 by a considerable amount. By the way, in FIG. 10, the portion of 4 rows × 1 column including the V5 byte indicated by reference numeral 237 is called a path overhead (VC12-POH) of VC12,
Like the VC2-POH 236, it has a format including a J2 byte, a Z6 byte, and a Z7 byte in addition to the V5 byte. The function of each of these bytes is described below.

(1) V5 byte: Path error monitoring of VC2 or VC12 by an operation process called BIP2 described later, FEBE for returning the presence or absence of the received BIP2 error to the transmitting side, and VC2 / VC12 mapping structure display by signal label , VC2 / VC12 are used for the game alarm indication (FERF) of the path. That is, this V5 byte is the VC3-POH23 described above.
5, the respective functions of the B3, C2, and G1 bytes are assigned to one byte (8 bits).

(2) J2 byte: VC3-PO described above
This byte is used as a path trace signal in the same manner as the J1 byte included in H235, and is used for confirming path continuity. (3) Z6, Z7 bytes: spare bytes. In the present embodiment, the V5 byte and the J2 byte among the above bytes are monitored (termination processing) by the POH termination processing described later.

(B) Overview of POH termination processing In the SDH transmission method, as described above, VC3 / VC2 /
By monitoring (termination processing) each of the POHs 235 to 237 of the VC 12, the state such as a code error of transmission information is monitored end-to-end. Here, the outline of the POH termination processing will be described.

(B1) Termination processing of J1 and J2 bytes As described above, J1 included in the VC3-POH 235
By monitoring the byte and the J2 byte included in the VC2 / VC12-POH 236, 237, the conduction of the path can be confirmed. For example, as shown in FIG. 11, a POH ("A") is added by the transmitting device "# 1", and the POH is set as a correct line setting by the transmitting device "# 2".
Considering that (“B”) is added, the receiving side device “# 3” monitors the J1 and J2 bytes by terminating the received POH (“A”, “B”).

Here, specifically, the J1 and J2 bytes (path trace signal) are VC3 / VC2 / VC12
The path signal is a signal obtained by adding a trace signal (name of path) composed of 15 ASCII characters to the path signal, and has, for example, a format as shown in FIG. Character (AS
CII data bits "X") can be transferred.

As a result, the receiving side device “# 3” checks whether the received value (name of the receiving path) matches the expected value of receiving (the name of the path to be received). It is possible to check whether the device is connected to the correct device, and if there is no match, a TIM indicating that fact
(Trace Indicator Mismatch) is detected and mismatch
An alarm occurs.

By the way, in the frame format of the path trace signal shown in FIG. 12, 16 frames (1
The MSB (most significant bit) for 6 bits is called a multi-frame indicator, and a path trace signal is detected by detecting the multi-frame indicator ("1000 0000 00000000"). This multi-frame indicator is out of frame synchronization (LOM: Loss
Of Multiframe) used for detection, under the following conditions,
Out-of-synchronization detection is performed for the front seven stages and the rear three stages.

Frame mismatch detection condition: When processing the 16th byte of the multiframe, 1
The 6-bit frame indicator pattern is "1000 00
If it is not 00 0000 0000 "Frame match detection condition: When processing the 16th byte of the multi-frame, the 16-bit frame indicator pattern in the received signal is" 1000 0000 0000 0000 "
In the case of FIG. 12, the MS of the frame number “0” is
Bits “C” except B are CRC (Cyclic Redundancy Ch).
eck) called -7 parity bit, used in the CRC-7 calculation by X ⁷ + X ³ +1 becomes generator polynomial.

For example, as shown in FIG.
The received data (path trace data) of the frame number “0” is set to 80 (HEX), and the CRC-7 operation is performed on the received data (bits 1 to 8) of the frame numbers “0” to “15”. A CRC error is detected by comparing the calculation result with the received CRC bit of the frame number “0” of the next multiframe. Here, the detection of the CRC error is performed in three forward steps and three backward steps.

(B2) Termination processing of B3 byte The B3 byte (see FIG. 14 for the format) included in the VC3-POH 235 is converted to BIP8 (Bit Interleaved Parit
y-8) By performing termination processing using an error parity method called an operation, an error (code error) in the path of the VC3 signal can be detected. However, in this case,
Even parity is applied as the error parity method.

More specifically, this BIP8 operation is a method of calculating a parity every eight bits of the counted data (byte unit) as shown in FIG. 15 (a), and counts the parity of the same digit in byte units. And Figure 1
As shown in FIG. 5B, the result is displayed in the same digit of BIP8. For example, on the receiving side, as shown in FIG. 16, data of one frame (85 bytes × 9 = 765 bytes) of one frame of the VC3 signal is subjected to all parity calculations in units of 1 byte (8 bits), and the calculation result and A parity error is detected for each bit from the MSB to the LSB (least significant bit) by comparing with the B3 byte extracted from the following next frame. When a parity error is detected during one frame, one alarm is generated.

(B3) Termination of C2 Byte By terminating (monitoring the signal label) the C2 byte (format shown in FIG. 17) included in the VC3-POH 235, the mapping structure of the VC3 signal can be recognized. , Signal label mismatch (mismatch: SLM) and UNEQ (indicating that the VC3 signal does not contain a payload).

Here, C2 byte (signal label)
For example, as shown in FIG. 18, a value (8-bit mapping code) set in accordance with the mapping structure of the VC3 signal is defined, and when the VC3 signal does not contain a payload, ALL which is UNEQ display is defined. “0” is set. On the receiving side, the C2 byte is monitored. For example, when the C2 byte indicated by UNEQ display (ALL “0”) is detected for four consecutive frames, UNEQ is displayed.
When a Q detection alarm is generated and the C2 byte other than the UNEQ display is detected for six consecutive frames, the UNEQ detection alarm is released.

At this time, the receiving side performs SLM detection by comparing the expected C2 byte value set by the maintenance person with the actual received value of the C2 byte. When a mismatch with the value is detected seven times in a row, an SLM detection alarm is generated. When a match is detected three times in a row, the SLM detection alarm is released.

(B4) Termination of G1 Byte By terminating the G1 byte included in the VC3-POH 235, the path state of the VC3 signal can be recognized. The G1 byte has a format as shown in FIG. 19, for example, and the upper 4 bits of the G1 byte (8 bits) are FEBE (Far End Block E).
rror) bit (see FIG. 19),
The next one bit is assigned as a FERF (Far End Receive Failure) bit (see FIG. 19). The remaining three bits (see FIG. 19) are currently unused.

Here, as described above, the FEBE bit is used to return the number of parity error bits of the received VC3 signal to the remote control apparatus (transmitting side) when a B3 (BIP8) parity error of the received VC3 signal is detected. As bits used, for example, as shown in FIG. 20, the number of detected errors in the B3 byte termination processing is set as the number of FEBE errors detected. As shown in FIG. 20, eight types of FEBE bits are defined at present out of the four bits (16 types).

The FERF bit is a bit used to notify the remote device that a failure has occurred in the receiving device that terminates the VC3 signal.
“1” indicates the notification state of “VC3 Far End Receive Failure”. Then, on the receiving side, this G1 byte is monitored,
The reception code of the upper 4 bits (FEBE bit) is “00”
If the value is other than "00", the number of errors in the game is detected and counted as one alarm. Also, if "1" of the FERF bit is detected, a FERF alarm is generated. An FERF alarm is generated when consecutive frames are detected, and R is detected when "0" of the FERF bit is detected for 10 consecutive frames.
Release the ERF alarm.

(B5) Termination Processing of V5 Byte The V5 byte included in the VC2-POH 236 or VC12-POH 237 has a format as shown in FIG. 21. Of the V5 byte (8 bits), A bit is a BIP2 bit (see FIG. 21), a subsequent bit is a FEBE bit (see FIG. 21), and a following 1
The bit is an RFI bit for notification of a V5 byte to the microcomputer (see FIG. 21), the following three bits are a signal label (see FIG. 21), and the least significant bit is a FERF bit (see FIG. 21). Each is assigned.

Therefore, by terminating the V5 byte on the receiving side, VC2 / VC1
Error in two signal paths (code error), mapping structure of VC2 / VC12 signal from signal label, FEBE
Bit and FERF bit, the state of the path of the VC2 / VC12 signal can be detected. Here, in the above BIP2 operation, even parity is applied in the same error parity system as the above-described BIP8 operation for the B3 byte. In this BIP2 operation, for example, as shown in FIG. The parity is calculated every other bit (in units of bytes). Therefore, the parity is counted for each of the odd and even bits in one byte, and the count result is displayed in the upper two bits of the V5 byte as shown in FIG.

As a result, on the receiving side, as shown by the shaded portion in FIG. 23, all the parity calculations are performed for every one bit in the range of the counted data for one multi-frame of the VC2 / VC12 signal. The result is compared with the V5 byte BIP 2 bits extracted from the next multiframe, and a parity error is detected with both the MSB and LSB bits. When a parity error is detected in one multiframe (maximum 2 bits), one alarm is generated.

Then, V5 of the received VC2 / VC12
(BIP2) When a parity error is detected, the number of parity error bits (V5
The number of detected errors in bytes) is set as FEBE and returned to the player device. As shown in FIG. 24, the FEBE bit of the V5 byte currently has two types of states that can be represented by one bit. Therefore, when the number of detected errors in the V5 byte is “2” or more, all “1” are set. ".

Next, for example, as shown in FIG. 25, the V5 byte signal label has a value [3 bits (bit numbers B5 to B7) mapping code set according to the mapping structure of the VC2 / VC12 signal. This signal label is also VC3-POH235
When the VC2 / VC12 signal does not contain a payload, the UNEQ display AL
L “0” is set.

On the receiving side, the signal label is monitored. For example, when a V5 byte with the signal label indicating UNEQ (ALL “0”) is detected for four consecutive frames, a UNEQ detection alarm is generated. ,
When a V5 byte with a signal label other than UNEQ display is detected for five consecutive frames, the UNEQ detection alarm is released.

At this time, on the receiving side, the expected value of the signal label set by the maintenance person is compared with the actual received value of the signal label, and if the mismatch of the signal label is detected seven times consecutively. Mismatch (SLM)
When a detection alarm is generated and the signal label coincidence is detected three times in succession, the SLM detection alarm is released.

Next, the above FERF bit is VC2 /
This bit is used to notify the remote device that a failure has occurred in the receiving device that terminates the VC12 signal. The bit is “0” in the normal state, and “1” is “VC2 / VC12 Far End Re”.
ceive Failure "notification status.
The FERF bit of the V5 byte is monitored, and the FERF
When the bit “1” is detected, a FERF alarm is set. In this case, when the FERF bit “1” is detected for 10 consecutive frames, a RERF alarm is generated.
When "0" of the FERF bit is detected for 10 consecutive frames, the RERF alarm is released.

(B6) Performance Monitor (PM) Function The performance monitor function is a function used for monitoring the line quality and maintaining the line of the transmission line in service. In this embodiment, as described later, a microcomputer is used. A period of a PM reset pulse from a microcomputer (hereinafter referred to as a microcomputer) is defined as a period, and a parity error (BIP8, BIP8,
IP2), the number of detected FEBE errors is counted, and the count result is notified to the microcomputer.

FIGS. 26 (a) to 26 (f) show an example of the performance monitoring operation of the BIP error, respectively. FIGS. 27 (a) to 27 (g) show the F
9 shows an example of an EBE error performance monitor operation. (C) Description of POH termination processing device (C1) Description of overall configuration of POH termination processing device FIG. 28 is a block diagram showing an example of an SDH transmission network. In FIG. 28, 301 is a subscriber terminal, and 302 is a line termination device. (NT), 303 and 306 are transmission terminal devices (LT), 304 is a switching device (SW), 305 is a multiplexer (MUX), and 307 is a relay transmission line.

In the SDH transmission network shown in FIG. 28, data from a plurality of subscriber terminals 301 are transmitted by an multiplexer 305 to STM-n frames (where n = 1, 4,
16, 64), and the transmission terminal device 306 terminates / replaces the overhead (SOH, POH).
Processing such as termination / replacement of the AU / TU pointer is performed, and the data is transmitted to the opposite subscriber terminal 301 through the relay transmission line 307.

FIG. 29 shows a PO as an embodiment of the present invention.
FIG. 29 is a block diagram illustrating a configuration of a main part of a transmission terminal device 306 to which the H-termination device is applied. As illustrated in FIG.
The transmission terminal unit 306 includes an SOH termination processing unit 4, an AU pointer processing unit 5, a TU pointer processing unit 6, an elastic memory (ES) unit 7, a POH termination processing unit (POH termination processing device) 8, and a path switch alarm insertion. An active system 3A and a standby system 3B each having a unit 9 are provided.

The transmission terminal device 3 shown in FIG.
In step 06, when various alarms defined by the SDH transmission method are detected in the POH termination processing unit 8, each alarm information of TIM, UNEQ, and SLM among the various alarm detection information is transmitted to the path switch alarm insertion unit 9. At the same time, the BIPPM is notified to the microcomputer (μ-COM) 10. In response to this notification, the microcomputer 10 performs an alarm process by software, and then sends the BPM to the path switch alarm insertion unit 9. Set the path switch alarm insertion. That is, TIM, SL
TU that detected each alarm of M, UNEQ, BIPPM
The signal of the channel is set to ALL “1”.

Thus, the cross connect device (XC)
At 11, an abnormality is detected, and switching from the active system 3A to the standby system 3B is performed. FIG. 30 is a block diagram showing the configuration of the transmission terminal apparatus 306 focusing on the TU pointer processing section 6 and the POH termination processing section 8. As shown in FIG. 30, the TU pointer processing section 6 includes a TU pointer serial Processing unit 61 and TU pointer timing generation unit 62
And, as described later, this T
The J1 / V5 byte timing signal generated by the U pointer processing unit 61, the SPE enable signal, and the TU address signal (T
UAD), a mapping signal, and the like are used for processing in the POH termination processing unit 8, respectively.

Therefore, as shown in FIG. 31, the TU pointer serial processing section (serial pointer processing section) 61
Are the pointer extraction unit 61-1 and the pointer processing unit 61-
2, RAM (random access memory) controller 61-
3. The TU pointer timing generator 62 is configured to include the RAM 61-4, and the TU pointer timing generator 62 is configured to include the address generator 62-1.

Here, in the TU pointer timing generator 62, an address generator (address generator)
62-1 is a TU multiplexed in an STM-1 frame (VC4 signal) based on a frame signal generated based on detection of a frame synchronization pattern (A1, A2 bytes) included in the SOH of the STM-1 frame. An address (channel address) to be assigned to each level channel (multiplexed data) is generated. In this embodiment, this TU channel address is used as POH as address information (TUAD) for identifying the TU channel of the VC4 signal. It is used for processing in the termination processing unit 8.

In the TU pointer serial processing section 61, the pointer extracting section 61-1 serially extracts pointer bytes (including at least H1 / V1 bytes and H2 / V2 bytes) of each channel from the multiplexed data. The pointer processing unit 61-2 serially performs the analysis of the pointer of each channel, the detection of the state, the replacement of the pointer, and the like based on the multiplexed data from the pointer extraction unit 61-1.

Further, the RAM control section 61-3 serially outputs the result of the pointer processing section 61-2 of each channel to R
It generates a control signal for controlling a series of operations for writing / reading to / from the AM 61-4.
M61-4 holds the output data of the pointer processing unit 61-2 in the area indicated by the channel address from the address generation unit 62-1 for each channel.

In FIG. 31, reference numeral 100 'denotes a mapping setting register group, 101' denotes a selector unit, and mapping setting register group 100 'stores multiplexed data (ST
M-1 frame) is TU3 / TU2 / T
The selector unit 101 'sets an address assigned to each channel by the address generation unit 62-1 from the mapping setting register group 100'. A signal size is selected, and mapping information is output serially (multiplexed). The mapping setting register group 100 'and the selector 10
The detailed configuration of 1 'will be described later with reference to FIG.

In the TU pointer processing unit 6 configured as described above, the pointer extraction unit 61-1 and the pointer processing unit 6
1-2, the information group generated through the address generation unit 6
The RAM control unit 61 stores the address of the RAM 61-4 indicated by the RAM address (channel address) generated in 2-1.
The data is written in accordance with the write enable signal (detection timing of the reception pointer byte) generated in step -3.

Then, in the pointer processing section 61-2, R
The information group of the previous frame is read from the AM 61-4 in accordance with the read enable signal generated by the RAM control unit 61-3, and pointer processing is performed serially using the read information group of each channel. FIG. 32 is a block diagram showing a detailed configuration of the above-described address generation unit 62-1. As shown in FIG.
UG3 address counter 15, TUG2 address counter 16, TU12 address counter 17, AND
Circuit (logical AND circuit) 18, 1-input inversion type AND circuit 1
9 and an address conversion unit 20.

Here, the TUG3 address counter (3
The octal counter 15 counts the number (the number of channels) of TUG3 (multiplexed by a maximum of three) multiplexed in the STM-1 frame (VC4 frame), and the TUG2 address counter (7 Hex counter)
16 is TUG2 multiplexed in the TUG3 frame
(Up to seven channels are multiplexed), and the TU12 address counter (3
The octal counter 17 counts the number of channels of the TUs 12 (multiplexed up to three) multiplexed in the TUG2 frame. Each of the address counters 15 to 17 loads an initial value by a frame signal.

In the present embodiment, as shown in FIG. 32, the carry-out (C
O) is connected to the carry-in (CI) of the address counter 16 and the carry-out of the address counter 16 is connected to the carry-in of the address counter 17, thereby forming a 63-base counter. The output of 15-17 is RAM61
4 is used as a RAM address (channel address).

The AND circuit (logical product circuit) 18
When the TU12 mode is not set by the TU12 setting signal described later (when the TU12 setting signal is at the L level), the output of the address counter 17 is converted to "0", and the one-input inversion type AND circuit 19 Converts the output of the address counter to "0" only when the TU3 mode is set by a TU3 setting signal described later (when the TU3 setting signal is at the H level).

The address conversion unit 20 includes the counters 15 to 15
A desired addition process is performed on the address output from the address generator 17 to generate an address conversion signal that does not generate an empty address in the RAM 14. Thereby, in the address generation unit 62-1, a combination of the counters 15 to 17 operated according to the TU12 mode setting signal and the TU3 mode setting signal (only the counter 15, only the counter 15 and the counter 16, and all the counters 15 to 17)
Is changed, and the address for the RAM 14 is changed, for example, as shown in FIG.
The TU is generated by the combination as shown in
RAM for channel address for 3 / TU2 / TU12
61-4.

Therefore, frames (VC4 / VC3 / VC2 / VC1) of different signal sizes are included in the STM-1 frame.
Regardless of the combination of 2), one address generation unit 61-4 can flexibly cope with it. In FIG. 33, addresses 00 to 02 _HEX are TUs.
3 / TU2 / TU12 shared address, address 0
3 to 14 _HEX are TU2 / TU12 shared addresses.

Further, the channel address generated as described above is subjected to an address conversion in the address conversion unit 20 to obtain an address output in which all empty addresses are compressed (see the address space in FIG. 34). , The address line to the RAM 61-4 is changed from 7 bits to 6
Converted to bits. This output is used as a TU channel address (TUAD) for the POH termination processing unit 8 described above.

That is, the POH termination processing unit 8 of this embodiment
The TU required for the POH byte serial termination processing according to VC3 / VC2 / VC12 is commonly used by using the TU address signal serially generated in the address generation unit 62-1 of the TU pointer processing unit 6. This eliminates the need to generate address signals individually.

Therefore, it is not necessary to provide a circuit for generating a TU address signal by the number of corresponding channels, and it is not necessary to perform a special process for identifying each TU channel. This will contribute to power reduction. Next, FIG.
FIG. 25 is a block diagram showing a configuration of a pointer processing unit 61-2 focusing on an E first byte (J1 / V5 byte) recognition function part. The pointer processing unit 61-2 shown in FIG.
M89 'and an SPE first byte recognition unit 97A.

Here, the SPE first byte recognition section 97A
Recognizes the J1 byte (the first byte of the VC3 signal) or the V5 byte (the first byte of the VC2 / VC12 signal) as the first byte of the SPE. As shown in FIG. Part 98 '
And an AND circuit 99 '. Then, the offset counter unit 97 'is triggered by the frame signal to
The coincidence detecting section 98 'reads the active pointer value from the RAM 89' by reading the active pointer value from the RAM 89 'as a read enable signal by counting the offset pointer value of the SPE described above with reference to FIG. The coincidence between the active pointer value and the offset counter value of the offset counter unit 97 'is detected, and the AND circuit 99'
A logical product of the SPE enable signal and the result of the match detection by the match detector 98 'is used to generate and output an SPE first byte position (J1 / V5 byte) instruction signal.

That is, the SPE first byte recognition unit 97
A has an offset counter unit 97A for searching for the first byte of the SPE, reads the active pointer value from the RAM 89 ', and calculates the logical product of the SPE enable signal and the coincidence detection result of the offset counter value and the active pointer value. , SPE are recognized.

The pointer processing unit 6 configured as described above
In 1-2, the RAM 8 according to the SPE enable signal
The held active pointer value is read from 9 ', and the offset counter unit 97' starts counting the offset pointer value of the SPE triggered by the frame signal. Then, the coincidence detection unit 89 'detects whether or not the active pointer value read from the RAM 89' coincides with the counter value of the offset counter unit 97 '.

Further, the result of the coincidence detection is ANDed with the SPE enable signal in the AND circuit 99 ', and the result of the AND is generated and output as a J1 / V5 byte instruction signal. Here, when the J1 / V5 byte instruction signal is "1" (H level), it indicates that the data of the time slot of the multiplexed data is J1 / V5 bytes. The J1 / V5 byte instruction signal and the SPE enable signal are used for the processing in the TU pointer processing unit 6 described above.

Next, FIG. 36 is a block diagram showing the configuration of the TU pointer processing unit 6 focusing on the signal size recognition function part. The TU pointer processing unit 6 shown in FIG.
Assuming that one frame of data is processed,
The above-described mapping setting register group 100 ′ has three (3
TU3 / TUG3 setting register (for TU3 / T)
UG3 # 1 to # 3) 123 and seven TU2 / TUG2 setting registers (TU2 / TUG2 # 1 to TU3 / TUG2 setting register 123), seven for each TU3 / TUG3 setting register 123
# 7) The selector unit 1 is configured to include
01 'is provided with a signal size recognition unit 125A.

Here, TU3 / TUG3 setting register 1
23 stores information indicating whether the TUG3 accommodated (mapped) in the VC4 frame is set to TU3 or TUG3. For example, when the value of the setting register 123 is “1”, TU3 is multiplexed in the TUG3 frame, and "0" indicates that TU2 or TU12 is multiplexed in the TUG3 frame.

The TU2 / TUG2 setting register 12
4 stores information indicating whether TUG2 mapped to TUG3 is set to TU2 or TUG2. For example, when the value of this setting register is "1", TU2 is included in the TUG2 frame. Are multiplexed, and "0" indicates that TU12 is multiplexed in the TUG2 frame.

Further, the signal size recognizing section 125A recognizes the signal size of the corresponding channel based on the set values stored in the setting registers 123 and 124, and the TU3 / TU2 / TU12 for the address generating section 10 is used. In this case, as shown in FIG. 36, selector circuits 125 to 127, a one-input inversion type AND circuit 128, and an all-input inversion type AND circuit 129 are provided.
The function is realized by using a TUG3 address counter 15 and a TUG2 address counter 16 similar to those shown in FIG.

Here, the selector circuit 125 sets the TU3 / TUG3 corresponding to the channel indicated by the counter value of the TUG3 address counter 15 of the address generator 62-1.
The selector circuit 126 selects the information of the setting register 123.
TU / TU corresponding to the channel indicated by the counter value of
G2 setting register 124 is selected.
The selector circuit 127 is an address counter 1 for TUG3.
TU2 / T corresponding to the channel indicated by the counter value of 5
This is for selecting the information of the UG2 setting register 124.

In the TU pointer processing unit 6 configured as described above, the set value (data “# 1 to # 3”) of the TU3 / TUG3 setting register 123 is changed by the selector circuit 125 according to the counter value of the TUG3 address counter 15. The selected TU3 setting signal is generated. Here, this TU setting signal indicates that the channel is TU3 only when it is "1".

The TU2 / TUG setting register 124 is set according to the counter value of the TUG2 address counter 16.
(For TUG3 # 1, TUG3 # 2, TUG3 # 3)
The data "# 1 to # 7" are selected from the seven registers by the three selector circuits 126, and the three selection signals are selected by the selector circuit 127 in accordance with the counter value of the TUG3 address counter 15.

The logical product of the inverted signal of the TU3 setting signal and the output signal of the selector circuit 127 is obtained by the AND circuit 1
At 28, a TU2 setting signal is generated. Here, this TU2 setting signal indicates that the channel is TU2 only when it is "1". Further, the AND circuit 129 calculates the logical product of the inverted signal of the TU3 setting signal and the inverted signal of the output signal of the selector circuit 127, thereby generating the TU12 setting signal. Note that this TU
Here, the 12 setting signal indicates that the channel is TU12 only when it is "1". Each of the above TU setting signals is used as a mapping setting signal for processing in a POH termination processing unit 8 described later.

Next, FIG. 37 is a block diagram showing the configuration of the POH termination processing unit 8 of the present embodiment. As shown in FIG. 37, the above-described POH termination processing unit (serial POH termination processing unit) 8 Timing generation section 21, J1 / J2 byte termination processing section 22, B3 / V5 byte termination processing section 23, C
It has a 2 / V5 byte termination processing unit 24 and a G1 / V5 byte termination processing unit 25.

Here, the timing generation section (POH timing signal serial generation section) 21 includes a J1V5TP signal (J1 / V5 byte instruction signal) indicating the head position of the TU data, and an SP indicating the position of the payload data of the TU data.
E enable signal (SPEN), TU signal size (T
U3 / TU2 / TU12), a mapping signal for performing identification, and VC4 data in which TU data is multiplexed,
Each of them is received from the TU pointer processing unit 6, and the TU PO
It generates various timing signals necessary for the termination processing of H and performs phase adjustment.

That is, the timing generation section 21 determines whether the J1 byte or the V5 byte included in the multiplex signal (VC4 signal)
Based on a timing signal indicating a byte position and type information (mapping signal) of the multiplex signal, a POH timing signal for processing in each of the termination processing units 22 to 25 is serially generated. The timing generator 21 can serially generate the POH timing signals required for the respective termination processors 22 to 25 in common for each TU channel.

The J1 / J2 byte termination processing section 22
Performs serial termination processing (detection of LOM, CRC, TIM (TiM)) of the J1 byte and J2 byte included in the multiplexed signal, and the B3 / V5 byte termination processing unit 23 The B3 byte and V5 byte BIP termination processing and the B3 byte and V5 byte BIPPM termination processing are serially performed, respectively.

Further, the C2 / V5 byte termination processing unit (U
The NEQ / SLM serial terminator 24 serially terminates the C2 byte and V5 byte UNEQ contained in the multiplexed signal,
The G1 / V 5-byte termination processing unit (FEBE / FERF) performs serial termination of the 5-byte SLM termination.
The serial termination processing unit) 25 is configured to control the G included in the multiplexed signal.
The 1-byte and V5-byte FEBE termination processing and the G1 and V5-byte FEBEPM termination processing are performed serially, respectively, and the G1 byte and V5
A 5-byte FERF termination process is performed serially.

For this reason, each of the above termination processing units 22 to 25
Are basically configured to include a POH terminal operation processing unit 26 and a storage unit 27, as shown in FIG.
Here, the POH termination calculation processing unit 26 determines that TU3 / TU2
A multiplexed signal in which each channel of / TU12 is serially multiplexed (VC4 signal: for TU3, a maximum of three channels, TU3
2 for a maximum of 21 channels, TU12 for a maximum of 63
POH termination processing is performed for each channel (multiplexed for channels). In the present embodiment, the above-mentioned channels are common to each channel.

The storage unit 27 stores the operation result of the POH termination operation processing unit 26 for each channel. The storage unit 27 stores the read TU channel address signal and write TU channel address signal supplied from the TU pointer processing unit 6 described above. TU channel address signal, write enable signal (WE
In accordance with N), reading and writing of the operation result are freely controlled.

The terminal processing unit 22 shown in FIG.
25 to 25, when performing the POH termination calculation processing on the VC4 signal, the POH termination calculation processing unit 26 performs the POH termination calculation processing using the storage information about the corresponding channel stored in the storage unit 27. , The resulting POH
By storing the termination calculation result in the storage area of the corresponding channel of the storage unit 27, the VC4 signal is converted to VC3 / VC
The POH termination arithmetic processing can be performed in serial without separating each channel of the 2 / VC12 signal.

FIG. 39 shows the above-mentioned POH terminal operation processing section 26.
FIG. 39 is a block diagram showing a configuration of the storage unit 27.
As shown in (1), the POH termination operation processing unit 26 includes a serial processing unit 26-1 and a flip-flop (FF) circuit 26-2 with an enable terminal.
RAM data holding unit 27-1 configured using AM and F
The FF data holding unit 27-2 is configured using an F circuit.

Here, in the POH termination calculation processing section 26, the serial processing section 26-1 performs termination processing on the POH byte serially. For example, J1 / J2
The byte termination unit 22 terminates the J1 and J2 bytes, and the B3 / V5 byte termination unit 23 computes the B3 and V2 bytes.
In the C2 / V5 byte termination processing unit 24, termination processing for C2 and V5 bytes, G1 / V5
The V5 byte termination processing unit 25 performs termination processing on G1 and V5 bytes, respectively.

The FF circuit (latch section) 26-2 is
At the time of the POH byte end operation processing in the serial processing unit 26-1, the data (operation result) for the corresponding channel read from the storage unit 27 and the POH byte data to be processed in the VC4 data are temporarily stored. This is to be stored (held). And this FF circuit 26-
2 causes the data held in the storage unit 2 and the POH byte data to be processed in the VC4 data to be latched at the POH timing, so that necessary data is supplied to the serial processing unit 26-1 according to the POH timing. , The serial processing unit 26-1 operates only when necessary. In other words, the FF circuit 26-2 lowers the operating frequency of the serial processing unit 26-1 to reduce its power consumption.

Further, in the storage unit 27, the RAM data holding unit 27-1 has a TU channel (0 to 62ch).
40A to 40T, for example, as shown in FIGS. 40A to 40T.
At the RAM read address, data of the corresponding TU channel for performing serial processing is read, and at the RAM write address and RAM write enable, information on the number of alarm protection stages of the serially processed TU channel is written. I have. In this embodiment, the power consumption is suppressed by lowering the operating frequency by inputting the RAM clock only when reading and writing of the RAM data holding unit 27-1 are performed.

The FF data holding unit 27-2 has a TU
The FF circuit holds the alarm bits of the channels (0 to 62 ch), and FIG. 40 (a) to FIG. 40 (t)
As shown in the figure, the TU channel alarm bit for performing serial processing is read at the FF read address and the FF read timing, and the TU channel alarm bit for serial processing is read at the FF write address and FF write enable. It is written.

Hereinafter, the above-described timing generator 21, J1
/ J2 byte termination processing unit 22, B3 / V5 byte termination processing unit 23, C2 / V5 byte termination processing unit 24, G1 / V
The details of the 5-byte termination processing unit 25 will be described item by item. (C2) Description of Timing Generation Unit 21 FIG. 41 is a block diagram showing the configuration of the above-described timing generation unit 21. The timing generation unit 21 shown in FIG.
An SPE count holding unit (RAM) 28, an SPE count value initialization unit 29, an SPE count value addition control unit 30, a timing signal generation processing unit 31, and an FF circuit 32 are provided.

Here, the SPE count value holding unit 28
This is a write / read-only storage unit that holds the SPE count addition value in the SPE count value addition control unit 30 for each TU channel, and can supply the held data for each TU channel to the SPE count value initialization unit 29. , SPE
The count value initialization unit 29 calculates VC3 / VC2 in VC4.
Upon receiving the J1V5 timing signal indicating the start position of the / VC12 signal (the position of the J1 byte / V5 byte), the SPE
This is to initialize the count value.

The SPE count value addition control unit 30
Performs the addition control of the SPE count value based on the signal from the SPE count value initialization unit 29, and the timing signal generation processing unit 31
, A mapping signal (a signal indicating the type of the VC signal having the same phase), an SPE enable signal (SPEN),
Upon receiving the TU address signal (TUAD), based on the signal from the count value initialization unit 29 and the mapping signal, the following various POH timings for processing in each of the termination processing units 22 to 25 (see FIG. 37): A signal is generated.

J1 timing signal (J1TP): J1
Signal indicating byte position. B3 timing signal (B3TP): a signal indicating the position of the B3 byte. C2 timing signal (C2TP): a signal indicating the position of the C2 byte. G1 timing signal (G1TP): a signal indicating the position of the G1 byte. V5 timing signal (V5TP): A signal indicating the position of the V5 byte.

J1J2 timing signal (J1J2T)
P): A signal indicating the position of the J1 and J2 bytes. C2V5 timing signal (C2V5TP): C2, V
Signal indicating the position of 5 bytes. G1V5 timing signal (G1V5TP): G1, V
Signal indicating the position of 5 bytes.

J1J2 write enable signal (J1J
2WEN): A signal indicating the write timing of data after the J1 and J2 byte end processing. J1J2 RAMCLK signal: RAM operation clock in the J1 / J2 byte end processing unit 22. BIPWEN signal: a signal for instructing the write timing of the BIP2, BIP8 operation result.

BIPPMWEN signal: a signal for instructing the data write timing after the BIPPM addition processing. BIPPMRAMCLK signal: BIPPM holding RAM 58 in the B3 / V5 byte termination processing unit 23 described later
1 operating clock. C2V5WEN signal: a signal for instructing the timing of writing data after UNEQ and SLM termination processing.

C2V5 RAMCLK signal: C described later
2 / V5 Operating clock of the RAM in the 5-byte termination processing unit 24. G1V5WEN signal: A signal for instructing the timing of writing data after FERF termination processing. G1V5 RAMCLK signal: an operation clock of the RAM in the G1 / V5 byte termination processing unit 25 described later.

Read TU address signal (RTUA)
D): A signal instructing to read the termination processing result one cycle before the TU channel for which the POH termination processing is performed. • TU address signal for writing (WTUAD): POH
A signal instructing writing of data after processing of the TU channel on which termination processing has been performed. SPE enable signal (SPEN): S input
A signal obtained by delaying the phase of the PE enable signal.

SPE count value write TU address signal (CNTTUAD): a signal for specifying an address to write the SPE count value of the TU channel after the SPE count value addition control. • SPE count value write enable signal (CNTWE)
N): A signal for instructing writing of a signal after SPE count value addition control.

FEBEPMRAMCLK: G to be described later
Operation clock of the FEBEPM holding RAM 93-1 in the 1 / V5 byte end processing unit 25. The FF circuit 32 delays the phase of the SPE count value before processing (one cycle before) from the SPE count holding unit 28 by one clock to adjust the input timing to the SPE count value initialization unit 29. is there.

In the timing generator 21 configured as described above, the information (SPE count value) relating to the start position (J1 byte, V5 byte) of the SPE in the multiplexed signal
42A through 42 through the SPE count value initialization unit 29 and the SPE count value addition control unit 30, for example.
By successively updating while holding (reading / writing) in the SPE count holding unit 28 for each TU channel at the operation timing shown in (q), the processing in each of the termination processing units 22 to 25 is performed. POH timing signals are serially generated by a timing signal generation processing unit 31 common to each channel. Therefore, the above serial processing can be realized with a very simple configuration.

For this reason, specifically, as shown in FIG. 43, the timing generation section 21 includes an overhead counter (OHCTR) RAM holding section 28 'and a phase shift section 3
2 ', an overhead counter serial processing section 33, and a POH timing signal generation section 34, a POH timing signal shift section 35, a LOM holding RAM operation control section 3 as the timing signal generation processing section 31.
6, RAM operation control unit 37 for holding frame number (FRNO), RAM operation control unit 38 for holding BIP2, RAM operation control unit 39 for holding signal label (SL), FE
RF holding RAM operation control unit 40, expected reception value (EXP
1,2) Holding RAM operation control unit 41, BIPPM holding RAM operation control unit 42, and FEBEPM holding RAM
It is configured with an operation control unit 43.

The overhead counter serial processing section 33 corresponds to the section including the SPE count value initialization section 29, the SPE count value addition control section 30, and the FF circuit 32 in FIG.
The AM holding unit 28 'holds the count value from the overhead counter serial processing unit 33 in the RAM.
This corresponds to the SPE count holding unit 28 in FIG.

FIG. 44 is a block diagram showing the detailed structure of the above-mentioned phase shift unit 32 '. As shown in FIG. 44, the phase shift unit 32' transmits each signal [TUDT] inputted from the TU pointer processing unit 6. (TU data), TU address signal, SPE enable signal, J1V5 timing signal,
In order to delay the phase of the mapping signal (VC3TUG / VC2VC12)] by a required amount, each of the above input signals is provided with a predetermined number of FF circuits 32 for delaying the phase (C1 to C8) of the input signal by one clock of the master clock. It is configured.

The phase shift unit 3 configured as described above
2 ', the TU data of the VC4 signal, the TU address signal indicating the TU channel, the SPE enable signal indicating the position of the payload data of the TU data, the J1V5 timing signal indicating the head position of the TU data, TU3 / TU2 /
The phase of the mapping signal for identifying the TU 12 is shifted by a required amount in the FF circuit 32 having the corresponding number of stages, and is used for serial processing in the overhead counter serial processing unit 33 and POH serial termination processing. .

More specifically, at this time, the phase shift section 32 'shifts the phase of the TU data by seven clocks by the seven-stage FF circuit 32 (C1 → C7), and thereby the TU address signal (TUDTC7) of the phase C7. ), And
By shifting the phase of the TU address signal by 1 to 8 clocks by the 8-stage FF circuit 32, the TU address signals (TUADC1 to 8) of the phases C1 to C8 are shifted.
Generate

Further, S is controlled by a seven-stage FF circuit 32.
By shifting the phase of the PE enable signal by 7 clocks, the SPE enable signal (SPEE
NC7) and the SPE enable signal (SPEENC3) of the phase C3 is generated by shifting the SPE enable signal by three clocks by the FF circuits 32 up to the third stage of the seven-stage FF circuit 32. I do.

Also, the J1V5 timing signal and the mapping signal (VC
By shifting the phase of each of the 3TUG · VC2VC12) by 3 clocks, the J1V5 timing signal (J1V5TPC3) of the phase C3 and the mapping signal (VC
3TUGC3.VC2VC12C3). FIG. 45 is a block diagram showing a detailed configuration of the overhead counter RAM holding unit 28 'and the overhead counter serial processing unit 33. As shown in FIG. 45, the overhead counter RAM holding unit 28' The overhead counter serial processing unit 33 includes a RAM 28'-1 and an inverting element 28'-2 for inverting the polarity of an input signal.
0 byte control unit (1 input inversion type AND circuit) 33-2,
TU3 detector (1 input inversion type AND circuit) 33-3, T
U2 detector (1 input inversion type AND circuit) 33-4, TU
12 detection section (all input inversion type AND circuit) 33-5, maximum value setting section 33-6, maximum value detection section 33-9, count value addition section 33-12, count value initialization control section (1 input inversion type circuit) AND circuit) 33-13.

Here, in the overhead counter RAM holding section 28 ', the overhead counter RAM 28'
-1 holds information on the byte number of the SPE data with the J1 and V5 bytes as the 0th byte.
T of the phase C1 supplied from the above-described phase shift unit 32 '
The U address signal (TUADC1) is a read address, the TU address signal (TUADC2) of phase C2 is a write address, and the SPE enable signal (SPEN) of phase C3.
The signal obtained by inverting C3) by the inverting element 28'-2 is operated as a write enable and the master clock is used as a RAM clock.

In the overhead counter serial processing section 33, the FF circuit 33-1 temporarily holds the information (count value) read from the overhead counter RAM 28'-1. Reference numeral 33-2 controls the count value to be 0 when a J1V5 timing signal (J1V5TPC3) indicating the head position of the TU data is input. POH termination processing is performed based on the controlled signal (OHCTRC3). Various POH timings are generated.

Further, the TU3 detecting section 33-3 detects that the TU channel to be processed is TU3, and performs an AND circuit (logical AND circuit) for obtaining the logical product of the VC3TUGC3 and the inverted VC2VC12C3. ), The function is realized, and the TU2 detector 33-4 detects that the TU channel to be processed is TU2, and calculates the logical product of the inverted VC3TUGC3 and the VC2VC12C3. AN
The function is realized using a D circuit.

Further, the TU12 detecting section 33-5 detects that the TU channel to be processed is TU12, and outputs a signal obtained by inverting the above VC3TUGC3,
AN that takes the logical product of the inverted version of C2VC12C3
The function is realized using a D circuit. The maximum value setting unit 33-6 selects the maximum value of the count value according to the setting of TU3 / TU2 / TU12. Here, the TU3 detection unit 33-3 and the TU2 detection unit 3 are used.
3-4, the maximum value [TU3: 2FC (he
x), TU2: 1AB (hex), TU12: 08B
(Hex)] is selectively output through an AND circuit 33-7 and an OR circuit (logical sum circuit) 33-8.

Further, the maximum value detection unit 33-9 determines whether the count value after control by the 0 byte control unit 33-2 matches the maximum value set (selected and output) by the maximum value setting unit 33-6. Here, the function is realized using an EXOR circuit (exclusive OR circuit) 33-10 and an OR circuit 33-11. When the maximum value is detected by the maximum value detection unit 33-9, it indicates that the SPE data is the last byte.
The SPE data of the U channel is J1 and V5 bytes which are the head of the TU data.

The count value adding section 33-12 outputs 0
The count value after control by the byte control unit 33-2 is incremented by +1.
And a count value initialization control unit 33-13.
When the maximum value is detected by the maximum value detection unit 33-9 as described above, since the next SPE data to be processed is J1 and V5 bytes at the head of the TU data, the overhead counter RAM 28'-1 Is controlled so that the count value to be held at 0 is 0 indicating J1 and V5 bytes.

With such a configuration, in the overhead counter serial processing section 33, the overhead (SPE) count value (OHCT) required when the timing signal generation processing section 31 generates various POH timing signals.
RC3) can be generated serially. Next, FIG. 46 is a block diagram showing a detailed configuration of the POH timing signal generation section 34 shown in FIG.
The timing signal generator 34 is configured to include the following units.

Decode circuit (DEC) 34-1: SP
It detects (decodes) 0 of the E count value (OHCTRC3). Decode circuit (DEC) 34-2: Detects (decodes) 85 of the SPE count value (OHCTRC3). Decode circuit (DEC) 34-3: Detects (decodes) 170 of the SPE count value (OHCTRC3).

Decode circuit (DEC) 34-4: SP
It detects (decodes) 255 of the E count value (OHCTRC3). Decode circuit (DEC) 34-5: Detects (decodes) 107 of the SPE count value (OHCTRC3). Decode circuit (DEC) 34-6: Detects (decodes) 35 of the SPE count value (OHCTRC3).

TU3 detector (1-input inversion type AND circuit) 34-7: Detects that the TU channel to be processed is TU3. TU2 detector (1-input inversion type AND circuit) 34-8:
It is to detect that the TU channel to be processed is TU2. -TU12 detector (all input inversion type AND circuit) 34-
9: Detects that the TU channel to be processed is TU12.

.J1 condition detector (AND circuit) 34-1
0: Detects that the TU channel to be processed is the 0th byte of TU3. B3 condition detection unit (AND circuit) 34-11: This detects that the TU channel to be processed is the 85th byte of TU3. C2 condition detector (AND circuit) 34-12: detects that the TU channel to be processed is the 170th byte of TU3.

G1 condition detector (AND circuit) 34-1
3: Detects that the TU channel to be processed is the 255th byte of TU3. .V5 condition detection unit (1 input inversion type AND circuit) 34-1
4: Detects that the TU channel to be processed is the 0th byte of TU2 / TU12. TU2J2 condition detector (AND circuit) 34-15: detects that the TU channel to be processed is the 107th byte of TU2.

TU12J2 condition detector (AND circuit)
34-16: Detecting that the TU channel to be processed is the 35th byte of TU12. • J2 condition detection unit (OR circuit) 34-17: TU described above
The 2J2 condition detector 34-15 and the TU12 J2 condition detector 34-16 detect that the J2 condition of TU2 / TU12 has been detected.

J1 timing signal generator (AND circuit) 34-18: By taking the logical product of the output signal of the J1 condition detector 34-10 and the SPE enable signal, a signal indicating the position of the J1 byte is obtained. To generate. -B3 timing signal generation unit (AND circuit) 34-1
9: SP3 output signal from B3 condition detector 34-11 and SP
By taking a logical product with the E enable signal, a signal indicating the position of the B3 byte is generated.

C2 timing signal generating section (AND circuit) 34-20: By taking the logical product of the output signal of the above C2 condition detecting section 34-12 and the SPE enable signal, a signal indicating the position of the C2 byte is obtained. To generate. G1 timing signal generation unit (AND circuit) 34-2
1: SP1 and the output signal of the above G1 condition detecting unit 34-13
A signal indicating the position of the G1 byte is generated by taking a logical product with the E enable signal.

V5 timing signal generating section (AND circuit) 34-22: By taking the logical product of the output signal of V5 condition detecting section 34-14 and the SPE enable signal, a signal indicating the position of the V5 byte is obtained. To generate. -J2 timing signal generator (AND circuit) 34-2
3: The output signal of the J2 condition detecting unit 34-17 and SP
By taking a logical product with the E enable signal, a signal indicating the position of the J2 byte is generated.

J1 J2 timing signal generator (OR circuit) 34-24: Generates a signal indicating the position of the J1 J2 byte. -B3V5 timing signal generation unit (OR circuit) 34-2
5: Generates a signal indicating the position of the B3 · V5 byte. -C2V5 timing signal generation unit (OR circuit) 34-2
6: A signal indicating the position of the C2V5 byte is generated.

G1V5 timing signal generator (OR circuit) 34-27: Generates a signal indicating the position of G1V5 byte. The timing signal generators 34-18 to 34-18 described above
-23 takes the logical product of the input signal and the SPE enable signal because the detection units 34-10 to 34-1 correspond to the timing when the TU is not the SPE data.
This is to prevent the detection condition of each byte from being satisfied (a timing signal is generated at an erroneous timing) in 7 so that various timing signals can always be generated at an accurate timing.

As a result, the POH timing signal generator 34 described above generates various POH timing signals (J1, B3, C2, G1, G1) necessary for termination processing in the termination processors 22 to 25 (see FIG. 37) described later. V5, J2 and other signals indicating the position of each byte) can be generated serially. Next, FIG. 47 is a block diagram showing a detailed configuration of the POH timing signal shift unit 35 in FIG. 43. As shown in FIG.
5 includes FF circuits 35-1 to 35-8 for delaying the phase of the input signal by one master clock, and various POH timing signals generated by the above-described POH timing signal generation unit 34. Are shifted to phases suitable for the POH termination processing in the termination processing units 22 to 25, respectively.

For example, the J1 timing signal (J1TPC
3) The phase C is obtained by a 5-stage FF circuit 35-1.
3 is delayed by 5 clocks, so that J1TPC8
The B3 timing signal (B3TPC3) becomes B3TPC8 by delaying its phase C3 by 5 clocks by the five-stage FF circuit 35-2, and C2
The timing signal (C2TPC3) becomes C2TPC8 when the phase C3 thereof is delayed by five clocks by the five-stage FF circuit 35-3.

The V5 timing signal (V5TPC)
3), J12 timing signal (J12TPC3), B3
The V5 timing signal (B3V5TPC3), the C2V5 timing signal (C2V5TPC3), and the G1V5 timing signal (G1V5TPC3) correspond to the corresponding F, respectively.
By the F circuits 35-4 to 35-8, the phase C3 is 2 to
By being delayed by 5 clocks, V5TPC5-C
8, J12TPC3-C8, B3V5TPC3-C8,
C2V5TPC3 to C8 and G1V5TPC3 to C8.

Next, FIG. 48 is a block diagram showing the detailed configuration of the LOM holding RAM operation control unit 36 in FIG. 43. As shown in FIG. , An operation clock mask generation unit (OR circuit) 36-1, an FF circuit 36-2, a clock mask unit (1 input inversion type OR circuit) 36-3, and an inversion element 36-4.

Here, the operation clock mask generator 36-
1 is a J12 timing signal (J12) generated by being phase-shifted by the POH timing signal shift unit 35 described above.
TPC5 to C8), the LOM holding RA in the J1 / J2 byte termination processing unit 22 to be described later from J12TPC5.
M50-1 (see FIG. 61) Read address capture clock mask, LOM holding R from J12TPC6
Clock mask for taking in the write address of AM50-1 and RAM 50-1 for holding LOM from J12TPC7
A write clock mask for writing data to the memory is generated.

The FF circuit 36-2 delays the output (clock mask) of the operation clock mask generator 36-1 by one master clock.
The clock mask unit 36-3 masks the master clock using the clock mask from the FF circuit 36-2, and generates clock edges (LOMCK) for reading and writing of the LOM holding RAM 50-1. The inverting element 36-4 is a J12TP
The polarity of C8 is inverted to generate a write enable signal (XLOWEN) of the negative polarity of the LOM holding RAM 50-1.

As a result, the above-described LOM holding RAM operation control unit 36 generates the clock edge (LOMCK) and the write enable signal (XLOMW) generated as described above.
EN), the LOM holding RAM 50-1 can be operated at an optimum timing. Next, FIG. 49 is a block diagram showing a detailed configuration of the FRNO holding RAM operation control unit 37 of FIG. 43. As shown in FIG.
Similarly, the operation clock mask generation unit (OR circuit) 37-1,
FF circuit 37-2, clock mask section (1 input inversion type O
R circuit) 37-3 and an inverting element 37-4.

Here, the operation clock mask generator 37-
1 is the POH timing signal (J12TPC3) generated by the POH timing signal generation unit 34 and the POH
Among the J12 timing signals (J12TPC5 to C8) generated by being phase-shifted by the timing signal shift unit 35, the FRNO holding RAM 51-1 (FIG. 6) in the J1 / J2 byte termination processing unit 22 to be described later from the J12TPC3.
2)) Read address capture clock mask, J12TPC6 to FRNO holding RAM 51-1
Clock mask of the write address of J12
The TPC 7 generates a write clock mask for writing data to the FRNO holding RAM 51-1.

The FF circuit 37-2 delays the output (clock mask) of the operation clock mask generator 37-1 by one master clock.
The clock mask unit 37-3 masks the master clock using the clock mask from the FF circuit 37-2, and generates clock edges (FRNOC) for reading and writing of the FRNO holding RAM 51-1.
K), and the inverting element 37-4 is connected to J1.
Reversing the polarity of 2TPC 8 and holding FRNO holding RAM 51
-1 negative write enable signal (XFRNOWE
N).

As a result, the above-mentioned FRNO holding RAM
The operation control unit 37 controls the clock edge (FRNOCK) generated as described above and the write enable signal (XFR).
NOWEN) and the FRNO holding RAM 51-1.
Is operated at the optimal timing. Next, FIG.
50 is a block diagram showing a detailed configuration of the BIP2 holding RAM operation control unit 38 in FIG. 50. As shown in FIG. 50, the BIP2 holding RAM operation control unit 38 of this embodiment is also the above-described FRNO holding RAM operation control unit. As in the case of 37, an operation clock mask generation unit (OR circuit) 38-1, an FF circuit 38-2, a clock mask unit (1-input inversion type OR circuit) 38-3, and an inversion element 38-4 are provided. I have.

Here, the operation clock mask generator 38-
1 is an SPE enable signal (SPE) generated by being phase-shifted by the above-described POH timing signal shift unit 35.
ENC5 to C8), the BIP2 holding R in the B3 / V5 byte termination processing unit 23 to be described later from SPEENC5.
The clock for capturing the read address of the AM 54-1 (see FIG. 85), the clock mask for capturing the write address of the RAM 54-1 for holding the BIP2 from SPEENC6, and the RAM 5 for storing the BIP2 from SPEENC7.
4-1 to generate a write clock mask for write data.

The FF circuit 38-2 delays the output (clock mask) of the operation clock mask generator 38-1 by one master clock.
The clock mask unit 38-3 masks the master clock using the clock mask from the FF circuit 38-2, and generates clock edges (BIPCK) for reading and writing of the BIP2 holding RAM 54-1.
, And the inverting element 38-4 has the SPEE
Reversing the polarity of NC8, BIP2 holding RAM 54-1
Negative write enable signal (XBIPWENC)
8).

Thus, the RAM for holding BIP2 described above can be used.
The operation control unit 38 controls the clock edge (BIPC
K), the BIP2 holding RAM 54-1 can be operated at an optimal timing by using the write enable signal (XBIPWENC8). Next, FIG.
51 is a block diagram showing a detailed configuration of the SL holding RAM operation control unit 39 in FIG. 51. As shown in FIG. 51, the SL holding RAM operation control unit 39 of the present embodiment also has the BIP
2, the operation clock mask generator (OR circuit) 39-1 and the FF circuit 39-
2. Clock mask section (1-input inversion type OR circuit)
3 and an inversion element 39-4.

Here, the operation clock mask generator 39-
1 is a C2V5 timing signal (C2
V5TPC5 to C8), a clock mask for fetching a read address from the C2V5TPC5 to the SL holding RAM 72-1 (see FIG. 104) in the C2 / V5 byte termination processing unit 24 described later, and writing from the C2V5TPC6 to the SL holding RAM 72-1. Address capture clock mask, C2V5 TPC7 to SL holding RAM7
A write clock mask for writing data to 2-1 is generated.

The FF circuit 39-2 delays the output (clock mask) of the operation clock mask generator 39-1 by one master clock.
The clock mask unit 39-3 masks the master clock using the clock mask from the FF circuit 39-2, and generates clock edges (SLCK) for reading and writing of the SL holding RAM 72-1. The inverting element 39-4 is a C2V5TPC
8 to generate a negative polarity write enable signal (XSLWENC8) for the SL holding RAM 72-1.

Thus, the above-mentioned SL holding RAM operation control unit 39 uses the above-mentioned clock edge (SLCK) and write enable signal (XSLWENC8) to generate
The L holding RAM 72-1 can be operated at an optimal timing. Next, FIG. 52 shows the FER in FIG.
FIG. 52 is a block diagram showing a detailed configuration of an F-hold RAM operation control unit 40. As shown in FIG.
The F holding RAM operation control unit 40 also has the SL holding R
Similarly to the AM operation control unit 39, an operation clock mask generation unit (OR circuit) 40-1, an FF circuit 40-2, a clock mask unit (1-input inversion type OR circuit) 40-3, and an inversion element 40-4 are provided. It is configured.

Here, the operation clock mask generator 40-
1 is a G1V5 timing signal (G1
V5TPC5 to C8), G1V5TPC5 to G1V5TPC6 to F1 capture clock mask for the read address of the read address of FERF holding RAM 96-1 (see FIG. 116) in G1 / V5 byte termination processing unit 25 described later.
A fetch clock mask for the write address of the ERF holding RAM 96-1 and a write clock mask for the write data of the write data from the G1V5TPC 7 to the FERF holding RAM 96-1 are generated.

The FF circuit 40-2 delays the output (clock mask) of the operation clock mask generator 40-1 by one master clock.
The clock mask unit 40-3 masks the master clock using the clock mask from the FF circuit 40-2, and generates clock edges (FERFC) for reading and writing to the FERF holding RAM 96-1.
K), and the inverting element 40-4 has G1
Invert the polarity of V5TPC8 and store RAM 9 for FERF
6-1 negative write enable signal (XFERFW
ENC8).

As a result, the above-mentioned FERF holding RAM
The operation control unit 40 receives the clock edge (FERFC)
K), write enable signal (XFERFWENC8)
Is generated, and the FERF holding RAM 96-1 can be operated at an optimum timing. Next, FIG. 53 is a block diagram showing the detailed configuration of the expected reception value holding RAM operation control unit 41 in FIG. 43. As shown in FIG.
1 is a reception expectation value read request detection unit (OR circuit) 41
-1, EXP1 expected value read operation clock mask generator (1 input inversion type AND circuit) 41-2, EXP2 expected value read operation clock mask generator (AND circuit) 4
1-3, EXP1 expected value setting access operation clock mask generator (1-input inversion type AND circuit) 41-4, EXP
2 Expected value setting access operation clock mask generator (AN
D circuit) 41-5, EXP1 clock mask generator (O
R circuit) 41-6, EXP2 clock mask generator (O
R circuit) 41-7, FF circuits 41-8, 41-9, EX
P1 clock mask section (1 input inversion type OR circuit) 41-
10, EXP2 clock mask section (1 input inversion type OR circuit) 41-11, EXP1 write enable generation section (1
An input inversion type NAND circuit) 41-12 and an EXP2 write enable generation unit (NAND circuit) 41-13 are provided.

Here, the expected reception value read request detecting section 4
1-1 detects the timing of reading the expected values of the path trace data of J1 and J2 bytes and the expected values of the signal labels of C2 and V5 bytes.
1 expected value read operation clock mask generator 41-2
If the most significant bit of the read expected value read address of REXPADC 5 (see FIG. 70) described below is “0”, the EXP1 hold RAM 48-1 (see FIG. 70) reads the expected receive value from the EXP1 hold RAM 48-1. RAM48
This is to generate a clock mask for taking in a -1 read address.

The EXP2 expected value read operation clock mask generator 41-3 reads the expected reception value from the EP2 holding RAM 48-2 if the most significant bit of the read address of the expected reception value of the REXPADC 5 is "1". Therefore, the EXP1 expected value setting access operation clock mask generator 41-4 receives the read address of the EXP2 holding RAM 48-2, and receives the EXP1 from the software (the microcomputer 10: see FIG. 29). When the expected value is set or the setting content is read, if the most significant bit of MEXPAD of the read / write address on the software side is “0”,
The clock mask of the EXP1 holding RAM 48-1 is generated so that the reading / writing to the EXP1 holding RAM 48-1 is performed.

Further, the EXP2 expected value setting access operation clock mask generation section 41-5 sets the most significant bit of the MEXPAD to "1" when setting the expected reception value or reading the setting contents from the software side. Then
The clock mask of the EXP2 holding RAM 48-2 is generated so that the reading / writing to the EXP2 holding RAM 48-2 is performed.

The EXP1 clock mask generator 41
-6 is a logical sum of each of the clock mask signals generated by the EXP1 expected value reading operation clock mask generation unit 41-2 and the EXP1 expected value setting access operation clock mask generation unit 41-4, and EXP2 The clock mask generator 41-7 calculates the logical sum of the clock mask signals generated by the EXP2 expected value reading operation clock mask generator 41-3 and the EXP2 expected value setting access operation clock mask generator 41-5. Things.

Further, the FF circuit 41-8 has the EX
The output (EXP1 clock mask) of the P1 clock mask generation unit 41-6 is delayed by one master clock, and the FF circuit 41-9 outputs the output of the EXP2 clock mask generation unit 41-7 (EXP2 clock mask). ) Is delayed by one master clock.

The EXP1 clock mask section 41-1
0 indicates that the master clock is masked using the output (EXP1 clock mask) of the FF circuit 41-8.
The data (EX) held in the XP1 holding RAM 48-1
A clock edge (EXP1CK) required for reading / writing of P1) is generated. The EXP2 clock mask unit 41-11 uses the output (EXP2 clock mask) of the FF circuit 41-9 to mask the master clock. To generate a clock edge (EXP2CK) necessary for reading / writing data (EXP2) held in the EXP2 holding RAM 48-2.

Further, when writing the expected reception value from the software side, if the most significant bit of the MEXPAD is “0”, the EXP1 write enable generation unit 41-12 writes the expected value to the EXP1 holding RAM 48-1. EXP1 holding RAM so that data can be written
The write enable (XEXP1WEN) 48-1 is generated, and the EXP2 write enable generation unit 41-13 sets the most significant bit of the MEXPAD to "1" when writing the expected reception value from the software side. ", The EXP2 holding RAM 48-2 is written so that data is written to the EXP2 holding RAM 48-2.
A write enable (XEXP2WEN) 48-2 is generated.

Thus, the above-mentioned RA for holding the expected reception value is
The M operation control unit 41 outputs the clock edges (EXP
1CK, EXP2CK), write enable (XEXP
1WEN, XEXP2WEN) to generate EX
RAM 48-1 for holding P1, RAM 48 for holding EXP2
-2 can be operated at optimal timing.

FIG. 54 is a block diagram showing a detailed configuration of the BIPPM holding RAM operation control unit 42 in FIG. 43. As shown in FIG.
The holding RAM operation control unit 42 performs, for example, the processing shown in FIG.
Similarly to the L holding RAM operation control unit 39, the operation clock mask generation unit (OR circuit) 42-1 and the FF circuit 42-
2. Clock mask section (1-input inversion type OR circuit) 42-
3 and an inverting element 42-4.

Here, the operation clock mask generator 42-
1 is a B3V5 timing signal (B3V5T
PC5 to PC8), the clock mask for the read address of the B3V5TPC5 to the read address of the BIPPM holding RAM 58-1 (see FIG. 87) in the B3 / V5 byte termination processing unit 23 described later, and the B3V5TPC6 to BIPP
A clock mask for writing the write address of the RAM 58-1 for holding M, a write clock mask for writing data from the B3V5TPC 7 to the RAM 58-1 for holding BIPPM are generated, and the BIPPM is counted from the BIPPM software notification request signal from the software side. This is to generate a clock mask for capturing a value read address.

The FF circuit 42-2 delays the output (clock mask) of the operation clock mask generator 42-1 by one master clock.
The clock mask unit 42-3 masks the master clock using the clock mask from the FF circuit 42-2, and generates clock edges (BIPPM) for reading and writing of the BIPPM holding RAM 58-1.
CK), and the inverting element 42-4 outputs B
Invert the polarity of 3V5TPC8 to BIPPM holding RA
M58-1 negative polarity write enable signal (XBIP
PMWEN).

As a result, the above-described RA for holding the BIPPM
The M operation control unit 42 generates the clock edge (BIPMCK) and the write enable signal (X
BIPPM holding RAM using BIPPMWEN)
58-1 can be operated at optimal timing. Next, FIG. 55 is a block diagram showing a detailed configuration of the FEBEPM holding RAM operation control unit 43 in FIG.
As shown in FIG. 55, similarly to the above-described BIPPM holding RAM operation control unit 42, the FEBEPM holding RAM operation control unit 43 of this embodiment also includes an operation clock mask generation unit (OR circuit) 43-1 and FF. The circuit 43-2 includes a circuit 43-2, a clock mask section (1 input inversion type OR circuit) 43-3, and an inversion element 43-4.

Here, the operation clock mask generator 43-
1 is a G1V5 timing signal (G1V5T) generated by being phase-shifted by the POH timing signal shift unit 35.
PC5 to PC8), the clock mask for the read address of the G1V5TPC5 to the FEBEPM holding RAM 93-1 (see FIG. 114) in the G1 / V5 byte termination processing unit 25 described later, and the G1V5TPC6 to the FE
BEPM holding RAM 93-1 capture address capture clock mask, G1V5TPC7 to FEBE
A write clock mask for writing data to the PM holding RAM 93-1 is generated, and the FEBEPM software notification request signal from the software side issues an FE
This is to generate a clock mask for taking in the read address of the BEPM count value.

The FF circuit 43-2 delays the output (clock mask) of the operation clock mask generator 43-1 by one master clock.
The clock mask unit 43-3 masks the master clock using the clock mask from the FF circuit 43-2, and generates clock edges (FEBE) for reading and writing to the FEBEPM holding RAM 93-1.
PMCK) and the inverting element 43-4.
Inverts the polarity of G1V5TPC8 and outputs a negative write enable signal (X
FEBEPMWEN).

As a result, the above-mentioned R for FEBPM holding is performed.
The AM operation control unit 43 can operate the FEBEPM holding RAM 93-1 at an optimal timing by using the clock edge (FEBEPMCK) and the write enable signal (XFEBEMWEN) generated as described above. Hereinafter, the overall operation of the timing generation unit 21 will be briefly described. First, the phase shift unit 32 '
TU data (here, J1 byte of VC3), TUAD, SPEN, J1V5TP, VC3T at timings as shown in FIGS. 56 (a) to 56 (h), for example.
Assuming that UG and VC2VC12 are respectively input, the overhead counter serial processing unit 33 operates at the timings as shown in FIGS. 57 (a) to 57 (p).

Then, in the timing signal generation processing unit 31, the POH timing signal generation unit, for example,
Each part operates at the timings shown in FIG. 58A to FIG. 58T to generate various POH timing signals serially, and the LOM holding RAM operation control unit 36 operates as shown in FIG.
9 (a) to 9 (f), each section operates at a timing as shown in FIG.
K), and generates a write enable signal (XLOMWEN). Note that the circled numbers (FIGS. 45- and 45-) in each of FIGS. 57 to 59 correspond to the signals indicated by the circled numbers in the corresponding drawings.

As described above, according to the POH termination processing unit 8 of the present embodiment, the timing generation unit 21 uses the various POH termination processing required by the termination processing units 22 to 25 for the POH termination processing.
Since the OH timing signal can be serially generated in common for each TU channel, it is not necessary to provide a circuit for generating the POH timing signal by the number of the corresponding TU channels, thereby reducing the circuit scale and power consumption. It can be significantly reduced.

(C3) J1 / J2 byte end processing unit 22
FIG. 60 shows the J1 / J2 byte end processing unit 22 shown in FIG.
60 is a block diagram showing the detailed configuration of the J1 / J2 byte termination processing unit 2 of the present embodiment, as shown in FIG.
2 indicates that the POH termination operation processing unit 26 shown in FIG.
J1 and J2 byte serial termination processing unit 26 that serially terminates J1 and J2 bytes included in the signal
38, the storage unit 27 shown in FIG. 38 stores the operation result of the J1, J2 byte serial termination processing unit 26A for each TU channel, and
It is configured as a storage unit 27A that can supply storage information to the 1, J2 byte serial termination processing unit 26A.

The J1 and J2 byte serial termination processing unit 26A includes a multi-frame pattern serial detection unit 44 and a multi-frame number serial control unit 4
5, a LOM serial detector 46, a CRC serial detector 47, a reception expected value holder 48, and a TIM serial detector 49. The storage 27A includes a LOM holder 50, a frame number (FRNO) holder 51. , And an alarm bit holding unit 52.

Here, in the J1 and J2 byte serial termination processing section 26A, the multi-frame pattern serial detection section 44 detects the multi-frame pattern of J1 and J2 bytes in serial, and the multi-frame number serial control section The (multi-frame pattern number serial control unit) 45 serially controls the number of multi-frames of J1 and J2 bytes, and the LOM serial detection unit 46 serially detects LOM of J1 and J2 bytes. Things.

The CRC serial detecting section 47
The detection of the CRC of 1, J2 bytes is performed serially. The expected reception value holding unit 48 holds the expected reception value of the path trace signal written / read from the software side by the maintenance person. The serial detection unit 49 detects the TIM of the J1 and J2 bytes in serial based on the expected reception value held in the expected reception value holding unit 48.

Further, in the storage section 27A, the LOM holding section 50 stores the multi-frame pattern serial detection section 4
4 can hold the processing result (calculation result) for each TU channel, and can supply the storage information held one cycle (one frame) before to the multi-frame pattern serial detection unit 44. Reference numeral 51 denotes a processing result of the multi-frame number serial control unit 45 as T
The information stored in each U channel can be supplied to the multi-frame number serial control unit 45 and the expected reception value storage unit 48 in one cycle (one frame). , LOM serial detector 46, CRC serial detector 47 and TI
The processing result of the M serial detection unit 48 is held for each TU channel, and the storage information held one cycle (one frame) is stored in the LOM serial detection unit 46, the CRC serial detection unit 47, and the TIM serial detection unit 48. It can be supplied.

That is, the storage unit 27A includes the multi-frame pattern serial detection unit 44, the multi-frame number serial control unit 45, and the LOM serial detection unit 4
6, the calculation results of the CRC serial detection unit 47 and the TIM serial detection unit 49 are stored for each TU channel, and the multi-frame pattern serial detection unit 44, the multi-frame number serial control unit 45, L
OM serial detector 46, CRC serial detector 47,
It is configured to supply stored information to the expected reception value holding unit 48 and the TIM serial detection unit 49.

As a result, the J1 / J2 byte termination processing unit 22 described above stores the J1 in the VC3-POH 235.
Byte termination processing and VC2-POH236, VC12
-Termination processing of J2 bytes included in the POH 237 (included in a multiplexed signal of a lower order group than the multiplexed signal including the J1 byte) is serially performed by the J1 and J2 byte serial termination processing unit 26A common to each channel. , LOM, CR
Various alarm information such as C, TIM, etc.
It can be obtained by the 2-byte serial termination processing unit 26A.

Hereinafter, the details of each of the above units will be described. FIG.
FIG. 61 is a block diagram showing a detailed configuration of the above-described multi-frame pattern serial detection section 44 and LOM holding section 50. As shown in FIG. 61, the multi-frame pattern serial detection section 44 includes an enable FF circuit 44-1.
(Corresponding to the FF circuit 26-2 shown in FIG. 39), 44-
2, 44-3, continuous zero count adder 44-4, continuous zero count reset unit (1-input inversion type AND circuit) 4
4-5, decode circuits (DEC) 44-6 to 44-8,
Multi-frame head bit detection information reset section (1-input inversion type AND circuit) 44-9, multi-frame head bit detection information setting section (OR circuit) 44-10, frame number correction detection section (AND circuit) 44-11, multi The LOM holding unit 50 is configured to include a frame pattern detection unit (AND circuit) 44-12.
It is configured with AM50-1.

Here, the LOM holding RAM 50-1 of the LOM holding unit 50 stores the processing result of the multi-frame pattern serial detection unit 44, that is, information necessary for detecting alarms of LOM, CRC, and TIM performed on J1 and J2 bytes. The TU address signal (TUADC6) supplied from the phase shift unit 32 '(see FIG. 44) of the timing generation unit 21 is used as a read address and a TUADC7.
Is the write address, and the LOM of the timing generation unit 21
XLOMWENC 8 supplied from the holding RAM operation control unit 36 (see FIG. 48) is write enabled, and LOMC
K operates as a RAM clock.

The LOM holding RAM 50-1
In this embodiment, data of 21 bits is held, for example, as described below. However,
The arrangement of the held data does not necessarily have to be in the following order. • Bit numbers 3 to 0: information on the number of consecutive MSB bits “0” in the J1 and J2 bytes • Bit number 4: Multi-frame head bit detection information • Bit numbers 7 to 5: LOM protection stage number information • Bit numbers 14 to 8: CRC -7 Operation result information • Bit number 15: CRC mismatch detection information before the multi-frame before • Bit number 16: CRC mismatch detection information before the two-multi frame • Bit number 17: Expected reception value mismatch detection information • Bit numbers 20 to 18 : TIM protection stage number information In the multi-frame pattern serial detection unit 44, the FF circuit 44-1 uses a timing signal (J12TPC7: POH timing shown in FIG. 47) indicating the position of the J1 and J2 bytes generated by the timing generation unit 21. The LOM holding RAM 50 is generated in the signal shift unit 35). Read data from 1 (RLOMDTC
7), the FF circuit 44-2 holds the data of the VC4 data (TUDTC7) with the above timing signal (J12TPC7).
FF circuit 44-3 holds the LOM alarm bit (RLOMC7) which is the processing result of one frame before by the timing signal (J12TPC7). Things.

The zero continuous count adder 44-4
Is to increment the “0” consecutive count information (count value) indicating how many times the MSB bits of the J1 and J2 bytes are “0” consecutively. Here, this information is 4-bit information, and the count value returns to “0” by adding +1 to the count value “15”. This means that a multi-frame is composed of 16 bytes of J1 and J2 bytes (15 bytes of trace data bytes starting with a CRC byte (1 byte): see FIG. 12), and only the CRC byte has an MSB bit of “1”. Since the MSB bits of the other trace data bytes are all “0”, J
The arrangement of the MSB bits of the 1, J2 byte is "1000 0000 000
This is because it is sufficient to detect that it is 0 0000 ".

Further, the zero continuous count reset unit 44
-5 resets the "0" consecutive count information to "0" when the FF circuit 44-2 holds data "1" indicating that the CRC byte at the head of the multiframe is detected. Then, the data after this processing (the information on the number of continuous “0”) is stored in the LOM holding RAM 50-1 as described above.
The third bit is written.

The decoding circuit (“0” detecting section) 44
-6 is for detecting that the "0" consecutive count information after processing is "0" (decoding "0") to indicate the start position of the multi-frame pattern. The "14" detection unit) 44-7 detects that the "0" consecutive count information after processing is "14" (decodes "14"), and the J1 and J2 bytes for processing are included in the trace data. This is for indicating the 14th byte, and the decoding circuit (“15” detection unit) 44-8 detects that the “0” consecutive count information after processing is “15” (“15”). J1 and J2
This is to indicate that the byte is the 15th byte in the trace data.

Further, the multi-frame head bit detection information reset section 44-9 resets the head bit detection information of the preceding multi-frame pattern when detecting the head position of the multi-frame pattern. Bit detection information setting section 44-10
Are “1” held by the FF circuit 44-2 and “0” consecutive count information after processing after the first bit is detected.
If not, the first bit of the current multiframe is detected.

The frame number correction detecting section 44-
Reference numeral 11 denotes multi-frame head bit detection information (F) when an alarm (LOM) of multi-frame pattern out-of-synchronization occurs (when RLOMC 7 is at H level).
By detecting that the output information of the F circuit 44-1) and the information on the number of consecutive “0” after processing (output information of the decode circuit 44-7) are “14”, the M1 of the J1 and J2 bytes is detected.
The sequence of SB bits "10000000 0000 000" is detected, and a frame number correction request signal (FRNOSETC8) is generated so that the J1 and J2 bytes of the next frame can be processed as the 15th byte of the trace data byte.

Further, the multi-frame pattern detector 4
4-12 are multi-frame head bit detection information (FF
By detecting that the output information of the circuit 44-1) and the information of the number of consecutive “0” after processing (the output information of the decoding circuit 44-8) are “15”, the MSB of the J1 and J2 bytes is detected.
The multi-frame pattern is detected (MFPATDETC8) by detecting the bit sequence "1000 0000 0000 0000".

With the above-described configuration, the multi-frame pattern serial detection unit 44 uses the LOM holding RAM 50-
While sequentially reading the above-mentioned “0” continuous count information and the multi-frame head bit detection information of 1 to the previous frame,
Arrangement of MSB bits of 1, J2 bytes "1000 0000 0000
By detecting "0000", a multi-frame pattern of J1 and J2 bytes (path trace data) can be serially detected in common for each TU channel.

FIG. 62 is a block diagram showing a detailed configuration of the above-described multi-frame number serial control unit 45 and FRNO holding unit 51. As shown in FIG. FF circuits (corresponding to the FF circuit 26-2 shown in FIG. 39) 45-1, FF circuits 45-2 and 45-3, a frame number control unit 45-4, and a decode circuit (DE
C) It is configured with 45-5, 45-6, FRNO
The holding unit 51 includes a RAM 51-1 for holding FRNO.

Here, the FRNO holding RAM 51-1 of the FRNO holding section 51 holds information indicating the number of bytes of the J1 and J2 bytes in the trace multiframe (hereinafter referred to as frame number information). In the embodiment, for example, as shown in FIG. 63, four bits (bit numbers 3 to 0) of frame number information can be held.

The FRNO holding RAM 51-
1 is a TU address signal (TUAD) supplied from the phase shift unit 32 '(see FIG. 44) of the timing generation unit 21.
C4) is a read address, TUADC 7 is a write address, and the FRNO holding RAM of the timing generator 21
XFRN supplied from the operation control unit 37 (see FIG. 49)
Write enable for OWENC8, RA for FRNOCK
It operates as an M clock, for example, as shown in FIG.
At the detection timing of the J1 byte of TU3 and the J2 byte of TU2 / TU12, the number of the next J1 / J2 byte is read out, and the J1 byte of TU3, TU2 /
At the timing of detecting the J2 byte of the TU12, the next J1 / byte is detected.
The number of the J2 byte is written.

Note that the relationship between the frame number information and the trace multiframe is the same as the frame number information “0”.
Are CRC bytes and frame number information "1" to "1"
"5" indicates the 1st to 15th bytes of the trace data byte, and each frame number information "0" to "15"
Is, for example, in the correspondence shown in FIG.
The data is held in the holding RAM 51-1.

On the other hand, in the multi-frame number serial control section 45, the FF circuit 45-1 has a timing signal indicating the position of the J1 and J2 bytes (J12TPC5: generated by the POH timing signal shift section 35 shown in FIG. 47). Thus, the data of the 3rd to 0th bits (the frame number information) of the read data from the RAM 51-1 for holding the FRNO is held.

The FF circuit 45-2 delays the phase of the frame number information held by the FF circuit 45-1 by one master clock.
The circuit 45-3 further delays the frame number information held by the FF circuit 45-2 by one clock of the master clock.
-4 is for adding +1 to the count value of the frame number information held in the FF circuit 45-3.

The frame number control unit 45-
4 is a frame number correction request signal (FRNO) supplied from the multi-frame pattern detector 44-11 of the multi-frame pattern serial detector 44 shown in FIG.
When SETC8) is "1", the count value of the frame number information is updated to "15".

Further, a decoding circuit ("0" detecting section) 4
5-5, the count value of the frame number information is “0”
Signal indicating that the J1 and J2 bytes to be processed are CRC bytes (CRCTPC
8), and the decoding circuit (“15” detection unit) 45-6 detects that the count value of the frame number information is “15”, and performs processing J1 and J2.
A signal (FRNO15TPC8) indicating that the J2 byte is the fifteenth byte of the trace data byte, that is, the last byte of the multi-frame pattern is generated.

With the above-described configuration, the multi-frame number serial control section 45 has the FRNO holding RAM 51.
The above-mentioned frame number information of the previous frame is sequentially read from -1 and the frame number information for the current multi-frame is updated based on the frame number information, thereby controlling the multi-frame number serially for each TU channel. Can do it.

Next, FIG. 66 is a block diagram showing a detailed configuration of the LOM serial detector 46 in FIG. 60. As shown in FIG. 66, the LOM serial detector 46 of the present embodiment comprises an FF circuit 46 with enable. -1, 46-2,
LOM protection stage number adder 46-3, decode circuit (DE
C) 46-4, 46-5, addition condition detection unit (exclusive NOR circuit) 46-6, LOM detection 7-stage detection unit (AND
Circuit) 46-7, LOM release 3-stage detection unit (AND circuit)
46-8, state transition occurrence detecting section (OR circuit) 46-9,
LOM protection stage number information reset unit (one-input inversion type AND circuit) 46-10, state transition unit (exclusive OR circuit) 46
-11 and a bypass controller (selector) 46-12.

Here, the FF circuit 46-1 comprises J1 and J2
Timing signal indicating byte position (J12TPC7:
47 is supplied from the POH timing signal shift unit 35 shown in FIG. 47).
7 of read data (RLOMDTC7) from 1
The FF circuit 46-2 holds the LOM alarm bit (RLOMC7), which is the processing result of the previous frame, with the above-mentioned timing signal (J12TPC7). Things.

Also, the LOM protection stage number adder 46-3 includes:
The count value of the LOM protection stage number information read from the LOM holding RAM 50-1 is added with +1. The decoding circuit (“6” detection unit) 46-4 outputs the count value of the read LOM protection stage number information. The decoding circuit ("2" detecting section) 46-5 detects that the count value of the read LOM protection stage number information is "2".

Further, the addition condition detecting section 46-6 outputs the LO
A multi-frame pattern was detected during the occurrence of M, and a multi-frame pattern was not detected during the absence of LOM (when RLOMC7 was "0") (MFPA).
TDETC8 is "0").
The OM detection seven-stage detection unit 46-7 includes a decoding circuit 46-4.
When the addition condition is detected for 6 consecutive multi-frames when the state is not a multi-frame pattern, and when the addition condition also occurs for the current multi-frame, it is detected that the addition condition has occurred for 7 consecutive multi-frames, and LOM detection is performed. Is performed.

Also, the LOM release three-stage detection unit 46-8
The decoding circuit 46-5 detects the addition condition for two consecutive multi-frames during the occurrence of the LOM. When the addition condition also occurs for the current multi-frame, it is detected that the addition condition has been generated for three consecutive multi-frames. And the LOM is released, and the state transition occurrence detecting unit 46-9
The LOM detection seven-stage detection unit 46-7 and the LOM cancellation three-stage detection unit 46-8 detect that a condition for detecting or canceling the LOM has occurred.

Further, the LOM protection stage number information reset unit 4
6-10, when the addition condition is not detected by the above-described addition condition detection unit 46-6, and when the state transition occurrence detection unit 46-
9, when the occurrence of a state transition is detected, the count value of the LOM protection stage number information is reset to “0”;
The state transition unit 46-11 includes a state transition occurrence detection unit 46-9.
When the occurrence of a state transition is detected in step (1), the polarity of the alarm bit of the LOM is inverted, and the state transition during the occurrence of LOMＭthe absence of LOM is performed.

The bypass control section 46-12 is connected to J1, J2
LOM at the 15th byte of byte trace data
The above-described LOM protection stage number information reset unit 46-
10 is written to the LOM holding RAM 50-1 and the processing result of the state transition unit 46-11 is written to the alarm bit holding unit 52. When it is other than the 15th byte, the LOM holding RAM 50-1 and the alarm bit are written. The information read from the holding unit 52 is written as it is to the LOM holding RAM 50-1 and the alarm bit holding unit 52.

With the above-described configuration, the LOM serial detection unit 46 outputs the LOM protection stage number information of the previous frame and the LOM alarm bit (indicating whether or not LOM is occurring / not occurring) from the LOM holding RAM 50-1 and the alarm bit holding unit 52. Status information) is sequentially read out, and the LOM updating process for the current multiframe is performed based on these pieces of information.
Can be detected.

Next, FIG. 67 is a block diagram showing a detailed configuration of the CRC serial detecting section 47 in FIG. 60. As shown in FIG. 67, the CRC serial detecting section 47 of the present embodiment comprises an FF circuit 47 with enable. -1 to 47-3,
CRC calculation result reset unit (AND circuit) 47-4, C
RC data insertion unit (80 hex insertion unit) 47-5, CR
C operation unit 47-6, mismatch detection unit 47-7, protection stage control unit 47-8, CRC error detection three-stage detection unit (1-input inversion type AND circuit) 47-9, CRC error cancellation three-stage detection unit (1 Input inversion type NOR circuit) 47-10, state transition occurrence detecting section (OR circuit) 47-11, state transition section (exclusive OR circuit) 47-12, and bypass control section (selector)
47-13.

Here, the FF circuit 47-1 includes J1 and J2
Timing signal indicating byte position (J12TPC7:
47 is supplied from the POH timing signal shift unit 35 shown in FIG. 47).
1 of read data (RLOMDTC7) from 1
6th to 8th bit data (CRC-7 operation result information, 1
It holds the CRC mismatch detection information before the multi-frame and the CRC mismatch detection information two multi-frames before.

The FF circuit 47-2 uses the timing signal (J12TPC7) to generate TU data (TUTDC).
7), the FF circuit 47-3 holds the J1 and J2 byte data.
TPC7) holds a CRC alarm bit (RCRCC7) as a processing result of the previous frame.
RC operation result reset section 47-4 performs processing J
R for LOM holding when 1, J2 bytes are CRC bytes
CR of the previous multi-frame read from AM50-1
This resets the C operation result.

Further, the CRC data insertion section 47-5
The CRC byte data is rewritten to 80 hex, and the CRC calculation unit 47-6 converts the CRC byte data to 80 hex by the CRC data insertion unit 47-5 to generate 1 to 15 bytes of trace data and generates a polynomial X ^7.
+ By X ³ +1 performs a CRC-7 calculation, the calculation result is set to be written to LOM holding RAM50-1.

The mismatch detector 47-7 detects a mismatch between the CRC operation result of the previous multiframe and the CRC value of the 2nd to 8th bits of the CRC byte. The output signal of the mismatch detecting section 47-7 is used as the 15th bit data of the LOM holding RAM 50-1, and the 15th bit data read from the LOM holding RAM 50-1 is shifted to the 16th bit. It is.

Further, the CRC error detection three-stage detection unit 47
-9 indicates that the mismatch detection unit 47-
7, the CRC mismatch detection information one frame before and the CRC mismatch detection information two frames before are all CRC
If a mismatch is detected, it is detected that a CRC match has occurred for three consecutive multi-frames.
During the occurrence of a CRC error, the C error cancellation three-stage detection unit 47-10 checks whether the detection result of the mismatch detection unit 47-7, the CRC mismatch detection information of one frame before, and the CRC mismatch detection information of two frames before are all CRC match. If detection is detected, C
It detects that the RC match has occurred for three consecutive multi-frames and cancels the CRC error.

Also, the state transition occurrence detecting section 47-11 includes:
The CRC error detection three-stage detection unit 47-9 and the CRC error cancellation three-stage detection unit 47-10 detect that a CRC error has been detected or released, and the state transition unit 47-12 performs this state detection. When the occurrence of a state transition is detected by the transition occurrence detecting unit 47-11, the polarity of the CRC error alarm bit is inverted, and a CRC error is generated.
A state transition during which no RC error has occurred is performed.

[0276] The bypass control unit 47-13 includes J1 and J2.
To update the CRC error at the time of the CRC byte, only when processing the CRC byte,
The processing result of the protection stage controller 47-8 is stored in the LOM holding RAM
While writing to 50-1 and the processing result of the state transition unit 47-12 to the alarm bit holding unit 52,
If it is not a CRC byte, the LOM holding RAM 50
-1 and the information read from the alarm bit holding unit 52 are directly written into the LOM holding RAM 50-1 and the alarm bit holding unit 52.

With the above-described configuration, the CRC serial detecting section 47 outputs the CRC-7 of the previous frame from the LOM holding RAM 50-1 and the alarm bit holding section 52, respectively.
Calculation result information, CRC mismatch detection information one multiframe before, CRC mismatch detection information two multiframes before, C
The RC alarm bits (status information indicating that a CRC error is occurring / not occurring) are sequentially read out, and based on each of these information, a CRC operation (update of the CRC error) is performed on the current multi-frame, so that each TU channel is shared. Can detect the CRC serially.

By the way, as shown in FIG. 68, for example, the CRC serial detection unit 47 shown in FIG. 67 includes the above-mentioned protection stage control unit 47-8, CRC error detection three-stage detection unit 47-
9, CRC error cancellation three-stage detection unit 47-10 and state transition occurrence detection unit 47-11, instead of CRC protection stage number addition unit 47-14, decoding circuit 47-15, addition condition detection unit (exclusive OR circuit) ) 47-16, a detection / cancellation three-stage detection unit (AND circuit) 47-17 and a protection stage number reset unit (1-input inversion type AND circuit) 47-18 may be provided.

However, in this case, the LOM holding RAM
The CRC mismatch detection information before one multiframe and the CRC mismatch detection information before two multiframes held in 50-1 are used as CRC protection stage number information indicating how many times CRC match / mismatch has occurred consecutively. . Where CR
The C protection stage number adder 47-14 is provided with the LOM holding RAM 5
The CRC protection stage number information read from 0-1 is incremented by 1, and the decoding circuit ("2" detection unit) 47-15
Is for detecting that the CRC protection stage number information is "2". The addition condition detection unit 47-16 determines that the match is detected by the mismatch detection unit 47-7 during the occurrence of the CRC error, and that the CRC error This is to detect that a mismatch has been detected by the mismatch detector 47-7 during the non-occurrence.

The detection / cancellation three-stage detection section 47-17 has a CR
It detects the occurrence of the C error detection / cancellation condition.
The protection stage number reset unit 47-18 resets CRC protection stage number information. As a result, the above C
The RC serial detector 47 can also detect the CRC serially as shown in FIG.

Next, FIG. 69 is a block diagram showing a detailed configuration of the TIM serial detector 49 in FIG. 60. As shown in FIG. 69, the TIM serial detector 49 of the present embodiment comprises an FF circuit 49 with enable. -1 to 49-4,
Discrepancy detection section 49-5, discrepancy detection display section (OR circuit)
49-6, mismatch detection display reset section (1 input inversion type A
ND circuit) 49-7, addition condition detection unit (exclusive OR circuit) 49-8, TIM protection stage number addition unit 49-9, decode circuits 49-10, 49-11, and TIM detection seven-stage detection unit (AND circuit) ) 49-12, TIM release three-stage detector (A
ND circuit) 49-13, state transition occurrence detection section (OR circuit) 49-14, TIM protection stage number information reset section (1-input inversion type AND circuit) 49-15, state transition section (exclusive OR circuit) 49- 16 and a bypass control section (selector) 49-17.

Here, the FF circuit 49-1 is connected to J1, J2
Timing signal indicating byte position (J12TPC7:
47 (supplied from the POH timing signal shift unit 35 shown in FIG. 47), the 20th to 17th bit data (reception expected value mismatch detection information, TIM protection) of the read data (RLOMTC7) from the LOM holding RAM 50-1. FF circuit 49-2).
Is a timing signal (J12TPC7) for holding J1 and J2 byte data from TU data (TUDTC7).

The FF circuit 49-3 performs processing on the J1 and J2 based on the timing signal (J12TPC7).
The FF circuit 49-4 holds the TIM alarm bit (RTIMC7), which is the processing result of the previous frame, using the timing signal (J12TPC7). It is.

Further, the mismatch detecting section 49-5 detects a mismatch between the 7 bits of the expected reception value and the 2 to 8 bits of the J1 and J2 bytes. The disparity detecting unit 49-5 generates a signal indicating that the disparity between the reception trace data of the current multiframe and the expected reception value is detected. In this case, the exclusive OR circuit 49-5A and the exclusive OR circuit 49-5A are used. The function is realized by the OR circuit 49-5B.

Also, the mismatch detection display reset section 49-7
Indicates a CRC byte mismatch detection display which does not need to be compared with the expected reception value when the CRC byte is the head position of the multi-frame, and the LOM holding RAM 50-1
This resets the mismatch detection display of the previous multi-frame read from the addition condition detection unit 49-8.
Indicates that the detection of the mismatch of the received value was performed while the TIM as the TIM detection condition was not generated, and that the TIM cancellation condition was T.
This is to detect that the reception value coincidence is performed during the IM generation.

Further, TIM protection stage number adder 49-9
Is for incrementing the count value of the TIM protection stage number information by +1. The decoding circuit ("6" detection unit) 49-10 detects that the read count value of the TIM protection stage number information is "6". The decode circuit (“2” detection unit) 49-11 detects that the read count value of the TIM protection stage number information is “2”.

The TIM detection 7-stage detection section 49-12
Detects that the addition condition is detected for six consecutive multi-frames in the decoding circuit 49-10, and that the addition condition is generated for seven consecutive multi-frames when the addition condition is also generated in the current multi-frame. The TIM release three-stage detection unit 49-13 performs
While the TIM is occurring, the above-described decode circuit 49-11
When the addition condition is detected for two consecutive multi-frames and the addition condition also occurs in the current multi-frame,
TIM cancellation is performed by detecting that an addition condition has occurred continuously for multiple frames.

Further, the state transition occurrence detecting section 49-14
Are the TIM detection 7-stage detection unit 49-12 and the TIM detection
This is to detect the occurrence of TIM detection or cancellation by the release three-stage detection unit 49-13, and the TIM protection stage number information reset unit 49-15 detects that the addition condition has not been detected by the addition condition detection unit 49-8. When the state transition occurrence is detected by the state transition occurrence detection unit 49-14,
The count value of the protection stage number information is reset to “0”.

When the state transition occurrence detecting section 49-14 detects the occurrence of the state transition, the state transition section 49-16 inverts the polarity of the TIM alarm bit, and
The state transition during the occurrence of M / the absence of TIM is performed, and the bypass control unit 49-17 performs the update of the TIM at the 15th byte of the J1 and J2 byte trace data in order to update the TIM. Only when performing the processing of (1), while writing the processing result of the TIM protection stage number information resetting unit 49-15 to the LOM holding RAM 50-1,
The processing result of the state transition unit 49-16 is written into the alarm bit holding unit 52.
The information read from the M holding RAM 50-1 and the alarm bit holding unit 52 is used as it is as the LOM holding RAM 50-
1 is written to the alarm bit holding unit 52.

With the above-described configuration, the TIM serial detection section 49 of the present embodiment allows the LOM holding RAM 50-1,
From the alarm bit holding unit 52, the T
By sequentially reading the IM protection stage number information and the TIM alarm bit (status information of TIM generation / non-generation) and updating the TIM protection stage number information for the current multi-frame based on each of these information, each TU channel is updated. The TIM can be serially detected in common.

FIG. 70 is a block diagram showing a detailed configuration of expected reception value holding section 48 in FIG.
As shown in (1), the expected reception value holding unit 48 of the present embodiment
RAM 48-1 for holding the first expected reception value (EXP1), RAM 48-2 for holding the second expected reception value (EXP2), signal label (SL) expected reception value MSB bit holding unit (F
F circuit) 48-3 to 48-5, MSB bit soft notification selection section 48-6, expected reception value software notification selection section (selector) 48-7, SL reception expected value read address control section (1-input inversion type AND circuit) ) 48-8, FF circuit 48-
9, 48-10, decode circuits 48-11 to 48-1
3, an MSB bit selector 48-14 and an expected reception value selector (selector) 48-15.

Here, the EXP1 holding RAM 48-1 is used.
Holds the expected value of the signal label of the TU channel = 0 to 62 ch and the expected value of the first to seventh bytes of the trace data when the STM-1 frame is considered as the received multiplexed signal. The XEXP1WEN supplied from the RAM operation control unit 41 for holding the expected reception value of the generation unit 21 (see FIG. 53) is write-enabled.
XP1CK is operated as a RAM clock, and an expected value of SL reception [EXP1: signal label (SL), path trace data (TR) is stored in a corresponding address (MEXPAD) area, for example, as shown in FIG.
C)] are sequentially written.

Further, the EXP2 holding RAM 48-2 is
TU channel = 8- of trace data of 0-62ch
This holds the expected reception value of the 15th byte. Similarly, the XEXP2WEN supplied from the RAM operation control unit 41 for holding the expected reception value of the timing generation unit 21 operates as a write enable, and EXP2CK operates as a RAM clock. In the address (MEXPAD) area, for example, as shown in FIG. 72, the SL reception expected value (EXP
2: TRC) are sequentially written.

At this time, the RAM address (M
EXPAD), the frame number, and the TU channel are as shown in FIG. 75 in the present embodiment. In other words, the expected reception value holding unit 48 of the present embodiment generally has only 512 addresses in the RAM due to its specifications.
In order to obtain an address, two RAMs for holding expected reception values are prepared in this way. In this embodiment, for example, as shown in FIGS.
The control (access switching) of the read / write (operation timing is shown in FIG. 73) of the RAMs 48-1 and 48-2 is performed by the MSB bit of the address contents (address bits) of -1 and 48-2. . If there is a RAM having a capacity capable of holding all the expected reception values, it is needless to say that two RAMs need not be prepared as described above but only one RAM is required.

Further, the expected SL reception value MSB bit holding unit 48-3 holds the MSB bit of the expected SL reception value of the TU channel = 0ch, and the expected SL reception MSB bit holding unit 48-4 includes: TU channel = 1
and holds the MSB bit of the expected SL reception value of the channel.
It holds the MSB bit of the expected SL reception value of the TU channel = 2ch.

That is, the expected reception value holding unit 48 needs the expected SL reception value of 8 bits when the input multiplexed signal is TU3, but lacks the bits in the 7-bit EXP1 holding RAM 48-1 as described above. Therefore, each of the above-mentioned SL reception expected value MSB bit holding units 48-3 to 48-
5 holds the expected value of the eighth bit for the expected value of TU3. Note that the above E
XP1 holding RAM 48-1, EXP2 holding RAM4
8-2, SL reception expected value MSB bit holding section 48-3 to
The setting of the expected reception value in 48-5 and the reading of the setting contents are performed from the software side.

The MSB bit software notification selecting section 48
-6 is used to select when the software reads the setting contents of the expected SL reception value of the TU channel = 0 to 2ch. Here, the AND circuits 48-6A to 48-
6C and the OR circuit 46-6D, the function is realized, and the expected reception value software notification selection unit 48-7 reads the setting contents of the expected reception value set by the software to the EXP1 holding RAM 48-1. , EXP2 holding RAM
48-2, the M of the address signal (MEXPAD) indicating the write / read address by software
This is to select the read data on the RAM side from which correct reading has been performed using the SB bit.

Further, when reading the expected SL reception value for performing the SLM process, the SL reception expected value read address control unit 48-8 outputs a timing signal (C2V5TPC5: FIG. 47) indicating the position of the C2 and V5 bytes.
, The frame number information (FRNODTC5) read from the above-mentioned FRNO holding unit 51 (FRNO holding RAM 51-1: see FIG. 62) is masked to “0”. Is performed.

[0299] The 10 bits of 4 bits for performing this control and 6 bits of the TU address signal (TUADC5) are:
10-bit expected expected value read address (REXPAD)
C5) is created. When reading the expected SL reception value by this control, the upper 4 bits of the 10-bit expected reception value read address become “0000”,
The expected SL reception value is read out using 10 bits including the TUAD 6 bits indicating the TU channel to be processed.

The FF circuit 48-9 delays the phase of the 10-bit reception expected value read address by one clock with the master clock.
Is to delay the phase of the 10-bit expected value read address by one clock further by the master clock. Further, a decoding circuit ("0" detecting section) 48-11
Detects that the 10-bit expected value read address is “0”, and the decoding circuit (“1”)
The detector (48-12) detects that the 10-bit expected expected value read address is “1”, and the decode circuit (“2” detector) 48-13 detects the 10-bit expected expected value read address. Is "2".

The MSB bit selecting section 48-14 also
In this case, the selection of the setting content of the expected SL reception value of the TU channel = 0 to 2 ch is selected.
Circuits 48-14A to 48-14C and OR circuit 48-1
The function is realized using 4D, and the expected reception value selection unit 48-15 uses the 9 bits of the 10-bit reception expected value read address to store the EXP1 holding RAM 48
-1, reading the expected reception value from the EXP2 holding RAM 48-2, and selecting the expected reception value read by the MSB bit of the 10-bit expected reception value read address. 15 output signal 7 bits are the path trace data reception expected value (REX
PDTC7), and the TIM serial detector 4
9 is notified as an expected value of trace data reception, and an 8-bit signal obtained by adding the output signal of the MSB bit selector 48-14 to the 7 bits of the output signal is an SL reception expected value (REX).
PS2 / C5 as described later with reference to FIG.
The SLM detection unit 73 of the byte end processing unit 24 is notified.

With the above configuration, the expected reception value holding section 48 of the present embodiment has the TIM serial detection section 49, C2 /
The V5 byte termination processing unit 24 can serially hold and supply various expected reception values required for processing on the software side for each TU channel. Next, FIG. 77 is a block diagram showing a detailed configuration of the alarm bit holding unit 52 in FIG. 60. As shown in FIG. 77, the alarm bit holding unit 52 of this embodiment is different from the TIM alarm bit holding unit 5 in FIG.
2-1, CRC alarm bit holding section 52-2, LOM
An alarm bit holding unit 52-3, an alarm bit write address control unit (1-input inversion type OR circuit) 52-4,
Write enable generator [decode circuit (DEC)] 5
2-5, alarm bit read address control unit (1-input inversion type OR circuit) 52-6, read select generation unit (DEC) 52-7, TIM select unit (selector) 5
2-8, CRC select section (selector) 52-9, LO
M select section (selector) 52-10, line switching information read select generating section (DEC) 52-11, line switching information select section (selector) 52-12, software notification read select generating section (DEC) 52-13, and software It is configured to include a notification selection section (selector) 52-14.

Here, the TIM alarm bit holding section 52
-1 indicates that the 63 FF circuits 52A hold the TIM alarm bits of the TU channel = 0 to 62 ch, and the CRC alarm bit holding unit 52-2 has:
TU channel = 0 to 6 by 63 FF circuits 52B
The 2ch CRC alarm bit is held, and the LOM alarm bit holding section 52-3 holds the LOM alarm bit by 63 FF circuits 52C.

When the write timing (J12TPC8) of the alarm bit is "1", the alarm bit write address control section 52-4 performs the TU to perform the processing.
The contents of the channel (TUADC8) are output and J12T
When the PC 8 is "0", the output signal is controlled to 63 ("111111" in binary notation). Further, the write enable generation unit 52-5 outputs the output signal of the alarm bit write address control unit 52-4 of 0.
In the case of ~ 62, a write enable signal for each alarm bit holding FF circuit 52A ~ 52C for 0 ~ 62ch is generated, and WTIMC8, WCRCC8, WLOM which are alarm signals after TIM, CRC, LOM processing.
This is supplied to the FF circuits 52A to 52C which hold the alarm bits of the TU channel that has undergone the processing of C8. Note that when the output signal of the alarm bit write address control unit 52-4 is 63, the write enable is not generated, and the write enable is not generated.

When the alarm bit read timing (J12TPC7) is "1", the alarm bit read address control section 52-6 performs TU to perform processing.
The contents of the channel (TUADC7) are output and J12T
When PC7 = “0”, the output signal is controlled to 63 (“111111” in binary notation), and the read select generation section 52-7 outputs the alarm bit read address control section 52-6 with the output signal. In the case of 0 to 62, it generates a read select signal for reading the alarm bits of channels 0 to 62. The output signal of the alarm bit read address control unit 52-6 is 6
At 3, the read select signal is not generated because it is not the alarm bit read timing.

Further, the TIM select section 52-8 reads the TIM alarm bit of the TU channel to be processed with the read select signal generated by the read select generation section 52-7. Reference numeral 52-9 denotes a read select signal generated by the read select generation unit 52-7, which reads out an alarm bit of the CRC of the TU channel to be processed. The read select signal generated by the section 52-7 reads out the LOM alarm bit of the TU channel to be processed.

The line switching information read select generation section 52-11 generates a read selection signal for the TU channel = 0 to 62 ch. The line switching information selection section 52-12 outputs the line switching information read select signal. The read select signal generated by the generation unit 52-11 reads the alarm bit of the TIM, and the software notification read select generation unit 52-13 generates a read selection signal of the TU channel = 0 to 62ch. Yes, the software notification selection unit 52-14 reads the TIM alarm bit with the read select signal generated by the software notification read selection generation unit 52-13, and notifies the software of the TIM alarm.

With the above-described configuration, the alarm bit holding unit 52 of the present embodiment can hold various alarm information such as TIM, CRC, and LOM in common for each TU channel and generate a TIM alarm serially. it can. Hereinafter, the overall operation of the J1 / J2 byte termination processing unit 22 configured as described above will be briefly described.
First, TU data (here, J1 byte of VC3), TUAD, SPEN,
Assuming that J1V5TP, VC3TUG, and VC2VC12 are respectively input, the multi-frame pattern serial detection unit 44 and the LOM holding unit 50 shown in FIG.
However, each unit operates according to the timing shown in FIGS. 79 (a) to 79 (l).

At this time, the multi-frame number serial detecting section 45 and the FRNO holding section 5 shown in FIG.
1 and the LOM serial detector 46 shown in FIG.
In the CRC serial detector 47 shown in FIG.
Each part operates in accordance with the timings shown in FIGS. 80A to 80N, and the TIM serial detector 49 shown in FIG.
And the expected reception value holding unit 48 shown in FIG.
Operating according to the timings shown in FIGS. 81 (a) to 81 (k), an expected SL reception value required for processing in the C2 / V5 byte termination processing unit 24 is generated.

As a result, in the alarm bit holding unit 52 shown in FIG. 82, each unit operates according to the timings shown in FIGS. 82 (a) to 82 (n), for example, and the alarm bit of the TIM is set for each TU channel. Generated serially. As described above, according to the POH termination processing unit 8 of the present embodiment, the J1 byte termination processing and the J2 byte termination processing are serially performed by the J1 / J2 byte termination processing unit 22 common to each TU channel. Since the multi-frame pattern detection of the multiplexed signal is performed by one J1 / J2 byte termination processing unit 22, the circuit for performing the termination processing for the J1 byte and the circuit for performing the termination processing for the J2 byte are each provided for the corresponding number of TU channels. There is no need to provide.

Therefore, the circuit (device) of the POH termination processing unit 8 is greatly reduced in scale and power consumption is greatly reduced.
At this time, specifically, in the J1 / J2 byte termination processing unit 22, various types of alarm information such as LOM, CRC, and TIM can be serially obtained in common for each TU channel. , A circuit for CRC detection, a circuit for TIM detection, and the like do not need to be separately prepared, so that the apparatus scale can be further reduced and power consumption can be further reduced.

(C4) B3 / V5 byte end processing unit 23
FIG. 83 is a block diagram showing the configuration of the B3 / V5 byte termination processing unit 23 described above with reference to FIG.
As shown in the figure, the B3 / V5 byte termination processing unit 23 of the present embodiment comprises a BIP2 error serial detection unit 53, a BIP
2 holding unit 54, BIP8 error serial detecting unit 55, B
IPPM count value initialization control unit 56, BIPPM serial processing unit 57, BIPPM holding unit 58, and PMRAM
An address control unit 59 is provided.

Here, the BIP2 error serial detection section (BIP2 serial operation processing section) 53
A BIP2 operation for VC2 and VC12 in the multiplexed signal is performed serially based on the IP2 error to detect a BIP2 error. The BIP2 holding unit 54 converts the BIP2 operation result from the BIP2 error serial detection unit 53 into a TU channel. And BIP2
The stored information (BIP2 calculation result one cycle before) is supplied to the error serial detection unit 53.

The BIP8 error serial detector (B
The IP8 serial operation processing unit 55 performs a BIP8 operation on the VC3 data in serial to detect a BIP8 error, and the BIPPM count value initialization control unit 56 performs a BIPPM operation in response to a PM reset signal from the software. The BIPPM serial processing unit 57 controls the initialization of the count value of the BIP2.
Output of the error serial detector 53 and the BIP8 error serial detector 55 (BIP2 error, BIP8 error)
And BI based on the selected BIP error signal.
The addition operation of the PPM is performed serially.

That is, the BIPPM serial processing unit 5
Reference numeral 7 denotes a BIP2 error serial detection unit 53 and a BIP8 error serial detection unit 55, for example, as shown in FIG.
BIP for selecting BIP error signal output from
An error selector 57A and the BIP error selector 57A
And a BIPPM serial adder 57B for performing a serial addition operation of the BIPPM based on the BIP error signal selected in the step (1).

Further, the BIPPM holding section 58
The calculation result (BIPPM) in the PM serial processing unit 57 is stored for each TU channel, and the stored information (the BIPP in the previous cycle) is stored in the BIPPM serial processing unit 57.
M), and the PMRAM address control unit 59 responds to the PM reset signal from the software to
RAM address for IPPM holding unit 58, G1 described later
FEBEPM holding unit 93 of / V5 byte end processing unit 25
(See FIGS. 110 and 114) for generating a RAM address.

That is, the above-described B3 / V5 byte termination processing unit 23 is configured to
A B3 and V5 byte serial termination processing unit 26B for serially performing the B3 byte and V5 byte BIP operation processing included in the C4 signal and the B3 byte and V5 byte BIPPM termination processing, respectively, is configured as shown in FIG.
The storage unit 27 shown in FIG. 8 stores the calculation result of the B3, V5 byte serial termination processing unit 26B for each TU channel,
6B is configured as a storage unit 27B that can supply storage information to 6B.

Thus, the B3 / B5 byte termination processing unit 23 can serially detect BIP errors to be detected by POH termination processing for each TU channel having a different signal size in common for each channel. . Therefore, each of the above-described units is specifically configured as follows. FIG. 85 is a block diagram showing a detailed configuration of the BIP error serial detection unit 53 and the BIP2 holding unit 54.
As shown in FIG. 85, the BIP error serial detection unit 53 includes enable FF circuits 53-1 and 53-2,
BIP2 operation value reset unit (1 input inversion type AND circuit)
53-3, odd bit BIP2 operation unit (exclusive OR circuit) 53-4, even bit BIP2 operation unit (exclusive OR circuit) 53-5, BIP2 operation comparison unit 53-6 and B
The BIP2 holding unit 54 is provided with an IP2 error detecting unit (AND circuit) 53-7.
M54-1 is provided.

First, the BIP of the BIP2 holding unit 54
2 holding RAM 54-1 has a BIP
The TU address signal (TUADC6) supplied from the phase shift unit 32 '(see FIG. 44) of the timing generation unit 21 is used as a read address and the TUADC 7 is used as a write address. BIP2 holding RAM operation control unit 38 (FIG. 5)
0) supplied from XBIP2WENC8 as a write enable, and BIP2CK as a RAM clock.

Note that the BIP2 holding RAM 54-1 is used.
Here, 2-bit data is held, and the storage result of odd-numbered bits is stored in the storage area of bit number “1”, and the storage result of even-numbered bits is stored in the storage area of bit number “0”.
The result of the IP2 operation processing is held. On the other hand, in the BIP2 error serial detection unit 53, the FF circuit 53-1 includes:
The timing signal (SPEENC7) indicating the position of the payload data of the TU is used as the BIP2 holding RAM 54-1.
The FF circuit 53-2 holds the VC4 data (T) in response to the above timing signal (SPEENC7).
UDTC 7) holds the payload data, and this signal is output as SPEDTC8.

The BIP2 operation value reset section 53-3
Is a V5 byte timing signal (V5TPC8) that is the head position of the BIP2 calculation range,
This masks the result of the BIP2 operation read out from M54-1, and resets the operation value in the previous BIP2 operation range.
-4 is the odd-numbered bit BIP2 operation processing result read from the BIP2 holding RAM 54-1 and the FF circuit 53-
The exclusive OR (EXOR) is performed on the first, third, fifth, and seventh bits of the payload data held in step 2 and the result is written into the first bit of the BIP2 holding RAM 54-1.

Furthermore, the even-bit BIP2 operation unit 53-
5 is a BIP2 operation processing result of even-numbered bits read from the BIP2 holding RAM 54-1 and the FF circuit 53-2.
The exclusive OR (EXOR) is performed on the second, fourth, sixth, and eighth bits of the payload data held in step (1), and the result is written into the zeroth bit of the BIP2 holding RAM 54-1.

Also, the BIP2 operation comparing section 53-6 outputs
The BIP2 arithmetic processing result read from the IP2 holding RAM 54-1 is compared with the first and second bits of the payload data held by the FF circuit 53-2, and "1" is output when they do not match. Here, FIG. 85
As shown in (1), the function is realized by using an exclusive OR circuit 53-6A and an OR gate 53-6B.

Further, the BIP2 error detecting section 53-7
Outputs the output of the BIP2 operation comparing unit 53-6 to the BIP2
Although this is output as an error, the BIP2 operation comparator 53-6 always performs 2-bit comparison, so that an invalid comparison result is output from the BIP2 operation comparator 53-6 at a timing other than the V5 byte. Will be done.
Therefore, the BIP2 error detecting unit 53-7 corrects the BIP2 error with the V5 byte timing signal (V5TPC8).
The two operation comparison results are extracted and output.

According to the above configuration, the BIP2
In the error serial detection unit 53, the RAM for holding the BIP2
54-1. The BIP2 errors of the previous frame are sequentially read out from 54-1.
By performing the IP2 operation and updating the BIP2 error information, a BIP2 error can be detected serially in common for each TU channel.

Next, FIG. 86 is a block diagram showing a detailed configuration of the BIP8 error serial detector 55 shown in FIG. 83.
As shown in FIG. 86, the BIP8 error serial detection unit 55 of this embodiment includes BIP8 operation value holding units (FF circuits) 55-1 to 55-3 and a BIP8 operation result holding unit (F
F circuit) 55-4 to 55-6, decode circuit (DEC)
55-7 to 55-9, BIP operation value selection unit (selector)
55-10, BIP8 operation value reset unit (1-input inversion type AND circuit) 55-11, BIP operation unit (exclusive OR circuit) 55-12, BIP8 operation value write enable generation unit (AND circuit) 55-13, BIP8 operation result write enable generation unit (AND circuit) 55-14, BIP
8 operation result selection unit (selector) 55-15, BIP8 operation comparison unit 55-16, and BIP8 error detection unit (AND
Circuit) 55-17.

Here, the BIP8 operation value holding unit 55-1
Is B for each TU channel = 0ch payload data
The BIP8 calculation value holding unit 55-2 holds the IP8 calculation result, and holds the BIP8 calculation result for each payload data of the TU channel = 1ch.
The BIP8 operation value holding unit 55-3 has a TU channel = 2
This holds the BIP8 operation result for each payload data of the channel.

Also, the BIP8 operation result holding unit 55-4
Holds the BIP8 calculation result from the J1 byte of the TU channel = 0 ch to the J1 byte of the next frame. The BIP8 calculation result holding unit 55-5 stores the BIP8 calculation result from the J1 byte of the TU channel = 1ch to the J1 byte of the next frame. BIP8 calculation results up to BI
The P8 operation result holding unit 55-6 has a TU channel = 2c
BI from the J1 byte of h to the J1 byte of the next frame
This holds the P8 calculation result.

Further, a decoding circuit ("0" detecting section) 5
5-7 are TU channels (TUADC) for processing.
8) is "0", and the decoding circuit ("1" detecting section) 55-8 detects the TU for processing.
It detects that the channel (TUADC8) is "1", and the decoding circuit ("2" detector) 55-
Numeral 9 detects that the TU channel (TUADC 8) for processing is "2".

Also, the BIP operation value selection section 55-10
BIP8 of each BIP8 operation value holding unit 55-1 to 55-3
The BIP8 calculation value reset unit 55-11 selects the calculation value according to the detection signals from the decoding circuits 55-7 to 55-9. The BIP8 calculation value reset unit 55-11 detects the timing (J1 byte) of the head position of the BIP8 calculation range. J1TUPC8)
The masking of the BIP8 operation values read from the BIP8 operation value holding units 55-1 to 55-3 is performed to reset the operation result in the previous BIP8 operation range.

[0331] Further, the BIP operation unit 55-12 performs the BIP8 operation value after the reset control by the above-described BIP8 operation value reset unit 55-11 and the SP which is the payload data.
The BIP8 operation is performed by taking an exclusive OR (EXOR) for each bit with the EDTC8. The BIP8 operation value write enable generation unit 55-13 performs the BIP8 operation after the BIP8 operation by the BIP operation unit 55-12. A signal (write enable signal) for writing a value to the BIP8 operation value holding units 55-1 to 55-3 is generated.

Also, the BIP8 calculation result write enable generation unit 55-14 outputs the BIP at the timing of the J1 byte (J1TUPC8) indicating the head position of the BIP8 calculation range.
BI held in P8 operation value holding units 55-1 to 55-3
The P8 operation value is stored in the BIP8 operation result holding unit 55-4 to 55-
6 to generate a signal (write enable signal) for writing.

Further, BIP8 operation result selecting section 55-1
5 is for selecting a BIP8 operation result according to the detection signals from the decode circuits 55-7 to 55-9.
The BIP8 operation comparing section 55-16 detects a mismatch between the BIP8 operation result selected by the BIP8 operation result selecting section 55-15 and the payload data. Here, the exclusive OR circuit 55-16A and the OR are used. Circuit 55-
The function is realized using 16B.

Also, the BIP8 error detecting section 55-17
Outputs the output of the BIP8 operation comparing section 55-16 to the BIP
8 (BIP8ERRC8), the BIP8 operation comparing unit 55-16 always outputs 8
Since the bit comparison is performed, the BIP2 operation comparing unit 5
From 5-16, an invalid comparison result is output at a timing other than the B3 byte. Therefore, the BIP8 error detector 55-17 extracts and outputs only the correct BIP8 operation comparison result using the B3 byte timing signal (B3TPC8).

With the configuration described above, the BIP8
The error serial detection unit 55 always accurately and accurately checks BIP8
Error information can be detected and output. Next, FIG.
7 is a BIPPM serial processing unit 57 and B shown in FIG.
FIG. 87 is a block diagram showing a detailed configuration of the IPPM holding unit 58. As shown in FIG. 87, the BIPPM serial processing unit 57
FF circuit with enable 57-1, error count value initialization control unit (1-input inversion type AND circuit) 57-2,
BIP error detector (OR circuit) 57-3 and BIPP
The BIPPM holding unit 58 includes an M adding unit 57-4, and the BIPPM holding RAM 58-1.

Here, first, B of the BIPPM holding unit 58
The IPPM holding RAM 58-1 holds the BIP error count value and the BIPPM count value to be notified to the software. The IPPM holding RAM 58-1 receives the address signal (RPMADC6) from the read address of the count surface and the address signal (WPMADC).
7) is the write address on the count surface, and the timing signal (XBIPPMWE) supplied from the BIP holding RAM operation control unit 42 (see FIG. 54) of the timing generation unit 21.
NC8) and the address signal (BIPP)
MRAD) is the read address on the notification surface, R for BIP holding
The clock (BIPP) supplied from the AM operation control unit 42
MCK) operates as a RAM clock. Note that each of the above address signals (RPMADC6,
WPMADC7, BIPPMRAD) are P
It is supplied from the MRAM address control unit 59.

Thus, the above-mentioned RA for holding BIPPM is
In M58-1, for example, as shown in FIG. 89, the PM count value of BIP2 / 8 is read at the timing of detecting the B3 byte of TU3 and the V5 byte of TU2 / TU12, and the read request (μ- COM Rea
In d), the BIP2 / 8 PM is notified to the software while the TU3 B3 byte and the TU2 / TU12 V
At the detection timing of 5 bytes, the updated value of the PM count value of BIP2 / 8 is written.

By the way, the BIPPM counts the number of BIP errors generated between the PM reset signals, and transfers the counted value to the software during the next PM reset signal. It is necessary to perform error counting and notification of the count value, and hold the count value of the error and hold the count value for notification.

For this reason, the BIPPM holding RAM 58-1 of this embodiment has, as shown in FIG. 91, for example, the lower side [address 0 (00 _HEX ) to 63 (3F _HEX )] and the upper side [address 64 (40). _HEX )-127 (7F _HEX )]
The role is divided into a counting surface for counting BIP errors and a notification surface for notifying the count value of BIPPM (a holding surface for PM results).

The role of each surface is such that the count surface and the notification surface are alternately switched every time a PM reset signal is input. In this embodiment, for example, FIG.
0, as shown in FIG. 92, by switching the polarity of the MSB bit (PM) of the RAM address, such a face exchange is performed. As a result, the BIPPM holding RAM 58-1 holds 13-bit data, for example, as shown in FIG. 88, holds the BIP error count value in bit numbers 12 to 0 on the count surface, and Bit numbers 12 to 0
Holds the BIPPM count value.

With the above configuration, the BIPP of this embodiment
In the M serial processing unit 57, the BIPPM holding RAM 5
8-1, the BIPPM of the previous frame is sequentially read, and the BIPP for the current frame is
By updating M, the BIPPM is detected serially in common for each TU channel, and the BIPPM holding RAM 5 is detected.
8-1 to notify the software.

Next, FIG. 93 is a block diagram showing a detailed configuration of the PMRAM address control section 59 shown in FIG. 83. As shown in FIG. 93, the PMRAM address control section 59 of this embodiment comprises a count plane holding section. (FF with enable
Circuit) 59-1, inverting element 59-2 and FF circuit 59-
3 to 59-6. Here, the count surface holding unit 59-1 is provided with the above-described BIPPM holding RA.
A signal (PM count address signal) indicating which side of the upper surface or the lower surface of M58-1 is used as the count surface is generated. Each time a PM reset signal is input, the output signal is generated. By taking in the signal whose polarity is inverted by the inversion element 59-2, the roles of the lower surface and the upper surface can be switched.

For example, if the output signal of the count plane holding unit 59-1 is "0" and the lower plane is used as the count plane and the upper plane is used as the notification plane, and the PM reset signal is input, the inversion element In step 59-2, "1" obtained by inverting the polarity of the output signal of the count surface holding unit 59-1 is taken into the count surface holding unit 59-1. As a result, after the PM reset, the output signal of the count surface holding unit 59-1 becomes "1", the lower surface is used as the notification surface, and the upper surface is used as the count surface, and the surfaces are replaced.

The FF circuit 59-3 delays the phase of the PM count address signal generated by the count plane holding unit 59-1 by one master clock, and its output (RPMADC6) is used to hold the BIPPM holding R
AM58-1 and FEBEPM holding RAM 93 described later
(See FIG. 110 and FIG. 114).

Further, the FF circuit 59-4 is provided with the FF circuit described above.
The phase of the PM count address signal from the circuit 59-3 is further delayed by one master clock, and this output (RPMADC7) is
It is used as a write address of the count surface of the RAM 58-1 and the FEBEPM holding RAM 93.

The FF circuit 59-5 includes an inverting element 59.
-2 BIPPM notification address generated through C.-2 [7 bits obtained by adding the address signal (MBIPPMRAD: 6 bits) indicating the TU channel for BIPPM read supplied from the software side and the output signal (1 bit) of the inverting element 59-2 Is delayed by one master clock, and this output (BIPPM notification address) is used as a read address of the notification surface of the BIPPM holding RAM 58-1.

Further, the FF circuit 59-6 includes the inverting element 5
9-2. The FEBEPM notification address generated through 9-2 [T for reading the FEBEPM supplied from the software side.
Address signal (FEBEPMRA) indicating U channel
D: 6 bits) and the output signal (1 bit) of the inverting element 59-2, a 7-bit signal] is delayed by one master clock.
The EPM notification address) is the FEBEPM holding RAM 93
Is used as the read address of the notification surface of the notification.

With the above-described configuration, the PMRA
The M address control unit 59 includes a BIPPM holding RAM 58.
-1, The count plane and the notification plane of the FEBEPM holding RAM 93 are switched at the optimum timing, and an accurate B
It becomes possible to notify IPPM and FEBPM to the software side. Next, FIG. 94 is a block diagram showing a detailed configuration of the BIPPM count value initialization control unit 56 shown in FIG. 83. As shown in FIG.
The count value initialization control unit 56 includes the FF circuits 56-1, 5
6-2, 56-8, Timing control unit (1 input inversion type O
R circuit) 56-3, read / write signal generation unit [decode circuit (DEC)] 56-4, write enable generation unit (OR circuit) 56-5, BIPPM count value initialization request signal holding unit (FF circuit) 56- 6 and a BIPPM count value initialization request signal selector (selector) 56-7.

Here, the FF circuits 56-1 and 56-2 are
Each delays the phase of the PM reset signal by one clock of the master clock.
By delaying the phase of the PM reset signal in 6-1 and 56-2, the above-described PMRAM address control unit 59
Switching control by PM reset signal and book B
The timing with the BIPPM count value initialization control in the IPPM count value initialization control unit 56 is adjusted.

Further, the timing control section 56-3 outputs
For controlling the timing of the PPM count value initialization request signal. For example, when the signal (B3V5TPC7) indicating the timing of performing the BIPPM process is "1", the contents of the TU channel (TUADC7) to be processed are output. When the timing signal (B3V5TPC7) is “0”, the output signal is changed to 63 (“1111 in binary notation”).
11 ").

Further, the read / write signal generator 56-4
Is a read select signal of a BIPPM count value initialization request signal of 0 to 62 channels corresponding to an output signal of the timing control unit 56-3 of 0 to 62 (supplied to the BIPPM count value initialization request signal selection unit 56-7). Be done)
And a BIPPM count value initialization request signal holding unit 56-
6 is generated.
When the output signal of the timing control section 56-3 is 63, the read select signal and the write enable signal are not generated because it is not the timing for performing the BIPPM processing.

The write enable generation section 56-5
When the PM reset signal is input through the FF circuit 56-2, the write enable signals of channels 0 to 62 are all set to “1”, whereas when the PM reset signal is not input, the read / write signal The BIPPM count value initialization request signal holding unit 56-6 holds the BIPPM count value initialization request signal of the TU channel = 0 to 62ch. FF circuit 56-
The function is realized using 6A.

In the BIPPM count value initialization request signal holding section 56-6, for example, the FF circuit 56-
2, the write enable signal of all the channels is set to "1" by the PM reset signal from the FF circuits 56-
The data of 6A becomes "1". That is, "1" is simultaneously written to the FF circuit 56-6A by the PM reset signal on all channels.

When the B3 and V5 timing signals (B3V5TPC7) are input after the PM reset, the timing control unit 56-3 and the read / write signal generation unit 56-
The write enable signal of the channel for processing the BIPPM count value becomes “1” by the processing in the write enable generation unit 56-5 and the write enable signal generation unit 56-5. At this time, PM
Since the reset signal is not input, the FF circuit 56-
6A becomes "0", "0" is written into the FF circuit 56-6A of the channel to be processed, and the first B3V5 timing signal (B3V5T
The PC 7) releases the BIPPM count value initialization request signal.

That is, after the PM reset, the first B3V5
Only at the timing, the BIP error count value read from the count surface is initialized. Further, the BIPPM count value initialization request signal selector 56-7 includes a read / write signal generator 56-4.
The FF circuit 56-8 selectively reads out the BIPPM count initialization request signals of the channels 0 to 62 according to the output signals of the BIPPM count value initialization request signal selector 56-7. Is delayed by one master clock, and the BIPPM serial processing unit 5
This is for adjusting to the phase at which the reset processing at 7 is performed.

With the above configuration, the BIPP of this embodiment is
The M count value initialization controller 56 always resets the BIPPM count value initialization reset signal (BIPPMCTRRSTC) at an optimal timing based on the PM reset signal, the TU address signal, and the B3V5 timing signal.
Since 8) is generated and supplied to the BIPPM serial processing unit 57, the BIPPM serial processing unit 57 can always be operated accurately.

The book B3 / V constructed as described above will now be described.
The overall operation of the 5-byte termination processing unit 23 will be briefly described. First, for example, the TU data (V5 byte), TU data at the timings shown in FIGS.
Assuming that AD, SPEN, and J1V5TP are input, respectively, the BIP2 error serial detection unit 53 and the BIP2 holding unit 54 shown in FIG. 85 operate according to the timing shown in FIGS. 96 (a) to 96 (o). I do.

At this time, the PMRA shown in FIG.
The M address control unit 59 and the BIPPM count value initialization control unit 56 shown in FIG.
(Q) [or each part operates in accordance with the timing as shown in FIGS. 99 (a) to 99 (o)].
The BIPPM serial processing unit 57 and the BIPPM holding unit 58 shown in FIG. 7 operate according to the timings shown in, for example, FIGS. 97A to 97N, and the BIPPM processing of each TU channel is performed serially.

As described above, according to the POH termination processing unit 8 of the present embodiment, the BIP termination (operation) processing for the B3 byte and the BIP termination processing for the V5 byte are performed by the B3 / V5 byte termination common to each channel. Since the processing can be performed serially by the processing unit 23, it is not necessary to provide a circuit for BIP termination processing for B3 bytes and V5 bytes by the number of corresponding channels, thereby further reducing the device scale and reducing power consumption. be able to.

More specifically, the B3 / V5 byte termination processing unit 23 normally sets the P3 for each channel having a different signal size.
BIP error to be detected by OH termination processing (BIP error
8 errors and BIP2 errors) are commonly detected in each channel. For example, a BIP8 error detection circuit,
It is not necessary to provide BIP2 error detection circuits for the corresponding number of channels, respectively.
Power consumption can be significantly reduced.

Note that the above-described B3 / V5 byte termination processing unit 23 (see FIG. 84), as shown in FIG.
BIP2 serial operation processing units 53A, 53B, BIP8
Serial operation processing unit 55, BIPPM serial addition unit for TU3 (first BIPPM serial addition unit) 57C, TU
2 / TU12 BIPPM serial adder (second BIP
PM serial adder) 57D, 57E, BIP for TU3
PM holding unit (first storage unit) 58A, BIPPM holding unit for TU2 / TU12 (second storage unit) 58B, 58C and B
With the IPPM selection unit 57F, the BIP8 serial termination processing and the BIP2 serial termination
After independently obtaining the P error signal (BIPPM), each B
The IPPM may be selectively output.

As a result, B3 / V shown in FIG.
In the 5-byte termination processing unit 23, the BIPPM
This is very effective when the BIPPM holding units 58A to 58C for holding the BIPPM do not need to be commonly used for all signal sizes. This will greatly contribute to versatility.

(C5) C2 / V5 byte end processing unit 24
Next, FIG. 101 is a block diagram showing the configuration of the C2 / V5 byte termination processing unit 24 described above with reference to FIG.
As shown in FIG. 01, the C2 / V5 byte termination processing unit 24 of the present embodiment includes a UNEQ detection unit 71, an SL holding unit 72,
It comprises an SLM detecting section 73 and an alarm bit holding section 74.

Here, the UNEQ detector 71 serially detects that the C2 byte and V5 byte (signal label: SL) included in the multiplexed signal (VC4 data) are displayed as UNEQ, SL holder (U
NEQ data holding unit) 72
While storing each detection result in each channel,
The stored information is supplied to the UNEQ detection unit 71.

[0365] The SLM detection unit 73 determines that the C2 byte and the V5 byte included in the VC4 data are mismatched (S
LM) The detection is performed in a serial manner, and the alarm bit holding unit (SLM data holding unit) 74
Stores (holds) each detection result of the SLM detection unit 73 for each channel, and supplies the stored information to the SLM detection unit 73.

In other words, the C2 / V5 byte termination processing unit 24 uses the POH termination calculation processing unit 26 shown in FIG.
UNE of C2 byte and V5 byte included in C4 data
UNEQ serial termination processing unit 26C that performs serial termination processing of Q, SLM serial termination processing unit 2 that performs serial termination processing of SLM of C2 byte and V5 byte.
6D, and the storage unit 27 shown in FIG.
The storage units 27C and SLM that can store the operation result of the EQ serial termination processing unit 26C for each channel and supply storage information to the UNEQ serial termination processing unit 26C.
The operation result of the serial termination processing unit 26D is stored for each channel, and the SLM serial termination processing unit 26D is stored.
It is configured as a storage unit 27D that can supply storage information to D.

Thus, the above C2 / V5 byte termination processing unit 24 serially detects the UNEQ indication and SLM which should be normally detected by the POH termination processing for each TU channel having a different signal size, common to each channel. Can be. Therefore, specifically, as shown in FIG. 102, for example, as shown in FIG. 102, the above-mentioned UNEQ detection unit 71 serially detects whether or not the C2 byte is in the UNEQ display. V5UNEQ display serial detecting section 76 for serially detecting whether or not the signal has been set, a UNEQ display selecting section 77 for selecting a UNEQ display detection signal output from each of these detecting sections 75 and 76,
Based on the UNEQ display detection signal selected by the display selection unit 77, a UNEQ serial detection unit 78 that performs C2 byte and V5 byte UNEQ detection in serial is configured.

On the other hand, the above-described SLM detection unit 73
For example, as shown in FIG. 103, a C2 mismatch serial detector 81 that serially detects that a C2 byte has detected a mismatch, a V5 mismatch serial detector 82 that serially detects that a V5 byte has detected a mismatch, A mismatch selection unit 8 for selecting a mismatch detection signal output from each of these detection units 81 and 82
3, based on the mismatch detection signal selected by the mismatch selection unit 83, an SLM serial detection unit 84 that serially detects C2 byte and V5 byte SLMs.

The details of the above-described UNEQ detection unit 71, SL holding unit 72, SLM detection unit 73, and alarm bit holding unit 74 will be described below. FIG. 104 is a block diagram showing a detailed configuration of the UNEQ detection unit 71 and the SL holding unit 72. As shown in FIG.
Are the FF circuits with enable 71-1 to 71-3, UN
EQ protection stage number adder 71-4, decode circuit (DEC)
71-5 to 71-7, number-of-release-stages selection section (selector) 71
−8, SL range control unit (AND circuit) 71-9, UNE
Q display detection section (NOR circuit) 71-10, addition condition detection section (exclusive OR circuit) 71-11, UNEQ detection 4-stage detection section (1-input inversion type AND circuit) 71-12, UNE
Q release stage number detection unit (AND circuit) 71-13, state transition occurrence detection unit (OR circuit) 71-14, UNEQ protection stage number information reset unit (1-input inversion type AND circuit) 71-15
And a state transition unit (exclusive OR circuit) 71-16, and the SL holding unit 72
2-1.

Here, the SL holding RA of the SL holding section 72 is used.
M72-1 holds the protection stage number information of the UNEQ and the SLM, and stores the phase shift unit 3 of the timing generation unit 21.
The TU address signal (TUADC6) supplied from 2 '(see FIG. 44) is used as the read address, and the TUADC7 is used as the write address, and X supplied from the SL holding RAM operation control unit 39 (see FIG. 51) of the timing generation unit 21.
Write enable SLWENC8, RAM SLCK
It operates as a clock.

Note that this SL holding RAM 72-1 is
In the present embodiment, 6-bit data is held, and UNEQ protection stage number information is stored in storage areas of bit numbers 2 to 0, and SLM protection stage number information is stored in storage areas of bit numbers 5 and 3, respectively. . Further, in the UNEQ detector 71, the FF circuit 71-1 uses the timing signal (C2V5TPC7) indicating the position of the C2 and V5 bytes to read the data of the 2nd to 0th bits of the read data from the SL holding RAM 72-1. The FF circuit 71-2 holds the VC4 data (TUDT) in response to the timing signal (C2V5TPC7).
C7) to C2 and V5 bytes of data. The FF circuit 71-3 holds the timing signal (C2
V5TPC7) UNEQ which is the processing result of the previous frame
This holds the alarm bit.

The UNEQ protection stage number adder 71-4
Is the UNEQ read from the SL holding RAM 72-1.
The count value of the protection stage number information is incremented by one, and the decoding circuit ("3" detection unit) 71-5 outputs the read U number.
This is to detect that the count value of the NEQ protection stage number information is “3”, and the decoding circuit (“4” detection unit) 7
1-6 detects that the count value of the read UNEQ protection stage number information is “4”, and the decoding circuit (“5” detection unit) 71-7 outputs the read UNEQ protection stage number information.
It detects that the count value of the EQ protection stage number information is “5”.

Further, the number-of-canceled-stages selection section 71-8 outputs the UN
The number of EQ release stages is 6 for TU3 and 5 for TU2 / TU12
The output signal of the decode circuit 71-7 is selected by a C2 byte timing signal for performing the UNEQ detection in the TU3 because it is different from the stage, and the SL range control unit 71-9
In the C2 byte of TU3, all 8 bits are signal labels, whereas in the V5 byte of TU2 / TU12, 5 bits are used.
Since the 7th bit is a signal label and the SL range is different, no control is performed when the data held in the FF circuit 71-2 is the C2 byte,
The control is performed to mask the eighth bit and replace it with “0”.

Also, the UNEQ display detection section 71-10
This is to detect that all eight bits of the signal after the control by the SL range control unit 71-9 are "0", and the addition condition detection unit 71-11 detects that the UNEQ display has not been detected during the generation of the UNEQ. Or UNEQ while UNEQ is not occurring
This is to detect that the display has been detected.
The detection four-stage detection unit 71-12 detects that the addition condition is detected for three consecutive frames by the decoding circuit 71-5 while the UNEQ is not detected, and further detects the addition condition in the current frame. The UNEQ is detected by recognizing that the addition condition has been detected for four consecutive frames.

Further, UNEQ release stage number detecting section 71-1
3 detects that the addition condition is detected for 4 or 5 consecutive frames from the output signals of the decoding circuits 71-6 and 71-7 selected by the release stage number selection section 71-8, In addition, if the addition condition is detected, it is recognized that the addition condition is detected for five or six consecutive frames and the UNEQ is released.

Also, the state transition occurrence detecting section 71-14
It detects the occurrence of a condition for detecting or canceling the UNEQ, and resets the UNEQ protection stage number information reset unit 71-
15 indicates that the count value of the UNEQ protection stage number information is "0" when the addition condition detection unit 71-11 detects no addition condition and when the state transition occurrence detection unit 71-14 detects the occurrence of a state transition. The output signal (count value) is written to the SL holding RAM 72-1.

Further, when the state transition occurrence detecting section 71-14 detects the occurrence of the state transition, the state transition section 71-16 inverts the polarity of the UNEQ alarm bit, and
This is to generate a signal (WUNECC8) indicating a state transition during the occurrence of EQ / UNEQ is not generated, and this signal is written to the alarm bit holding unit 74.

With the above configuration, the UNEQ of this embodiment is
The detecting unit 71 sequentially reads out the UNEQ of the previous frame from the SL holding RAM 72-1 and updates the UNEQ for the current frame based on the read information, thereby serially detecting the UNEQ for each TU channel. Can be notified on the software side. Next, FIG. 105 is a block diagram showing a detailed configuration of the SLM detection unit 73 shown in FIG. 101. As shown in FIG.
The SLM detection unit 73 of the present embodiment is a
Circuits 73-1 to 73-4, SLM protection stage number adder 73-
5, decoding circuit (DEC) 73-6, 73-7, SL
Range control unit (AND circuit) 73-8, mismatch detection unit 73
-9, addition condition detection unit (exclusive OR circuit) 73-1
0, SLM detection 7-stage detection unit (AND circuit) 73-11,
SLM cancellation three-stage detection unit (AND circuit) 73-12, state transition occurrence detection unit (OR circuit) 73-13, SLM protection stage number information reset unit (OR circuit) 73-14, and state transition unit (exclusive OR circuit) ) 73-15.

Here, the FF circuit 73-1 is connected to C2, V5
Timing signal indicating byte position (C2V5TPC
In 7), the data of the fifth and third bits of the read data from the SL holding RAM 72-1 (SLM protection stage number information:
RSLDTC7), and the FF circuit 73
-2 is the timing signal (C2V5TPC7)
It holds data of C2 and V5 bytes from C4 data (TUDTC7).

The FF circuit 73-3 holds the signal label expected reception value (REXPSLC7) read from the expected reception value holding unit 48 (see FIGS. 60 and 70) using the timing signal (C2V5TPC7). The FF circuit 73-4 holds the SLM detection processing result data (RSLMC7) of the previous frame by the timing signal (C2V5TPC7).

Further, the SLM protection stage number adder 73-5
Is for incrementing the count value of the SLM protection stage number information read from the SL holding RAM 72-1 by +1. The decoding circuit ("6" detection unit) 73-6 reads the SLM.
This is to detect that the count value of the protection stage number information is “6”, and the decoding circuit (“2” detection unit) 73-7
Detects that the count value of the read SLM protection stage number information is “2”.

[0382] Also, the SL range control unit 73-8 sets the TU3
In the C2 byte of, all 8 bits are signal labels, whereas in the V5 byte of TU2 / TU12, the 5th to 7th bits are signal labels and SL ranges are different.
When the data held by the F circuit 73-3 is the C2 byte, the control is not performed. When the data is the V5 byte, the control is performed so that the first to fourth and eighth bits are masked and replaced with "0".

Further, the non-coincidence detecting section 73-9 detects a non-coincidence between the 8-bit received data after the mask control by the SL range control section 73-8 and the expected SL reception value. The condition detection unit 73-10 determines whether the received value of the SL matches the expected value of the SL during the occurrence of the SLM,
An addition condition is detected when the received value of SL and the expected value of SL do not match while LM is not occurring.

Also, the SLM detection seven-stage detection unit 73-11
Indicates that the decoding circuit 73-6 detects that the addition condition has been detected for six consecutive frames while the SLM has not been detected. If the addition condition is also detected for the current frame, the addition condition is detected for seven consecutive frames. Recognizing the detection, S
LM is detected, and the SLM release three-stage detection unit 73
-12, when the decoding circuit 73-7 detects that the addition condition is detected for two consecutive frames during the SLM detection, and further detects the addition condition in the current frame,
The SLM is released by recognizing that the addition condition has been detected for three consecutive frames.

Further, the state transition occurrence detecting section 73-13
Is for detecting that a condition for detecting or canceling the SLM has occurred. The SLM protection stage number information reset unit 73-
14 indicates that the count value of the SLM protection stage number information is "0" when the addition condition detection unit 73-10 does not detect the addition condition and when the state transition occurrence detection unit 73-13 detects the occurrence of the state transition. When the state transition occurrence detecting unit 73-13 detects the occurrence of the state transition, the state transition unit 73-15 inverts the polarity of the SLM alarm bit to indicate that the SLM is occurring. The state transition that has not occurred is performed. This output signal (WSLMC
8) is written to the alarm bit holding unit 74.

For this reason, the above-described alarm bit holding unit 7
Numeral 4 denotes a UNEQ alarm bit holding unit 74-1 and an SLM alarm bit holding unit 7 as shown in FIG.
4-2, Alarm Bit Write Address Control Unit (1 Input Inversion OR Circuit) 74-3, Write Enable Generation Unit [Decode Circuit (DEC)] 74-4, Alarm Bit Read Address Control Unit (1 Input Inversion OR Circuit) ) 74
-5, read select generation unit [decode circuit (DE
C)] 74-6, UNEQ select section (selector) 74
-7, SLM select section (selector) 74-8, line switching information read select generation section [decode circuit (DE
C)] 74-9, UNEQ line switching information selector (selector) 74-10, SLM line switching information selector (selector) 74-11, software notification read select generator (selector) 74-12, UNEQ software notification selection (Selector) 74-13 and an SLM software notification selector (selector) 74-14.

Here, UNEQ alarm bit holding section 7
4-1 holds the UNEQ alarm bits of the TU channel = 0 to 62 ch in the 63 FF circuits 74-1A, and the SLM alarm bit holding unit 74-2 includes:
The SLM alarm bits of the TU channel = 0 to 62 ch are held in 63 FF circuits 74-2A.

When the timing signal (C2V5TPC8) indicating the writing timing of the alarm bit is "1", the alarm bit write address control section 74-3 outputs the contents of the TU channel (TUADC8) to be processed. The timing signal (C2V5T)
When PC8) is "0", the output signal is controlled to 63 ("111111" in binary notation).

Further, write enable generation section 74-4
Is the alarm bit write address control unit 74
When the output signal of -3 is 0-62, a write enable signal for the FF circuits 74-1A and 74-2A for holding the alarm bits of 0-62ch is generated, and the UNEQ, S
Each alarm signal after LM processing (WUNECC8, WSL
MC8) is written to the FF circuits 74-1A and 74-2A which hold the processed TU channel alarm bits. Note that when the output signal of the alarm bit write address control unit 74-3 is 63, the write enable signal is not generated and no write enable signal is generated.

When the timing signal (C2V5TPC7) indicating the read timing of the alarm bit is "1", the alarm bit read address control section 74-5 outputs the contents of the TU channel (TUADC7) to be processed. The timing signal (C2V5T)
When PC7) is "0", the output signal is controlled to 63 ("111111" in binary notation).

Further, read select generation section 74-6
Is the alarm bit read address controller 74-
When the output signal of No. 5 is 0 to 62, a read select signal for reading the alarm bits of 0 to 62 ch is generated. When the output signal of the alarm bit read address control unit 74-5 is 63, the read select signal is not generated because the alarm bit read timing is not reached.

The UNEQ select section 74-7 uses the read select signal generated by the read select generation section 74-6 to generate the UNQ of the TU channel to be processed.
The SLM select unit 74-8 also reads the alarm bits of the read select generation unit 74-6.
TU to perform processing with read select signal generated in
This is to read the alarm bit of the SLM of the channel.

Further, the line switching information read select generation section 74-9 generates a read select signal for TU channels = 0 to 62ch, and the UNEQ line switching information selection section 74-10 outputs the line switching information. The read select signal generated by the read select generation unit 74-9 reads out the UNEQ alarm. The SLM line switching information selection unit 74-11 is also generated by the line switching information read selection generation unit 74-9. The read select signal is used to read an SLM alarm.

The software notification read select generation section 7
4-12 generates a read select signal for the TU channel = 0-62ch, and the UNEQ soft notification select section 74-13 generates the read select signal generated by the soft notification read select generation section 74-12. The SLM software notification selecting unit 74-14 also reads the UNEQ alarm and notifies the software of the UNEQ alarm. The SLM software notification selecting unit 74-14 also uses the read select signal generated by the software notification read select generating unit 74-12 to generate the SLM alarm. And notifies the software of the SLM alarm.

With the above configuration, the SLM detecting section 73 of this embodiment sequentially reads out the SLM alarm bits of the previous frame from the alarm bit holding section 74, and updates the SLM alarm for the current frame based on the read information. , It is possible to serially detect the SLM and notify the software of the SLM serially for each TU channel.

Hereinafter, the book B3 / V constructed as described above will be described.
The overall operation of the 5-byte termination processing unit 23 will be briefly described. For example, TU data (C2 byte), TUA at timings as shown in FIGS.
Assuming that D (“0”), SPEEN, and J1V5TP are input, respectively, it is assumed that the UNEQ detection unit 71 and the SL holding unit 72 shown in FIG. 104 and the SLM detection unit 7 shown in FIG.
107 and FIG. 107 (α), respectively.
Each part operates according to the timing shown in FIG.
Channel UNEQ termination processing (UNEQ display detection, U
NEQ software notification), SLM termination processing (SLM detection, SLM
LM software notification) is performed serially.

As described above, according to the POH termination processing unit 8 of this embodiment, the UNEK termination processing for the C2 byte and the UNEK termination processing for the V5 byte are performed by the C2 / V5 byte termination processing unit 24 common to each channel. (UNE
Q serial termination processing unit), so that the C2 byte and V5 byte
It is not necessary to equip the circuits for EQ termination processing with the number of corresponding channels, and in this case, it is possible to further reduce the device scale and reduce power consumption.

Specifically, the C2 / V5 byte termination processing section 24 normally displays the UNEQ display to be performed by the POH termination processing for each channel having a different signal size.
Since the NEQ detection unit 71 performs the same operation for each channel, it is not necessary to provide circuits for performing the UNEQ display by the number of corresponding channels, and the scale and power consumption of the apparatus can be greatly reduced.

According to the POH termination processing unit 8 of this embodiment, the SLM termination processing for the C2 byte and the SLM termination processing for the V5 byte are also performed by the C2 / V5 byte termination processing unit 24 (SLM serial Termination processing section),
It is possible to further reduce the size of the device and reduce power consumption.

More specifically, the C2 / V5 byte termination processing unit 24 normally performs SLM detection to be performed by POH termination processing for each channel having a different signal size for each channel, so that a circuit for SLM detection is provided. It is not necessary to provide as many channels as the number of corresponding channels, and the scale and power consumption of the device can be greatly reduced.

The C2 / V5 byte termination processing unit 24 (see FIG. 102) includes, for example, a C2UNEQ display serial detection unit 75A and V5UN as shown in FIG.
EQ display serial detection unit 76A, 76B, UN for TU3
EQ serial detector (first UNEQ serial detector) 7
8A, TU2 / TU12 UNEQ serial detection unit (second UNEQ serial detection unit) 78B, 78C, TU3 UNEQ data holding unit (first storage unit) 72A, TU2 /
UNEQ data holding unit for TU12 (second storage unit) 78
B, 78C and UNEQ data selector 77A, C2 byte UNEQ display processing, V5 byte UN
After performing the EQ display processing independently and serially, each UNEQ display may be selectively output.

As a result, C2 / V shown in FIG.
The 5-byte termination processing unit 24 can serially perform UNEQ display with a simple configuration, and there is no particular need to unify the UNEQ data holding units 72A to 72C for holding UNEQ displays for all signal sizes. This is very effective in such cases, and greatly contributes to flexibility and versatility in device construction.

The C2 / V5 byte termination processing unit 24 (see FIG. 103) includes a C2 mismatch serial detection unit 81A, a V5 mismatch serial detection unit 82A, 82B, and an SLM serial for TU3, as shown in FIG. Detector (first SLM serial detector) 84A, T
SLM serial detector for U2 / TU12 (second SLM serial detector) 84B, 84C, SLM data holding unit for TU3 (first storage unit) 84A, SL for TU2 / TU12
M data holding unit (second storage unit) 74B, 74C and SL
With the M data selection unit 83A, the SLM detection processing for the C2 byte and the SLM detection processing for the V5 byte are independently and serially performed, and then each SL is detected.
M data may be selectively output.

As a result, C2 / V shown in FIG.
The 5-byte termination processing unit 24 can perform SLM detection serially with a simple configuration, and there is no particular need to share the SLM data holding units 74A to 74C for holding SLM data with all signal sizes. This is very effective in such cases, and greatly contributes to flexibility and versatility in device construction.

(C6) G1 / V5 byte end processing unit 25
110 is a block diagram showing the configuration of the G1 / V5 byte termination processing unit 25 described above with reference to FIG.
As shown in FIG. 10, the G1 / V5 byte termination processing unit 25 of the present embodiment includes a FEBE detection unit 91, a FEBEPM serial processing unit 92, a FEBEPM holding unit 93, and a FEBEP.
An M count value initialization control unit 94, a FERF serial processing unit 95, a FERF holding unit 96, and an alarm bit holding unit 97 are provided.

Here, the FEBE detection section 91 performs FEBE detection of G1 byte and V5 byte included in the multiplexed signal (VC4 data) in a serial manner.
The EPM serial processing unit 92 includes the FEBE detection unit 91
In this case, an addition operation is performed serially on the FEBEPM count value based on the FEBE detection signal from the CPU.

Also, the FEBPM holding section 93 stores the FEB
Each addition result (count value) in the EPM serial processing unit 92 is stored for each channel, and the FEBEP
The FEBEPM count value initialization control unit 94 supplies the stored information to the M serial processing unit 92.
FEBEPM serial processing unit 9 in response to M reset signal
This is for initializing the result of addition at 2.

[0408] Further, the FERF serial processing unit 95
FE of G1 byte and V5 byte included in VC4 data
RF termination processing is performed serially.
The F holding unit (FERF data holding unit) 96
The F-serial processing unit 95 stores (holds) each processing result (FERF) for each channel, and supplies the stored information to the FERF serial processing unit 95. The alarm bit holding unit (FERF data holding unit) ) 9
Reference numeral 7 also stores (holds) each processing result (FERF alarm bit) in the FERF serial processing unit 95 for each channel, and supplies the stored information to the FERF serial processing unit 95.

In other words, the G1 / V5 byte termination processing unit 25 uses the VOH termination calculation processing unit 26 shown in FIG.
G1 byte and V5 byte FEB included in C4 data
FEB that performs E and FEBPM termination processing serially
E serial termination unit 26E, G1 byte and V5
FERF that performs serial termination of byte FERF
The storage unit 27 shown in FIG. 38 is configured as a serial termination processing unit 26F, and stores the calculation result of the FEBE serial termination processing unit 26E for each channel, and
The storage unit 27E that can supply the storage information to the BE serial termination processing unit 26E and the calculation result of the FERF serial termination processing unit 26F are stored for each channel, and the FER
It is configured as a storage unit 27F that can supply storage information to the F serial termination processing unit 26F.

[0410] Thus, the above-described G1 / V5 byte termination processing unit 25 normally detects FEBE, FEBE, which should be detected by POH termination processing for each TU channel having a different signal size.
FEBEPM and FERF can be serially detected for each channel. Therefore, specifically, as shown in FIG. 111, for example, the FEBE detecting section 91 described above performs a G1 FEBE serial detecting section 98 for serially detecting the FEBE of the G1 byte, the F5 of the V5 byte, and so on.
V5FEBE serial detector 99 for performing EBE detection serially and FEBE selector 10 for selecting a FEBE detection signal output from each of these detectors 98 and 99
FEBEPM serial processing unit 9
2 includes an FEBEPM serial adder 101 that serially performs an FEBEPM addition operation based on the FEBE detection signal selected by the FEBE selector 100.

[0411] On the other hand, the above-mentioned FERF serial processing section 95 serially detects that the G1 byte indicates FERF as shown in FIG. 112, for example.
FERF display serial detector 102, V5 byte is FE
V5FE that detects RF display serially
RF display serial detector 103, each of these detectors 10
FERF display detection selection unit 104 for selecting the FERF display detection signal output from the FERF
Based on the FERF display detection signal selected by the display detection selection unit 104, the FER of the G1 byte and the V5 byte
FERF serial detector 10 that performs F detection serially
6.

[0412] Hereinafter, the above-mentioned FEBE detector 91, FEB
EPM serial processing unit 92, FEBEPM holding unit 93,
The details of the FEBEPM count value initialization control unit 94, the FERF serial processing unit 95, the FERF holding unit 96, and the alarm bit holding unit 97 will be described. FIG. 113 shows F
FIG. 113 is a block diagram showing a detailed configuration of the EBE detection unit 91. As shown in FIG.
1 is an FF circuit 91-1 with enable, G1 byte F
An EBE detection unit 91-2 and a selector 91-3 as the FEBE selection unit 100 shown in FIG. 111 are provided.

Here, the FF circuit 91-1 has G1, V5
Timing signal (G1V5T) indicating byte timing
G1 and V1 from VC4 data (TUDTC7) by PC7)
The G1 byte FEBE detector 91-2 holds the first to fourth bit data of the 5 bytes. The G1 byte FEBE detector 91-2 stores the upper 4 bits of the G1 and V5 byte data held by the FF circuit 91-1.
It is to detect that the content of the bit is 1 to 8.

The selector 91-3 selects the FEBE in the G1 byte and the FEBE in the V5 byte with a V5 byte timing signal (V5TPC8).
This output signal (FEBE) allows the performance monitor (P
M) Processing is performed. In addition, FEB
In the range of E, the contents of the upper 4 bits are FE in the G1 byte.
BE code (see FIG. 19), and the content of the code is 1 to
At the time of 8, FEBE is detected. In the V5 byte, the third bit is a FEBE code (see FIG. 21).
When it is "1", FEBE is detected.

With the above configuration, the FEBE of the present embodiment
In the detection unit 91, for example, FIG.
TU data (G1 byte), TUAD (“0”), SPEN, J1V5TP at the timing shown in FIG.
Assuming that are input respectively, FIG.
Each part operates according to the timing shown in FIG. 120 (m), and the FEBE of G1 byte (see FIG. 120 (j)) and the FEBE of V5 byte [see FIG. 120 (k)]
And FEBE are serially output by the FEBEPM serial processing unit 92 in common for each channel.
Supply to

Next, FIG. 114 is a block diagram showing a detailed configuration of the above-mentioned FEBEPM serial processing unit 92 and FEBEPM holding unit 93. As shown in FIG. 114, first, the FEBEPM serial processing unit 92
F circuit 92-1 and FEBE count value initialization control unit (1
An input inversion type AND circuit) 92-2 and a FEBEPM adder 92-3;
Reference numeral 3 is provided with a FEBEPM holding RAM 93-1.

Here, the FEB of the FEBPM holding unit 93 is
The EPM holding RAM 93-1 holds the FEBE error count value and the FEBEPM count value to be notified to software. The FEBEPM counts the number of FEBEs generated between the PM reset signals, similarly to the BIPPM. In order to notify the count value to the software during the next PM reset signal,
It is necessary to count the error and notify the count value between the reset signals, and it is necessary to hold the count value of the error and hold the count value for notifying.

For this reason, the FEBEPM holding RAM 93-1 of this embodiment also has a lower plane [address 0 (00 _HEX )].
~ 63 (3F _HEX )] and the upper surface [address 64 (40
_HEX ) to 127 (7F _HEX )], and the FEBE count and count surface and FEBE
The role is shared with a notification surface (PM result holding surface) for notifying the PM count value. In this case,
By switching the polarity of the MSB bit (PM) of the RAM address, such a face exchange is performed.

Also, the FEBEPM holding RAM 93
-1, RPADC 6 is a read address on the count surface, WPMADC 7 is a write address on the count surface, X
FEBEPMWENC8 (see FIG. 55) is write-enabled, FEBEPMRAD is the read address on the notification surface,
FEBEPMCK (see FIG. 55) operates as a RAM clock.

Then, the FEBEPM holding RAM 9
3-1 holds 13-bit data in the present embodiment, holds the FEBE count value on the count surface,
On the notification side, the FEBEPM count value is held. on the other hand,
In the FEBEPM serial processing unit 92, the FF circuit 9
2-1 is a timing signal (G1V5TPC7) indicating the timing of the G1 and V5 bytes, which reads out the FEBE count value from the count surface of the FEBEPM holding RAM 93-1 and holds the data of the 12th to 0th bits. FEBE count value initialization control unit 9
2-2 resets the FEBE count value read out when performing the first FEBEPM serial processing after PM reset.

[0421] The FEBEPM adder 92-3 outputs the F
FE after control of EBE count value initialization control unit 92-2
The BE count value is incremented by +1 when FEBE is detected.
This output signal is stored in the FEBEPM holding RAM.
93-1. When FEBE is not detected, the FEBE count value after the control of the FEBE count value initialization control unit 92-2 is output as it is without performing the addition processing by the FEBEPM addition unit 92-3.

With the above configuration, the FEBE of the present embodiment
In the PM serial processing unit 92, the FEBE detection unit 91
TU data (G1 byte) and TU data at timings as shown in FIGS.
Assuming that AD (“0”), SPEEN, and J1V5TP are respectively input, FIG.
Each section operates according to the timing shown in (x).

That is, the FEBEPM serial processing section 9
2 sequentially reads out the FEBEPM (count value) of the previous frame from the above-mentioned FEBEPPM holding unit 93 and, based on the read information, executes the FEBEPM for the current frame.
FEBE termination processing and software notification of FEBERPM are serially performed in common for each TU channel.

FIG. 115 is a block diagram showing a detailed configuration of the FEBE count value initialization control section 94.
As shown in FIG. 15, the FEBE count value initialization control unit 94 of the present embodiment includes the FF circuits 94-1, 94-2, 94
−8, timing control section (one-input inversion type OR circuit) 94
-3, read / write signal generator [decode circuit (DE
C)] 94-4, Write enable generator (OR circuit)
94-5, a FEBPM count value initialization request signal holding section 94-6 and a FEBPM count value initialization request signal selection section (selector) 94-7.

Here, the FF circuit 94-1 delays the phase of the PM reset signal (FEBEPM count value initialization request signal) by one clock of the master clock. At -1, the phase of the PM reset signal subjected to the delay processing is further delayed by one master clock.

[0426] The timing control section 94-3 sets the FE
The timing control of the BEPM count value initialization request signal is performed. For example, when the timing signal (G1V5TPC7) indicating the timing of performing the FEBEPM processing is “1”, the TU channel (TUAD) for performing the processing is performed.
C7) and outputs the timing signal (G1V5
When TPC7) is "0", the output signal is controlled to 63 ("111111" in binary notation).

Further, the read / write signal generator 94-4
Indicates that the output signal of the timing control unit 94-3 is 0 to 0
At the time of 62, a read select signal and a write enable signal for the corresponding FEBPM count value initialization request signals of 0 to 62 ch are generated. Note that the output signal of the timing control unit 94-3 is 0 to
In the case of 62, since it is not the timing to perform the FEBEPM process, the generation of the read select signal and the write write enable signal is not performed.

Also, the write enable generation section 94-5
When the PM reset signal, which is the output signal of the FF circuit 94-2, is input (when the PM reset signal is "1"), the write enable signals of channels 0 to 62 are all set to "1", while the PM When the reset signal is not input, the output signal of the read / write signal generator 94-4 is output as it is.

Further, the FEBEPM count value initialization request signal holding section 94-6 includes 63 FF circuits 94-6A.
FE channel of TU channel = 0-62ch
The count value initialization request signal is held. The PM reset signal from the FF circuit 94-2 sets the write enable signals of all the channels to "1", and at the same time, sets the input data to the FF circuits 94-6A of all the channels to "1". It becomes 1 ", and the FEBPM count value initialization request signal is set at the same time for all channels.

If the G1V5 byte timing signal (G1V5TPC7) is input after PM reset,
Timing controller 94-3, read / write signal generator 9
4-4. The write enable signal of the channel for processing the FEBPM count value becomes "1" by the processing in the write enable generation unit 94-5. At this time, since the PM reset signal is not input, the FF circuit 94 -2 becomes "0" and the FF circuit 9
"0" is written to 4-6A.

[0431] That is, the FEBPM count value initialization request signal holding unit 94-6 releases the FEBPM count value initialization request signal at the first G1 and V5 byte timings after the PM reset.
FEBEPM only at the first G1, V5 timing
FE read from the count surface of the holding RAM 93-1
The BE count value can be initialized.

Further, the FEBPM count value initialization request signal selection section 94-7 includes a read / write signal generation section 94.
-4 output signal held in the FF circuit 94-6A.
The FF circuit 94-8 reads out the FEBEPM count value initialization request signal of the 62ch.
By delaying the phase of the output signal of the PM count value initialization request signal selection unit 94-7 by one master clock,
This is to match the phase of the reset processing.

With the above configuration, the FEBE of the present embodiment
The PM count value initialization control unit 94 is configured as shown in FIGS.
TU data (G1 byte), TUAD (“0”), SPEEN, J at the timing shown in FIG.
Assuming that 1V5TP is input, FIG.
1 (a) to 121 (q), each part operates according to the timing shown in FIG. 121 (q), and always initializes the FEBEPM count value at the optimal timing based on the PM reset signal, the TU address signal, and the G1V5 timing signal. Since the reset signal (FEBEPMCTRRSTC8) is generated and supplied to the FEBEPM serial processing unit 92, the FEBEPM serial processing unit 92 can always be operated accurately.

As described above, according to the POH termination processing unit 8 of the present embodiment, the FEBE and the FE
The BEPM termination processing and the FEBE and FEBEPM termination processing for the V5 byte are performed by G common to each channel.
Since this can be performed serially by the 1 / V5 byte termination processing unit 25, the device scale can be further reduced in this case.
Low power consumption can be achieved.

Specifically, the G1 / V5 byte termination processing unit 25 normally performs FEBE and FEB to be performed by POH termination processing for each channel having a different signal size.
The termination processing of the EPM is performed by the FEBE detection unit 91 and the FEBEP.
Since the M serial processing unit 92 performs the same processing for each channel, it is not necessary to provide FEBE and FEBEPM termination processing circuits for the corresponding number of channels, respectively, and further reduce the scale and power consumption of the apparatus. can do.

Next, FIG. 116 is a block diagram showing a detailed configuration of the above-mentioned FERF serial processing section 95 and FERF holding section 96. As shown in FIG. -1 to
95-3, FERF protection stage number adder 95-4, decode circuit (DEC) 95-5, FERF selector (selector)
95-6, Addition condition detection unit (exclusive OR circuit)
7, FERF detection release 10-stage detection unit (AND circuit) 95
-8, a FERF protection stage number information reset unit (one-input inversion type AND circuit) 95-9 and a state transition unit (exclusive OR circuit) 95-10.
6 is provided with a FERF holding RAM 96-1.

The FERF holding RAM 96-1 of the FERF holding section 96 holds FERF protection stage number information. The TU address signal (TUADC6) is a read address, the TUADC7 is a write address, and the XFER is
FWENC8 (generated by the FERF holding RAM operation control unit 40 shown in FIG. 52) is write-enabled.
The ERCK (see FIG. 52) operates as a RAM clock. The FERF holding RA
M96-1 is 4-bit data (F
ERF protection stage number information) is held.

On the other hand, in the FERF serial processing section 95, the FF circuit 95-1 uses the timing signal (G1V5TPC7) indicating the position of the G1 and V5 bytes to read the data (FERF protection stage number information) from the FERF holding RAM 96-1. And the FF circuit 95-2
Is the timing signal (G1V5TPC7), VC
From the 4 data (TUDTC7), the fifth and eighth bits of the G1 and V5 byte data are held.
The circuit 95-3 receives the timing signal (G1V5TPC).
7) holds the FERF processing result (FERF alarm bit: FERFC7) of the previous frame supplied from the alarm bit holding unit 97.

The FERF protection stage number adder 95-4
Is the FE read from the FERF holding RAM 96-1.
+1 is added to the count value of the RF protection stage number information,
The decode circuit (“9” detection unit) 95-5 detects that the read count value of the FERF protection stage number information is “9”.
The FERF bit for U3 processing and the FERF bit for TU2 / TU12 processing are selected.

Here, in the G1 byte of TU3, the fifth bit is the FERF bit (see FIG. 19), and in the V5 byte of TU2 / TU12, the least significant bit (eighth bit) is the FERF bit. Therefore, when FERF detection is performed with the V5 byte, the timing signal (V5TPC8) of the V5 byte is used to perform FERF detection.
The signal of the bit is selected as the FERF bit.

Further, addition condition detecting section 95-7 determines whether
When the FERF bit is “0” during RF generation,
This is to detect when the FERF bit is "1" while F is not occurring, and the FERF detection release 10-stage detection unit 95-8
Indicates that the addition condition is detected for nine consecutive frames by the above-described decoding circuit 95-5, and that the addition condition is detected for ten consecutive frames by detecting the addition condition also in the current frame. Recognizing that, FERF
Is detected or canceled.

The FERF protection stage number information reset unit 9
5-9, when the addition condition is not detected by the addition condition detection unit 95-7, and when the FERF detection release 10-stage detection unit 95
When the detection or release condition is detected at -8, the count value of the FERF protection stage number information is reset to 0. When the occurrence of the state transition is detected, the state transition unit 95-10 resets the FERF alarm bit. Reverse the polarity,
During FERF generation⇔ State transition is performed while FERF is not generated.

With the above configuration, the FERF of this embodiment
In this case, the serial processing unit 95 also executes, for example, FIG.
TU at timings as shown in FIGS.
Data (G1 byte), TUAD ("0"), SPEE
Assuming that N and J1V5TP are input respectively,
Each part operates according to the timings shown in FIGS. 122 (g) to 122 (s), respectively.

That is, the FERF serial processing section 95
Is a FERF holding unit 96 (RAM 96-for holding FERF).
1) To sequentially read the processing result (FERF protection stage number information, FERF alarm bit) of the previous frame from the alarm bit holding unit 97, and to perform FERF update processing (state transition processing) for the current frame based on the read information. Thus, the termination processing of the FERF is performed serially in common for each TU channel.

FIG. 117 is a block diagram showing a detailed configuration of the above-mentioned alarm bit holding section 97.
As shown in FIG.
Are an FERF alarm bit holding unit 97-1, an alarm bit write address control unit (one input inversion type OR circuit) 97-2, a write enable generation unit [decode circuit (DEC)] 97-3, and an alarm bit read address control unit (1 input inversion type OR circuit) 97-4, read select generation unit [decode circuit (DEC)] 97-5, F
ERF select section (selector) 97-6, software notification read select generation section [decode circuit (DEC)] 97-
7 and FERF software notification selector (selector) 97
-8.

Here, the FERF alarm bit holding unit 9
Reference numeral 7-1 denotes that 63 FF circuits 97-1A hold FERF alarm bits of the TU channel = 0 to 62ch, and the alarm bit write address control section 97-2 indicates the write timing of the alarm bit. When the timing signal (G1V5TPC8) is "1", the contents of the TU channel (TUADC8) to be processed are output, and the timing signal (G1V5TPC8) is output.
8) is "0", the output signal is 63 ("1" in binary notation).
11111 ").

The write enable generation section 97-3
The alarm bit write address control section 97-
2 is 0-62, the F for 0-62ch
Generate a write enable signal to the F circuit 97-1A,
The alarm signal (WFERFC8) after the FERF processing is written into the processed TU channel FF circuit 97-1A. When the output signal of the alarm bit write address control section 97-2 is 63, it is not the alarm bit write timing, and no write enable signal is generated.

When the alarm bit read timing signal (G1V5TPC7) is "1", the alarm bit read address control section 97-4 outputs the contents of the TU channel (TUADC7) to be processed.
When the timing signal (G1V5TPC7) is "0", the output signal is controlled to 63 ("111111" in binary notation).

[0449] Also, the read select generation unit 97-5
When the output signal of the alarm bit read address control section 97-4 is 0 to 62, a read select signal for reading alarm bits of 0 to 62 channels is generated. When the output signal of the alarm bit read address control section 97-4 is 63, the read select signal is not generated because the alarm bit read timing is not reached.

Further, the FERF select section 97-6 is
The FER of the TU channel to be processed is determined by the read select signal generated by the read select generation section 97-5.
F is to read the alarm bit of F, and the software notification read select generation unit 97-7 outputs the TU channel = 0.
The FERF software notification selection unit 97-8 generates a read select signal for selecting the alarm bits of the up to 62 ch.
It reads out the ERF alarm bit and notifies the software of the FERF alarm.

With the above-described configuration, the alarm bit holding section 97 of the present embodiment holds the FERF alarm bit in common for all channels and selectively outputs the same.
Software notification of the FERF alarm can be made serially. As described above, according to the POH termination processing unit 8 of the present embodiment, the FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte are performed by the G1 / V5 byte termination processing unit 25 common to each channel. Since the operation can be performed serially, it is possible to further reduce the size of the device and reduce power consumption.

More specifically, in the G1 / V5 byte termination processing unit 25, the FERF termination processing to be normally performed by the POH termination processing for each channel having a different signal size is shared by the FERF serial processing unit 95 for each channel. Therefore, it is not necessary to provide FERF termination processing circuits for the corresponding number of channels, and the scale and power consumption of the device can be significantly reduced.

The G1 / V5 byte termination processing unit 25 (see FIG. 111) includes, for example, a G1FEBE serial detection unit 98A and a V5FEB as shown in FIG.
E serial detectors 99A, 99B, FEBEP for TU3
M serial adder (first FEBPM serial adder)
101A, FE2 / PM12 FEBEPM serial adder (second FEBEPM serial adder) 93B, 79
3. FEBEPM holding unit for TU3 (first storage unit) 93
A, the FEBEPM holding units (second storage units) 93B and 93C for TU2 / TU12 and the FEBE selecting unit 77A are provided, and the G1 byte FEBE and FEBEPM termination processing and the V5 byte FEBE and FEBEPM termination processing are independent of each other. After performing serially, each FEB
The EPM may be selectively output to the software side.

As a result, G1 / V shown in FIG.
In the 5-byte termination processing unit 25, the termination processing of FEBE and FEBEPM can be performed serially with a simple configuration, and the FEBEPM holding unit 9 for holding FEBEPM is provided.
This is very effective when there is no particular need to share 3A to 93C for all signal sizes, and greatly contributes to flexibility and versatility in device construction.

The G1 / V5 byte termination processing unit 25 (see FIG. 112) includes, for example, a G1FERF display serial detection unit 102A and a V5F
ERF display serial detection units 103A, 103B, TU3
FERF serial detection unit (first FERF serial detection unit) 106A for TU2 / TU12 FERF serial detection unit (second SLM serial detection unit) 106B, 106
C, TU3 FERF data data holding unit (first storage unit) 96A, TU2 / TU12 FERF data data holding unit (second storage unit) 96B, 96C, and FERF data selection unit 104A are provided.
After performing ERF termination processing and FERUF termination processing for V5 bytes independently and serially, each F
The ERF data may be selectively output to the software.

As a result, G1 / V shown in FIG.
In the 5-byte termination processing unit 25, the FERF termination processing can be performed serially with a simple configuration, and the FERF data holding units 96A to 96C for holding FERF data need to be commonly used for all signal sizes. It is very effective when there is no such device, and greatly contributes to flexibility and versatility in device construction.

As described above, according to the POH termination processing section 8 of the present embodiment, POH termination processing can be performed in a serial manner without separating a multiplexed signal transmitted by the SDH transmission method for each channel. Therefore, it is not necessary to provide a circuit for POH termination processing for the number of channels multiplexed in the multiplexed signal, and the apparatus (circuit) scale and power consumption of the present apparatus can be greatly reduced.

(D) Others In the above embodiment, the transmission terminal station apparatus 306 has a TU
Although the present invention is configured as a pointer / POH termination processing device including the pointer processing unit 6 and the POH termination processing unit 8, the present invention is not limited to this, and includes only the POH termination processing unit 8 and is dedicated to POH termination processing. It may be configured as a device.

[0459]

As described in detail above, according to the POH termination processing device of the present invention, a multiplexed signal transmitted by the SDH transmission method is not separated for each channel, and the PO
Since the H terminal operation processing can be performed by the common POH terminal operation processing unit for each channel, it is not necessary to provide a circuit for the POH terminal operation processing by the number of channels multiplexed in the multiplexed signal. Therefore, the device (circuit) scale, power consumption, and the like of the present POH termination processing device can be significantly reduced (claims 1 to 24).

At this time, the storage information corresponding to each channel required for the POH termination arithmetic processing and the POH byte data to be processed in the multiplexed signal are transmitted at desired timing to the PO.
By supplying the POH termination processing unit to the H termination processing unit only when it is necessary, the power consumption of the POH termination processing device can be further reduced. 2).

By the way, in the above-described POH termination arithmetic processing section, the J1 byte termination processing and the J2 byte termination processing are serially performed by the J1 and J2 byte serial termination processing sections common to each channel, and the multi-signal multiplication is performed. Since the frame pattern detection is performed by one J1 and J2 byte serial termination processing unit, a circuit for performing the termination processing for the J1 byte and a circuit for performing the termination processing for the J2 byte are respectively provided.
There is no need to provide for the number of corresponding channels. Therefore, the present POH terminal processing device greatly contributes to a drastic reduction in device scale and a reduction in power consumption (claim 3).

At this time, if the above POH termination arithmetic processing unit is specifically configured as a J1 and J2 byte serial termination processing unit, the J1 and J2 byte serial termination processing unit can perform various operations such as LOM, CRC, and TIM. Since alarm information is obtained serially in common for each channel,
There is no need to separately prepare a circuit for M detection, a circuit for CRC detection, a circuit for TIM detection, and the like, and it is possible to further reduce the device scale and reduce power consumption.

Also, the above POH terminal calculation processing section is
If configured as a 3, V5 byte serial termination unit,
BIP termination (operation) processing for B3 bytes and BIP termination processing for V5 bytes
3, V5 bytes Since the serial termination processing can be performed serially, B3 bytes and V5 bytes
It is not necessary to provide IP termination processing circuits corresponding to the number of corresponding channels, and it is possible to further reduce the device scale and reduce power consumption.

Specifically, the B3, V5 byte serial termination processing unit normally detects a BIP error (B) to be detected by POH termination processing for each channel having a different signal size.
IP8 error and BIP2 error) are detected in common for each channel, so that it is not necessary to provide, for example, a BIP8 error detection circuit and a BIP2 error detection circuit for the number of corresponding channels, respectively. , Power consumption can be greatly reduced (claim 6).

The B3, V5 byte serial termination processing unit performs BIP error (BIPPM) by BIP8 serial termination processing and BIP2 serial termination processing, respectively.
Is obtained independently, and then each BIPPM is selectively output, whereby a BIP error can be serially detected with a simple configuration. Therefore, it is very effective when there is no particular need to use a common storage unit for holding the BIPPM for all signal sizes, and greatly contributes to flexibility and versatility in device construction ( Claim 7).

[0466] Furthermore, the above POH terminal operation processing unit is
If configured as an NEQ serial termination unit, this UN
Since the EQ serial termination processing unit can perform serially the UNEQ termination processing for the C2 byte and the UNEQ termination processing for the V5 byte in common for each channel, a circuit for the UNEQ termination processing for the C2 byte and the V5 byte is provided. There is no need to provide the same number of channels as the number of corresponding channels, and in this case, it is possible to further reduce the device scale and reduce power consumption.

More specifically, the UNEQ serial termination processing unit normally uses a POH for each channel having a different signal size.
Since the UNEQ display to be performed by the termination processing is performed in common for each channel, it is not necessary to provide a circuit for performing the UNEQ display by the number of the corresponding channels, and the scale and power consumption of the present apparatus are greatly reduced. (Claim 9).

The UNEQ serial termination processing section performs C2 byte UNEQ display processing and V5 byte UNEQ display processing.
If the EQ display processing is performed independently and serially, and then each UNEQ display is selectively output, the UNEQ display can be performed serially with a simple configuration. Therefore, it is very effective when there is no particular need to use a common storage unit for holding the UNEQ display for all signal sizes, greatly contributing to flexibility and versatility in device construction. (Claim 10).

Also, the above POH terminal operation processing unit is set to SL
If configured as an M serial termination processing unit, this SLM serial termination processing unit
Since termination processing and SLM termination processing for V5 bytes can be performed serially in common for each channel,
Also in this case, it is possible to further reduce the device scale and reduce power consumption (claim 11).

More specifically, in this SLM serial termination processing unit, SLM detection which should be performed by POH termination processing for each channel having a different signal size is commonly performed for each channel, so that circuits for SLM detection are respectively provided. ,
There is no need to provide as many channels as the number of corresponding channels, and the scale and power consumption of the device can be significantly reduced.

Note that this SLM serial termination processing unit
C2 byte SLM detection processing and V5 byte SLM detection processing are performed independently and serially, respectively.
If the LM is selectively output, the SLM can be configured with a simple configuration.
Detection can be performed serially. Therefore, SLM
This is very effective when it is not particularly necessary to use a common storage unit for all signal sizes, and greatly contributes to flexibility and versatility in device construction. ).

[0472] Further, the above POH terminal calculation processing unit is
If configured as an EBE serial termination processing unit, this FE
The BE serial termination processing unit can perform the FEBE and FEBEPM termination processing on the G1 byte and the FEBE and FEBEPM termination processing on the V5 byte in a serial manner in common for each channel. And power consumption can be reduced (claim 14).

[0473] Specifically, the FEBE serial termination processing unit normally uses a POH for each channel having a different signal size.
FEBE and FEBEPM to be performed by termination processing
Is performed in common for each channel, so that FEB
E and FEBEPM termination circuits, respectively,
There is no need to provide as many channels as the number of corresponding channels, and the scale and power consumption of the device can be significantly reduced.

The FEBE serial termination processing unit detects the FEBE for the G1 byte and performs FEBE detection.
The PM addition operation, the FEBE detection for the V5 byte, and the FEBEPM addition operation are performed independently and serially, and then each FEBEPM is selected and output. Can be done at Therefore, FEBE
This is very effective when there is no particular need to use a common storage unit for holding PMs for all signal sizes, greatly contributing to flexibility and versatility in device construction. 16).

[0475] Further, the above POH terminal calculation processing unit is
If configured as an ERF serial termination processor, this FE
The RF serial termination processing unit can perform serial termination of the FERF termination processing for the G1 byte and the FERF termination processing for the V5 byte in common to each channel.
Low power consumption can be achieved (claim 17).

[0476] Specifically, in this FERF serial termination processing unit, normally, the POH for each channel having a different signal size is used.
Since the termination processing of the FERF to be performed by the termination processing is performed in common for each channel, it is not necessary to provide the circuits for the FERF termination processing by the number of the corresponding channels, respectively, and further, the scale and power consumption of the present apparatus are greatly reduced. It can be reduced (claim 18).

The FERF serial termination processing unit detects and displays the FERF for the G1 byte,
If the FERF detection and display processing for the V5 byte is performed independently and serially, and each FERF is selectively output, the FERF display can be performed serially with a simple configuration, and the FERF is retained. This is very effective when there is no particular need to use a common storage unit, and greatly contributes to flexibility and versatility in device construction (claim 19).

Further, according to the POH termination processing device of the present invention, the POH timing signal serial generation unit is provided, so that the POH timing signal required for the POH termination operation processing unit is serially generated in common for each channel. Therefore, it is not necessary to provide a circuit for generating the POH timing signal by the number of corresponding channels, and the scale and power consumption of the device can be significantly reduced (claim 20).

More specifically, the POH timing signal serial generation section performs the SPE start position (J1
, V5 bytes) is sequentially updated while being initialized, added, and updated while being stored in the storage unit for each channel, so that various types of data necessary for processing in the POH termination operation processing unit are obtained. Since the POH timing signal is serially generated in common for each channel, the above processing can be realized with an extremely simple configuration.

According to the POH termination processing device of the present invention, an address creating section for generating address information for identifying each channel of a multiplex signal is provided, so that an address for the storage section is provided. Since the information can be generated by the common address generator for each channel, it is not necessary to provide the circuits for generating the address information by the number of the corresponding channels, respectively.
It is not necessary to perform a special process for identifying each channel in the POH termination arithmetic processing unit. Therefore, the scale and power consumption of the present apparatus can be further greatly reduced (claim 22).

Further, according to the POH termination processing device of the present invention, termination processing on J1 and J2 bytes for detecting a multi-frame pattern of a multiplex signal, B3 and V5 bytes for obtaining BIP (BIPPM) from a multiplex signal Termination processing, UNEQ, C for obtaining SLM
2, V5 byte termination processing, FEBE (FEBE
Since the termination processing of G1 and V5 bytes for obtaining PM) and the termination processing of G1 and V5 bytes for obtaining FERF can be performed serially in common for each channel, the above processing is performed. It is not necessary to provide the same number of circuits as the number of corresponding channels, so that the device scale and power consumption of the present device can be greatly reduced.

According to the pointer / POH termination processing device of the present invention, both pointer processing and POH termination processing for a multiplexed signal transmitted by the SDH transmission method are performed.
Since each of the multiplexed signals can be performed serially without demultiplexing for each channel, the present apparatus can be realized with a minimum scale and a minimum power consumption.
5).

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram for explaining a hierarchy structure in the SDH transmission scheme.

FIG. 3 is a diagram showing an STM-1 frame format in the SDH transmission method.

FIG. 4 is a diagram for explaining the accommodation position of VC4 accommodated in an STM-1 frame.

FIG. 5 is a diagram showing a frame format of TU3 in the SDH transmission scheme.

FIG. 6 is a diagram for explaining the accommodation position of VC3 accommodated in a TU3 frame.

FIG. 7 is a diagram showing a frame format of TU2 in the SDH transmission method.

FIG. 8 is a diagram for explaining a housing position of a VC3 housed in a TU2 frame.

FIG. 9 shows a frame of TU12 in the SDH transmission system.
It is a figure showing a format.

FIG. 10 is a diagram for explaining a housing position of a VC3 housed in a TU12 frame.

FIG. 11 is a diagram for explaining a method of detecting a mismatch alarm in the SDH transmission method.

FIG. 12 is a diagram showing a format of J1 and J2 bytes (path trace signal) in the SDH transmission method.

FIG. 13 is a diagram for explaining CRC calculation processing in the SDH transmission scheme.

FIG. 14 is a diagram illustrating a format of B3 bytes in the SDH transmission method.

FIGS. 15A and 15B are diagrams for explaining a BIP8 calculation process in the SDH transmission scheme.

FIG. 16 is a diagram for describing BIP8 calculation processing in the SDH transmission method.

FIG. 17 is a diagram illustrating a format of C2 bytes in the SDH transmission method.

FIG. 18 is a diagram for explaining a value (mapping code) set in the C2 byte in the SDH transmission method.

FIG. 19 is a diagram illustrating a G1 byte format in the SDH transmission scheme.

FIG. 20 is a diagram illustrating a value (FEBE code) set in the G1 byte in the SDH transmission scheme.

FIG. 21 is a diagram illustrating a format of V5 bytes in the SDH transmission method.

FIGS. 22A and 22B are diagrams for explaining BIP2 calculation processing in the SDH transmission scheme.

FIG. 23 is a diagram for describing BIP2 calculation processing in the SDH transmission method.

FIG. 24 is a diagram for explaining a value (FEBE code) set in a V5 byte in the SDH transmission method.

FIG. 25 is a diagram for explaining a value (mapping code) set in the V5 byte in the SDH transmission method.

FIGS. 26A to 26F are time charts for explaining a performance monitor (BIPPM) process in the SDH transmission method.

FIGS. 27A to 27G are time charts for explaining a performance monitor (FEBEPM) process in the SDH transmission method.

FIG. 28 is a block diagram illustrating an example of an SDH transmission network.

FIG. 29 is a block diagram illustrating a configuration of a main part of a transmission terminal apparatus to which the POH termination processing device according to an embodiment of the present invention is applied.

FIG. 30 shows a TU pointer processing unit, P
FIG. 3 is a block diagram illustrating a configuration of a transmission terminal apparatus focusing on an OH termination processing unit.

FIG. 31 is a block diagram illustrating a configuration of a TU pointer serial processing unit and a TU pointer timing generation unit according to the present embodiment.

FIG. 32 is a block diagram illustrating a detailed configuration of an address generation unit according to the present embodiment.

FIG. 33 is a diagram illustrating an example of an address conversion table for explaining the operation of the address generation unit according to the present embodiment.

FIG. 34 is a diagram for explaining the operation of the address conversion unit of the present embodiment.

FIG. 35 shows the SPE first byte (J1 / V5) of the present embodiment.
FIG. 4 is a block diagram illustrating a configuration of a pointer processing unit focusing on a (byte) recognition function part.

FIG. 36 is a block diagram illustrating a configuration of a TU pointer processing unit focusing on a signal size recognition function part according to the present embodiment.

FIG. 37 is a block diagram illustrating a configuration of a POH termination processing unit according to the present embodiment.

FIG. 38 is a block diagram illustrating a basic configuration of each termination processing unit of the present embodiment.

FIG. 39 is a block diagram illustrating a basic configuration of each termination processing unit of the present embodiment.

FIGS. 40 (a) to (t) are time charts for explaining the basic operation of each termination processing unit of the present embodiment.

FIG. 41 is a block diagram illustrating a configuration of a timing generation unit according to the present embodiment.

FIGS. 42 (a) to (q) are time charts for explaining the operation of the timing generator of the present embodiment.

FIG. 43 is a block diagram illustrating a detailed configuration of a timing generation unit according to the present embodiment.

FIG. 44 is a block diagram illustrating a detailed configuration of a phase shift unit according to the present embodiment.

FIG. 45 is a block diagram illustrating a detailed configuration of an overhead counter RAM holding unit and an overhead counter serial processing unit according to the present embodiment.

FIG. 46 is a block diagram showing a detailed configuration of a POH timing signal generator of the present embodiment.

FIG. 47 is a block diagram showing a detailed configuration of a POH timing signal shift unit of the present embodiment.

FIG. 48 is a block diagram showing a detailed configuration of a LOM holding RAM operation control unit of the present embodiment.

FIG. 49 is a block diagram showing a detailed configuration of a FRNO holding RAM operation control unit of the present embodiment.

FIG. 50 is a block diagram illustrating a detailed configuration of a BIP2 holding RAM operation control unit according to the present embodiment.

FIG. 51 is a block diagram illustrating a detailed configuration of an SL holding RAM operation control unit according to the embodiment;

FIG. 52 is a block diagram illustrating a detailed configuration of a FERF holding RAM operation control unit according to the embodiment;

FIG. 53 is a block diagram illustrating a detailed configuration of a RAM for controlling reception of expected values according to the embodiment;

FIG. 54 is a block diagram illustrating a detailed configuration of a BIPPM holding RAM operation control unit according to the embodiment;

FIG. 55 is a block diagram showing a detailed configuration of a FEBEPM holding RAM operation control unit of the present embodiment.

FIGS. 56 (a) to 56 (h) are time charts for explaining the operation of the timing generator of the present embodiment.

FIGS. 57 (a) to 57 (p) are time charts for explaining the operation of the timing generator of the present embodiment.

FIGS. 58 (a) to (t) are time charts for explaining the operation of the timing generator of the present embodiment.

FIGS. 59 (a) to 59 (f) are time charts for explaining the operation of the timing generation unit of the present embodiment.

FIG. 60 is a block diagram illustrating a configuration of a J1 / J2 byte termination processing unit according to the present embodiment.

FIG. 61 is a block diagram illustrating a detailed configuration of a multi-frame pattern serial detection unit and a LOM holding unit according to the embodiment.

FIG. 62 is a block diagram illustrating a detailed configuration of a multi-frame number serial control unit and a FRNO holding unit according to the present embodiment.

FIG. 63 is a diagram showing a format example of a FRNO holding RAM of the present embodiment.

FIG. 64 is a diagram for explaining the operation timing of the FRNO holding RAM of the present embodiment.

FIG. 65 is a diagram illustrating an example of a relationship between information of a FRNO holding RAM and a frame number according to the embodiment;

FIG. 66 is a block diagram illustrating a detailed configuration of a LOM serial detection unit according to the present embodiment.

FIG. 67 is a block diagram illustrating a detailed configuration of a CRC serial detection unit according to the present embodiment.

FIG. 68 is a block diagram showing another detailed configuration of the CRC serial detector of the present embodiment.

FIG. 69 is a block diagram showing another detailed configuration of the TIM serial detector of the embodiment.

FIG. 70 is a block diagram illustrating a detailed configuration of a reception expectation value holding unit according to the present embodiment.

FIG. 71 is a diagram showing an example of a data format of an EXP1 holding RAM of the present embodiment.

FIG. 72 is a diagram showing an example of a data format of an EXP2 holding RAM of the present embodiment.

FIG. 73 is a diagram for explaining the operation timing of the expected reception value holding unit according to the embodiment;

FIG. 74 is an RA for holding EXP1 and EXP2 of the present embodiment;
FIG. 6 is a diagram illustrating an example of an address content of M.

FIG. 75 is an RA for holding EXP1 and EXP2 of the present embodiment.
FIG. 4 is a diagram illustrating an example of a relationship between an M address, a frame number, and a TU channel.

FIG. 76 is an RA for holding EXP1 and EXP2 of the present embodiment.
It is a figure for explaining switching control of M.

FIG. 77 is a block diagram illustrating a detailed configuration of an alarm bit holding unit according to the embodiment.

FIGS. 78 (a) to (h) each show J1 of the present embodiment.
6 is a time chart for explaining the operation of the / J2 byte end processing unit.

FIGS. 79 (a) to (l) each show J1 of the present embodiment.
6 is a time chart for explaining the operation of the / J2 byte end processing unit.

FIGS. 80A to 80N are J1 of the present embodiment, respectively.
6 is a time chart for explaining the operation of the / J2 byte end processing unit.

81 (a) to (k) each show J1 of the present embodiment.
6 is a time chart for explaining the operation of the / J2 byte end processing unit.

82 (a) to (n) are J1 of the present embodiment, respectively.
6 is a time chart for explaining the operation of the / J2 byte end processing unit.

FIG. 83 is a block diagram illustrating a configuration of a B3 / V5 byte termination processing unit according to the present embodiment.

FIG. 84 is a block diagram illustrating a configuration of a B3 / V5 byte termination processing unit of the present embodiment.

FIG. 85 is a block diagram illustrating a detailed configuration of a BIP error serial detection unit and a BIP2 holding unit according to the embodiment.

FIG. 86 is a block diagram illustrating a detailed configuration of a BIP8 error serial detection unit according to the embodiment.

FIG. 87 is a block diagram illustrating a detailed configuration of a BIPPM serial processing unit and a BIPPM holding unit according to the embodiment.

FIG. 88 is a diagram illustrating a data format example of a BIPPM holding RAM according to the present embodiment.

FIG. 89 is a diagram for explaining the operation timing of the BIPPM holding RAM of the present embodiment.

FIG. 90 is a diagram illustrating an example of address contents of a BIPPM holding RAM according to the embodiment;

FIG. 91 is an RA for holding EXP1 and EXP2 of the present embodiment;
It is a figure for explaining switching control of M.

FIG. 92 is an RA for holding EXP1 and EXP2 of the present embodiment.
It is a figure for explaining switching control of M.

FIG. 93 is a block diagram showing a detailed configuration of a PMRAM address control unit of the embodiment.

FIG. 94 is a block diagram illustrating a detailed configuration of a BIPPM count value initialization control unit according to the embodiment.

FIGS. 95 (a) to (f) each show B3 of the present embodiment.
6 is a time chart for explaining the operation of a / V5 byte end processing unit.

FIG. 96 (a) to (o) each show B3 of the present embodiment.
6 is a time chart for explaining the operation of a / V5 byte end processing unit.

97 (a) to (n) are B3 of this embodiment, respectively.
6 is a time chart for explaining the operation of a / V5 byte end processing unit.

FIG. 98 (a) to (q) are B3 of the present embodiment, respectively.
6 is a time chart for explaining the operation of a / V5 byte end processing unit.

FIG. 99 (a) to (o) are B3 of the present embodiment, respectively.
6 is a time chart for explaining the operation of a / V5 byte end processing unit.

FIG. 100 is a block diagram showing another configuration of the B3 / V5 byte termination processing unit of the embodiment.

FIG. 101 is a block diagram illustrating a configuration of a C2 / V5 byte termination processing unit according to the present embodiment.

FIG. 102 is a block diagram illustrating a configuration of a C2 / V5 byte termination processing unit according to the present embodiment.

FIG. 103 is a block diagram illustrating a configuration of a C2 / V5 byte termination processing unit according to the present embodiment.

FIG. 104 is a block diagram illustrating a detailed configuration of a UNEQ serial detection unit according to the embodiment.

FIG. 105 is a block diagram illustrating a detailed configuration of an SLM serial detection unit according to the embodiment.

FIG. 106 is a block diagram illustrating a detailed configuration of an alarm bit holding unit according to the present embodiment.

FIGS. 107 (a) to (z) and (α) are time charts for explaining the operation of the C2 / V5 byte end processing unit of the present embodiment.

FIG. 108 is a block diagram illustrating another configuration of the C2 / V5 byte termination processing unit of the present embodiment.

FIG. 109 is a block diagram illustrating another configuration of the C2 / V5 byte termination processing unit of the present embodiment.

FIG. 110 is a block diagram illustrating a configuration of a G1 / V5 byte termination processing unit according to the present embodiment.

FIG. 111 is a block diagram illustrating a configuration of a G1 / V5 byte termination processing unit according to the present embodiment.

FIG. 112 is a block diagram illustrating a configuration of a G1 / V5 byte termination processing unit according to the present embodiment.

FIG. 113 is a block diagram illustrating a detailed configuration of a FEBE detection unit according to the present embodiment.

FIG. 114 is a block diagram illustrating a detailed configuration of a FEBEPM serial processing unit and a FEBEPM holding unit according to the embodiment;

FIG. 115 is a block diagram illustrating a detailed configuration of a FEBEPM count value initialization control unit according to the embodiment.

FIG. 116 is a block diagram illustrating a detailed configuration of a FERF serial processing unit and a FERF holding unit according to the embodiment.

FIG. 117 is a block diagram illustrating a detailed configuration of a FERF alarm bit holding unit according to the embodiment.

FIG. 118 is a block diagram illustrating another configuration of the G1 / V5 byte termination processing unit of the present embodiment.

FIG. 119 is a block diagram showing another configuration of the G1 / V5 byte termination processing unit of the present embodiment.

120 (a) to 120 (x) each show G in the present embodiment.
6 is a time chart for explaining the operation of a 1 / V5 byte end processing unit.

FIGS. 121 (a) to (q) each show G in the present embodiment.
6 is a time chart for explaining the operation of a 1 / V5 byte end processing unit.

FIGS. 122 (a) to (s) each show G in the present embodiment;
6 is a time chart for explaining the operation of a 1 / V5 byte end processing unit.

[Explanation of symbols]

1, 26 POH termination operation processing unit 2, 27, 27A to 27F storage unit 3A active system 3B standby system 4 SOH termination processing unit 5 AU pointer processing unit 6 TU pointer processing unit 7 ES unit 8 POH termination processing unit (POH termination processing) 9) Path switch alarm insertion unit 10 Microcomputer (μ-COM) 11 Cross-connect device (XC) 15 Address counter for TUG3 16 Address counter for TUG2 17 Address counter for TU12 18, 19, 99 ', 128, 129 AND circuit (AND circuit) 20 Address conversion unit 21 Timing generation unit 22 J1 / J2 byte termination processing unit 23 B3 / V5 byte termination processing unit 24 C2 / V5 byte termination processing unit (UNEQ / SLM)
Serial termination processing unit) 25 G1 / V5 byte termination processing unit (FEBE / FER
F serial termination processing unit) 26A J1, J2 byte serial termination processing unit 26B B3, V5 byte serial termination processing unit 26C UNEQ serial termination processing unit 26D SLM serial termination processing unit 26E FEBE serial termination processing unit 26F FERF serial termination processing unit 26- 1 serial processing unit 26-2, 32, 33-1, 35-1 to 35-8, 36
-2-40-2, 41-8, 41-9, 42-2, 43
−2, 44-1 to 44-3, 45-1 to 45-3, 46
-1, 46-2, 46-4, 46-5, 47-1 to 47
-3,48-9,48-10,49-1 to 49-4,5
2A to 52C, 53-1, 53-2, 56-1, 56-
2,56-6A, 56-8,57-1,59-3-59
-6,71-1 to 71-3,73-1 to 73-4,91
-1,92-1,94-1,94-2,94-8,95
-1 to 95-3 FF (flip-flop) circuit 27-1 RAM data holding unit 27-2 FF data holding unit 28 SPE count holding unit 28 'Overhead counter (OHCTR) RAM holding unit 28'-1 Overhead counter RAM 28' -2,36-4 to 40-4,42-4,43-
4,59-2 Inverting element 29 SPE count value initialization unit 30 SPE count value addition control unit 31 Timing signal generation processing unit 32 'Phase shift unit 33 Overhead counter serial processing unit 33-2 0 byte control unit (1 input inversion type) 33-3 TU3 detection section (1 input inversion type AND circuit) 33-4 TU2 detection section (1 input inversion type AND circuit) 33-5 TU12 detection section (all input inversion type AND circuit) 33-6 Maximum value Setting unit 33-7, 48-6A to 48-6C, 48-14A to 4
8-14C AND circuit (logical product circuit) 33-8, 33-11, 48-8D, 48-14D, 5
3-6B, 55-16B, 91-2A OR circuit (OR circuit) 33-9 Maximum value detection unit 33-10, 53-6A, 55-16A, 91-2B
Exclusive OR circuit 33-12 Count value adder 33-13 Count value initialization controller (1-input inversion type A
ND circuit) 34 POH timing signal generator 34-1 to 34-6, 44-6 to 44-8, 45-5
45-6, 47-15, 49-10, 49-11, 55
-7 to 55-9, 71-5 to 71-7, 73-6, 73
-7,95-5 Decoding circuit (DEC) 34-7 TU3 detector (1 input inversion type AND circuit) 34-8 TU2 detector (1 input inversion type AND circuit) 34-9 TU12 detection unit (all input inversion type) AND circuit 34-10 J1 condition detector (AND circuit) 34-11 B3 condition detector (AND circuit) 34-12 C2 condition detector (AND circuit) 34-13 G1 condition detector (AND circuit) 34-14 V5 condition detector (1 input inversion type AND circuit) 34-15 TU2J2 condition detector (AND circuit) 34-16 TU12J2 condition detector (AND circuit) 34-17 J2 condition detector (OR circuit) 34-18 J1 timing Signal generator (AND circuit) 34-19 B3 timing signal generator (AND circuit) 34-20 C2 timing signal generator (AND circuit) 34-21 G1 timing signal generator (AND circuit) 34-22 V5 timing signal generator (AND circuit) 34-23 J2 timing signal generator (AND circuit) 34-24 J1J2 timing signal generator (OR circuit) 34- 25 B3V5 timing signal generation unit (OR circuit) 34-26 C2V5 timing signal generation unit (OR circuit) 34-27 G1V5 timing signal generation unit (OR circuit) 35 POH timing signal shift unit 36 LOM holding RAM operation control unit 36- 1 to 40-1, 42-1, 43-1 Operation clock mask generator (OR circuit) 36-3 to 40-3, 42-3, 43-3 Clock masker (1 input inversion type OR circuit) 37 FRNO RAM operation control unit for holding 38 BRAM operation control unit for BIP2 holding 39 SL holding RA Operation control unit 40 RAM operation control unit for holding FERF 41 RAM operation control unit for holding expected expected value 41-1 Expected value read request detection unit (OR circuit) 41-2 EXP1 expected value read operation clock mask generation unit (1 input) 41-3 EXP2 expected value read operation clock mask generator (AND circuit) 41-4 EXP1 expected value setting access operation Clock mask generator (1-input inverted AND circuit) 41-5 EXP2 expected value setting access Operation clock mask generation unit (AND circuit) 41-6 EXP1 clock mask generation unit (OR circuit) 41-7 EXP2 clock mask generation unit (OR circuit) 41-10 EXP1 clock mask generation unit (1-input inversion type OR circuit) 41- 11 EXP2 Clock Mask Unit (1 Input Inverting OR Circuit) 2 EXP1 write enable generation unit (1 input inverting type NAND circuit) 41-13 EXP2 write enable generator (NAN
D circuit) 42 RAM operation control unit for BIPPM holding 43 RAM operation control unit for FEBEPM holding 44 Multi-frame pattern serial detection unit 44-4 Zero continuous count adding unit 44-5 Zero continuous count reset unit (1 input inversion type AND circuit) 44-9 Multi-frame head bit detection information reset unit (1-input inversion type AND circuit) 44-10 Multi-frame head bit detection information setting unit (OR circuit) 44-11 Frame number correction detection unit (AND circuit) 44-12 Multi Frame pattern detector (AND circuit) 45 Multi-frame number (FRNO) serial controller 45-4 Frame number controller 46 LOM serial detector 46-3 LOM protection stage number adder 46-6 Addition condition detector (exclusive NOT logic) Sum circuit) 46-7 LOM Output 7-stage detection unit (AND circuit) 46-8 LOM release 3-stage detection unit (AND circuit) 46-9, 47-11 State transition occurrence detection unit (OR circuit) 46-10 LOM protection stage number information reset unit (1 input) Inverting type AND circuit) 46-11, 47-12, 49-16 State transition unit (exclusive OR circuit) 46-12, 47-13, 49-17 Bypass control unit (selector) 47 CRC serial detection unit 47- 3 CRC calculation result reset section (AND circuit) 47-5 CRC data insertion section (80 hex insertion section) 47-6 CRC calculation section 47-7, 49-5 Non-coincidence detection section 47-8 Protection stage control section 47-9 CRC error Detection 3-stage detection unit (1-input inversion type AND circuit) 47-10 CRC error cancellation 3-stage detection unit (1-input inversion type NOR circuit) 47-14 CRC protection stage number addition unit 4 7-16, 49-8 Addition condition detection unit (exclusive OR circuit) 47-17 Detection / release three-stage detection unit (AND circuit) 47-18 Protection stage number reset unit (1-input inversion type AND)
Circuit) 48 expected reception value holding unit 48-1 RAM for holding first expected reception value (EXP1) 48-2 RAM for holding second expected reception value (EXP2) 48-3 to 48-5 expectation of signal label (SL) reception Value MSB bit holding unit (FF circuit) 48-6 MSB bit soft notification selection unit 48-7 Expected reception value software notification selection unit (selector) 48-8 SL expected reception value read address control unit (1
Input inversion type AND circuit) 48-8, FF circuits 48-9, 48-10, decode circuits 48-11 to 48-13, MSB bit selection section 48-
14 and expected reception value selection unit (selector) 48-15 49 TIM serial detection unit 49-6 mismatch detection display unit (OR circuit) 49-7 mismatch detection display reset unit (1-input inversion type A)
ND circuit) 49-9 TIM protection stage number addition unit 49-12 IM detection seven-stage detection unit (AND circuit) 49-13 TIM cancellation three-stage detection unit (AND circuit) 49-14 State transition occurrence detection unit (OR circuit) 49 -15 TIM protection stage number information reset unit (1-input inversion type AND circuit) 50 LOM holding unit 50-1 LOM holding RAM 51 FRNO holding unit 51-1 FRNO holding RAM 52 alarm bit holding unit 52-1 TIM alarm bit holding Unit 52-2 CRC alarm bit holding unit 52-3 LOM alarm bit holding unit 52-4 Alarm bit writing address control unit (1
Input inverting OR circuit) 52-5 Write enable generator [decode circuit (D
EC)] 52-6 Alarm bit read address control unit (1
Input inversion type OR circuit) 52-7 Read select generation unit (DEC) 52-8 TIM select unit (selector) 52-9 CRC select unit (selector) 52-10 LOM select unit (selector) 52-11 Line switching information read Select generation unit (D
EC) 52-12 Line switching information selection unit (selector) 52-13 Software notification read select generation unit (DE
C) 52-14 Software notification selection unit (selector) 53 BIP2 error serial detection unit (BIP2 serial operation processing unit) 53A, 53B BIP2 serial operation processing unit 53-3 BIP2 operation value reset unit (1 input inversion type A)
ND circuit) 53-4 Odd bit BIP2 operation unit (exclusive OR circuit) 53-5 Even bit BIP2 operation unit (exclusive OR circuit) 53-6 BIP2 operation comparison unit 53-7 BIP2 error detection unit (AND circuit) 54) BIP2 holding section 54-1 RAM for holding BIP2 55 BIP8 error serial detection section (BIP8 serial operation processing section) 55-1 to 55-3 BIP8 operation value holding section (FF circuit) 55-4 to 55-6 BIP8 operation Result holding unit (FF circuit) 55-10 BIP operation value selection unit (selector) 55-11 BIP8 operation value reset unit (1-input inversion type AND circuit) 55-12 BIP operation unit (exclusive OR circuit) 55-13 BIP8 operation value write enable generation unit (AND circuit) 55-14 BIP8 operation result write enable generation unit (AN D circuit) 55-15 BIP8 operation result selection unit (selector) 55-16 BIP8 operation comparison unit 55-17 BIP8 error detection unit (AND circuit) 56 BIPPM count value initialization control unit 56-3 Timing control unit (1 input inversion) Type OR circuit) 56-4 read / write signal generator [decode circuit (D
EC)] 56-5 Write enable generation unit (OR circuit) 56-6 BIPPM count value initialization request signal holding unit (FF circuit) 56-7 BIPPM count value initialization request signal selection unit (selector) 57 BIPPM serial processing unit 57A BIP error selection unit 57B BIPPM serial addition unit 57C TU3 BIPPM serial addition unit 57D TU2 BIPPM serial addition unit 57E TU12 BIPPM serial addition unit 57F BIPPM selection unit 57-2 Error count value initialization control unit (1 input inversion type) AND circuit) 57-3 BIP error detector (OR circuit) 57-4 BIPPM adder 58 BIPPM holder 58A BIPPM holder for TU3 58B BIPPM holder for TU2 58C BIPPM holder for TU12 58-1 BIPP RAM for holding 59 PMRAM address control unit 59-1 count plane holding unit (FF circuit with enable) 61 TU pointer serial processing unit 61-1 pointer extraction unit 61-2 pointer processing unit 61-3 RAM control unit 61-4, 89 'RAM 62 TU pointer timing generator 62-1 address generator 71 UNEQ detector 71-4 UNEQ protection stage number adder 71-8 release stage number selector (selector) 71-9 SL range controller (AND circuit) 71-10 UNEQ display detection section (NOR circuit) 71-11 Addition condition detection section (exclusive OR circuit) 71-12 UNEQ detection 4-stage detection section (1 input inversion type A)
ND circuit) 71-13 UNEQ release stage number detection section (AND circuit) 71-14 State transition occurrence detection section (OR circuit) 71-15 UNEQ protection stage number information reset section (1-input inversion type AND circuit) 71-16 State transition section (Exclusive OR circuit) 72 SL holding unit (UNEQ data holding unit) 72A TU3 UNEQ data holding unit 72B TU2 UNEQ data holding unit 72C TU12 UNEQ data holding unit 72-1 SL holding RAM 73 SLM detection unit 73 -5 SLM protection stage number addition unit 73-8 SL range control unit (AND circuit) 73-9 mismatch detection unit 73-10 addition condition detection unit (exclusive OR circuit) 73-11 SLM detection 7 stage detection unit (AND circuit) 73-12 SLM release 3 stage detection section (AND circuit) 73-13 State transition occurrence detection section (OR circuit) 7 -14 SLM protection stage number information reset section (OR circuit) 73-15 State transition section (exclusive OR circuit) 74 Alarm bit holding section (SLM data holding section) 74A SLM data holding section for TU3 74B SLM data holding section for TU2 74C TU12 SLM data holding unit 74-1 UNEQ alarm bit holding unit 74-2 SLM alarm bit holding unit 74-3 Alarm bit writing address control unit (1
Input inversion type OR circuit) 74-4 Write enable generator [decode circuit (D
EC)] 74-5 Alarm bit read address control unit (1
Input inversion type OR circuit) 74-6 Read select generation unit [decode circuit (DE
C)] 74-7 UNEQ select section (selector) 74-8 SLM select section (selector) 74-9 Line switching information read select generation section [decode circuit (DEC)] 74-10 UNEQ line switching information select section (selector) 74-11 SLM line switching information selector (selector) 74-12 Software notification read select generator (selector) 74-13 UNEQ software notification selector (selector) 74-14 SLM software notification selector (selector) 75, 75A C2UNEQ Display serial detection unit 76, 76A, 76B V5UNEQ display serial detection unit 77 UNEQ display selection unit 77A UNEQ data selection unit 78 UNEQ serial detection unit 78A UNEQ serial detection unit 78A for TU3 Unique serial detector for C TU12 81, 81A C2 mismatch serial detector 82, 82A, 82B V5 mismatch serial detector 83 mismatch detection selector 83A SLM data selector 84 SLM serial detector 84A SLM serial detector for TU3 84B TU2 SLM serial detector 84C SLM serial detector for TU12 91 FEBE detector 91-2 G1 byte FEBE detector 91-3 selector 92 FEBEPM serial processor 92-2 FEBE count value initialization controller (1 input inversion type AND circuit) 92-3 FEBEPM addition unit 93 FEBEPM holding unit 93A FEBEPM holding unit for TU3 93B FEBEPM holding unit for TU2 93C FEBEPM holding unit for TU12 93-1 RAM for holding FEBEPM 94 FEBEPM count value initialization control unit 94-3 timing control unit (1-input inversion type OR circuit) 94-4 read / write signal generation unit [decode circuit (D
EC)] 94-5 Write enable generation unit (OR circuit) 94-6 FEBEPM count value initialization request signal holding unit 94-7 FEBEPM count value initialization request signal selection unit (selector) 95 FERF serial processing unit 95-4 FERF Protection stage number addition unit 95-6 FERF selection unit (selector) 95-7 Addition condition detection unit (exclusive OR circuit) 95-8 FERF detection cancellation 10 stage detection unit (AND circuit) 95-9 FERF protection stage number information reset unit (1 input inversion type AND circuit) 95-10 State transition section (exclusive OR circuit) 96 FERF holding section 96A FE3 data holding section for TU3 96B FERF data holding section for TU2 96C FERF data holding section for TU12 96-1 FERF RAM for holding 97 Alarm bit holding unit (FERF data holding unit) 97-1 FERF alarm bit holder 97-2 alarm bit write address control unit (1
Input inverted OR circuit) 97-3 Write enable generator [decode circuit (D
EC)] 97-4 Alarm bit read address control unit (1
Input inversion type OR circuit) 97-5 Read select generation unit [decode circuit (DE
C)] 97-6 FERF select section (selector) 97-7 Soft notification read select generation section [decode circuit (DEC)] 97-8 FERF software notification select section (selector) 97 'Offset counter section 98, 98A G1FEBE serial detection Unit 98 'Match detection unit 99, 99A, 99B V5FEBE serial detection unit 100 FEBE selection unit 100A FEBE selection unit 100' Mapping setting register group 101 FEBEPM serial addition unit 101A FEBEPM serial addition unit for TU3 101B FEBEPM serial addition unit for TU2 FEBEPM serial adder 101 'selector 102, 102A G1 FERF display serial detector 103, 103A, 103B V5 FERF display serial detector 104 FERF display detection selection unit 104A FERF data selection unit 106 FERF serial detection unit 106A FERF serial detection unit for TU3 106B FERF serial detection unit for TU2 106C FERF serial detection unit for TU12 123 TU3 / TUG3 setting register 124 TU2 / TUG2 setting register 125A Size recognition unit 125 to 127 Selector 231 Section overhead (SOH) 232 AU4 pointer 233 Payload (SPE) 234 TU pointer 235 VC3-POH 236 VC2-POH 237 VC12-POH 246 TU pointer detection unit 301 Subscriber terminal 302 Line termination device ( NT) 303,306 Transmission terminal equipment (LT) 304 Switching equipment (SW) 305 Multiplexer (MUX) 307 Relay transmission path

Claims (25)

[Claims] 1. A POH termination processing device for performing POH termination processing on a signal multiplexed with a plurality of channel information transmitted by the SDH transmission method, wherein a common POH is used for each channel for performing POH termination calculation processing on the multiplexed signal. A terminating operation processing unit; and a read-write and writable storage unit for storing the operation result in the POH terminating operation unit for each channel, and performing the POH terminating operation on the multiplexed signal.
Using the storage information of the corresponding channel stored in the storage unit, the POH termination operation processing unit
H-terminating operation processing is performed, and the obtained POH-terminating operation result is stored in the storage area of the corresponding channel in the storage unit, so that the multiplexed signal is subjected to POH-terminating operation processing in a serial manner without being separated for each channel A POH termination processing device in the SDH transmission system, characterized in that it is configured as follows. 2. In the POH termination operation processing in the POH termination operation processing unit, storage information on a corresponding channel read from the storage unit and POH byte data to be processed in the multiplexed signal are stored. 2. The POH termination processing device according to claim 1, further comprising a latch unit for temporarily storing the data. 3. The POH termination arithmetic processing unit is configured as a J1 and J2 byte serial termination processing unit that serially terminates J1 and J2 bytes included in the multiplexed signal, and the storage unit is , And J1 and J2 byte The result of the operation in the serial termination unit is stored for each channel.
2. The SD according to claim 1, wherein the storage information is configured to be supplied to a 1, J2 byte serial termination processing unit.
POH termination device in H transmission system. 4. A multi-frame pattern serial detection unit for serially detecting the J1 byte and J2 byte multi-frame pattern, the J1 and J2 byte serial termination processing unit; A multi-frame pattern number serial control unit for serially controlling the number of frames; a LOM serial detection unit for serially detecting the J1 byte and J2 byte LOM; and a CRC detection for the J1 byte and J2 byte. And a TIM serial detector for serially detecting the TIM of the J1 byte and the J2 byte, and the storage unit includes the multi-frame pattern serial detector. Section, multi-frame pattern number serial control section , LO
The calculation results of the M serial detection unit, the CRC serial detection unit, and the TIM serial detection unit are stored for each channel, and the above-described multi-frame pattern serial detection unit, multi-frame pattern number serial control unit, LOM
The POH in the SDH transmission system according to claim 3, characterized in that it is configured to supply stored information to a serial detection unit, a CRC serial detection unit, and a TIM serial detection unit.
H terminator. 5. The POH termination arithmetic processing unit serially performs termination processing of B3 bytes and V5 bytes of BIP included in the multiplexed signal and termination processing of B3 bytes and V5 bytes of BIPPM included in the multiplexed signal, respectively. The storage unit is configured as a V5 byte serial termination processing unit, and the storage unit stores the operation result of the V5 byte serial termination processing unit for each channel.
2. The POH termination device in the SDH transmission system according to claim 1, wherein the device is configured to supply stored information to a V5 byte serial termination processing unit. 6. A BIP8 operation serial processing unit that serially performs a BIP8 operation on the multiplexed signal, and a BIP2 operation serial processing unit that serially performs a BIP2 operation on the multiplexed signal. A BIP error selection unit for selecting a BIP error signal output from the BIP8 operation serial processing unit and the BIP2 operation serial processing unit; and a BIPPM addition based on the BIP error signal selected by the BIP error selection unit. BI that performs arithmetic operations serially
And a PPM serial addition unit. The storage unit stores each operation result of the BIPPM serial addition unit for each channel, and supplies storage information to the BIPPM serial addition unit. The PH in the SDH transmission method according to claim 5, wherein
OH termination device. 7. The B3, V5 byte serial termination processing section performs a BIP8 calculation serial processing on the multiplexed signal in serial, and a BIPPM processing section based on a BIP error signal from the BIP8 calculation serial processing section. A first BIPPM serial adder that serially performs an addition operation; a BIP2 arithmetic serial processor that serially performs a BIP2 arithmetic operation on the multiplexed signal; and a BIPPM addition arithmetic operation based on a BIP error signal from the BIP2 arithmetic serial processor. A second BIPPM serial adder that performs serial, the first BIPPM serial adder and the second BIPP
A BIPPM selection unit for selecting a BIPPM output from the M serial addition unit, and the storage unit stores each calculation result in the first BIPPM serial addition unit for each channel, The first BI
A first storage unit that can supply storage information to the PPM serial addition unit; and a calculation result of the second BIPPM serial addition unit for each channel, and a second storage unit.
6. The POH termination processing apparatus according to claim 5, further comprising a second storage unit that can supply storage information to the serial addition unit. 8. The POH termination operation processing unit is configured as a UNEQ serial termination processing unit that serially terminates a C2 byte and a V5 byte UNEQ included in the multiplexed signal, and the storage unit is 2. The SDH transmission system according to claim 1, wherein the operation result in the UNEQ serial termination processing unit is stored for each channel, and storage information is supplied to the UNEQ serial termination processing unit.
OH termination device. 9. A C2UNEQ display serial detecting section for serially detecting whether or not the C2 byte is in UNEQ display, and a serially detecting whether or not the V5 byte is in UNEQ display. A V5UNEQ display serial detection section for detecting, a C2UNEQ display serial detection section and a V5UNE
A UNEQ display selection section for selecting a UNEQ display detection signal output from the Q display serial detection section; and a C2 byte, V5 byte UNEQ display in serial based on the UNEQ display detection signal selected by the UNEQ display selection section. And a storage unit for storing, for each channel, a detection result of the UNEQ serial detection unit, and for supplying storage information to the UNEQ serial detection unit. 9. The P in the SDH transmission system according to claim 8, wherein
OH termination device. 10. A C2UNEQ display serial detection section for serially detecting whether or not the C2 byte is in a UNEQ display, and a UNEQ display detection signal from the C2UNEQ display serial detection section. , A first UNEQ serial detector for serially displaying a UNEQ display of C2 bytes, a V5UNEQ display serial detector for serially detecting whether or not the V5 byte is in UNEQ display, and a UNEQ display from the V5UNEQ display serial detector A second UNEQ serial detector that serially displays a V5 byte UNEQ display based on the detection signal; and a UNEQ display selector that selects the UNEQ display output from the first UNEQ serial detector and the second UNEQ serial detector. Configuration Together are, together the storage unit stores the detection results in said 1UNEQ serial detector for each channel, said 1UNEQ
A first storage unit that can supply storage information to the serial detection unit;
A second storage unit that stores the detection result of the second UNEQ serial detection unit for each channel and that can supply storage information to the second UNEQ serial detection unit. A POH termination device in the SDH transmission method according to claim 8. 11. The POH termination arithmetic processing unit is configured as an SLM serial termination processing unit that serially terminates a C2 byte and a V5 byte SLM included in the multiplex signal, and the storage unit includes 2. The POH in the SDH transmission system according to claim 1, wherein an operation result in the SLM serial termination processing unit is stored for each channel, and storage information is supplied to the SLM serial termination processing unit.
Terminator. 12. The SLM serial termination processing section serially detects that the C2 byte has detected a mismatch, and serially detects that the V5 byte has detected a mismatch. A V5 mismatch serial detection unit, a mismatch detection selection unit for selecting a mismatch detection signal output from the C2 mismatch serial detection unit and the V5 mismatch serial detection unit, and a mismatch detection signal selected by the mismatch detection selection unit. And an SLM serial detection unit for serially detecting C2 byte and V5 byte SLMs, and the storage unit stores each detection result of the SLM serial detection unit for each channel. Both are configured to supply stored information to the SLM serial detection unit. It characterized the door, POH termination processing apparatus in SDH transmission system according to claim 11, wherein. 13. An SLM serial termination processing unit, comprising: a C2 mismatch serial detection unit for serially detecting that the C2 byte has detected a mismatch; and a C2 mismatch detection signal based on a mismatch detection signal from the C2 mismatch serial detection unit. A first SLM serial detection unit for serially detecting byte SLM, a V5 mismatch serial detection unit for serially detecting that the V5 byte has detected a mismatch, and a mismatch detection signal from the V5 mismatch serial detection unit. A second SLM serial detector for serially detecting a V5 byte SLM, and an SLM selector for selecting an SLM output from the first and second SLM serial detectors. And the storage unit stores the first SLM serial detection Each of the detection results at the output unit is stored for each channel, and a first storage unit capable of supplying storage information to the first SLM serial detection unit; and a detection result at the second SLM serial detection unit is stored for each channel. 12. The POH termination processing device in the SDH transmission system according to claim 11, further comprising a second storage unit that stores the information in the second SLM serial detection unit and that can supply the storage information to the second SLM serial detection unit. 14. The POH termination arithmetic processing unit terminates the G1 byte and V5 byte FEBE included in the multiplexed signal and the G1 byte and V5 byte FEBEP.
M is configured as a FEBE serial termination processing unit that serially performs the termination processing of M. The storage unit stores the operation result of the FEBE serial termination processing unit for each channel and transmits the result to the FEBE serial termination processing unit. The PH in the SDH transmission system according to claim 1, characterized in that it is configured to supply stored information.
OH termination device. 15. The G1F, wherein the FEBE serial termination processing unit serially detects the FEBE of the G1 byte.
An EBE serial detection section, and a V5F for serially detecting the FEBE of the V5 byte.
An EBE serial detection unit; a FEBE selection unit for selecting a FEBE detection signal output from the G1FEBE serial detection unit and the V5FEBE serial detection unit; and a FEBEPM addition based on the FEBE detection signal selected by the FEBE selection unit. FEB that performs arithmetic operation serially
An EPM serial addition unit, and the storage unit stores the addition result of the FEBPM serial addition unit for each channel.
15. The POH termination processing device in the SDH transmission system according to claim 14, wherein the POH termination processing device is configured to supply storage information to a serial addition unit. 16. The G1F, wherein the FEBE serial termination processing unit performs FEBE detection of the G1 byte serially.
An EBE serial detector, a first FEBPM serial adder that serially performs an FEBEPM addition operation based on the FEBE detection signal from the G1FEBE serial detector, and a V5F that serially detects the V5 byte FEBE.
An EBE serial detector, a second FEBPM serial adder that serially performs an FEBPM addition operation based on the FEBE detection signal from the V5FEBE serial detector, and the first FEBPM serial adder and the second FEB.
The FEBPM selection section is configured to select the FEBPM output from the EPM serial addition section. The storage section stores each addition result of the FEBPM serial addition section for each channel, and FEBEPM
15. The POH termination processing device in the SDH transmission system according to claim 14, wherein the POH termination processing device is configured to supply storage information to a serial addition unit. 17. The POH termination arithmetic processing unit is configured as a FERF serial termination processing unit that serially terminates G1 byte and V5 byte FERFs contained in the multiplexed signal, and the storage unit is The PH in the SDH transmission system according to claim 1, wherein a calculation result in the FERF serial termination processing unit is stored for each channel, and storage information is supplied to the FERF serial termination processing unit.
OH termination device. 18. A G1 FERF display serial detector for serially detecting that the G1 byte indicates FERF, and a serial for detecting that the V5 byte indicates FERF. V5FERF display serial detection unit for detecting, G1FERF display serial detection unit and V5FER
A FERF display detection selector that selects a FERF display detection signal output from the F display serial detector; and a G1 byte and a V5 byte based on the FERF display detection signal selected by the FERF display detection selector. F
A storage unit configured to store a detection result of the FERF serial detection unit for each channel and to store the detection result in the FERF serial detection unit; 18. The P in the SDH transmission system according to claim 17, wherein the P is configured to supply information.
OH termination device. 19. A FERF serial termination processing unit, comprising: a G1 FERF display serial detection unit that serially detects that the G1 byte indicates FERF; and a FERF display detection signal from the G1 FERF display serial detection unit. A first FERF serial detector for serially detecting the FERF of the G1 byte, a V5FERF display serial detector for serially detecting that the V5 byte indicates FERF, and a V5FERF display serial detector. Based on the FERF display detection signal, the second FERF serial detector that performs the V5 byte FERF detection in serial and the FERF display output from the first FERF serial detector and the second FERF serial detector are selected. Constructed with FERF display selection section Together are, the storage unit stores the detection results in said 1FERF serial detector for each channel, said 1FER
A first storage unit that can supply storage information to the F-serial detection unit; and a detection result of the second FERF serial detection unit that is stored for each channel and that can supply storage information to the second FERF serial detection unit. 18. The SD according to claim 17, further comprising a second storage unit.
POH termination device in H transmission system. 20. A POH for processing in the POH termination arithmetic processing unit based on a timing signal indicating the position of the J1 byte and the V5 byte of the multiplex signal and type information of the multiplex signal.
2. The POH termination processing device in the SDH transmission system according to claim 1, further comprising a POH timing signal serial generator for serially generating an OH timing signal. 21. A count value initialization unit for receiving a timing signal indicating a position of a J1 byte and a V5 byte of the multiplexed signal, the POH timing signal serial generation unit initializing an SPE count value, A count value addition control unit that performs addition control of the SPE count value based on a signal from the initialization unit; and an SPE count addition value in the count value addition control unit that is held for each channel, and held for each channel. The POH termination arithmetic processing unit, based on a signal from the count value initialization unit and the type information of the multiplexed signal, based on the signal from the count value initialization unit and the type information of the multiplexed signal. 21. The SDH transmission device according to claim 20, further comprising a POH timing signal generation unit for generating a POH timing signal for the processing of (1). POH termination processor in system. 22. An apparatus according to claim 1, further comprising an address generator for generating address information for identifying each channel of the multiplexed signal. 23. A POH termination processing device for performing POH termination processing on a signal multiplexed with a plurality of pieces of channel information transmitted by the SDH transmission method, wherein a common POH is used for each channel for performing POH termination computation processing on the multiplexed signal. A terminal operation processing unit, and a read / write free storage unit for storing the operation result of the POH terminal operation processing unit for each channel, wherein the POH terminal operation processing unit is included in the multiplexed signal. J1 and J2 byte serial terminating units for serially terminating J1 and J2 bytes, and BI of B3 and V5 bytes included in the multiplexed signal
P termination processing and BIP of B3 byte and V5 byte
A B3, V5 byte serial termination processing unit for serially terminating PM, and a UN of C2 byte and V5 byte included in the multiplexed signal
While performing EQ termination processing serially, the above C2
And a V5 byte SLM termination processing unit for serially terminating the SLM, a G1 byte and a V5 byte FE included in the multiplexed signal.
BE termination processing and F of G1 byte and V5 byte
A FEBE / FERF serial termination unit for serially performing the G1 byte and the V5 byte FERF termination process while serially performing the EBEPM termination process, and the storage unit includes the J1 , J2 byte serial termination unit,
The B3, V5 byte serial termination processing unit, the UNEQ
The SLM serial termination unit, the operation result of the FEBE / FERF serial termination unit is stored for each channel, and the J1, J2 byte serial termination unit, the B3, V5 byte serial termination unit, the UNEQ. S
A POH termination processing device in the SDH transmission system, characterized in that it is configured to supply stored information to the LM serial termination processing unit and the FEBE / FERF serial termination processing unit. 24. When performing a POH termination process on a signal multiplexed with a plurality of channel information transmitted by the SDH transmission method, a POH termination for a corresponding channel stored in a readable and writable storage unit. The POH common to each channel is used by using the storage information regarding the processing operation result.
The POH termination calculation processing is performed in the termination calculation processing unit, and the obtained POH termination calculation result is stored in the storage area of the corresponding channel in the storage unit, so that the multiplexed signal is kept serial without being separated for each channel. A POH termination processing method in the SDH transmission method, wherein a POH termination calculation process is performed. 25. A pointer / POH termination processing device for performing pointer processing and POH termination processing on a signal multiplexed with a plurality of channel information transmitted by the SDH transmission method, wherein the multiplexed signal is not separated for each channel. An SDH comprising: a serial pointer processing unit that performs pointer processing as it is serial; and a serial POH termination processing unit that performs POH termination processing as it is serial without separating the multiplexed signal for each channel. Pointer / POH termination processing device in transmission system.