CN1154302C

CN1154302C - Poiter processing device, channel overhead terminal processor and method thereof

Info

Publication number: CN1154302C
Application number: CNB971146586A
Authority: CN
Inventors: 丰山武; 夫; 吉田洋; 义; 江本秀夫; 延; 藏屋久义; 枝泽正延
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1996-07-11
Filing date: 1997-07-10
Publication date: 2004-06-16
Anticipated expiration: 2017-07-10
Also published as: CN1177874A

Abstract

A pointer processing apparatus in an SDH transmission system used to serially conducting a pointer process on inputted multiplex data has an address generating unit, a RAM, and RAM controlling unit, thereby largely decreasing the circuit scale, the power consumption, the number of distributions and the like. A POH terminating operation process is conducted in a POH terminating operation process unit, and an obtained result of the POH terminating operation is stored in a storage area for a corresponding channel of a storage unit, whereby the POH terminating operation process can be conducted without separating a multiplex signal into channels. Thereby, a scale and a power consumption of an apparatus can be largely decreased.

Description

Pointer processing apparatus, path overhead terminal processes apparatus and method

Technical field

Be applicable to pointer processing apparatus, POH terminal processes device, POH terminal processing method and the pointer/POH terminal processes device in the SDH transmission system of carrying out pointer processing and path overhead (POH) terminal processes when the present invention relates in the synchronous terminal network that with the SDH (Synchronous Digital Hierarchy) (SDH) of formulating standard by ITU-T (portion of international telecommunication union telecommunication) is benchmark, transmit information.

Background technology

By means of present high integration and low-power consumption LSI (large scale integrated circuit), the development of semiconductor device art is realizing having other function of different system level on a LSI chip always.In recent years, need to invent and constitute the hardware configuration that hardware size and power consumption reduces as far as possible urgently and on a LSI chip, be equipped with more function, thereby reduce the scale and the power consumption of system's (SDH transmission system) so that can constitute a system (SDH transmission system) with a spot of LSI.

(A) SDH transmission system general introduction

For the high-speed equipment and the existing low-speed device and interface is unified of multiplexing countries in the world effectively, well-known, SDH has been made and clearly stipulated and formulated standard.In SDH, all transmission rates (bit rate) of the data that can be transmitted, all unify (to speak by the book for 155Mbps for its basic rate (multiplexed unit), should be 155.52Mbps) message transmission rate (155Mbpd * n: wherein n=1,4,16,64), and these data are comprised that by multiplexed the various data of existing low speed data (low digital stage information) all can be multiplexed.Therefore, SDH can adapt to following novel device neatly.

Specifically, SDH adopts a kind of system that has stipulated to be known as virtual " box " of virtual container (VC) therein, in this " box ", deposit a plurality of low digital stage information, be used to constitute the information of higher number level, these " boxes " concentrated be placed in bigger " box ", transmit thereby a plurality of information that will have a different transmission rates leave in one big " box ".

For example, shown in Figure 148, one among the SDH multiplexed substantially unit is called a STM-1 (synchronous transfer module level 1) frame.This STM-1 frame is deposited an AU-4, to the additional deposit position that is used to indicate described VC-4 hereinafter of this AU-4 and with the Administrative Unit Pointer [AU (administrative unit) pointer] of Frequency Synchronization.In addition, VC-4 frame is deposited 1 channel of the 138Mbps series data that is called C (container)-4 or 3 channels of TUG (tributary unit group)-3.

Further, in the frame of TUG-3 that 7 channels of 1 channel of TU (tributary unit)-3 (34Mbps series) or TUG-2 (6Mbps series) are multiplexed, and in TUG-2,3 channels of 1 channel of TU-2 or TU-12 are multiplexed.The constituted mode of above-mentioned TU-3 is, with path overhead (POH: transmission objectives information) with the frame of the 34Mbps series that is called C-3 that forms VC-3 and be additional to this VC-3 be used to indicate deposit position and with the TU pointer addition of Frequency Synchronization.

TU-2 is with the frame addition of the C-2 (6Mbps series) of POH and formation VC-2, again the TU pointer is additional to the frame that constitutes behind the VC-2.TU-12 is with the frame addition of the C-12 (2Mbps series) of POH and formation VC-12, again the TU pointer is additional to the frame that constitutes behind the VC-12.

In a frame of STM-1 signal, can maximum 63 channels of maximum 21 channels of maximum 3 channels of TU-3, TU-2 or TU-12 are multiplexed.

Below, with the frame format of explanation above-mentioned each STM-1, TU-3, TU-2 and TU-12.Point out that in passing above-mentioned TU-3, TU-2 and TU-12 etc. will describe with TU3, TU2, TU12 etc. hereinafter simply.

(A-1) STM-1 frame format

Figure 149 is the figure of the frame format of the above-mentioned STM-1 of expression.Shown in Figure 149, a STM-1 frame has the two-dimentional array of bytes of 9 row * 270 row (byte).Preceding 9 row * 9 row are made of section overhead (SOH) 231 and AU (AU4) pointer 232.Back 9 row * 261 row are called net load (SPE: net load is sealed synchronously) 233, are used to deposit multiplexed information.

Section overhead 231 comprises various Operation and Maintenance information, for example indicate the frame synchronization mode of STM-1 frame A1 and A2 byte, be used to B1 byte that monitors error code etc.AU4 pointer 232 is made of H1 byte (H1#1-H1#3 byte), H2 byte (H2#1-H2#3 byte) and the H3 byte (H3#1-H3#3 byte) of the deposit position (leading address) of indication VC (VC4: with reference to Figure 150) in net load 233.

Actual AU4 pointer value generally is stored in above-mentioned H1 byte (H1#1 byte), the H2 byte (H2#1 byte), and fixed value as and put pointer (CI: and put indication) and be stored in H1#1 byte, H2 byte, the H2#3 byte.

Shown in Figure 149, the offset pointer value of the lead byte address of indication VC4 is to stipulate that so promptly for example the 0th address begins after the H3#3 byte, and finished before the H1#1 byte the 782nd address.Therefore, be " 0 " as the AU4 pointer value, the frame phase place that then means STM-1 is consistent with VC4's, thereby makes VC4 be right after H3 byte (H3#3 byte) to deposit continuously afterwards.

As the AU4 pointer value is " 0 " value in addition, then means the inconsistent of the frame phase place of STM-1 and VC4, thereby VC4 is deposited by this way, for example, the lead byte of VC4 (j1 byte) is positioned at the address after the 0th address displacement, and its phase pushing figure is shown in Figure 150.Simultaneously, the pointer offset value of AU4 is generally by every 3 regulations, so, if pointer value changes 1,3 bytes of the frame phase change of VC4 then.

3 bytes of above-mentioned H3 byte (H3#1-H3#3 byte) and H3 byte back are respectively the frequency that is called negative byte of padding and positive byte of padding and adjust byte.If between the clock frequency of the clock frequency of transmission frame (STM-1) and multiplexed information, have small difference, then this just/negative byte of padding is used for (promptly, fill control) adjust frequency, so that the fluctuation of difference in the absorption clock frequency or transmission frame phase place, therefore can prevent the disappearance of the information that transmits.

(A-2) TU3 frame format

Figure 151 is the figure of the frame format of the above-mentioned TU3 of expression.Shown in Figure 151, a TU3 frame is represented with the two-dimentional array of bytes of 9 row * 86 row (byte).H1 byte in preceding 9 row * 1 row and H2 byte be used for indicating VC (VC3 :) with reference to Figure 152 the deposit position of net load 233 and with TU (TU3) pointer of its Frequency Synchronization.1 byte of H3 byte and H3 back (offset pointer value " 0 ") is respectively the negative byte of padding and the positive byte of padding of be used to adjust frequency (frame phase place).Wherein, all the other 6 row * 1 row parts in 9 row * 1 row in front except that H1～H3 byte are fixing byte of paddings (fix filling).

Shown in Figure 151, the offset pointer value of the lead byte address of indication VC3 is to stipulate that so promptly the 0th address begins after the H3 byte, and finished before the H3 byte the 764th address.Therefore, be " 0 " as the TU3 pointer value, the frame phase place that then means TU3 is consistent with VC3's, thereby VC3 is deposited after being right after (the 0th address) H3 byte continuously.

As the TU3 pointer value is " 0 " value in addition, then means the inconsistent of the frame phase place of TU3 and VC3, thereby VC3 is deposited by this way successively, for example, the lead byte of VC3 (j1 byte) is positioned at the address after the 0th address displacement, and its phase pushing figure is shown in Figure 152.

In Figure 152, part with 9 row * 1 row that comprise j1 byte of indicating with reference to numbering 235, the path overhead (VC3-POH) that is called VC3, this path overhead provides at the point with the VC3 combination of channels (multiplexed processing) of a passage and regulation, and remains to demultiplexing point (demultiplexing processing) after transmission information.By monitoring to VC3-POH, can be with error code state of end-to-end mode monitor transmissions information etc. etc.

For this reason, the form that VC3-POH has except that above-mentioned j1 byte, also comprises B3 byte, C2 byte, G1 byte, F2 byte, H4 byte and Z3～Z5 byte.The function of above-mentioned each byte is as follows:

(1) j1 byte: be called the channels track signal, be used for confirming by send signal (supervision) repeatedly with fixed mode whether receiver side normally is connected continuously with transmitter side (confirming the connection of passage);

(2) B3 byte: be used to monitor the error of passage, the operating result that will obtain by the operating process (will illustrate below) that is called BIP (Bip) 8 inserts as the B3 byte of next frame;

(3) C2 byte: be used for representing the byte (signal mark) of the mapping structure of VC3, as described later, various information be set therein, for example indicate VC3 not hold the UNEQ indication etc. of net load;

(4) G1 byte: this byte is used to represent channel status, is used in the supervision reception result of passage error code to be transmitted back to the function (FEBE) of the transmitter side of VC3 and the channel transfer state is transmitted back to the function (FERF) that the far-end of transmitter side receive to lose efficacy;

(5) F2 byte: the byte that can under the subscriber channel state, freely use by network operator.

(6) Z3～Z5 byte: keep in the world as standby byte;

According to one embodiment of the present of invention, in the described later POH terminal processes j1 byte in the above-mentioned byte, B3 byte, C2 byte, G1 byte are monitored (terminal processes).

(A-3) TU2 frame format

Figure 153 is the figure of the frame format of the above-mentioned TU2 of expression.Shown in Figure 153, a TU2 frame has the two-dimentional array of bytes of 4 row * 108 row (byte).V1 byte in preceding 4 row * 1 row and V2 byte be used to indicate VC2 (with reference to Figure 154) deposit position and with TU (TU2) pointer of its Frequency Synchronization.1 byte of V3 byte and V3 back (among the figure at its right) is respectively the negative byte of padding and the positive byte of padding of be used to adjust frequency (frame phase place).Point out that in passing the V4 byte is the byte that keeps in the world for using in the future.

Shown in Figure 153, the offset pointer value of the lead byte address of indication VC2 is to stipulate that so promptly the 0th address begins after the V2 byte, and finished before the V2 byte the 427th address.Therefore, be " 0 " as the TU2 pointer value, the frame phase place that then means TU2 is consistent with VC2's, thereby makes VC2 be right after V2 byte (the 0th address) equally to deposit continuously afterwards.

As the TU2 pointer value is " 0 " value in addition, then means the inconsistent of the frame phase place of TU2 and VC2, thereby VC2 is deposited by this way successively, for example, the lead byte of VC2 (V5 byte) is positioned at the address after the 0th address displacement, and its phase pushing figure is shown in Figure 154.

In Figure 154,, be called the path overhead (VC2-POH) of VC2 with the part that 4 row * 1 that comprise the V5 byte with reference to numbering 236 indications are listed as.By monitoring to VC2-POH, can be with error code state of end-to-end mode monitor transmissions information etc. etc.

For this reason, the form that VC2-POH has except that above-mentioned V5 byte, also comprises J2 byte, Z6 byte and Z7 byte.Because the path overhead of VC12 has the form identical with VC2-POH 236, so the frame format of explanation TU12 earlier here, the function of above-mentioned each byte will illustrate below.

(A-4) TU12 frame format

Figure 155 is the figure of the frame format of the above-mentioned TU12 of expression.Shown in Figure 155, a TU12 frame has the two-dimentional array of bytes of 4 row * 36 row (byte).Similar with above-mentioned TU2 frame format, V1 byte in preceding 4 row * 1 row and V2 byte be used to indicate VC12 (with reference to Figure 156) deposit position and with TU (TU12) pointer of its Frequency Synchronization.1 byte of V3 byte and V3 back is respectively the negative byte of padding and the positive byte of padding of be used to adjust frequency (frame phase place).Point out that in passing the V4 byte among the TU12 is the spare bytes that keeps in the world for using in the future.

Shown in Figure 155, the offset pointer value of the lead byte address of indication VC12 is to stipulate that so promptly the 0th address begins after the V2 byte, and finished before the V2 byte the 139th address.Therefore, be " 0 " as the TU12 pointer value, the frame phase place that then means TU12 is consistent with VC12's, thereby VC12 is deposited after being right after (the 0th address) V2 byte continuously.

As the TU12 pointer value is " 0 " value in addition, then means the inconsistent of the frame phase place of TU12 and VC12, thereby VC2 is deposited by this way successively, for example, the lead byte of VC12 (V5 byte) is positioned at the address after the 0th address displacement, and its phase pushing figure is shown in Figure 156.

In Figure 156,, be called the path overhead (VC12-POH) of VC12 with the part that 4 row * 1 that comprise the V5 byte with reference to numbering 237 indications are listed as.The form that this VC12-POH has, similar to VC2-POH, except that above-mentioned V5 byte, also comprise J2 byte, Z6 byte and Z7 byte.The function of above-mentioned each byte is as follows:

(1) V5 byte: this byte is used for by the operating process that is called BIP2 (will illustrate below) VC2 or VC12 being carried out passage-error code supervision, be used in and whether receive the function (FEBE) that the error code notification of information that obtains by BIP2 is transmitted back to transmitter side, be used for representing the mapping structure of VC2/VC12, and be used for the Far End Receive Failure function (FERF) of the passage of VC2/VC12 with the signal mark; Be actually B3, the C2 that to comprise among the above-mentioned VC3-POH 235, a byte (8) that reaches the function endowing V5 byte of G1 byte;

(2) J2 byte: similar with the j1 byte that is included in the above-mentioned VC3-POH 235, this byte is used to confirm the connection of passage as the channels track signal;

(3) Z6 and Z7 byte: spare bytes.

In an embodiment of the present invention, in the described later POH terminal processes V5 byte in the above-mentioned byte and J2 byte are monitored (terminal processes).

(A-5) AU4/TU3/TU2/TU12 pointer format

The pointer byte of above-mentioned pointer (AU4/TU3/TU2/TU12 pointer) has and the same form shown in Figure 157, comprises 4 NDF (new data flag) position (N), 2 SS position, 10 pointer value and negative byte of padding.

Below, (N) function of position, SS position and 10 bit pointer values of above-mentioned NDF (new data flag) is described.

(1) NDF position: represent following 2 kinds of states.

NDF allows (" 1001 ")

This signal is used for operation pointer value (now using pointer value) is changed to new pointer value immediately.As more than 3 or 3 when consistent of the pointer value that is received, detect NDF and allow with NDF position " 1001 ".But, if hereinafter described SS position is not suitable value, then can not detects NDF and allow, will produce a null pointer.

NDF forbids (" 0110 ")

This signal is used to transmit normal pointer value, also comprises hereinafter described incremented/decremented (I/D) indication.As the SS position is not suitable value, and then pointer will become null pointer.

If the NDF position is in state beyond the above-mentioned situation (neither NDF allows, neither NDF forbid), then pointer will become null pointer.

(2) SS position: the specification of the VC among this signal indication AU/TU, as shown in the table.

Corresponding relation between table 1 signal specification and the SS place value

The signal specification	The SS place value
The signal specification	The SS place value	AU4
	10	AU4
	10	TU3	10
TU2	00	TU3	10
TU2	00	TU12	10

(3) 10 bit pointer values: the leading position of VC among this signal indication AU/TU (offset pointer value) as binary code.This value is made up of with (D) position of successively decreasing (I) position that increases progressively that respectively is 5.The effective range of pointer value is according to the specification decision of each signal, and is as shown in the table.

Corresponding relation between table 2 signal specification and the valid pointer value

The signal specification	The valid pointer value
The signal specification	The valid pointer value	AU4	0-782
TU3	0-764	AU4	0-782
TU3	0-764	TU2	0-427
TU12	0-139	TU2	0-427

When operation pointer value and I position be reversed to more than 3 or 3 and D position be reversed to 2 or 2 when following, this increases progressively indication effectively.When increasing progressively indication when effective, do not read the data in the positive byte of padding district (being right after after the H3/V3).On the other hand, when operation pointer value and D position be reversed to more than 3 or 3 and I position be reversed to 2 or 2 when following, this successively decreases indication effectively.When the indication of successively decreasing is effective, read the data in the negative byte of padding district (H3/V3 byte).

When H1 and H2 byte or V1 and V2 byte all were " 1 ", indication became PAIS (passage AIS) indication.

Figure 158 is the figure that is used to illustrate the state transitions of pointer.Shown in Figure 158, pointer shifts 3 states, i.e. normal condition (NORM), abnormality (LOP) and alarm detection state (PAIS).In Figure 158, " NDF " expression NDF allows to detect, the continuous consistency detection of " NORx3 " normal pointer value 3-frame of expression, the indication of " INC/DEC " expression incremented/decremented detects, " INVxN " expression N-frame consecutive invalid pointer detects, " NDFxN " expression N-frame N continuous DF-allows to detect, and " AISx3 " expression 3-frame continuous P AIS-indication detects.

Detect positive constant pointer as continuous 3 times (surpassing 3 frames), then only detect INC/DEC once under normal condition, or only detect NDF permission signal once, shown in Figure 158, the state of pointer remains on normal condition.Allow signal as be consecutively detected null pointer (INF) or NDF in pre-determined number, then pointer state becomes the LOP state.Be received 3 times as AIS, then pointer state becomes alarm detection (PAIS) state.

As detect AIS continuous 3 times under the LOP state, then pointer state is transferred to alarm condition.Be consecutively detected null pointer under in alarm condition in pre-determined number, then pointer state is transferred to the LOP state.For make pointer from the LOP state transitions to normal condition, only need detect normal condition 3 times continuously.For making pointer transfer to normal condition, only need detect normal condition 3 times continuously, or detect NDF permission signal once from alarm condition.

(B) explanation of SDH transmission network

Figure 159 is the block diagram of expression SDH transmission network one example.In Figure 159, with reference to numbering 301 expression user terminals, 302 expression NTUs (NT), 303 and 306 expression line termination devices (LT), 304 expression conversion equipments (SW), 305 expression multiplex machines (MUX), and 307 expression repeated lines.

In the SDH network shown in Figure 159, data from a plurality of user terminals 301 (or a repeater), be assembled into a STM-n frame (wherein by multiplex machine 305, n=1,4,16,64), and carry out expense (SOH by line termination device 306, POH) terminal/change is handled and AU/TU pointer terminal/change processing etc., is transferred to the user terminal 301 of the relative side on repeated line 307 then.

Therefore, for example, if notice the pointer handling part shown in Figure 160, above-mentioned line termination device 306 generally have AU4 pointer processing unit 244 ' and TU pointer processing unit 245 ', as pointer processing apparatus 243.When considering the multiplexed data that the conduct of STM-1 frame is received, as illustrating with reference to Figure 148 in front, maximum 63 channel multiplexings are in the STM-1 frame under maximum 21 channels or the situation at TU12 under maximum 3 channels under the situation of TU3, the situation at TU2.Therefore, elastic storage (ES) memory 247 and pointer that TU pointer processing unit 245 ' generally has pointer detecting unit 246, be used to change the TU pointer are handled (insertions) unit 248, each unit number at least with leave the STM-1 frame in the TU level in several equate (maximum 63 channels) of frame (channel).

TU4 pointer processing unit 244 ' in, with reference to numbering 244 expression AU4 pointer detecting units, 245 expression serial (S/P) converting units.249 expressions walk abreast/serial (P/S) converting unit with reference to numbering.

AU4 pointer detecting unit 244 is used for detecting the AU4 pointer of the multiplexed data (AU4 frame, the SOH to STM-1 carried out terminal processes in this frame) that (extraction) received, and this AU4 pointer is carried out terminal processes.The VC4 signal that S/P converting unit 245 will be carried out terminal processes to wherein AU4 pointer is divided into the frame (channel) in the TU level (TU3/TU2/TU12).

TU pointer processing unit 245 ' in, 246 pairs of TU pointers that received of each pointer detecting unit are analyzed, and detect the state of the TU pointer received.The clock of device side transferred to data clock by each ES memory 247 from the clock of transmission line trackside.Each pointer processing unit 248 carries out the computing of pointer, and inserts this pointer etc. in the data of reading from the ES memory 247 of correspondence.The data of multiplexed separated each channel of P/S converting unit 249.

Above-mentioned pointer processing apparatus 243 utilizes said structure that the frame in the TU level multiplexed in STM-1 frame (VC4 frame) is handled by each channel.That is, the data in 245 pairs of STM-1 frames of S/P converting unit (VC4 frame) in the multiplexed TU level are changed, and to each channel, Dui Ying pointer detecting unit 246 is from each mask data detection (extraction) TU pointer then with this data separating.

Data on each channel that is extracted (TU pointer) are temporarily write corresponding ES memory 247 according to the clock of transmission line trackside, read according to the clock of device side then, shift to carry out clock.After this, in the pointer processing unit 248 of correspondence, each data are carried out pointer and handle, and carry out the P/S conversion, realizes multiplexedly, export as sending multiplexed data then by P/S converting unit 249 according to the clock of device side.

The pointer that carries out in each pointer processing unit 248 is handled and is meaned such processing, promptly analyzes the pointer, alarm detection, the renewal that are received and operates pointer (now using pointer), conversion (transmission) pointer etc.

(C) POH terminal processes general introduction

In the SDH transmission system, 2 circuits are set usually, i.e. working line and extension wire between two line termination devices 306.Receiver side is confirmed communication line, is the quality of working line and extension wire, so that suitably switch to extension wire from working line according to the degree that degrades of working line.

For this reason, line termination device 306 according to the frame format of the multiplex signal in the SDH transmission system (, being assumed to the STM-1 frame here) and in this STM-1 frame the TU format signal of TU3, TU2, the TU12 etc. of multiplexed (mapping), the quality of affirmation circuit.

Specifically, line termination device 306 carries out various POH terminal processes such as for example BIP (bit interleave parity check) operation, according to TU3, TU2 multiplexed in the STM-1 frame that is received or the POH in the TU12 signal, monitor the error in the passage, so that the quality of detection line reduces situation, and produce the control signal that is used for circuit switched by each form of TU3, TU2 and TU12.

As mentioned above, in the STM-1 frame, under the situation of TU3, be mapped with 3 channels at most, under the situation of TU2, be mapped with 21 channels at most, under the situation of TU12, be mapped with 63 channels at most.Therefore, respectively (concurrently) number of times of carrying out the POH terminal processes must equal the number of channel corresponding with the signal specification of TU format signal.

Therefore, line termination device 306 generally is the leading position that the pointer value from the H1 of STM-1 frame and H2 byte detects the VC-4 form, multiplexed set information (mapping set information) according to the leading position that is detected and TU3, TU2 and TU12 separates TU format signal multiplexed among the VC-4, and respectively each TU channel is carried out the POH terminal processes in different circuit.

When signal multiplexed in the STM-1 frame all is TU12, must carry out 63 times POH terminal processes to 63 channels among the TU12.Therefore, in order to carry out 63 POH terminal processes on the channel 63 circuit must be arranged at most.

Below, be briefly described the POH terminal processes.

(C1) J1 and J2 byte terminal processes

As mentioned above, by monitoring, can confirm the connection of passage to being included in the j1 byte in the VC3-POH 235 and being included in VC2/VC12-POH 236 and 237.

Shown in Figure 161, for example, suppose to add POH (" A ") in the device " #1 " at transmitter side, in the device " #2 " of transmitter side, add POH (" B ") as correct circuit, the device of receiver side " #3 " is for receiving the terminal of POH (" A " and " B "), so that j1 byte and J2 byte are monitored.

Specifically, above-mentioned each j1 byte and J2 byte (channels track signal) are the signals that obtains after the channel signal addition by the tracking signal (passage name) that will be made up of 15 ascii characters and VC3/VC2/VC12, for example have the form shown in Figure 162, and can be with multi-frame conversion 15 ascii characters (ascii data position " X ") of 16 bytes.

As long as check the value (receive path name) received whether with to receive desired value (the passage name that should receive) consistent, the device of receiver side " #3 " just can confirm that whether the signal that received is connected with correct device.If inconsistent, then detect expression institute reception value and receive the inconsistent TIM of desired value (following the tracks of the directive mismatch), report to the police to produce mismatch.

In the frame format of the channels track signal shown in Figure 162, the MSB (highest significant position) of 16 frames (amounting to 16) is called as the multi-frame directive.By detection multi-frame directive (" 1,000 00,000,000 0000 "), but the sense channel tracking signal.This multi-frame directive is used to detect step-out (Loss Of Multiframe).Detection of loss of mains carried out for 7 steps forward under following situation, carried out for 3 steps backward:

The inconsistent detection case of frame: when handling the 16th of multi-frame, 16 frame pointing-type is not " 1,000 0,000 0,000 0000 " in received signal;

The consistent detection case of frame: when handling the 16th of multi-frame, 16 frame pointing-type is " 1,000 0,000 0,000 0000 " in received signal;

In Figure 162, the position " C " the MSB in the frame of sequence number " 0 " is called as CRC (cyclic redundancy check (CRC))-7 parity check bit, uses in the CRC-7 computing of adopting generator polynomial X7+X3+1.

Shown in Figure 163, for example, receiver side with sequence number be the reception data of frame of " 0 " as 80 ( _HEX) carry out the CRC-7 computing to receiving data, and operation result and sequence number at next multi-frame are compared for the reception CRC position in the frame of " 0 ", thereby the detection crc error.Point out that in passing, crc error detects and carried out forward for 3 steps, carries out for 3 steps backward here.

(C2) B3 byte terminal processes

The error parity check system that is called BIP8 (bit interleave parity check-8) operation by employing is to being included in B3 byte among the VC3-POH 235 (about its form, can be with reference to Figure 164) carry out terminal processes, can detect the error (error code) in the passage of VC3 signal.In this case, carry out even parity as the error parity check system.

Specifically, the BIP8 operation is to be 8 a kind of technology of carrying out parity calculations of unit every enumeration data with the byte, for example the parity as the identical numerical digit of a byte of unit shown in Figure 165 (a) is counted, and with this identical numerical digit indication counter result of the BIP8 shown in Figure 165 (b).

For example, shown in Figure 166, receiver side carries out parity calculations to each byte (8) of 1 frame (85 bytes * 9=765 byte) data of VC3 signal, and result of calculation and the B3 byte that extracts from next frame compared, so as to detecting each the parity error of from MSB to LSB (least significant bit).When in a certain frame, detecting parity error, produce 1 warning.

(C3) C2 byte terminal processes

By carrying out terminal processes (supervisory signal mark) and make signal mark (SLM) or UNEQ (expression VC3 signal does not hold net load) inconsistent, can discern the mapping structure of VC signal to being included in C2 byte (with reference to Figure 167) among the VC3-POH 235.

As C2 byte (signal mark), for example, shown in Figure 168, be set at certain value (8 mapping codes) according to the mapping structure of VC3 signal.When this VC3 signal does not hold net load, all be set at " 0 " of expression UNEQ.

Receiver side monitors the C2 byte.When the byte C2 (all being " 0 ") that is consecutively detected indication UNEQ surpassed 4 frames, receiver side produced the UNEQ detection alarm.When detecting the byte C2 with the indication except that UNEQ and surpass 6 frames, receiver side is eliminated the UNEQ detection alarm.

At this moment, the reception desired value of the C2 byte that receiver side will be set by administrative staff (service engineer) and actual reception to the value of C2 byte compare, so as to detection SLM.For example, when detecting for continuous 7 times in the reception value and receiving between the desired value when inconsistent, produce the SLM detection alarm.When detecting unanimity continuous 3 times, this SLM detection alarm is eliminated.

(C4) G1 byte terminal processes

By the G1 byte that is included among the VC3-POH 235 is carried out the channel status that terminal processes can be discerned the VC3 signal.For example, the G1 byte has the form shown in Figure 169.With 4 of the high positions of G1 byte be defined as FEBE (far end block error) position [with reference among Figure 169 1.], and will be subsequently 1 be defined as FERF (far-end receives and lost efficacy) position [with reference among Figure 169 2.].Point out in passing, all the other 3 [with reference among Figure 169 3.] use at present.

When detecting B3 (BIP8) parity error in the VC3 signal that is receiving, the FEBE position is used for the odd parity figure place is transmitted back to relative device (transmitter side).For example, shown in Figure 170, the error-detecting number of times that obtains in the B3 byte terminal processes is set at FEBE error-detecting number of times.Shown in Figure 170, outside can (16 kinds) state, stipulate 8 kinds of states at present with 4 indications.

Another relative device of signalling trouble that the receiver side device that the FERF position is used for the VC3 signal being carried out terminal processes takes place, " 0 " expression normal condition wherein, and " 1 " expression " the VC3 far-end receives inefficacy " notify status.

Receiver side monitors the G1 byte, when the code of a high position 4 (FEBE positions) that receives is not " 0000 ", detects the error amount in the relative device, and as 1 warning it is counted.When detecting the FERF position for " 1 ", receiver side is identified as FERF with it and reports to the police.In this case, when being consecutively detected the FERF position and surpassing 10 frames, produce FERF and report to the police for " 1 ".When being consecutively detected the FERF position and surpassing 10 frames, RERF reported to the police eliminate for " 0 ".

(C5) V5 byte terminal processes

Be included in the V5 byte among VC2-POH 236 or the VC12-POH 237, for example have the form shown in Figure 171.In the V5 byte, with high-order 2 be defined as the BIP2 position [with reference among Figure 171 1.], with subsequently 1 be defined as the FEBE position [with reference among Figure 171 2.], with 1 of being connected on the back be defined as the RFI position [with reference among Figure 171 3.], again will be subsequently 3 be defined as the signal mark [with reference among Figure 171 4.], and with 1 of LSB be defined as the FERF position [with reference among Figure 169 5.].

Therefore, receiver side can detect the channel status of VC2/VC12 signal etc. by the terminal processes to the V5 byte by the error (error code) on the BIP2 operation detection passage, from signal mark detection mapping structure, from the FERF position.

In above-mentioned BIP2 operation, similar with the BIP8 operation that the front illustrated to B3, carry out even parity.The method that the BIP2 operation is adopted is for example, shown in Figure 172 (a), to carry out parity calculations every (each byte) of enumeration data.Therefore, carry out parity count by the even bit and the odd bits of a byte, and shown in Figure 172 (b) with 2 indication counter results of a high position of V5 byte.

Receiver side is in the enumeration data district by a multi-frame of the VC2/VC12 signal shown in the webbed region among Figure 173, carry out parity calculations every 2, and the BIP2 position of result of calculation with the V5 byte that extracts from next frame compared, so as to the odd parity of two positions detecting MSB and LSB.When in 1 multi-frame, detecting odd parity (maximum 2), produce 1 warning.

When receiver side detects V5 (BIP2) odd parity of the VC2/VC12 of reception, shown in Figure 174, odd parity figure place (detected error amount in the V5 byte) is set at FEBE, and is transmitted back to relative device.The FEBE position of V5 byte at present can be with a bit representation two states, thus when detected number of bit errors in the V5 byte be 2 or 2 it to be defined as all the time when above and to be set at " 1 ".

As the signal mark of above-mentioned V5 byte, for example, shown in Figure 175, be defined as certain value of setting according to the mapping structure of VC2/VC12 signal [3 (bit number is the mapping code of B5～B7)].As the signal mark, identical with C2 in being included in VC3-POH 235, when this VC2/VC12 signal does not hold net load, all be set at " 0 " of expression UNEQ.

Receiver side monitors this signal mark.For example, when the V5 byte that is consecutively detected its signal mark indication UNEQ (all being " 0 ") surpassed 4 frames, receiver side produced the UNEQ detection alarm.When not being the V5 byte of UNEQ when surpassing 5 frames when what be consecutively detected the indication of its signal mark, receiver side is eliminated the UNEQ detection alarm.

At this moment, the reception desired value of the signal mark that will set by administrative staff of receiver side and actual reception to the value of signal mark compare.When detecting the signal mark for continuous 7 times when inconsistent, receiver side produces mismatch (SLM) detection alarm.When detecting signal mark unanimity continuous 3 times, the SLM detection alarm is eliminated.

Another relative device of signalling trouble that the receiver side device that the FERF position is used for the VC2/VC12 signal being carried out terminal processes takes place, " 0 " expression normal condition wherein, and " 1 " expression " VC2/VC12 Far End Receive Failure " notify status.

Receiver side monitors the FERF position of V5 byte.When detecting the FERF position for " 1 ", receiver side is identified as FERF with it and reports to the police.In this case, when being consecutively detected the FERF position and surpassing 10 frames, produce FERF and report to the police for " 1 ".When being consecutively detected the FERF position and surpassing 10 frames, RERF reported to the police eliminate for " 0 ".

(C6) performance monitoring (PM) function

The performance monitoring function is a kind of function that is used for the transmission line maintenance of line quality monitoring and use.In the one-period of the PM reset pulse of supplying with by microcomputer, odd even error code (BIP8 and the BIP2) number and the FEBE error that detect are counted, and with the hereinafter described microcomputer of count results notice.

Figure 176 (a)～176 (f) expression is to an example of the performance monitoring operation of BIP error.Figure 177 (a)～177 (g) expression is to an example of the performance monitoring operation of FEBE error.

But the pointer that each channel on 243 pairs of STM-1 frames of above-mentioned pointer processing apparatus (multiplexed data) (by the variant signal specification that leaves in the STM-1 frame) walks abreast is handled.For this reason, pointer processing apparatus 243 has pointer detecting unit 246 that number equates with maximum 63 channels, ES memory 247, pointer processing unit 248 etc.This will cause the very big increase of circuit scale, power consumption, circuit (wiring) number etc. of device.

In above-mentioned pointer processing apparatus 243,, in each ES memory 247, data clock is transferred to the clock of device side from the clock of transmission line trackside for switching the TU pointer.This will require the ES memory to have a lot of progression, so that absorb the shake of clock of the clock of transmission line trackside and device side and the influence of drift, equally also will cause the very big increase of the circuit scale, power consumption, distribution number etc. of device.

In addition, in above-mentioned pointer processing apparatus 243, be to carry out respectively with different hardware to the processing (specifically, the pointer change is handled) of AU4 pointer and to the processing of TU pointer.When the signal cross in signal in the VC4 level and the VC3/VC2/VC12 level connects, different hardware must be provided, for example be used for each signal cross of VC4 level and connect that (TSI: cross-connection unit 224 time slot interchange) and be used for the cross-connection unit 225 that each signal cross of VC3/VC2/VC12 level connects equally also will cause the scale of line termination device 306 to increase.

In addition, above-mentioned SDH transmission method separates TU format signal and STM-1 frame, and each TU format signal is carried out the POH terminal processes concurrently., must provide and corresponding maximum 63 POH terminal processes devices that have with spline structure of 63 channels in the line termination device 306 for this reason, equally also will cause the very big increase of the circuit scale and the power consumption of device.

Summary of the invention

In view of the above problems, the purpose of this invention is to provide a kind of pointer processing apparatus that in the SDH transmission system, uses, in the mode of serial the STM-1 frame is carried out (TU) pointer and handle, thereby can reduce circuit scale, power consumption, distribution number etc. to the utmost.

Another object of the present invention provides a kind of pointer processing apparatus that uses in the SDH transmission system, wherein be reduced to minimum degree for the required memory of clock that data clock is transferred to device side from the clock of transmission line trackside, thereby can reduce circuit scale, power consumption, distribution number etc. to the utmost, and when the frame of interconnection unlike signal specification, can use general cross connection device.

Another object of the present invention provides a kind of POH terminal processes device, POH terminal processing method, reaches pointer/POH terminal processes device, it is characterized in that: the multiplex signal that sends in the SDH transmission system is carried out the POH terminal processes and need not this multiplex signal is assigned to each channel with serial mode, thereby can reduce unit scale and power consumption to the utmost.

Therefore, the pointer terminal processes device in the SDH transmission system provided by the invention comprises: address-generation unit is used for address assignment is given each channel of the multiplexed data of being imported; The pointer extracting unit is used to extract the pointer byte that comprises H1/V1 byte and H2/V1 byte at least; The pointer processing unit is used to carry out desired pointer and handles; RAM, the information sets that is used to keep to represent, the information sets that begins by the pointer byte that receives to make pointer action required by the pointer byte that pointer extracting unit or pointer processing unit obtain in the zone of the address indication that each channel is produced by address-generation unit with each channel of extracting from multiplexed data, and begin as pointer action after the information sets that obtains of result; And the RAM control unit, be used to control writing/the read operation order of RAM, handle thereby multiplexed data is carried out pointer with serial mode.

According to the present invention, pointer terminal processes device in the SDH transmission system, in RAM, each channel is kept handling necessary various information sets from what multiplexed data obtained for carrying out pointer with serial mode, can carry out the pointer processing with serial mode thereby this multiplexed data need not be assigned to each channel.Therefore, do not need to provide being used to of equating with a plurality of numbers of channel to carry out the circuit that pointer is handled, thus can reduce to the utmost device (circuit) scale, power consumption, and functional block (circuit) between the distribution number.

The present invention also provides a kind of POH terminal processes device in the SDH transmission system, be used for its information multiplexed multiplex signal on a plurality of channels that sends in the SDH transmission system is carried out the POH terminal processes, this device comprises: the POH terminal operation processing unit public to all channels is used for that multiplex signal is carried out the POH terminal operation and handles; And the memory cell that can read and write flexibly, be used for being stored in the operating result that POH terminal operation processing unit carries out each channel; When this multiplex signal is carried out the POH terminal processes, this POH terminal processes device uses in POH terminal operation processing unit in the stored information relevant with respective channels of memory cell storage and carries out the processing of POH terminal operation, and the POH terminal operation result who obtains is stored in the respective channels memory block of memory cell, just can carry out the POH terminal operation and handle thereby this multiplex signal need not be assigned to each channel this multiplex signal.

The present invention also provides a kind of POH terminal processing method that uses in the SDH transmission system, it may further comprise the steps: when multiplexed signal carries out the POH terminal processes on a plurality of channels to its information of sending in the SDH transmission system, using the stored information relevant with the operation of POH terminal processes of storing with respect to respective channels in the memory cell that can read and write flexibly to carry out the POH terminal operation in the POH terminal operation processing unit public to all channels handles, and the POH terminal operation result who obtains is stored in the memory block that respective channels uses, can carry out the POH terminal operation and handle thereby this multiplex signal need not be assigned to each channel.

According to POH terminal processes device of the present invention and POH terminal processing method, can in the public POH terminal operation processing unit of all channels, carry out the POH terminal operation and handle, and this multiplex signal need not be assigned to each channel the multiplex signal that in the SDH transmission system, sends.Therefore, do not need to install and being used to of being equated by the multiplexed number of channel of multiplex signal carried out the circuit that the POH terminal operation is handled, thereby reduce (circuit) scale, power consumption etc. of POH terminal processes device to the utmost.

The present invention also provides a kind of POH terminal processes device in the SDH transmission system, be used for its information multiplexed multiplex signal on a plurality of channels that sends in the SDH transmission system is carried out the POH terminal processes, this device comprises: the POH terminal operation processing unit public to all channels is used for that multiplex signal is carried out the POH terminal operation and handles; And the memory cell that can read and write flexibly, be used for being stored in the operating result that POH terminal operation processing unit carries out; This device is characterised in that: POH terminal operation processing unit comprises J1/J2 byte serial terminal processes unit, is used for serial mode the j1 byte and the J2 byte that comprise being carried out terminal processes in this multiplex signal; B3/V5 byte serial terminal processes unit is used for serial mode the B3 byte that comprises and the BIP of V5 byte being carried out terminal processes in this multiplex signal, and the BIPPM of B3 byte and V5 byte is carried out terminal processes; UNEQ/SLM serial terminal processing unit is used for serial mode the C2 byte that comprises and the UNEQ of V5 byte being carried out terminal processes in this multiplex signal, and with serial mode the SLM of C2 byte and V5 byte is carried out terminal processes; And FEBE/FERF serial terminal processing unit, be used for the G1 byte that comprises and the FEBE of V5 byte being carried out terminal processes in this multiplex signal with serial mode, and the FEBEPM of G1 byte and V5 byte carrying out terminal processes with serial mode, the FERF to G1 byte and V5 byte carries out terminal processes in addition; Its feature also is: the operating result that cell stores is carried out each channel by J1/J2 byte serial terminal processes unit, B3/V5 byte serial terminal processes unit, UNEQ/SLM serial terminal processing unit and FEBE/FERF serial terminal processing unit, in addition, also provide information to J1/J2 byte serial terminal processes unit, B3/V5 byte serial terminal processes unit, UNEQ/SLM serial terminal processing unit and FEBE/FERF serial terminal processing unit.

According to the POH terminal processes device in the SDH transmission system of the present invention, can with serial mode to J1 and (or) the J2 byte carries out terminal processes, to detect the multi-frame pattern of multiplex signal, to B3 and (or) the V5 byte carries out terminal processes, to obtain BIP (BIPPPM) from multiplex signal, to C2 and (or) the V5 byte carries out terminal processes, to obtain UNEQ and SLM, to G1 and (or) the V5 byte carries out terminal processes, to obtain FEBE (FEBEPM), and to G1 and (or) the V5 byte carries out terminal processes, to obtain the public FERF of all channels.Therefore, do not need the circuit that is used to carry out above-mentioned every processing that equates with the respective channels number is installed, thereby reduce the scale and the power consumption of device to the utmost.

The present invention also is provided at the pointer/POH terminal processes device in the SDH transmission system, being used for that its information multiplexed signal on a plurality of channels that sends in the SDH transmission system is carried out pointer handles and the POH terminal processes, this device comprises: the list pointer processing unit, be used for multiplex signal being carried out pointer and handle, and this multiplex signal need not be assigned to each channel with serial mode; And serial POH terminal processes unit, be used for multiplex signal being carried out the POH terminal processes, and this multiplex signal need not be assigned to each channel with serial mode.

According to the pointer/POH terminal processes device in the SDH transmission system of the present invention, can carry out pointer processing and the processing of POH terminal operation to the multiplex signal that in the SDH transmission system, sends with serial mode, and this multiplex signal need not be assigned to each channel, thereby can realize this device with the scale of minimum and minimum power consumption.

Description of drawings

Fig. 1 and 2 is the block diagram of expression form of the present invention.

Fig. 3 is the block diagram of major part structure of the line termination device that pointer processing apparatus was suitable for of the expression embodiment of the invention.

Fig. 4 is the block diagram of TU pointer processing unit major part in the pointer processing apparatus of expression present embodiment.

Fig. 5 is the block diagram of another kind of structure of the TU pointer processing unit major part of expression present embodiment.

Fig. 6 is the block diagram of address-generation unit detailed structure in the TU pointer processing unit of expression present embodiment.

Fig. 7 is the figure of an example of ATT of the operation of the expression address-generation unit that is used to illustrate present embodiment.

Fig. 8 is the block diagram of the another kind of detailed structure of address-generation unit of expression present embodiment.

Fig. 9 is the block diagram of the address conversioning unit detailed structure of expression present embodiment.

Figure 10 is the figure of operation of the address conversioning unit of expression present embodiment.

Figure 11 is the block diagram of the 1st pointer converting unit structure that has in the pointer processing apparatus of expression present embodiment.

Figure 12 is the figure that is illustrated in data content one example that keeps in the RAM of present embodiment.

Figure 13 is the block diagram of TU pointer processing unit structure that the 2nd pointer converting unit of present embodiment is noticed in expression.

Figure 14 is the block diagram of detailed structure of the 2nd pointer converting unit of expression present embodiment.

Figure 15 is that expression notices that the reception pointer value of present embodiment keeps the block diagram of the TU pointer processing unit structure of function.

Figure 16 is 3 continuous consistent block diagrams that receive the pointer processing unit structure of measuring ability of normal pointer value that present embodiment is noticed in expression.

Figure 17 is the block diagram of pointer processing unit structure that the LOP measuring ability of present embodiment is noticed in expression.

Figure 18 is the block diagram of pointer processing unit structure that the INC/DEC reception result recognition function of present embodiment is noticed in expression.

Figure 19 is the block diagram of detailed structure of the ternary counting unit of expression present embodiment.

Figure 20 is that expression notices that the alarm condition of present embodiment shifts the block diagram of the pointer processing unit structure of measuring ability.

Figure 21 is the block diagram of detailed structure of the counting control unit of expression present embodiment.

Figure 22 is the block diagram of pointer processing unit structure that the AIS state transitions measuring ability of present embodiment is noticed in expression.

Figure 23 is the figure that is illustrated in data content one example that keeps in the RAM of present embodiment.

Figure 24 is the existing block diagram that keeps the pointer processing unit structure of function with pointer value that present embodiment is noticed in expression.

Figure 25 is the block diagram of pointer processing unit structure that SPE lead byte (J1/V5 byte) recognition function of present embodiment is noticed in expression.

Figure 26 is a kind of block diagram of variation of the TU pointer processing unit of expression present embodiment.

Figure 27 is the block diagram of the major part structure of a pointer processing unit in this variation of expression.

Figure 28 is the block diagram of the major part structure of this pointer processing unit in this variation of expression.

Figure 29 is the block diagram of the major part structure of the RAM control unit in this variation of expression.

Figure 30 is the mapping set point registers group of expression in this variation and the block diagram of the detailed structure of selected cell.

Figure 31 is the block diagram that the pointer processing unit structure of SPE lead byte (J1/V5 byte) recognition function in this variation is noticed in expression.

Figure 32 is the block diagram that the pointer processing unit structure of the pointer change function in this variation is noticed in expression.

Figure 33 is the figure that switches expression being used to of keeping in this variation data content one example of pointer in RAM.

Figure 34 is the block diagram that writes (reading) number of words counter structure in this variation of expression.

Figure 35 is the block diagram of the another kind of structure that writes (reading) number of words counter in this variation of expression.

Figure 36 is the block diagram that is illustrated in the TU3/TU2/TU12 shared cell structure in writing in this variation (reading) the number of words counter.

Figure 37 is the block diagram that is illustrated in the TU2/TU12 shared cell structure in writing in this variation (reading) the number of words counter.

Figure 38 is the block diagram of pointer processing unit structure that the AU4 pointer processing unit of present embodiment is noticed in expression.

Figure 39 is the block diagram of ES memory cell structure in the TU pointer processing unit of expression present embodiment.

Figure 40 is the block diagram that the TU pointer in the TU pointer processing unit of expression present embodiment calculated and inserted cellular construction.

Figure 41 is the block diagram that the TU pointer in the TU pointer processing unit of expression present embodiment calculated and inserted cellular construction.

Figure 42 is the block diagram of variation of the pointer processing apparatus of the expression AU4 pointer processing unit of noticing present embodiment.

Figure 43 is the block diagram of variation of the pointer processing apparatus of the expression AU4 pointer processing unit of noticing present embodiment.

Figure 44 schematically represents the block diagram of an example of the cross connection device of present embodiment.

Figure 45～50,51 (a)～51 (C), 52 (a)～52 (C), 53 and 54 (a)～54 (C) are the figure that is used for illustrating the effect that obtains at the present embodiment pointer processing apparatus.

Figure 55 is the block diagram of expression another embodiment of the present invention.

Figure 56 is the block diagram of major part structure of the line termination device that is suitable for of POH terminal processes device of the expression embodiment of the invention.

Figure 57 is the block diagram that the line termination device structure of the TU pointer processing unit of present embodiment and POH terminal processes unit is noticed in expression.

Figure 58 is the TU pointer serial process unit of expression present embodiment and the block diagram of TU pointer timing generation unit structure.

Figure 59 is the block diagram of the address-generation unit detailed structure of expression present embodiment.

Figure 60 is the block diagram of pointer processing unit structure that SPE lead byte (J1/V5 byte) recognition function of present embodiment is noticed in expression.

Figure 61 is the block diagram of TU pointer processing unit structure that the signal specification recognition function of present embodiment is noticed in expression.

Figure 62 is the block diagram of the POH terminal processes cellular construction of expression present embodiment.

The block diagram of the basic structure of each terminal processes unit of Figure 63 and 64 expression present embodiments.

Figure 65 (a)～65 (t) is the time diagram of basic operation that is used to illustrate the terminal processes unit of present embodiment.

Figure 66 is the block diagram of the timing generation unit structure of expression present embodiment.

Figure 67 (a)～67 (q) is the time diagram of operation that is used to illustrate the timing generation unit of present embodiment.

Figure 68 is the block diagram of the timing generation unit detailed structure of expression present embodiment.

Figure 69 is the block diagram of the phase-shift unit detailed structure of expression present embodiment.

Figure 70 is the expense counter RAM holding unit of expression present embodiment and the block diagram of expense counter serial process unit detailed structure.

Figure 71 is the block diagram of the POH timing signal for generating unit detailed structure of expression present embodiment.

Figure 72 is the block diagram of the bald facies unit detailed structure of POH timing signal of expression present embodiment.

Figure 73 is the block diagram that the LOM of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 74 is the block diagram that the FRNO of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 75 is the block diagram that the BIP2 of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 76 is the block diagram that the SL of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 77 is the block diagram that the FERF of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 78 is the block diagram that the reception desired value of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 79 is the block diagram that the BIPPM of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 80 is the block diagram that the FEBEPM of expression present embodiment keeps RAM operation control unit detailed structure.

Figure 81 (a)～81 (h) is the time diagram of operation that is used to illustrate the timing generation unit of present embodiment.

Figure 82 (a)～82 (p), 83 (a)～83 (t) and 84 (a)～84 (f) are the time diagrams of operation that is used to illustrate the timing generation unit of present embodiment.

Figure 85 is the block diagram of the J1/J2 byte terminal processes cellular construction of expression present embodiment.

Figure 86 is the multi-frame pattern serial detecting unit of expression present embodiment and the block diagram of LOM holding unit detailed structure.

Figure 87 is the multi-frame string row control unit of expression present embodiment and the block diagram of FRNO holding unit detailed structure.

Figure 88 is the figure of an example of the FRNO of the expression present embodiment form that keeps RAM.

Figure 89 is the time diagram that the FRNO that is used to illustrate present embodiment keeps the operation timing of RAM.

Figure 90 is the figure that the FRNO of expression present embodiment keeps an example of interior information of RAM and the relation between the frame number.

Figure 91 is the block diagram of the LOM serial detecting unit detailed structure of expression present embodiment.

Figure 92 is the block diagram of the CRC serial detecting unit detailed structure of expression present embodiment.

Figure 93 is the block diagram of another kind of detailed structure of the CRC serial detecting unit of expression present embodiment.

Figure 94 is the block diagram of the TIM serial detecting unit detailed structure of expression present embodiment.

Figure 95 is the block diagram of the reception desired value holding unit detailed structure of expression present embodiment.

Figure 96 is the figure of an example of the EXP1 of the expression present embodiment data format that keeps RAM.

Figure 97 is the figure of an example of the EXP2 of the expression present embodiment data format that keeps RAM.

Figure 98 is the time diagram of operation timing that is used to illustrate the reception desired value holding unit of present embodiment.

Figure 99 is the figure of an example of the EXP1/EXP2 of the expression present embodiment address contents that keeps RAM.

Figure 100 is the figure of an example of the relation of the EXP1/EXP2 that the is illustrated in present embodiment address, frame number and the TU interchannel that keep RAM.

Figure 101 is used to illustrate the EXP1 of present embodiment and the figure that EXP2 keeps the switching controls of RAM.

Figure 102 is the block diagram of the alarm bit holding unit detailed structure of expression present embodiment.

Figure 103 (a)～103 (h), Figure 104 (a)～104 (l), Figure 105 (a)～105 (n), Figure 106 (a)～106 (k) and Figure 107 (a)～107 (n) are used to illustrate the time diagram of the operation of present embodiment J1/J2 byte terminal processes unit.

Figure 108 and 109 is block diagrams of the BB3/V5 byte terminal processes cellular construction of expression present embodiment.

Figure 110 is the BIP error serial detecting unit of expression present embodiment and the block diagram of BIP2 holding unit detailed structure.

Figure 111 is the block diagram of the BIP8 error serial detecting unit detailed structure of expression present embodiment.

Figure 112 is the BIPPM serial detecting unit of expression present embodiment and the block diagram of BIPPM holding unit detailed structure.

Figure 113 is the figure of an example of the BIPPM of the expression present embodiment data format that keeps RAM.

Figure 114 is the time diagram that the BIPPM that is used to illustrate present embodiment keeps the operation timing of RAM.

Figure 115 is the figure of an example of the BIPPM of the expression present embodiment address contents that keeps RAM.

Figure 116 and 117 is used to illustrate the EXP1 of present embodiment and the figure that EXP2 keeps the switching controls of RAM.

Figure 118 is the block diagram of the PMRAM address control unit detailed structure of expression present embodiment.

Figure 119 is the block diagram of the BIPPM count value initialization control unit detailed structure of expression present embodiment.

Figure 120 (a)～120 (f), Figure 121 (a)～121 (o), Figure 122 (a)～122 (n), Figure 123 (a)～123 (q) and Figure 124 (a)～124 (o) are the time diagrams of operation that is used to illustrate the B3/V5 byte terminal processes unit of present embodiment.

Figure 125～128th, the block diagram of the another kind of structure of the B3/V5 byte terminal processes unit of expression present embodiment.

Figure 129 is the block diagram of the UNEQ serial detecting unit detailed structure of expression present embodiment.

Figure 130 is the block diagram of the SLM serial detecting unit detailed structure of expression present embodiment.

Figure 131 is the block diagram of the alarm bit holding unit detailed structure of expression present embodiment.

Figure 132 (a)～132 (z) and 132 (α) are the time diagrams of operation that is used to illustrate the C2/V5 byte terminal processes unit of present embodiment.

Figure 133 and 134 is block diagrams of another kind of structure of the C2/V5 byte terminal processes unit of expression present embodiment.

Figure 135～137th, the block diagram of the G1/V5 byte terminal processes cellular construction of expression present embodiment.

Figure 138 is the block diagram of the FEBE detecting unit detailed structure of expression present embodiment.

Figure 139 is the FEBEPM serial process unit of expression present embodiment and the block diagram of FEBEPM holding unit detailed structure.

Figure 140 is the block diagram of the FEBEPM count value initialization control unit detailed structure of expression present embodiment.

Figure 141 is the FERF serial process unit of expression present embodiment and the block diagram of FERF holding unit detailed structure.

Figure 142 is the block diagram of the FERF alarm bit holding unit detailed structure of expression present embodiment.

Figure 143～144th, the block diagram of the another kind of structure of the G1/V5 byte terminal processes unit of expression present embodiment.

Figure 145 (a)～145 (x), Figure 146 (a)～146 (q) and Figure 147 (a)～147 (s) are the time diagrams of operation that is used to illustrate the G1/V5 byte terminal processes unit of present embodiment.

Figure 148 is the figure that is used for illustrating the hierarchy of SDH transmission system.

Figure 149 is the figure of the frame format of the STM-1 in the expression SDH transmission system.

Figure 150 is the figure that is used to illustrate the deposit position of VC4 in the STM-1 frame.

Figure 151 is the figure of the frame format of the TU3 in the expression SDH transmission system.

Figure 152 is the figure that is used to illustrate the deposit position of VC3 in the TU3 frame.

Figure 153 is the figure of the frame format of the TU2 in the expression SDH transmission system.

Figure 154 is the figure that is used to illustrate the deposit position of VC2 in the TU2 frame.

Figure 155 is the figure of the frame format of the TU12 in the expression SDH transmission system.

Figure 156 is the figure that is used to illustrate the deposit position of VC12 in the TU12 frame.

Figure 157 is the figure of the pointer format in the expression SDH transmission system.

Figure 158 is the figure that is used for illustrating the state transitions of SDH transmission system pointer value.

Figure 159 is the figure of an example of expression SDH transmission network.

Figure 160 represents the figure of an example of pointer processing unit.

Figure 161 is the figure that is used for illustrating the mismatch alarm detection method of SDH transmission system.

Figure 162 is the figure of the form of the J1/J2 byte (channels track signal) in the expression SDH transmission system.

Figure 163 is the figure that is used for illustrating the CRC operational processes of SDH transmission system.

Figure 164 is the figure of the form of the B3 byte in the expression SDH transmission system.

Figure 165 (a), 165 (b) and 166 are the figure that are used for illustrating the BIP8 operation of SDH transmission system.

Figure 167 is the figure of the form of the C2 byte in the expression SDH transmission system.

Figure 168 is the figure that is used for illustrating the value of setting (mapping code) in the C2 of SDH transmission system byte.

Figure 169 is the figure of the form of the G1 byte in the expression SDH transmission system.

Figure 170 is the figure that is used for illustrating the value of setting (FEBE code) in the G1 of SDH transmission system byte.

Figure 171 is the figure of the form of the V5 byte in the expression SDH transmission system.

Figure 172 (a) and 172 (b) are the figure that is used for illustrating the BIP2 operational processes of SDH transmission system.

Figure 173 is the figure that is used for illustrating the BIP2 operational processes of SDH transmission system.

Figure 174 is the figure that is used for illustrating the value of setting (FEBE code) in the V5 of SDH transmission system byte.

Figure 175 is the figure that is used for illustrating the value of setting (mapping code) in the V5 of SDH transmission system byte.

Figure 176 (a)～176 (f) is the time diagram that the performance monitoring (BIPPM) that is used for illustrating the SDH transmission system is handled.

Figure 177 (a)～177 (g) is the time diagram that the performance monitoring (FEBEPM) that is used for illustrating the SDH transmission system is handled.

Figure 178 is the figure of expression cross connection device one example.

Embodiment

(a) explanation of form of the present invention

Followingly various forms of the present invention are described with reference to accompanying drawing.

Fig. 1 is the block diagram of expression a kind of form of the present invention.Pointer processing apparatus in the SDG transmission system shown in Figure 1 has address-generation unit 1, pointer extracting unit 2, pointer processing unit 3, RAM (random access memory) 4 and RAM control unit 5, is used for the pointer of the multiplexed data imported is carried out serial process.

Address-generation unit 1 is given address assignment each channel of the multiplexed data of being imported.Pointer extracting unit 2 extracts the pointer byte that comprises H1 byte or V1 byte (H1/V1 byte) and H2 byte or V2 byte (H2/V2 byte) at least.Pointer processing unit 3 carries out necessary pointer to be handled.

RAM4 keep the information sets of representing by the pointer byte that above-mentioned pointer extracting unit 2 and pointer processing unit 3 obtain in the zone of the address indication that is produced by 1 pair of each channel of address-generation unit, the information sets that begins to make pointer action required by the pointer byte that receives with each channel of extracting from multiplexed data, and begin as pointer action after result's information sets.RAM control unit 5 control RAM write/the read operation order.

Pointer processing apparatus with said structure of the present invention will deposit RAM in by above-mentioned each information sets that pointer extracting unit 2 and pointer processing unit 3 are obtained from multiplexed data according to the address that address-generation unit 1 produces, thereby with serial mode the multiplexed data of being imported is carried out the pointer processing, and this multiplexed data need not be separated into the data (need not convert this multiplexed data to parallel data) on each channel.

According to above-mentioned pointer processing apparatus, do not need to provide the circuit that is used for the pointer processing that equates with a plurality of numbers of channel thereby can reduce device (circuit) scale, power consumption, the distribution number between function (circuit) piece etc. to the utmost.

Above-mentioned RAM4 can be divided into 1RAM and 2RAM.In this case, 1RAM keeps the information sets by the H1/V1 byte representation of above-mentioned reception pointer byte, and 2RAM keep by the information sets of the H2/V2 byte representation of the pointer byte of above-mentioned reception, begin to make the required information sets of above-mentioned pointer action and begin as pointer action after result's information sets.

Pointer processing apparatus of the present invention writes 1RAM according to the timing of H1/V1 byte with above-mentioned information sets, reads this information sets according to the timing of H2/V2 byte simultaneously.On the other hand, this pointer processing apparatus can write above-mentioned various information sets or read from 2RAM according to the timing of H2/V2 byte.

To reduce (H1/V1 regularly) access times like this to above-mentioned 2RAM.Therefore, can further reduce the power consumption of RAM4.

Specifically, above-mentioned pointer processing unit 3 can have the 1st pointer converting unit, is used to compress the figure place of the H1/V1 byte of reception, so that the information after its figure place is compressed remains in the RAM4, thereby can reduce the figure place that should remain on the information sets in the RAM4.Consequently can reduce the necessary figure place of RAM4, thereby the RAM4 capacity in also reducing to use.

Except that above-mentioned the 1st pointer converting unit, pointer processing unit 3 also can have the 2nd pointer converting unit, the compressed information of figure place that is used for producing according to multiplexed data, by the 1st pointer converting unit, by the information sets of the H2/V2 byte representation of the pointer byte of above-mentioned reception, begin to make the required information sets of above-mentioned pointer action and begin as pointer action after result's information sets, produce pointer processing control signals and pointer result in the moment of extracting the H2/V2 byte from this multiplexed data, and these information sets are remained in the RAM4.Therefore, can be produced as each channel and carry out pointer and handle necessary various pointer processing control signals, or in a pointer processing unit 3, carry out common pointer and handle.Can reduce unit scale, power consumption, the distribution number between functional block etc. so to the utmost.

Pointer processing apparatus shown in Figure 1 can extract the information signal of the pointer value of each channel of indication from multiplexed data, and will remain in the RAM4 except that the low-order bit the MSB (highest significant position) of information signal, has latch cicuit in addition, position of MSB of the information signal that obtains when being used to keep signal specification when each channel of multiplexed data for TU3.In this case, will be used as the control signal that writes and read of above-mentioned latch cicuit by the signal that obtains after the address value of distributing to above-mentioned each channel of TU3 is deciphered.

Pointer processing apparatus of the present invention only remains on the low level beyond the MSB in the RAM4, thereby can further reduce the necessary figure place of RAM4.

Therefore, can further reduce the capacity of RAM4.When the signal specification was TU3, the value of above-mentioned MSB may be different with the value that obtains when the TU3.In this case, position of MSB is remained in the latch cicuit, in order to guaranteeing the required information of promising pointer processing all the time, so that can carry out this processing reliably.

Above-mentioned pointer processing unit 3 can have: the consistency detection unit, be used to detect the consistency between the reception pointer value of the frame of pointer value that receives and front, and the consistency detection result is remained in the RAM4 as an information; The pointer value converting unit that transfinites, when receiving the pointer byte of expression invalid information, be used for remain on pointer value in the RAM4 be converted to certain value that exceeds the pointer value scope and will change after information remain in the RAM4; And 3 continuous consistent detecting units that receive of normal pointer value, by consistency detection result's that expression is kept in the RAM4 signal and the logic product computing that the consistency detection result between the pointer byte value of prior pointer value and reception carries out, detect 3 receptions of unanimities continuously of normal pointer value.

Pointer processing unit 3 by consistency detection result that expression is kept in the RAM4 signal (information) and to the logic product computing that the consistency detection result of the pointer byte value of the pointer value that receives and reception carries out, detect 3 consistent continuously receptions of normal pointer value.Therefore, only can correctly carry out 3 continuous consistent detections that receive of normal pointer value to each channel with serial mode by the consistency detection result being remained in the RAM4, and need not repeatedly to count and each special circuit is provided, or provide each special circuit in order to keep the count results that equates with a plurality of numbers of channel in order to align the constant pointer value.

Therefore, the capacity of RAM can be reduced, unit scale, power consumption, the distribution number between functional block etc. can be reduced in addition equally to the utmost.

Above-mentioned pointer processing unit 3 can have the LOP detecting unit, is used to detect LOP (Loss Of Pointer) state.This LOP detecting unit can have counting control unit, be used for allowing the NDF of reception, null pointer reception, former frame to allow the count value of reception information and former frame, allow the number of times of reception continuously or the continuous reception number of times of null pointer to count to NDF according to a predetermined truth table according to NDF.

Pointer processing unit 3 only can detect the LOP state by allowing continuous number of times that receives or invalid continuous reception number of times to count to NDF.Therefore, can detect the LOP state of each channel, and need not to count and each special circuit is provided, or provide each special circuit in order to keep the count results that equates with a plurality of numbers of channel for the number of times that NDF is allowed receive continuously with serial mode.

In this case, can reduce unit scale, power consumption, the distribution number between functional block etc. to the utmost.

Except that above-mentioned LOP detecting unit, above-mentioned pointer processing unit 3 can also have INC/DEC reception result recognition unit, is used to discern INC/DEC (incremented/decremented) reception result.This INC/DEC reception result recognition unit can have: the INC/DEC detecting unit is used for detecting INC or DEC from the pointer byte that receives; And the filling control with n system counting unit suppresses the unit, be used for receive that NDF allows and INC/DEC after receive by INC/DEC image duration at n (n is a natural number) and to suppress to fill control, thereby prevent to receive the memory slip that causes continuously by INC/DEC.Adopt this configuration, pointer processing unit 3 remains on the reception result of the count results of n system counting unit and INC or DEC and is used to discern in the RAM of INC/DEC reception result, so that utilize the reception result of the INC/DEC that in RAM4, keeps, the count value of n system counting unit and the result who allows reception by the NDF that above-mentioned LOP detecting unit obtains, discern the INC/DEC reception result.

Above-mentioned pointer processing unit 3 only remains in the RAM that is used to discern the INC/DEC reception result by the reception result with INC or DEC can discern the reception result of INC or DEC, thereby does not need reception result both with the reception result of INC and DEC to remain on to be used to discern in the RAM of INC/DEC reception result.Can reduce the necessary figure place of RAM like this.

Therefore, except the power consumption that can reduce RAM, can also further reduce to be used to receive the capacity of the RAM of INC/DEC reception result.

Above-mentioned pointer processing unit 3 can have alarm condition and shift protected location.This alarm condition shifts protected location and has: have the counting control unit of tally function, as m (m is a natural number) level protective circuit, be used to carry out alarm condition and shift; And RAM, be used to protect alarm condition to shift, store up the count value of this counting control unit at this memory ram.Therefore, when receiving that alarm condition diverts the aim signal, pointer is handled processing unit 3 and is counted in counting control unit, if do not receive the alarm condition signal that diverts the aim, then with the count resets of counting control unit, when the count value of counting control unit reaches maximum, transfer to alarm condition, before receiving warning elimination condition, the count value of counting control unit is remained in the RAM4 as maximum, judge whether a relevant channel is in alarm condition thereby can whether reach maximum according to resulting count value when RAM4 reads count value.

Above-mentioned pointer processing unit 3 is only remained on the count value corresponding with the number of times of the signal that diverts the aim by respective channel address reception alarm condition in the RAM4 by counting control unit, thereby can discern the alarm condition of a plurality of channels with serial mode, simultaneously that RAM4 is required figure place is suppressed to bottom line.

In this case, do not need to provide respectively the circuit that is used to discern alarm condition that equates with a plurality of numbers of channel, thus can reduce to the utmost device scale, power consumption, and functional block between distribution number etc.

Above-mentioned pointer processing unit 3 can have the existing pointer value holding unit of using, and is used to keep the showing except that the reception pointer value of each channel that hardware in fact working to use pointer value.This now will be used to keep existing with in the RAM of pointer value except that above-mentioned now remaining on the low level the MSB of pointer value with the pointer value holding unit, has latch cicuit in addition, when the signal specification of each channel of multiplexed data is TU3, be used to latch position of MSB.In this case, will write and read the control signal of usefulness by the signal that obtains after the address value of a channel distributing to TU3 is deciphered as latch cicuit.

Pointer processing unit 3 can be produced as the pointer of each channel and handle the required existing pointer value of using, be used to keep existing and need not this is now remained on all positions of pointer value, thereby can reduce and be used to keep the existing required figure place of RAM with pointer value with in the RAM of pointer value.

Therefore, the required figure place of RAM that is used to keep existing usefulness pointer value be can reduce, thereby capacity and the power consumption of RAM helped to reduce.

Now use the pointer value holding unit except that above-mentioned, above-mentioned pointer processing unit 3 can also have SPE lead byte recognition unit, is used for j1 byte or the V5 byte of identification as the lead byte of SPE (net load is sealed synchronously).This SPE lead byte recognition unit has skew counting unit, be used to retrieve the lead byte of SPE, now read the existing pointer value of using from above-mentioned with the pointer value holding unit, by SPE being allowed signal and, discerning the position of the lead byte of SPE in the logic product computing that is offset count value and now carries out with the consistency detection result between the pointer value.

Pointer processing unit 3 with serial mode from now reading the existing pointer value of using with the pointer value holding unit, and by SPE being allowed signal and, discerning the position of the lead byte of SPE in the logic product computing that is offset count value and now carries out with the consistency detection result between the pointer value.Therefore, can discern the lead byte of the SPE of each channel with serial mode, and need not provide respectively equate with a plurality of numbers of channel be used to keep the existing pointer value circuit of using, or be used for circuit that deviant is counted.

Therefore, can reduce to the utmost device scale, power consumption, and functional block between distribution number etc.

Pointer processing apparatus shown in Figure 1 can have: mapping set point registers group, and each channel of TU3/TU2/TU12 that is used for being set in multiplexed data with what kind of signal specification shines upon; And signal specification selection circuit, be used for according to the signal specification of the address of distributing to each channel by address-generation unit 1 from a correlated channels of above-mentioned mapping set point registers group selection.This pointer processing apparatus is selected the signal specification of each channel of circuit identification multiplexed data by above-mentioned mapping set point registers group and signal specification, by providing the information relevant, in a public circuit, carry out pointer extraction and pointer processing according to the signal specification with the signal specification to pointer extracting unit 2, pointer processing unit 3 and RAM control unit 5.

Pointer processing apparatus of the present invention always can be identified in each channel of TU3/TU2/TU12 of multiplexed data and with what kind of signal specification shines upon, thereby can in a public circuit, carry out pointer extraction and pointer processing according to the signal specification, even and each channel exists with different signal specification mixing in multiplexed data, also need not to be provided with the equal pointer extracting unit 2 of the number of channel different, pointer processing unit 3 etc. with the signal specification.

Specifically, above-mentioned pointer processing apparatus has 3 TU3/TUG3 set point registers and 7 and is used for TU2/TUG2 set point register to each TU3/TUG3 set point register summation.This pointer processing apparatus also has: signal specification recognition unit, be used to judge whether a correlated channels is to be shone upon with TU3 by above-mentioned TU3/TUG3 set point register, and when this channel be not when shining upon with TU3, judge whether this channel is to be shone upon with TU2 or TU12 by above-mentioned TU2/TUG2 set point register, thus the signal specification of identification channel.

Pointer processing apparatus of the present invention can only carry out pointer with 24 all channels of set point register pair to be handled, and need not to have the set point register that equates with whole numbers of channel, promptly, set point register to TU3 is used for 3 kinds of signal specifications, set point register to TU2 is used for 21 channels, and the set point register of TU12 is used for 63 channels.

That is, can carry out pointer to all channels of set point register pair of about 1/3 (amounting to 24) with decreased number and handle, can be and need not to provide in accordance with the set point register (being used for 87 channels) of all signal specifications.Therefore, can reduce to the utmost device scale, power consumption, and functional block between distribution number etc.

Shown in Figure 1 can carry out the pointer processing apparatus that pointer extracts and pointer is handled according to the signal specification in a public circuit, offset counter be equipped with can by each signal specification, and select the count value of each offset counter according to the mapping set information that provides from mapping set point registers group, so that the position of the lead byte of identification SPE.

Even each channel exists with different signal specification mixing in multiplexed data, pointer processing apparatus of the present invention also can be discerned the processing of the lead byte position of SPE to each channel in all channels in a public circuit.

Above-mentioned pointer processing unit 3 has a RAM with ES (elasticity) memory function that is used to switch pointer, the information bit of the lead byte of SPE data that will obtain from the multiplexed data of being imported and expression SPE writes this RAM, and read, so that the leading position of the value identification SPE of the information bit of the SPE lead byte of reading from expression by the data that the timing of reading side will write RAM.

Therefore, pointer processing unit 3 can use RAM that a public switching pointer the uses leading position to all channel identification SPE with serial mode, so as to carrying out the switching of pointer.

Promptly, even each channel exists with different signal specification mixing in multiplexed data, also can be in a public circuit to the switching of line pointer of going forward side by side of the leading position of all channel identification SPE, thereby can reduce to the utmost device scale, power consumption, and functional block between distribution number etc.

Above-mentioned pointer processing apparatus can have: Writing/Reading number of words counter is used to control the RAM that above-mentioned switching pointer is used; And TU3 decoding circuit and TU2 decoding circuit, respectively the count value of TU3 and the count value of TU2 are deciphered, purpose is a switch count value between the setting constantly of the setting moment of TU3 mapping and TU2 mapping, in device, select any one output signal in the decoding circuit according to the signal specification, used as the signal of packing into of above-mentioned counter, therefore the Writing/Reading number of words counter of above-mentioned RAM can be used as a public counter when TU3 shines upon and when TU2 shines upon.

Pointer processing apparatus of the present invention is selected any one output signal in the decoding circuit, so as in the setting of TU3 mapping switch count value constantly and between the setting constantly of TU2 mapping, even thereby mixing exists different for example TU3 of signal specification and the channel of TU2 in multiplexed data, also can be counted the line number of Writing/Reading by a public counter.

Although need be used for 3 channels, need be used for the Writing/Reading number of words counter of 21 channels to TU2 TU3 in the past, and Writing/Reading number of words counter number can be reduced to a number that channel is required here, so can reduce to the utmost device scale, power consumption, and functional block between distribution number etc.

Above-mentioned pointer processing apparatus can have: Writing/Reading number of words counter is used to control the RAM that above-mentioned switching pointer is used; And TU3 with decoding circuit, TU2 with decoding circuit and TU12 decoding circuit, respectively the count value of TU3, the count value of TU2 and the count value of TU12 are deciphered, in order that the setting of TU3 mapping constantly, the setting of TU2 mapping switch count value constantly and between the setting constantly of TU12 mapping, in device, select any one output signal in the decoding circuit according to the signal specification, used as the load signal of above-mentioned counter, therefore the Writing/Reading number of words counter of above-mentioned RAM when shining upon, can be used as a public counter TU3/TU2/TU12.

Pointer processing apparatus of the present invention is selected any one output signal in the decoding circuit, so as to the setting of TU3 mapping constantly, the setting of TU2 mapping switch count value constantly and between the setting constantly of TU12 mapping, even thereby mixing exists signal specification different for example TU3, TU2 and the channel of TU12 in multiplexed data, also can be counted the line number of Writing/Reading by a public counter.

Fig. 2 is the block diagram of expression another kind of form of the present invention.Pointer processing apparatus in the SDG transmission system shown in Figure 2 has: AU4 pointer processing unit 6 is used for the AU4 pointer is handled; And TU pointer processing unit 7, be used for after handling, the TU pointer being handled by AU4 pointer processing unit 6.This pointer processing unit 6 has ES memory 6b, the ES that AU4 pointer detecting unit 6a, transfering clock use and writes counter 6c and ES read-out counter 6d.

AU4 pointer detecting unit 6a changes the AU4 pointer, and allows the signal of the j1 byte position of signal and indication VC4POH (path overhead) according to the clock generating VC4 of transmission line trackside.ES memory 6b is used for and will detects the signal that obtains behind the AU4 pointer is transferred to device side from the clock of transmission line trackside clock by AU4 pointer detecting unit 6a.

ES writes counter 6c according to the clock control of the transmission line trackside processing that writes to ES memory 6B.ES read-out counter 6d is according to the clock control of the device side processing of reading to ES memory 6b.

In having the pointer processing apparatus of the present invention of said structure, ES writes counter 6c and operates according to the clock of transmission line trackside, ES read-out counter 6d then operates according to the clock of device side, detection writes phase difference between counter 6c and the ES read-out counter 6d at ES, filling control, thereby in AU4 pointer processing unit 6, signal is sent to the clock of device side from the clock of transmission line trackside.

TU pointer processing unit 7 can carry out the TU pointer to the multiplexed data that obtains behind the transfering clock to be handled, thereby does not need to provide the ES level that is used for absorbing the clock signal influence of fluctuations that for example takes place when transfering clock that equates with whole numbers of channel.

According to above-mentioned pointer processing apparatus, can reduce scale, power consumption of this device etc. effectively.

Above-mentioned AU4 pointer processing unit 6 can have AU4 pointer calculating/insertion unit, is used for calculating the AU4 pointer and being inserted into according to transmit frame signals, and will supplies with TU pointer processing unit 7 by the data behind the AU4 pointer calculating/insertion unit insertion AU4 pointer.Pointer processing apparatus of the present invention can be according to the state by the processing procedure (filling control etc.) among the Data Control ES memory 6b behind the AU4 pointer calculating/insertion unit insertion AU4 pointer.

Therefore, can check the operating state of ES memory 6b at an easy rate.For example, as any problem takes place in pointer is handled, then problem identificatioin occurs in the processing of AU4 pointer still to the processing of TU pointer soon, thereby addresses this problem.

Above-mentioned pointer processing apparatus can have the selection circuit, be used to select by more the correct one's mistakes signal of AU4 pointer or of the AU4 pointer processing unit 6 with AU4 pointer calculating/insertion unit, and send this selected signal by the TU pointer processing unit signal of TU pointer of more correcting one's mistakes.Pointer processing apparatus of the present invention can be exported the signal that signal that its AU4 pointer changed or its TU pointer have changed selectively, thereby makes the device in the one-level of back adapt to these two kinds of signals with a device.Device size in the one-level of back will be reduced more.

Above-mentioned TU pointer processing unit 7 can have address-generation unit 1, pointer extracting unit 2, pointer processing unit 3, RAM4 and RAM control unit 5 as shown in Figure 1.Therefore, Fig. 1 illustrated as reference, TU pointer processing unit 7 shown in Figure 2 can carry out pointer to the multiplexed data of being imported with serial mode and handle (processing of TU pointer), and this multiplexed data need not be separated into the data (need not convert this multiplexed data to parallel data) on each channel.This will help to reduce the scale and the power consumption of device significantly.

Figure 55 is the block diagram of expression another form of the present invention.Its information that 1000 pairs in POH terminal processes device shown in Figure 55 sends in the SDH transmission system multiplexed signal on a plurality of channels carries out the POH terminal processes.This POH terminal processes device 1000 has: the POH terminal operation processing unit 1001 public to all channels is used for that multiplexed signal is carried out the POH terminal operation and handles; And the memory cell 1002 that can read and write flexibly, be used for being stored in the operating result that POH terminal operation processing unit 1001 carries out each channel.

When this multiplex signal is carried out the POH terminal processes, POH terminal processes device 1000 shown in Figure 55 uses in the stored information relevant with respective channels of memory cell 1002 stored and carry out the processing of POH terminal operation in POH terminal operation processing unit 1001, and the POH terminal operation result who obtains is stored in the memory block that respective channels uses, just can carry out the POH terminal operation to this multiplex signal and handle thereby multiplex signal need not be assigned to each channel with serial mode.

Above-mentioned POH terminal processes device 1000 can carry out the POH terminal operation to this multiplex signal with serial mode to be handled, and multiplex signal need not be separated to each channel.Therefore, do not need to install equate with the number of channel in the multiplex signal be used to carry out the circuit that the POH terminal operation is handled.

According to the present invention.Can reduce (circuit) scale and the power consumption of POH terminal processes device 1000 to the utmost.

Above-mentioned POH terminal processes device 1000 can have latch units, be used for temporary transient POH byte data of storing stored information relevant of reading and the multiplex signal that when carrying out the processing of POH terminal operation by POH terminal operation processing unit 1001, should handle from memory cell with respective channels, stored informations that this latch units are latched in keep in the memory cell 1002 and should offer POH terminal operation processing unit 1001 thereby will handle required stored information by required timing by the POH byte data in the multiplex signal of the detection Timing Processing of POH for the POH terminal operation.Therefore, POH terminal operation processing unit 1001 is only operated when needed.

Above-mentioned POH terminal processes device 1000 offers POH terminal operation processing unit 1001 with the stored information of respective channels and the POH byte data of handling in the required multiplex signal that should handle for the POH terminal operation by required timing, and POH terminal operation processing unit 1001 is only operated when needed.This can be further greatly limit reduce the power consumption of POH terminal processes device 1000.

Above-mentioned POH terminal operation processing unit 1001 for example can be configured to J1/J2 byte serial terminal processes unit, is used for serial mode the j1 byte and the J2 byte that comprise being carried out terminal processes in this multiplex signal.In this case, memory cell 1002 storages in addition, also provide information to this J1/J2 byte serial terminal processes unit by the operating result that J1/J2 byte serial terminal processes unit carries out each channel.

POH terminal processes device can be by the public J1/J2 byte serial terminal processes unit of all channels being carried out to the terminal processes of j1 byte [is the STM-1 frame as multiplex signal, then be included in VC (virtual container)-3 in] and to the terminal processes of the J2 byte in the POH of the signal specification that is included in its low digital stage multiplex signal different with the signal specification of the multiplex signal that comprises j1 byte.

Therefore, in POH terminal processes device 1000, do not need to install respectively the circuit that being used for of equating with the respective channels number carry out the circuit of terminal processes to j1 byte and the J2 byte is carried out terminal processes.Thereby can reduce the scale and the power consumption of POH terminal processes device 1000 to the utmost.

Specifically, above-mentioned J1/J2 byte serial terminal processes unit for example has following each unit:

Multi-frame pattern serial detecting unit is used for the multi-frame pattern with serial mode detection j1 byte and J2 byte;

Multi-frame pattern count Serial Control unit is used for the multi-frame number with serial mode control j1 byte and J2 byte;

LOM serial detecting unit is used for the LOM (Loss Of Multiframe) with serial mode detection j1 byte and J2 byte;

CRC serial detecting unit is used for the CRC (cyclic redundancy check (CRC)) with serial mode detection j1 byte and J2 byte; And

TIM serial detecting unit is used for the TIM (following the tracks of the directive mismatch) with serial mode detection j1 byte and J2 byte.

In this case, said memory cells 1002 storages provide stored information to multi-frame pattern serial detecting unit, multi-frame pattern count Serial Control unit, LOM serial detecting unit, CRC serial detecting unit and TIM serial detecting unit in addition by the operating result that above-mentioned multi-frame pattern serial detecting unit, multi-frame pattern count Serial Control unit, LOM serial detecting unit, CRC serial detecting unit and TIM serial detecting unit carry out each channel.

Therefore, POH terminal processes device 1000 can be by the public J1/J2 byte serial terminal processes unit of all channels is obtained for example various warning messages such as LOM, CRC, TIM with serial mode.

So, do not need POH terminal processes device 1000 is installed the circuit, the circuit that is used to detect CRC that are used to detect LOM respectively, is used to detect the circuit of TIM, thereby can further reduce the scale and the power consumption of device.

POH terminal operation processing unit 1001 shown in Figure 55 can be configured to B3/V5 byte serial terminal processes unit, is used for carrying out to the terminal processes of the BIP (bit interleave parity check) of the B3 byte that comprises in multiplex signal and V5 byte and to the terminal processes of the BIPPM (BIP performance monitoring) of above-mentioned byte B3 and V5 with serial mode.In this case, memory cell 1002 storages provide stored information to this B3/V5 byte serial terminal processes unit in addition by the operating result that B3/V5 byte serial terminal processes unit carries out each channel.

Therefore, POH terminal processes device 1000 can be by the public B3/V5 byte serial terminal processes unit of all channels is carried out the BIP terminal (operation) of B3 byte (as multiplex signal is the STM-1 frame, then is included in the POH of VC-3) is handled the BIP terminal processes that reaches the V5 byte in the POH that is included in its signal specification of hanging down digital stage multiplex signal different with the signal specification of the multiplex signal that comprises the B3 byte with serial mode.

So, do not need to install being used for of equating with the respective channels number to B3 byte and V5 byte carry out the BIP terminal processes circuit, thereby can further reduce the scale and the power consumption of device.

Specifically, B3/V5 byte serial terminal processes unit for example has following each unit:

BIP-8 operation serial process unit is used for serial mode multiplex signal being carried out BIP8 (bit interleave parity check-8) operation;

BIP2 operation serial process unit is used for serial mode multiplex signal being carried out BIP2 (bit interleave parity check-2) operation;

BIP error selected cell is used to select from BIP-8 operation serial process unit or the BIP error signal of BIP2 operation serial process unit output; And

BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being selected by BIP error selected cell.

In this case, said memory cells 1002 storages provide stored information to this BIPPM serial addition unit in addition by the operating result that above-mentioned BIPPM serial addition unit carries out each channel.

Therefore, POH terminal processes device 1000 can be by the public B3/V5 byte serial terminal processes unit of all channels is detected the BIP error that should detect by the POH terminal processes that each channel that has the unlike signal specification is usually carried out with serial mode.

So, do not need to install respectively the circuit that being used to of equating with the respective channels number detect the circuit of BIP8 error and be used to detect the BIP2 error, thereby can reduce the scale and the power consumption of device to the utmost.

B3/V5 byte serial terminal processes unit can have following each unit:

BIP8 operation serial process unit is used for serial mode multiplex signal being carried out the BIP8 operation;

The 1st BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being supplied with by BIP8 operation serial process unit;

BIP2 operation serial process unit is used for serial mode multiplex signal being carried out the BIP2 operation; And

The 2nd BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being supplied with by BIP2 operation serial process unit.

In this case, said memory cells 1002 has: the 1st memory cell, be used to store the result of every computing of being undertaken by above-mentioned the 1st BIPPM serial addition unit, and provide stored information to this 1BIPPM serial addition unit in addition; Reach the 2nd memory cell, be used to store the result of every computing of being undertaken by above-mentioned 2BIPPM serial addition unit, provide stored information to the 2nd BIPPM serial addition unit in addition.

That is, BIP error signal (BIPPM) is one by one tried to achieve by processing of BIP8 serial terminal and the processing of BIP2 serial terminal in above-mentioned B3/V5 byte serial terminal processes unit, then, exports among each BIPPM selectively.Therefore, can try to achieve BIPPM with simple structure with serial mode.Especially, if there is no need to use memory cell 1002 to the public maintenance BIPPM of all channels, then said structure is more effective.

This can provide great flexibility and versatility when constituting this device.

POH terminal operation processing unit 1001 shown in Figure 55 can be configured to UNEQ serial terminal processing unit, is used for serial mode the C2 byte that comprises and the UNEQ (not holding) of V5 byte being carried out terminal processes in multiplex signal.In this case, memory cell 1002 storages provide stored information to this UNEQ serial terminal processing unit in addition by the operating result that UNEQ serial terminal processing unit carries out each channel.

POH terminal processes device 1000 can by to the public UNEQ serial terminal processing unit of all channels with serial mode carry out to C2 byte (as multiplex signal is the STM-1 frame, then is included in the POH of VC-3) the UNEQ terminal processes, and to the UNEQ terminal processes of the V5 byte in the POH of the signal specification that is included in its low digital stage multiplex signal different with the multiplex signal that comprises the C2 byte.

Therefore, not needing to install being used for of equating with the respective channels number carries out the circuit of UNEQ terminal processes to C2 byte and V5 byte, thereby can reduce the scale and the power consumption of device to the utmost.

Specifically, above-mentioned UNEQ serial terminal processing unit for example has following each unit:

C2UNEQ indication serial detecting unit is used for detecting the C2 byte with serial mode and whether indicates UNEQ;

V5UNEQ indication serial detecting unit is used for detecting the V5 byte with serial mode and whether indicates UNEQ;

UNEQ indicates selected cell, is used to select the UNEQ by C2UNEQ indication serial detecting unit or the output of V5UNEQ indication serial detecting unit to indicate detection signal; And

UNEQ serial detecting unit is used for according to the UNEQ of the UNEQ indication detection signal of being selected by UNEQ indication selected cell with serial mode indication C2 byte and V5 byte.

In this case, said memory cells 1002 storages provide stored information to this UNEQ serial detecting unit in addition by the operating result that above-mentioned UNEQ serial detecting unit carries out each channel.

POH terminal processes device 1000 can be by the UNEQ that should indicate in the POH terminal processes that each channel that has the unlike signal specification is usually carried out with the serial mode indication the public UNEQ serial detecting unit of all channels.

So, do not need to install respectively the circuit that is used to indicate UNEQ that equates with the respective channels number, thereby can reduce the scale and the power consumption of device to the utmost.

Point out that in passing UNEQ serial terminal processing unit can have following each unit:

The 1st UNEQ serial detecting unit is used for according to the UNEQ of the UNEQ indication detection signal of being supplied with by above-mentioned C2UNEQ indication serial detecting unit with serial mode indication C2 byte;

The 2nd UNEQ serial detecting unit is used for according to the UNEQ of the UNEQ indication detection signal of being supplied with by above-mentioned V5UNEQ indication serial detecting unit with serial mode indication V5 byte; And

UNEQ indicates selected cell, is used to select the UNEQ by above-mentioned the 1st UNEQ serial detecting unit or the output of 2UNEQ serial detecting unit to indicate detection signal.

In this case, the said memory cells 1002 shown in Figure 55 has: the 1st memory cell, be used to store the testing result of each channel being carried out by the 1st UNEQ serial detecting unit, and provide stored information to this 1UNEQ serial detecting unit in addition; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned 2UNEQ serial detecting unit, provide stored information to the 2nd UNEQ serial detecting unit in addition.

That is, above-mentioned UNEQ serial terminal processing unit one by one carries out the UNEQ indication of C2 byte is handled and the UNEQ indication of V5 byte is handled with serial mode, then, exports in each UNEQ indication selectively.Therefore, can indicate UNEQ with simple structure with serial mode.Especially, if there is no need to use the memory cell 1002 that the public maintenance UNEQ of all signal specifications is indicated, then said structure is extremely effective.

Therefore, when constituting this device, the present invention can provide great flexibility and versatility.

POH terminal operation processing unit 1001 shown in Figure 55 can be configured to SLM serial terminal processing unit, is used for serial mode the C2 byte that comprises and the SLM (signal mark mismatch) of V5 byte being carried out terminal processes in multiplex signal.In this case, memory cell 1002 storages provide stored information to this SLM serial terminal processing unit in addition by the operating result that SLM serial terminal processing unit carries out each channel.

POH terminal processes device 1000 can be by the public SLM serial terminal processing unit of all channels is carried out to the SLM terminal processes of C2 byte and to the SLM terminal processes of V5 byte with serial mode.

Therefore, can further reduce the scale and the power consumption of device.

Specifically, above-mentioned SLM serial terminal processing unit for example has following each unit:

C2 mismatch serial detecting unit is used for detecting the mismatch that detects in the C2 byte with serial mode;

V5 mismatch serial detecting unit is used for detecting the mismatch that detects in the V5 byte with serial mode;

The detection of mismatch selected cell is used to select the detection of mismatch signal by C2 mismatch serial detecting unit and the output of V5 mismatch serial detecting unit; And

SLM serial detecting unit is used for according to the SLM of the detection of mismatch signal of being selected by above-mentioned detection of mismatch selected cell with serial mode indication C2 byte and V5 byte.

In this case, memory cell 1002 storages provide stored information to this SLMQ serial detecting unit in addition by the testing result that above-mentioned SLM serial detecting unit carries out each channel.

Therefore, POH terminal processes device 1000 can be by the public SLM serial unit of all channels is detected the SLM that should detect in the POH terminal processes that each channel that has the unlike signal specification is usually carried out with serial mode.

So, do not need to install respectively the circuit that is used to detect SLM that equates with the respective channels number, thereby can reduce the scale and the power consumption of device to the utmost.

Point out that in passing SLM serial terminal processing unit can have following each unit:

The 1st SLM serial detecting unit is used for according to the SLM of the detection of mismatch signal of being supplied with by above-mentioned C2 mismatch serial detecting unit with serial mode detection C2 byte;

The 2nd SLM serial detecting unit is used for according to the SLM of the detection of mismatch signal of being supplied with by above-mentioned V5 mismatch serial detecting unit with serial mode detection V5 byte; And

The SLM selected cell is used to select the SLM by the 1st SLM serial detecting unit or the output of the 2nd SLM serial detecting unit.

In this case, the said memory cells 1002 shown in Figure 55 has: the 1st memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 1st SLM serial detecting unit, and provide stored information to the 1st SLM serial detecting unit in addition; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned 2SLM serial detecting unit, provide stored information to the 2nd SLM serial detecting unit in addition.

That is, above-mentioned SLM serial terminal processing unit one by one carries out the SLM detection of C2 byte is handled and the SLM detection of V5 byte is handled with serial mode, then, exports among each SLM selectively.Therefore, can be with serial mode with simple structure detection SLM.Especially, if there is no need to use the memory cell 1002 that the public maintenance SLM of all signal specifications is indicated, then said structure is extremely effective.

In addition, POH terminal operation processing unit 1001 shown in Figure 55 can be configured to FEBE serial terminal processing unit, is used for carrying out to the terminal processes of the FEBE (far end block error) of the G1 byte that comprises in multiplex signal and V5 byte and to the processing of the FEBEPM (FEBE performance monitoring) of above-mentioned G1 byte and V5 byte with serial mode.In this case, memory cell 1002 storages provide stored information to this FEBE serial terminal processing unit in addition by the operating result that FEBE serial terminal processing unit carries out each channel.

Therefore, POH terminal processes device 1000 can by to the public FEBE serial terminal processing unit of all channels with serial mode carry out to the FEBE of G1 byte (as multiplex signal is the STM-1 frame, then is included in the POH of VC-3) and FEBEPM terminal processes, and to the FEBE of the V5 byte in the POH of the signal specification that is included in its low digital stage multiplex signal different and the terminal processes of FEBEPM with the multiplex signal that comprises the G1 byte.

In this case, can further reduce the scale and the power consumption of device.

Specifically, above-mentioned FEBE serial terminal processing unit for example has following each several part:

G1FEBE serial detecting unit is used for the FEBE with serial mode detection G1 byte;

V5FEBE serial detecting unit is used for the FEBE with serial mode detection V5 byte;

The FEBE selected cell is used to select the FEBE detection signal by G1FEBE serial detecting unit or the output of V5FEBE serial detecting unit; And

FEBEPM serial addition unit is used for serial mode FEBEPM being carried out add operation according to the FEBE detection signal of being selected by above-mentioned FEBE selected cell.

In this case, memory cell 1002 storages provide stored information to this FEBEPM serial addition unit in addition by the operating result that above-mentioned FEBEPM serial addition unit carries out each channel.

Therefore, POH terminal processes device 1000 can be by the terminal processes of the public FEBE serial terminal processing unit of all channels being carried out FEBE and FEBEPM with serial mode should carry out in the POH terminal processes to each channel of having the unlike signal specification usually.

So, do not need to install respectively being used for of equating with the respective channels number carry out terminal processes to FEBE and FEBEPM circuit.This can reduce the scale and the power consumption of device to the utmost.

Point out that in passing FEBE serial terminal processing unit can have following each unit:

The 1st FEBEPM serial addition unit is used for serial mode FEBEPM being carried out add operation according to the FEBE detection signal of being supplied with by above-mentioned G1FEBE serial detecting unit;

The 2nd FEBEPM serial addition unit is used for serial mode FEBEPM being carried out add operation according to the FEBE detection signal of being supplied with by above-mentioned V5FEBE serial detecting unit; And

The FEBEPM selected cell is used to select the FEBEPM by the 1st FEBEPM serial addition unit or the output of the 2nd FEBEPM serial addition unit.

In this case, memory cell 1002 storages provide stored information to this FEBEPM serial addition unit in addition by the result that FEBEPM serial addition unit carries out addition to each channel.

That is, above-mentioned FEBE serial terminal processing unit one by one carries out the FEBE of G1 byte is detected and the add operation of FEBEPM, and to the FEBE detection of V5 byte and the add operation of FEBEPM, then, exports among each FEBEPM selectively with serial mode.Therefore, can be with serial mode with simple structure detection FEBE and FEBEPM.Especially, if there is no need to use memory cell 1002 to the public maintenance FEBEPM of all signal specifications, then said structure is extremely effective.

In addition, POH terminal operation processing unit 1001 shown in Figure 55 can be configured to FERF serial terminal processing unit, is used for serial mode the G1 byte that comprises in multiplex signal and V5 byte being carried out the terminal processes of FERF (far-end receives and lost efficacy).In this case, memory cell 1002 storages provide stored information to this FERF serial terminal processing unit in addition by the operating result that FERF serial terminal processing unit carries out each channel.

Therefore, POH terminal processes device 1000 can by to the public FERF serial terminal processing unit of all channels with serial mode carry out to the FERF of G1 byte terminal processes, and to the terminal processes of the FERF of V5 byte.

So, can further reduce the scale and the power consumption of device.

Specifically, above-mentioned FERF serial terminal processing unit for example has following each device:

G1FERF indication serial detecting unit is used for detecting G1 byte indication FERF with serial mode;

V5FERF indication serial detecting unit is used for detecting V5 byte indication FERF with serial mode;

The FERF indication detects selected cell, is used to select to be indicated by G1FERF indication serial detecting unit or V5FERF the FERF indication detection signal of serial detecting unit output; And

FERF serial detecting unit is used for indicating detection signal to detect the FERF of G1 byte and V5 byte with the serial mode indication according to the FERF that detects the selected cell selection by above-mentioned FERF indication.

In this case, memory cell 1002 storages provide stored information to this FERF serial detecting unit in addition by the testing result that FERF serial detecting unit carries out each channel.

Therefore, POH terminal processes device 1000 can be by the terminal processes of the public FERF serial terminal processing unit of all channels being carried out FERF with serial mode should carry out in the POH terminal processes to each channel of having the unlike signal specification usually.

So, do not need to install respectively the circuit that is used for FERF is carried out terminal processes that equates with the respective channels number.This can further reduce the scale and the power consumption of device to the utmost.

FERF serial terminal processing unit can have following each unit:

The 1st FERF serial detecting unit is used for indicating detection signal to detect the FERF of above-mentioned G1 byte with serial mode according to the FERF that is supplied with by G1FERF indication serial detecting unit;

The 2nd FERF serial detecting unit is used for indicating detection signal to detect the FERF of above-mentioned V5 byte with serial mode according to the FERF that is supplied with by V5FERF indication serial detecting unit; And

FERF indicates selected cell, is used to select the FEFERF by the 1st FERF serial detecting unit or the output of the 2nd FERF serial detecting unit to indicate.

In this case, memory cell 1002 has: the 1st memory cell, be used to store the testing result of each channel being carried out by the 1st FERF serial detecting unit, and provide stored information to the 1st FERF serial detecting unit in addition; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 2nd FERF serial detecting unit, provide stored information to the 2nd FERF serial detecting unit in addition.

That is, above-mentioned FERF serial terminal processing unit one by one carries out detection and the indication of the FERF of G1 byte are handled, and detection and the indication of the FERF of V5 byte handled with serial mode, then, exports among each FERF selectively.Therefore, can be with simple structure indication FERF.Especially, if there is no need to use memory cell 1002 to the public maintenance FERF of all signal specifications, then said structure is extremely effective.

In addition, POH terminal processes device 1000 shown in Figure 55 can have POH timing signal serial generation unit, be created in the POH timing signal that uses when handling in the POH terminal operation processing unit 1001 with serial mode according to j1 byte and the timing signal of the position of V5 byte and the type of multiplex signal of indication in the multiplex signal, therefore, be produced as the required POH timing signal of the public POH terminal operation processing unit of all channels 1001 with serial mode.

Therefore, do not need to install respectively being used for of equating with the respective channels number to producing the circuit of POH timing signal.This can further reduce the scale and the power consumption of device to the utmost.

Specifically, POH timing signal serial generation unit for example has following each device:

The count value initialization unit, the timing signal by receiving j1 byte in the indication multiplex signal and V5 byte location is with SPE (net load is sealed synchronously) count value initialization;

Count value addition control unit is according to by above-mentioned count value initialization unit signal supplied the SPE count value being carried out addition control;

The memory cell that can read and write flexibly is used to keep the SPE by above-mentioned count value addition control unit is tried to achieve each channel to count additive value, and will supplies with the count value initialization unit to the maintenance data of each channel; And

POH timing signal for generating unit is created in the POH timing signal that uses when handling in the POH terminal operation processing unit 1001 according to the type by above-mentioned count value initialization unit signal supplied and multiplex signal.

In having the pointer processing apparatus of the present invention 1000 of said structure, POH timing signal serial generation unit carries out initialization, addition and renewal successively to the information relevant with the leading position (j1 byte and V5 byte) of SPE in the multiplex signal of each channel, simultaneously this information is remained in the memory cell, thereby by the public POH timing signal serial generation unit of all channels is produced as the required timing information of processing that carries out in POH terminal operation processing unit 1001 with serial mode.

Therefore, can realize the processing procedure that above-mentioned POH timing signal serial produces with foolproof structure.

POH terminal processes device 1000 shown in Figure 55 has address-generation unit, generation is used to differentiate the address information of each channel of multiplex signal, thereby by the address information that the public address-generation unit of all channels is produced for memory cell 1002 usefulness.

Therefore, do not need to install respectively the circuit that is used to produce the address information that supplies memory cell 1002 usefulness that equates with the respective channels number, and need in POH terminal operation processing unit 1001, not differentiate the special processing of each channel.

According to POH terminal processes device 1000 of the present invention, can further reduce the scale and the power consumption of device to the utmost.

POH terminal processes device 1000 shown in Figure 55 can have following each unit, as POH terminal operation processing unit 1001:

J1/J2 byte serial terminal processes unit is used for serial mode the j1 byte and the J2 byte that comprise being carried out terminal processes in this multiplex signal;

B3/V5 byte serial terminal processes unit is used for carrying out to the terminal processes of the BIP of the B3 byte that comprises in this multiplex signal and V5 byte and to the terminal processes of the BIPPM of B3 byte and V5 byte with serial mode;

UNEQ/SLM serial terminal processing unit is used for serial mode the C2 byte that comprises and the UNEQ of V5 byte being carried out terminal processes in this multiplex signal, and with serial mode the SLM of above-mentioned C2 byte and V5 byte is carried out terminal processes; And

FEBE/FERF serial terminal processing unit, be used for carrying out to the terminal processes of the FEBE of the G1 byte that in this multiplex signal, comprises and V5 byte with to the terminal processes of the FEBEPM of above-mentioned G1 byte and V5 byte, with serial mode the FERF of G1 byte and V5 byte carried out terminal processes in addition with serial mode.

In this case, the operating result that cell stores is carried out each channel by J1/J2 byte serial terminal processes unit, B3/V5 byte serial terminal processes unit, UNEQ/SLM serial terminal processing unit and FEBE/FERF serial terminal processing unit, in addition, also provide information to J1/J2 byte serial terminal processes unit, B3/V5 byte serial terminal processes unit, UNEQ/SLM serial terminal processing unit and FEBE/FERF serial terminal processing unit.

Pointer processing apparatus of the present invention 1000 with said structure can carry out terminal processes to j1 byte and J2 byte with serial mode, to detect the multi-frame pattern of multiplex signal, B3 byte and V5 byte are carried out terminal processes, to obtain BIP (BIPPM) from multiplex signal, C2 byte and V5 byte are carried out terminal processes, to obtain UNEQ and SLM, to G1 and (or) the V5 byte carries out terminal processes, to obtain FEBE (FEBEPM), and to G1 and (or) the V5 byte carries out terminal processes, to obtain the public FERF of all channels.

According to POH terminal processes device 1000 of the present invention, do not need to install the circuit that is used to carry out above-mentioned every processing that equates with the respective channels number.Therefore, can reduce the scale and the power consumption of device to the utmost.

Pointer of the present invention/POH terminal processes device, being used for that its information multiplexed signal on a plurality of channels that sends in the SDH transmission system is carried out pointer handles and the POH terminal processes, this device has: the list pointer processing unit, be used for multiplex signal being carried out pointer and handle, and this multiplex signal need not be assigned to each channel with serial mode; And serial POH terminal processes unit, be used for multiplex signal being carried out the POH terminal processes, and this multiplex signal need not be assigned to each channel with serial mode.

Above-mentioned pointer/POH terminal processes device, can carry out pointer processing and the processing of POH terminal operation to the multiplex signal that in the SDH transmission system, sends with serial mode, and this multiplex signal need not be assigned to each channel, thereby can realize this pointer/POH terminal processes device with the scale and the minimum power consumption of minimum.

Below, with reference to accompanying drawing embodiments of the invention are described.

(b-1) the integrally-built explanation of pointer processing apparatus

Fig. 3 is the block diagram of major part structure of the line termination device that pointer processing apparatus was suitable for of the expression embodiment of the invention.Line termination device shown in Figure 3 (LT) 8, corresponding with the line termination device 306 shown in Figure 66, have section overhead/line overhead (SOH/LOH) terminal processes unit 8A, pointer processing apparatus 8B, path overhead (POH) terminal processes unit 8C, interconnection (XC) device 8D, POH insertion processing unit 8E, AU4 pointer insertion processing unit 8F and SOH/LOH and insert processing unit 8G.

SOH/LOH terminal processes unit 8A detects the overhead part (SOH/LOH) of the multiplexed data (the STM-1 frame: wherein n is multiplexed degree, n=1,4,16 or 64) that receives, and carries out removing from the STM-1 frame terminal processes of this overhead part.Pointer processing apparatus 8B carried out pointer terminal/change and handled carrying out the AU4 pointer of multiplexed data (AU4 frame) of terminal processes or TU pointer by SOH/LOH terminal processes unit 8A.

For this reason, as shown in Figure 3, pointer processing apparatus 8B has AU4 pointer processing unit 81B, TU pointer processing unit 82B and selects circuit 83B.AU4 pointer processing unit 81B carries out for example detecting from the AU4 frame terminal processes of AU4 pointer, so that this AU4 pointer is removed from the AU4 frame, make the AU4 frame become VA4, or carry out for example the AU4 pointer being added to the pointer change processing that (insertion) carried out the AU4 frame of terminal processes (being VC4).TU pointer processing unit 82B for example changes the TU pointer of the deposit position that is used to indicate VC4.

Select circuit 83B according to the interconnection setting signal of supplying with from the outside export selectively by AU4 pointer protected location 81B and TU pointer processing unit 82B input carried out AU4 pointer terminal processes (promptly; its TU pointer is more corrected one's mistakes) multiplexed data, or export the multiplexed data of more correcting one's mistakes from its AU pointer of AU4 pointer processing unit 81B input.

POH terminal processes unit 8C carries out terminal processes or supervision to the POH of the multiplexed data that the AU4 pointer processing unit 81B from above-mentioned pointer processing apparatus 8B infeeds.The multiplexed data (VC4/VC3/VC2/VC12) that cross connection device 8D will supply with from above-mentioned pointer processing apparatus 8B is a unit with VC4 or is a unit interconnection (TSI: time slot interleaving) with VC3/VC2/VC12.

POH inserts processing unit 8E and when POH carries out terminal processes by above-mentioned POH terminal processes unit 8C this POH is inserted the VC4 frame of supplying with from cross connection device 8D, maybe export when this POH presses the VC4 frame during without terminal processes previous status (by).The AU4 pointer inserts processing unit 8F and when AU4 pointer POH carries out terminal processes by above-mentioned POH terminal processes unit 8C this AU4 pointer is inserted the VC4 frame, maybe the VC4 frame is pressed previous status when this AU4 pointer during without terminal processes and exports.

SOH/LOH inserts processing unit 8G by SOH/LOH being inserted the VC4 frame (being AU4) that has inserted the AU4 pointer this STM-n frame that collects, and sends multiplexed data to produce

Promptly, the pointer processing apparatus 8B of present embodiment, described in (C) item hereinafter, selectively export its AU4 pointer according to being set with of carrying out from the outside by above-mentioned selection circuit 83B and carried out the multiplexed data (VC4) of terminal processes or inserted multiplexed data (AU4) that (change) crosses the AU4 pointer, thereby the signal of VC4 level and the signal cross that is lower than the VC4 level are connected by cross connection device 8D.

For example, be under the cross-coupled situation of unit with VC4, AU4 pointer processing unit 81B change AU4 pointer is supplied with cross connection device 8D by the multiplexed data of selecting circuit 83B will insert the AU4 pointer by selecting circuit 83B then.At this moment, the POH of VC4 carries out terminal processes in POH terminal processes unit 8C, but directly by (can monitor).

By the multiplexed data after the cross connection device 8D interconnection, insert processing unit 8E and AU4 pointer insertion processing unit 8F by POH, behind the POH that inserts AU4 pointer and VC4, insert processing unit 8G by SOH/LOH and insert SOH/LOH therein, be assembled into a STM-n frame.

Be under the cross-coupled situation of unit with VC3/VC2/VC12, AU4 pointer processing unit 81B and POH terminal processes unit 8C carry out terminal processes to AU4 pointer and POH respectively, TU pointer processing unit 82B change TU pointer, and will carry out the multiplexed data of terminal processes by selecting circuit 83B supply cross connection device 8D to the AU4 pointer.

In this case, inserting processing unit 8F by POH insertion processing unit 8E and AU4 pointer inserts POH and AU4 pointer by the multiplexed data after the cross connection device 8D interconnection respectively, after the POH to AU4 pointer and VC4 carries out terminal processes, insert processing unit 8G by SOH/LOH and insert SOH/LOH therein, be assembled into a STM-n frame.

Below, describe above-mentioned pointer processing apparatus 8 in detail.But for simplicity, explanation will be undertaken by the order of TU pointer processing unit 82B and AU4 pointer processing unit 81B.Below explanation is that the reception multiplexed data is the situation of STM-1 frame, but before STM-n frame (n=1,4,16,64) is separated into the STM-1 frame this STM-n frame is carried out same processing.

(b-2) explanation of TU pointer processing unit

Fig. 4 is the block diagram of expression TU pointer processing unit 82B major part.In Fig. 4, Ref. No. 10 presentation address generation units, 11 expression pointer extracting units, 12 expression pointer processing units, 13 expression RAM (random access memory) control units, and 14 expression RAM.

Address-generation unit 10 produces the address (channel address) of each channel of distributing to TU level multiplexed in the STM-1 frame, and this STM-1 frame is the frame signal that produces based on the detection based on frame synchronization mode included among the SOH to the STM-1 frame (A1 and A2 byte).Pointer extracting unit 11 extracts pointer byte (comprising H1/V1 byte and H2/V2 byte at least) with serial mode from multiplexed data.Pointer processing unit 12 receives the multiplexed data from pointer extracting unit 11, and successively the multiplexed data of each channel is carried out the detection of pointer analysis, pointer state and the change of pointer etc. with serial mode.

Pointer processing unit 12 has following each funtion part that illustrates below.

(1) the reception pointer value keeps function

(2) positive 3 continuous consistent measuring abilities that receive of constant pointer

(3) LOP (Loss Of Pointer) measuring ability

(4) incremented/decremented (INC/DEC) reception result recognition function

(5) alarm condition shifts measuring ability

(6) now keep function with pointer value

(7) SPF lead byte (J1/V5) recognition function

The RAM control unit produces control signal, and the result who is used for each channel that will be obtained by pointer processing unit 12 with serial mode writes or read RAM14.RAM14 remains on pointer processing unit 12 in the indicated zone of the channel address supplied with by 10 pairs of each channels of address-generation unit.

RAM14 keep will be later with reference to the following listed information sets of Figure 10 explanation (being the required information sets of pointer processing) from what multiplexed data obtained.

1. the information sets of representing with the pointer byte of each channel of extracting from resulting multiplexed data by pointer extracting unit 11 (for example, the high position of reception pointer value is 2)

2. make pointer begin to move required information sets [NDF allows (EN) signal etc.] by the pointer byte that receives

3. the information sets of the result after beginning as pointer action [INV-V1, AIS detection signal (AIS-V1) etc.]

In the TU pointer processing unit 82B with said structure of present embodiment, according to the permission write signal that produces by RAM control unit 13 (detection of reception pointer value regularly), 1.～3. above-mentioned each information sets is write RAM14 according to the indicated address of address ram (channel address) that produces by address-generation unit 10.

1.～3. each information sets that pointer processing unit 12 is read former frame from RAM14 according to the permission read output signal that is produced by RAM control unit 13 and is utilized each information sets of each channel of reading 1.～3. to carry out pointer with serial mode and is handled.

That is, above-mentioned TU pointer processing unit 82B can with serial mode according to the address of distributing to each channel will by each information sets that the public pointer extracting unit 11 of all channels and pointer processing unit 12 are produced 1.～3. remain in the RAM14.Therefore, even should carry out (the TU level signal in the STM-1 frame) number of channel increase that pointer is handled, also can handle multiplexed data, and this multiplexed data need not be separated into the data on each channel by a circuit public (a pointer processing unit 12) to all channels.

Therefore, do not need to provide being used for the circuit that pointer handles and adapting to all channels of equating with a plurality of numbers of channel (maximum 63 channels), thereby can reduce the unit scale, power consumption, the distribution number between each function (circuit) piece etc. of this pointer processing apparatus 8B to the utmost.

Above-mentioned RAM14 for example, as shown in Figure 5, can be divided into RAM21 (the 1st RAM:RAM R1) and RAM22 (the 2nd RAM:RAM R2), keeps above-mentioned each information sets of being kept by RAM14 1.～3. as follows respectively.

RAM 21(RAMR1)

1. by the information sets of the H1/V1 byte representation in the reception pointer value

RAM 22(RAMR2)

1. by the information sets of the H2/V2 byte representation in the reception pointer value

2. make pointer begin the required information sets of above-mentioned action

3. the information sets of the result after beginning as pointer action

In this case, must obtain information sets by H1/V1 and H2/V2 byte representation.For this reason, pointer extracting unit 11 has: H1/V1 byte extracting unit 23 is used for extracting from multiplexed data the H1 byte state V1 byte of each channel; Reach H2/V2 byte extracting unit 24, be used for extracting the H2 byte or the V2 byte of each channel, thereby utilization each self-sustaining data in RAM21 and RAM22 are carried out the pointer processing with serial mode from multiplexed data.

In above-mentioned TU pointer processing unit 82B, according to the detection timing of the H1/V1 that produces by RAM control unit 13, will write address (zone) by the information sets (pointer byte) that H1/V1 byte extracting unit 23 extracts from multiplexed data by the indicated RAM21 of the address ram (channel address) of address-generation unit 10 generations.On the other hand, according to the detection timing of the H2/V2 that produces by RAM control unit 13, will reach the information sets that produces by pointer processing unit 12 by the information sets that H2/V2 byte extracting unit 24 extracts from multiplexed data and write RAM22.

Pointer processing unit 12 is according to the detection timing of the H2/V2 that is received, read each information sets from RAM21 and 22, the information sets of the H2/V2 byte that each channel received of utilize the information sets of the H1/V1 byte that each channel received of reading from RAM22 then, reading from RAM22 and carry out pointer by the signal that H2/V2 byte extracting unit 24 produces and handle.

Promptly, in above-mentioned TU pointer processing unit 82B, RAM14 shown in Figure 4 is divided into RAM21 and RAM22, so that data are write RAM21 by the timing of the H1/V1 byte that is received and read from RAM21, then write or read on the other hand from RAM22 by the timing of the H2/V2 that is received by the timing of the H2/V2 that is received.

Therefore, reduce the number of times of visit RAM22, thereby can reduce the power consumption of RAM21 and RAM22.In the following description, for simplicity, RAM14 is divided into RAM21 and RAM22 sometimes, is regardless of sometimes.But in essence, RAM14 can divide, and also can be regardless of.

Fig. 6 is the block diagram of the detailed structure of the above-mentioned address-generation unit 10 of expression.As shown in Figure 6, address-generation unit 10 has the address counter 15 that is used for TUG3, the address counter 16 that is used for TUG2, TU12 address counter 17, AND door 18 and 1-input inversion formula AND door 19.

The multiplexed TUG3 number (number of channel) (multiplexed maximum 3 channels) of 15 pairs of STM-1 frames of address counter (ternary counter) that is used for TUG3 is counted.The number of channel (multiplexed maximum 7 channels) that is used for 16 couples of TUG2 that the TUG3 frame is multiplexed of address counter (septenary counter) of TUG2 is counted.The number of channel (multiplexed maximum 3 channels) that is used for the multiplexed TU12 of 17 pairs of TUG2 frames of address counter (ternary counter) of TU12 is counted.

According to present embodiment, the carry output (CO) of address counter 15 is connected with the carry input (CI) of address counter 16, and the carry output (CO) of address counter 16 is connected in the carry input (CI) of address counter 17, therefore, is configured to one 63 system counter.The output of 15～17 these 3 address counters is used as the address ram (channel address) of RAM14.

AND door (logic product arithmetic unit) 18, and when this AND door 18 is not set at the TU12 pattern by the TU12 setting signal as described later (, when the TU12 setting signal is the L level), the output of address counter 17 is converted to " 0 ".1-input inversion formula AND door 19, only when this AND door 19 is set at the TU3 pattern by the TU3 setting signal as described later (, only when the TU3 setting signal is the H level) is converted to " 0 " with the output of address counter 16.

10 pairs of combinations according to the counter 15～17 of TU12 mode initialization signal and the work of TU3 mode initialization signal of address-generation unit (only counter 15, counter 15 sum counters 16 or 15～17 all counters) are switched, producing for example address that is used for RAM14 in combination shown in Figure 7, thus in RAM14 to the public channel address of TU3/TU2/TU12.

Therefore, no matter be any combined frames, can both handle neatly in the unlike signal specification that mixing exists in the STM-1 frame by using an address-generation unit 10.Point out in passing, as shown in Figure 7, address 00 _HEX～02 _HEXBe the address public to TU3/TU2/TU12, and 03 _HEX～14 _HEXBe the address public to TU2/TU12.

Above-mentioned address-generation unit 10, except that the structure of Fig. 6, for example, as shown in Figure 8.Can have address conversioning unit 20.Here, desired addition processing is carried out in the output of the address of 20 pairs of each counters 15～17 of this address conversioning unit, so as to producing an address conversion signal, is used for preventing to produce the invalid address at RAM14.

For this reason, for example, as shown in Figure 9,, then address conversioning unit 20 is configured to circuit by half adder 20-1, full adder 20-2～20-8 and EXOR door ("or" else circuit) 20-9 combination as maximum 63 channels of multiplexed TU12 in the STM-1 frame.

As maximum 63 channels of multiplexed TU12 as mentioned above in the STM-1 frame, the address conversion system that constitutes by address conversioning unit 20 (relation between count value and address) as shown in Figure 7 then.For satisfying this relation, with the position " 1 " of address counter 17 (T1CN1) and the position " 2 " of address counter 16 (T2CN2) be input to A and the B input of half adder 20-1 respectively, and with the position " 0 " of address counter 17 (T1CN0), the position " 2 " of address counter 16 (T2CN2) and the position " 1 " of address counter 16 (T2CN1) be input to A, B and the Ci input of full adder 20-2 respectively.

With the position " 1 " of address counter 17 (T1CN1), the position " 1 " of address counter 16 (T2CN1) and the position " 0 " of address counter 16 (T2CN0) be input to A, B and the Ci input of full adder 20-3 respectively.With the position " 0 " of address counter 17 (T1CN0), the position " 0 " of address counter 16 (T2CN0) and the position " 0 " of address counter 15 (T3CN0) be input to A, B and the Ci input of full adder 20-4 respectively.

With the position " 0 " of address counter 17 (T1CN0), the carry output of the output of the carry of half adder 20-1 and full adder 20-6 is input to A, B and the Ci input of full adder 20-5 respectively.The carry output of carry output half adder 20-1 and output, full adder 20-2 and full adder 20-7 is input to A, B and the Ci input of full adder 20-6 respectively.

The carry output of carry output full adder 20-2 and output, full adder 20-3 and full adder 20-8 is input to A, B and the Ci input of full adder 20-7 respectively.With full adder 20-3 and position " 1 " output, address counter 15 (T3CN1) and the carry of full adder 20-4 output be input to A, B and the Ci input of full adder 20-8 respectively.

With the position " 1 " of address counter 15 (T3CN1) and the carry of full adder 20-5 output be input to EXOR door 20-9 respectively.The output of EXOR door 20-9 and full adder 20-5～20-8 and 20-4 constitute the output of address conversioning unit 20 with output.

That is, shown in Fig. 7 and 9, owing to address number " 0 "～" 2 " constitute the output of 0-2 address by original state, so " 0 " and " 1 " of address counter 15 is input to the 0th position and the 1st position of address conversioning unit 20 respectively.

When the address number is " 3 ", address counter 16 indications " 1 ".In order to export " 3 ", the LSB (least significant bit " 0 ") of address counter 16 is input to the 0th position and the 1st position of address conversioning unit 20.With above-mentioned the 0th position and the addition respectively of the 1st position of input data, thus address acquisition number " 0 "～" 5 ".

Then, when the address number is " 6 ", address counter 16 indications " 2 ".In order to export " 6 ", the position " 1 " of address counter 16 is input to the 0th position and the 1st position of address conversioning unit 20 in this moment.Relevant position addition in an identical manner with the input data.

In addition, when the address number is " 12 ", address counter indication " 4 ".In order to export " 12 ", the MSB (highest significant position " 2 ") of address counter 16 is input to the 2nd position and the 3rd position of address conversioning unit 20 in this moment.Relevant position addition with the input data.

Number is " 21 " (15 when the address _HEX) time, address counter 17 indications " 1 ".In order to export " 21 ", the LSB (least significant bit " 0 ") of address counter 15 is input to the 4th position, the 2nd position and the 0th position of address conversioning unit 20 in this moment.That is, add 15 _HEX

Then, when the address number be " 42 " (2A _HEX) time, address counter 15 indications " 2 ".In order to export " 42 ", the MSB (highest significant position " 1 ") of address counter 15 is input to the 5th position, the 3rd position of address conversioning unit 20 in this moment.That is, add 2A _HEX

In this case, address-generation unit 10 produces the wherein compressed address outputs in all invalid addresses (with reference to the address space of Figure 10) by aforesaid operations, thereby converts the address wire of RAM14 to 6 from 7.Therefore, the invalid address that takes place in RAM14 is clipped, thereby can reduce the scale of RAM14.

Secondly, Figure 11 is the block diagram that is illustrated in the structure of the pointer converting unit 12A that has in the pointer processing apparatus 12.Pointer converting unit (the 1st pointer converting unit) 12A have alarm condition detecting unit 26, NDF detecting unit 27, the inconsistent detecting unit 28 in SS position, NDF allow detecting unit 29, high-order 2 bit extracting units 30 of pointer value, OR door (logic and circuit) 31, inverse gate (inverter) 32 and AND door (logic integrated circuit) 32 '.

Alarm condition detecting unit 26 detects whether the multiplexed data (H1/V1 byte) that receives is " 1 " (ALL " 1 ") entirely.NDF detecting unit 27 detects invalid N position, NDF position () from the H1/V1 byte that receives: with reference to Figure 64).The inconsistent detecting unit in SS position 28 detects inconsistent between the SS position of the H1/V1 byte that receives and SS position reception desired value.

Whether NDF allows detecting unit 29 to detect the NDF position from the H1/V1 byte that receives is " 1001 " that expression allows.High-order 2 bit extracting units 30 of pointer value extract 2 of the high positions of pointer value from the H1/V1 byte that receives.

Pointer converting unit 12A with said structure detects the ALL " 1 " of the H1/V1 byte (8) that receives by alarm condition detecting unit 26, exports the signal that produced by alarm condition detecting unit 26 then as one alarm condition detection signal.At this moment, NDF detecting unit 27 detects from the NIDF position (4) of the H1/V1 that receives neither normal NDF (" 0110 ") neither NDF allows the reception of the NDF position of (" 1001 ").

The value of SS position is determined by the signal specification.For this reason, the inconsistent detecting unit 28 in SS position adopts this value as the reception desired value, and receives 2 SS positions that desired value detects the H1/V1 byte that receives according to this.NDF allows detecting unit 29 to detect NDF from the NDF position (4) of the H1/V1 byte of reception and allows (" 1001 ").High-order 2 bit extracting units 30 of pointer value extract 2 of the high positions of pointer value from the H1/V1 byte that receives.

Then, the logic and the output of the signal that will be tried to achieve by OR door 31, the signal that is promptly produced by NDF detecting unit 27 and the signal that produced by the inconsistent detecting unit 28 in SS position are as one null pointer detection signal (INV-V1).On the other hand, to reach the logic product output that allows the signal of detecting unit 29 generations by NDF by OR door 32 ' signal of trying to achieve, the inversion signal (output of inverter 32) that promptly produces signal, allow signal (NDF-EN) as one NDF by the inconsistent detecting unit 28 in SS position.

Therefore, RAM21 (or RAM14) keeps comprising that 1 alarm condition detection signal, 1 null pointer detection signal, 1 NDF permission signal and 2 pointer value amount to 5 data.Point out that in passing these data are to keep according to the permission write signal of supplying with from RAM control unit 13 (detection of H1/V1 byte regularly).

That is, the pointer converting unit of present embodiment (the 1st pointer converting unit) 12A is 5 of figure place (8) boil down tos of the H1/V1 byte that receives, and the information after its figure place is compressed remains in the RAM21 (or RAM14).Therefore, the required figure place of RAM21 (or RAM14) reduces to 5 from 8.So can reduce the scale of RAM21 (or RAM14).

Figure 12 is the figure that is illustrated in data content one example that keeps in the RAM21 (or RAM14).But, do not need always to keep this data according to order shown in Figure 12.

As mentioned above, remain on the interior data of RAM21 (or RAM14) by pointer converting unit 12A, timing by the H1/V1 byte is read by pointer converting unit (the 2nd pointer converting unit) 33 as shown in figure 13, then, for example utilizes the value of these data and H2/V2 byte to carry out the pointer processing.The pointer result is remained in the above-mentioned RAM22 (or RAM14).

Pointer converting unit 33, timing according to the H2/V2 byte that extracts from multiplexed data, the figure place compressed information that produces according to multiplexed data, by pointer converting unit 12A, produce pointer processing control signals and pointer result, and these information sets are remained in the RAM22 by the beginning result's of required information sets of information sets, the start pointer action of the H2/V2 byte representation of the pointer byte of above-mentioned reception and pointer action information sets.

For this reason, for example, as shown in figure 14, pointer converting unit 33 have pointer value transfinite detecting unit (OUT OFRANGE) 35, increase progressively (INC) indication detecting unit 40, successively decrease (DEC) indication detecting unit 41, inconsistent detecting unit 45, AND

door

34,38,39,43,44 and 47, OR door 48, inverter 37, NOR door (NOR circuit) 36,42, and 46 and 1-input inversion formula AND door 49.

Transfinite detecting unit 35 of pointer value detects the pointer value that is received and whether surpasses effective range according to the pointer value of size [TU3 is that 0-764 (with reference to Figure 151), TU2 are that 0-427 (with reference to Figure 153), TU12 are 0-139 (with reference to Figure 155)] decision of each signal.INC indication detecting unit 40 is with the pointer value that receives and now compare with pointer value, so as to detecting I position (with reference to Figure 157) counter-rotating more than 3 or 3 and the D bit reversal is the state (INC indicating status) below 2 or 2.Point out in passing, now be and the different pointer value of pointer value that receives, and hardware is to operate by this value with pointer value.

DEC indication detecting unit 41 is with the pointer value that receives and now compare with pointer value, so as to detecting the D bit reversal more than 3 or 3 and the I bit reversal is the state (DEC indicating status) below 2 or 2.Inconsistent detecting unit 45 detects pointer value that receives and existing inconsistent between carrying out with pointer value.

Pointer converting unit 33 with said structure is carried out described hereinafter pointer processing according to each data (with reference to Figure 12) that keep in RAM21, thereby produce pointer processing control signals and pointer result (the TU-PAIS detection signal 1., pointer value transfinite detection signal 2., positive constant pointer detection signal 3., the INC detection signal 4., the DEC detection signal 5., the NDF detection signal 6., the null pointer detection signal 7.).

Specifically, the TU-PAIS detection signal is 1. by being calculated the logic product generation of the AIS-V1 signal read from RAM21 and the H2/V2 byte of reception by AND door 34.

Pointer value transfinites detection signal 2. by pointer value 10 generations that detecting unit 35 obtains according to 2 by the reception pointer value that will read from RAM21 by the timing of the H@/V2 byte H2/V2 byte additions with reception of transfiniting.For example, because be 0-764 in the effective range of pointer value under the situation of TU3 as mentioned above, under the situation at TU2 for being 0-139 under 0-427, the situation at TU12, so when receiving the pointer value that exceeds these scopes, the pointer value detection signal that transfinites becomes the H level.

Positive constant pointer detection signal producing method 3. is, try to achieve the INV-V1 signal read from RAM21 and the NOR of NDF-EN signal by NOR door 36, calculate the output signal of NOR doors 36 by AND door 38 then and by inverter 37 with the transfinite logic product of the signal that the detection signal output signal of detecting unit 35 (pointer value transfinite) obtains after anti-phase of above-mentioned pointer value.

INC detection signal producing method 4. is to be tried to achieve by the signal of INC indication detecting unit 40 generations, the output signal of NOR door 36 by AND door 43 and reach the logic product of the signal (all continuous 3 consistent NOR that receive detection signal and 3 frame inhibit signals of normal value as described later) that is produced by NOR door 42; And DEC detection signal producing method 5. is, is tried to achieve the logic product that is reached the signal that is produced by NOR door 42 by the output signal of the signal of DEC indication detecting unit 41 generations, above-mentioned NOR door 36 by AND door 44.NDF detection signal producing method 6. is, tries to achieve the transfinite logic product of inversion signal (output of inverter 37) with the NDF-EN signal of reading from RAM21 of detection signal of above-mentioned pointer value by AND door 39.

At this moment, INC indication detecting unit 40 and DEC indication detecting unit 41 compare with existing the pointer value that receives respectively with pointer value.INC indication detecting unit 40 detects the counter-rotating more than 3 or 3 of I position and the counter-rotating below 2 or 2 of D position, and DEC indication detecting unit 41 detects the counter-rotating more than 3 or 3 of D position and the counter-rotating below 2 or 2 of I position.

The null pointer detection signal is 7.) producing method be, detect in the pointer value that receives and now use inconsistent between the pointer value by inconsistent detecting unit 45, (the NDF detection signal 6. to try to achieve the output of above-mentioned testing result and NOR door 46 by AND door 47, continuous 3 consistent detection signal and the 3 frame inhibit signals of receiving of hereinafter described normal value, the INC detection signal 4., and DEC detection signal NOR operation result 5.) logic product, try to achieve above-mentioned logic product operation result by OR door 48, INV-V1 signal and pointer value transfinite detection signal logic 2. and, try to achieve the output of OR door 48 and the logic product of TU-PAIS detection signal inversion signal 1. by AND door 49 then.

Pointer processing apparatus 8B (TU pointer processing unit 82B) according to present embodiment can be produced various for carrying out the required pointer processing control signals and the pointer result of pointer processing of each channel by the pointer processing unit 12 public to all channels (pointer converting unit 33).Therefore, for example, do not need to provide as shown in figure 45 the number of channel (mostly being 63 channels under the situation of TU12 most) with in the TU level equates be used to judge reception pointer value 10 bit pointer values whether entirely for " 1 " respectively be the AND door (logic product arithmetic unit) 187 of 10 inputs, thereby can further reduce to the utmost unit scale, power consumption, and functional block between the distribution number.

Figure 15 is that expression notices that the reception pointer value of present embodiment keeps the block diagram of the TU pointer processing unit structure of function.As shown in figure 15, except that above-mentioned RAM22 (or RAM14), TU pointer processing unit 82B also has

decoding circuit

50 and 54, circuits for triggering (FF) 51～53 and selects circuit 55.

Decoding circuit 50 is deciphered the address value of distributing to each channel of TU3 frame from the address (channel address) that writes of supplying with RAM22 (or RAM14) by address-generation unit 10, to produce the permission signal to each FF circuit 51～53.The MSB of the reception pointer value of the channel (in the STM-1 frame, holding 3 channels at most) of each FF circuit (latch cicuit) 51～53 maintenance TU3.

Decoding circuit 54 is deciphered the address value of distributing to each channel of TU3 frame from the address of reading of RAM22 (or RAM14).Select decoded signal that circuit 55 will be supplied with by decoding circuit 54 with the signal that elects,

selection FF circuit

51,52 or 53 output.As not selecting the output of

FF circuit

51,52 or 53, then output " 0 ".

In having the TU pointer processing unit 82B of said structure, the 9 bit pointer values that only will remove from 10 reception pointer values behind the MSB remain in the RAM22 (or RAM14).When the signal specification was TU3, decoding circuit 50 was deciphered the address value of distributing to TU3 from address ram, exported decoded signal then as the permission signal to each FF circuit 51～53.

Do not remain on all the other the receiver address values (MSB) in the RAM22 (or RAM14), be maintained in the

corresponding FF circuit

51,52 or 53.

To writing of RAM22 (or RAM14) and each FF circuit 51～53, be regularly to carry out according to the extraction of H2/V2.When reading the reception pointer value, decoding circuit 54 is deciphered the address value of distributing to TU3 from address ram, select then circuit 55 with decoded signal with the signal that elects, select to keep the

FF circuit

51,52 of MSB of TU3 pointer value or 53 output signal.Represent a value different as address ram, then MSB is assumed to " 0 " with TU3.

In above-mentioned TU pointer processing unit 82B, under the situation that receives TU2/TU12, when pointer value in pointer value scope Nei Shiyin MSB always " 0 ", so should remain on receiver address value in the RAM22 (or RAM14) and be 9 except that MSB, in addition (under the situation of TU3), MSB is " 0 " not necessarily, so at this moment MSB is remained in the FF circuit 51～53.

Therefore, can further reduce the required figure place of RAM22 (or RAM14), thereby reduce the size of RAM22 (or RAM14).When the signal specification was TU3, the value that above-mentioned MSB has was different with value when the TU2/TU12.At this moment 1 with MSB remains in the FF circuit 51～53, thereby can guarantee all the time to handle required information for carrying out pointer.Therefore, can handle reliably.

Figure 16 is 3 continuous consistent block diagrams that receive pointer processing unit 12 structures of measuring ability of normal pointer value that present embodiment is noticed in expression.Pointer processing unit 12 as shown in figure 16 has consistent continuously detecting unit 58a and the pointer value converting unit 64 that transfinites that receives of OR door 56, RAM57, consistency detection unit 58, normal pointer value 3 times.

Calculate OR door 56 INV-V1 signals (with reference to Figure 11 and 12) and pointer value transfinite detection signal (with reference among Figure 14 2.) logic and, to produce to the transfinite control signal of converting unit 64 of pointer value.RAM57 keeps the pointer value of reception etc.Consistency detection unit 58 detect the reception pointer values and the reception pointer value of the former frame that in RAM57, keeps between consistency, and keep the result to remain in the RAM57 consistency as 1 information.

3 continuous consistent detecting unit 58a that receive of normal pointer value detect 3 continuous consistent receptions of normal pointer value according to the signal that is illustrated in the consistency detection result of RAM57 stored with the result's of the consistency detection that the value of previous pointer value and reception pointer byte is carried out logic product, for example, as shown in figure 16, it has OR door 59, AND door 60 and 61, reaches

inverter

62 and 63.

The pointer value converting unit 64 that transfinites, the pointer value that will remain in the RAM57 when receiving the pointer byte of expression invalid information is converted to certain value that exceeds the pointer value scope, and the information after will changing then remains in the RAM57.For example, when the output signal of OR door 56 is " 1 " (for the H level) (when receiving the INV-V1 signal or transfinite detection signal or both when receiving), transfinite converting unit 64 of pointer value is converted to the signal that exceeds the pointer value scope with the pointer value of being received.When the output signal of OR door 56 is " 1 " (for the H level), pointer value transfinite converting unit 64 make this pointer value that receives directly by and it is outputed to RAM57.

When the transfinite logic of detection signal and during of the INV-V1 signal of trying to achieve and pointer value for " 1 " by OR door 56, pointer processing unit 12 with said structure will remain on certain value that exceeds pointer value scope (being more than 765 or 765 under the TU3 situation, being more than 428 or 428 under the TU2 situation, being more than 140 or 140 under the TU12 situation) that is converted in the RAM57, hold it in the RAM57 then.

At this moment, 58 detections of consistency detection unit remain on the reception pointer value of the former frame in the RAM57 and the consistency between the current reception pointer value, AND door 60 is asked for the logic product of the output (the NDF detection signal of being tried to achieve by OR door 59 and inverter 3 with by inverter 62 inversion signal after anti-phase with normal pointer value NOR) of this testing result and inverter 63, thereby produce a current reception pointer value of expression and whether be the equal normal value received signal that equates with the pointer value of former frame (it is known whether receiving on 2 times the number of times this point in normal pointer value), and remain in the RAM57.

When receiving next pointer value, ask for this reception pointer value and the logic product that equates the normal value received signal of reading by AND door 61, and the operation result that is produced is exported as normal 3 continuous consistent detection signals that receive of pointer value from RAM57.Above-mentioned pointer processing unit 12 (pointer processing apparatus 8B) can be only by keeping that the consistency detection result of the reception pointer value of the former frame in receiving pointer value and remaining on RAM57 is carried out 3 continuous consistent detections that receive of normal pointer value (information) with serial mode to each channel, thereby can reduce the required figure place of RAM57.In addition, do not need to provide with the STM-1 frame in the number of channel equate for example as shown in figure 47 be used to detect 3 continuous 3 continuous consistent receiving test circuits of the consistent normal pointer value that receives of normal pointer value.

Therefore, can reduce unit scale, power consumption, the distribution number between the functional block of this pointer processing apparatus 8B etc. to the utmost.

3 continuous consistent receiving test circuits of normal pointer value shown in Figure 47 are detected the consistency between the reception pointer value of the reception pointer values former frame interior with remaining on reception pointer holding unit 195 by consistency detection unit 195, and will be reset to+1 (unanimity) or 0 (inconsistent) by triggering the count value that (FF) circuit (promptly being used to keep the circuit of count results) keeps according to testing result, when counter (promptly being used for the normal pointer value how many times of continuous reception is advanced the circuit of counting) 192 is output as " 2 ", this count value " 2 " is deciphered, and produced and export 3 continuous consistent detection signals (to a channel) that receive of normal pointer value.

Figure 17 is the block diagram of structure that the pointer processing unit 12 of LOP measuring ability is noticed in expression.Pointer processing unit 12 shown in Figure 17 has counting control unit 65 ' and RAM72.

Above-mentioned counting control unit 65 ', allow detection signal, null pointer detection signal to reach the state of the NDF permission detection signal of the former frame that in RAM72, keeps according to NDF, noticing that NDF allows under the situation that signal and null pointer detection signal do not detect at one time number of times that continuous reception NDF is allowed according to 3 truth tables that provide of tabulating down or the number of times that receives null pointer continuously to count, and producing and output LOP state detection signal according to this count results.RAM72 counting control unit 65 ' the count results and the NDF of former frame allow detection signal.

Table 3

Counting control unit operation truth table

The NDF detection signal of former frame	The null pointer detection signal	The NDF detection signal	Count value (receiving number of times continuously)
The NDF detection signal of former frame	The null pointer detection signal	The NDF detection signal	Count value (receiving number of times continuously)	0	0	0	0 (removing)
0	0	1	1	0	0	0	0 (removing)
0	0	1	1	0	1	0	Last count value+1
0	1	1	This state does not exist	0	1	0	Last count value+1
0	1	1	This state does not exist	1	0	0	0 (removing)
1	0	1	Last count value+1	1	0	0	0 (removing)
1	0	1	Last count value+1	1	1	0	1
1	1	1	This state does not exist	1	1	0	1

Specifically; above-mentioned counting control unit 65 ' adopted is used for the add circuit (protection counter) that the number of times that continuous reception NDF is allowed or the number of times that receives null pointer are continuously counted; OR door 66; 1-input inversion formula AND

door

67 and 70; 3 input OR doors 68; full input inversion formula AND door 69 and AND door 71; this counting control unit 65 ' " 0 " or " 1 " is input to input of add circuit 65 from OR door 66; and will remain on another input that " last count value " or " 0 " in the RAM72 is input to add circuit 65 from AND door 67, carry out computing according to truth table shown in the table 3 thus.

In having the pointer processing unit 12 of said structure, counting control unit 65 ' according to NDF allows, null pointer detection signal and the NDF that remains on the former frame in the RAM72 allow signal accepting state, be scavenged into " 0 " according to count value with the truth table add circuit shown in the table 3, and count value is set at " 1 ", or last count value is set at "+1 ", thereby the continuous reception number of times that continuous reception NDF is allowed or the continuous reception number of times of null pointer are counted.

The protected level that detects as LOP is that 8 grades of (inferior) NDF allow signal to receive continuously and 8 grades of null pointers receive continuously, then exports the LOP state detection signals from add circuit 65 when count value reaches " 8 ".

Promptly, as long as the order reception number of times of NDF permission or the continuous reception number of times of null pointer are counted, then above-mentioned counting control unit 65 ' just can detect the LOP state will be used for the counter that the continuous reception number of times that NDF allows is counted and be used in combination with the counter that the continuous reception number of times of null pointer is counted in this unit.

Therefore, do not need to provide respectively for example as shown in figure 46 the order that is used for that NDF is allowed that equates with the number of channel to receive special circuit (NDF allows signal to receive number of times counting unit 188 continuously) that number of times counts and the special circuit (null pointer receives number of times counting unit 189 continuously) that the continuous reception number of times of null pointer is counted.This can reduce unit scale, power consumption, the distribution number between functional block of this pointer processing apparatus 8B etc. to the utmost.

Figure 18 is the block diagram of structure that the pointer processing unit 12 of INC/DEC reception result recognition function is noticed in expression.Pointer processing unit 12 shown in Figure 18, as the INC/DEC reception result recognition unit 73A that is used to discern the INC/DEC reception result, have the control of filling and suppress unit 73B, RAM74, decoding circuit 75,1-input inversion formula AND door 76, AND door 77 and OR door 79.

Filling is controlled inhibition unit 73B after receiving by INC indication detecting unit 40, AND door 43, DEC indication detecting unit 41 and the AND door INC/DEC detection signal or the NDF permission signal (NDF detection signal) by 39 detections of AND door as preamble described INC/DEC detecting unit detection with reference to Figure 14, receive inhibition by INC/DEC and fill control in 3 image durations, to prevent owing to receiving the memory slip that causes continuously, the ternary counting unit 73 that this unit 73B has 3 input OR doors 80 and operates according to the truth table shown in 4 of tabulating down.

Table 4

1:3 counting unit operation truth table

NDF detection signal (INC detection signal/DEC detection signal)	The count value of former frame	The New count value
	The count value of former frame	The New count value	0	0	0
0	1	2	0	0	0
0	1	2	0	2	3
0	3	0	0	2	3
0	3	0	1	0	1
1	1	1	1	0	1
1	1	1	1	2	1
1	3	1	1	2	1

Ternary counting unit 73, for example, as shown in figure 19, by EXOR73-1,1-input inversion formula AND door 73-2 and 73-3 and OR door 73-4 realization, so that operate according to the truth table shown in the table 4.

RAM74 (being used to discern the RAM of INC/DEC reception result) keeps count value, NDF detection signal and INC (or DEC) detection signal of ternary counting unit 73.75 pairs of decoding circuits remain on " 1 " of the count value in the RAM74 and decipher.

In having the pointer processing unit 12 of said structure (INC/DEC reception result recognition unit 73A), fill the ternary counting unit 73 that control suppresses unit 73B and operates, and the detection signal (reception result) of count value (New count value), NDF detection signal (reception result) and the INC or the DEC of ternary counting unit 73 is remained in the RAM74 according to the truth table shown in the table 4.

When remaining on above-mentioned in the RAM74 after this when respectively receiving data and reading, decipher " 1 " of 75 pairs of count values of decoding circuit, by AND door 76 signal of logic product generation from the inversion signal of this decode results and NDF detection signal, try to achieve the logic product of this signal that produces and INC (or DEC) detection signal then respectively by AND door 77 and 78, thereby output (identifying) INC receives knot and or DEC reception result.From the logic of the count value of reading from RAM74 of trying to achieve with produce 3 frame inhibit signals by OR door 79.

According to above-mentioned pointer processing unit 12 (pointer processing apparatus 8B), only can discern the INC/DEC reception result, thereby not need INC testing result and DEC testing result are all remained in the RAM74 by a reception result among maintenance INC or the DEC.Therefore, not only can reduce the size of RAM74, can also reduce its power consumption simultaneously.

Above-mentioned ternary counting unit 73 can be configured to n system (n is not equal to 3 natural number) counting unit, after receiving INC/DEC detection signal and NDF signal, receives by the INC/DEC in n image duration and to suppress to fill control.

Figure 20 is that expression notices that alarm condition shifts the block diagram of structure of the pointer processing unit 12 of measuring ability.Pointer processing unit 12 shown in Figure 20 shifts protected location 81A as alarm condition, has counting control unit 81, RAM82 and decoding circuit 83.

Counting control unit 81 has the function that protected level is counted as being used for m (m is a natural number) the level protective circuit that alarm condition shifts.Counting control unit 81 for example, as shown in figure 21, has AND door 81-1 and 81-3, OR door 81-2,81-5 and 81-6 and 1-input inversion formula AND door 81-7 and 81-8, so that operate according to the truth table shown in the table 5.

Table 5

Be used to protect the operation truth table of the counting control unit of alarm detection

Alarm condition signal (the TU PAIS detection signal that diverts the aim	Report to the police and eliminate conditioned signal	The count value of former frame	The New count value
	Report to the police and eliminate conditioned signal	The count value of former frame	The New count value	0	0	0	0
0	1	0	0	0	0	0	0
0	1	0	0	0	0	1	0
0	1	1	0	0	0	1	0
0	1	1	0	0	0	2	0
0	1	2	0	0	0	2	0
0	1	2	0	0	0	3	3
0	1	3	0	0	0	3	3
0	1	3	0	1	0	0	1
1	0	1	2	1	0	0	1
1	0	1	2	1	0	2	3
1	0	3	3	1	0	2	3

RAM (being used to protect alarm condition to shift) 82 keeps the count value of counting control unit 81.The maximum of the count value of the auspicious counting control unit 81 of reading from RAM82 of decoding circuit 83 is deciphered.

That is, as shown in figure 20 alarm condition shifts protected location 81A (pointer processing unit 12), when receiving the alarm condition shown in the above-mentioned table 5 when diverting the aim signal (TU PAIS signal), the counting of accumulated counts control unit 81.As do not receive the alarm condition signal that diverts the aim; then alarm condition shifts the count resets of protected location 81A with counting control unit 81; when the count value of counting control unit 81 reaches maximum (or reaching protected level m); the count value of counting control unit 81 is remained in the RAM82 as maximum, when receiving warning elimination condition till.Therefore, when when RAM82 reads count value, can according to this count value whether reach maximum discern consider the alarm condition of channel.

In having the pointer processing unit 12 of said structure (alarm condition shifts protected location 81A), remain in the RAM82 according to the count value of the address that provides by address-generation unit with counting control unit 81.Judge that by decoding circuit 83 whether count value (or the count value from counting control unit 81 outputs shown in chain-dotted line among Figure 20) reaches maximum, is whether count value reaches protected level m value, reaches maximum as count value, then the output alarm status signal.

As concrete example, when being described now for detected state, the AIS state discerns the situation of its above-mentioned alarm condition.。When as preamble with reference to continuous when receiving TU PAIS detection signals 3 times as described in Figure 158, pointer is transferred to the AIS state, thereby above-mentioned protected level m is m=3.Therefore, for example, as shown in figure 22, above-mentioned decoding circuit 83 have respectively decoding circuit 84 that maximum " 3 " is deciphered and 85 and be used to ask for decoding

circuit

84 and 85 logic and OR door 88.

In having the pointer processing unit 12 of said structure, counting control unit 81 is controlled the count value of counting control unit 81 based on the as above truth table shown in the table 5 and according to receiving result and the TU PAIS signal of eliminating conditioned signal (normal 3 continuous consistent detection signals of pointer value or NDF allow detection signal) of reporting to the police, and this count value is remained in the RAM82 with serial mode according to the channel address that is provided by address-generation unit 10 then.

The count value that to read from RAM82 and the output count value of counting control unit 81 output to

corresponding decoding circuit

84 and 85 respectively.As count value is maximum " 3 ", and then decoding

circuit

84 and 85 is deciphered " 3 " by being decoded as AIS detection protection progression respectively.Then, by OR door 88 from logic with produce a signal, so that identification AIS state.

Above-mentioned pointer processing unit 12 (pointer processing apparatus 8B), only will remain in the RAM82 with the number of times of the signal (TU PAIS signal) that diverts the aim by corresponding address reception alarm condition, can discern the alarm condition of a plurality of channels with serial mode, simultaneously that RAM82 is required figure place is suppressed to bottom line.

Therefore, do not need to provide for example having respectively as shown in figure 48 of equating with a plurality of numbers of channel (the signal specification in leaving the STM-1 frame in mostly is 63 channels most when all being TU12) to be used for counting control unit 196, the decoding circuit 197 that protection progression is counted and to be used to keep the alarm condition of count value and alarm detection result's register 198 to detect protective circuit.Further can reduce unit scale, power consumption, the distribution number between each function (circuit) piece of this pointer processing apparatus 8B etc. to the utmost.

In the above-described embodiments, RAM57 shown in Figure 16, RAM72 shown in Figure 17, RAM74 shown in Figure 180 and the RAM82 shown in Figure 20 and 22 are different with RAM14 (RAM22 during Fig. 5 institute) shown in Figure 4.But, can in same RAM14 (22), concentrate the function of using above-mentioned each RAM.

For example, as above-mentioned RAM57,72,74 and 82 is concentrated in the RAM22, then RAM22 keeps following various data as shown in figure 23.

(1) from " 0 " figure place of " 8 " extremely: as reference Figure 15 institute] the reception pointer value except that MSB (9) is described;

(2) figure place " 9 ": the normal pointer value received signal that the pointer value that is produced by AND door shown in Figure 16 60 equates with former frame;

(3) from " 10 " figure place of " 12 " extremely: be used to detect the protection count value (3) of LOP, i.e. the output of addition electric furnace 65 that is used to detect LOP as shown in figure 17;

(4) figure place " 3 ": NDF detection signal.The i.e. logic product operation result of AND door 39 as shown in figure 14;

(5) position speed " 14 " extremely " 15 ": be used to forbid the count value (2) of 3 frames, i.e. the output of ternary counting unit 73 as shown in figure 18;

(6) from " 16 " figure place of " 17 " extremely: the output of counting control unit 81 as shown in figure 22 (being used for the protection count value that AIS detects); And

(7) figure place " 8 ": INC detection signal, i.e. the logic product operation result of AND door 43 as shown in figure 14.

Point out that in passing the order of not necessarily always pressing Figure 23 keeps data.

Figure 24 is the block diagram that the structure of the existing pointer processing unit 12 that keeps function with pointer value is noticed in expression.Pointer processing unit 12 shown in Figure 24, as now using pointer value holding unit 89A, be used to keep its hardware in fact with the existing pointer value of use of each channel of the irrelevant mode work bed mat made of woven strips of bamboo of reception pointer value, it has RAM89, decoding

circuit

90 and 94, triggers (FF) circuit 91～93, selector 95 and existing with pointer value renewal control unit 96.

RAM (being used to keep the existing pointer value of using) 89 keeps except that the MSB that now uses pointer value (10: with reference to Figure 157) 9 for each channel.Decoding circuit 90 is according to the address value of distributing to TU3 being deciphered as the address value that address (channel address) produces that writes to RAM89 by address-generation unit 10.

Each FF circuit 91～93 as latch cicuit, is used to keep the existing pointer value of using of the channel of TU3, under the situation of STM-1 frame frame, holds 3 channels of TU3 at most.Here, FF circuit 91 keeps the MSB of ch1, and FF circuit 92 keeps the MSB of ch2, and FF circuit 93 keeps the MSB of ch3.

Decoding circuit 94 is deciphered the address value of distributing to TU3 according to the address signal of reading of RAM89.Selector 95 is being exported the data that kept by each FF circuit 91～93 under the situation of signal as the selection signal after the decoding that will be supplied with by decoding circuit 94 selectively.When the data in not remaining on FF circuit 91～93 are selected, then output " 0 ".

Now upgrade control unit 96 with pointer value, INC/DEC receives when detecting, NDF receives or during continuous consistent reception of normal pointer value 3 times, will remain on now upgrading with pointer value in the RAM89.

Above-mentionedly now the low level position except that MSB is remained in the RAM89 with pointer value holding unit 89A, it comprises FF circuit 91～93, when multiplexed data is TU3, latch MSB respectively 1, and the signal that will obtain after will being deciphered by the address value that decoding

circuit

90 and 94 pairs are distributed to each respective channels of TU3 is with the control signal of doing FF circuit 91～93 is write and reads.

In having the pointer processing unit 12 of said structure, will remain in the RAM89 except that 9 of the totals the MSB that now uses pointer value (10) according to 5 channel addresss supplying with by address-generation unit 10.As at this moment signal specification is TU#, and then the address value of distributing to TU3 by channel address by 90 pairs of decoding circuits is deciphered, and the signal after will deciphering then is as allowing signal to remain in

FF circuit

91,92 or 93 by the channel of the correspondence MSB with pointer value.

Remain on existing in the RAM89 when using pointer value when reading, the address value of distributing to TU3 is deciphered according to the channel address (reading the address) of RAM89 by decoding circuit 94, with electing the selection signal of circuit 95, and select maintenance now to use the

FF circuit

91,92 of MSB of pointer value or 93 output in the same manner as described above the signal after this decoding by selector 95.Represent a value different as channel address, then MSB is assumed to " 0 ", as now using pointer value with TU3.

At this moment, the NDF detection signal receives whenever detecting, INC/DEC receives or during continuous consistent reception of normal pointer value 3 times, now just will remain on now upgrading with pointer value in the RAM89 with pointer value renewal control unit 96.

According to above-mentioned pointer processing unit 12 (pointer processing apparatus 8B), not now to use all positions of pointer value (10) to remain in the RAM89, but will be except that MSB 9 remain in the RAM89, and will be now remain in

FF circuit

91,92 or 93 with the MSB of pointer value.Therefore, can be produced as each channel with serial mode each channel is carried out the required existing pointer value of using of pointer processing, and all positions need not be remained in the RAM89

Therefore, the required figure place of RAM89 be can reduce, thereby size and the power consumption of RAM89 helped to reduce.

Above-mentioned RAM89 can be configured to the identical RAM with (or shown in Figure 22) shown in Figure 4 RAM14.But, when discerning the SPE lead byte as described later, owing to use the existing pointer value of using that remains in the RAM89, so preferably RAM89 is configured to basically a different RAM.

Figure 25 is the block diagram of structure that the pointer processing unit 12 of SPE lead byte (J1/V5 byte) recognition function is noticed in expression.Pointer processing unit 12 shown in Figure 25, existing the using the pointer value holding unit 89A except that reference Figure 24 illustrated has a SPE lead byte recognition unit 97A.

SPE lead byte recognition unit 97A is used to discern j1 byte (lead byte of VC4 and VC3: with reference to Figure 150 and 152) or the V5 byte (lead byte of VC2 and VC12: with reference to Figure 154 and 156) as the SPE lead byte, as shown in figure 25, it has skew counting unit 97, consistency detection unit 98 and AND door 99.

Skew counting unit 97 illustrated with reference to Figure 149～156 as preamble, under with the situation of frame signal as the initial signal of the lead byte of retrieval SPE the offset pointer value of SPE was counted.Consistency detection unit 98 allow with SPE signal as the situation that allows read output signal under the existing pointer value of use from now reading as mentioned above to be kept with the RAM89 of pointer value holding unit 89A, and detect at this and now use pointer value and be offset consistency between the skew count value in the counting unit 97.AND door 99 is asked for the logic product that SPE allows signal and the consistency detection result who is obtained by consistency detection unit 98, thereby produces and export a SPE lead byte position (J1/V5 byte) index signal.

SPE lead byte recognition unit 97A has the skew counting unit 97 that is used to retrieve the SPE lead byte, from now reading the existing pointer value of using with pointer value holding unit 89A, and by SPE allow signal with to the skew count value with now discern the lead byte position of SPE with the consistency detection result's of pointer value logic product.

In having the pointer processing unit 12 of said structure, allow signal to read to remain on showing in the RAM89 to use pointer value according to SPE.Skew counting unit 97 is that initial signal is counted the offset pointer value of SPE with the frame signal.Whether 98 detections in consistency detection unit are consistent with the count value of skew counting unit 97 from the existing pointer value of using that RAM89 reads.

Then, AND door 99 is asked for the logic product of consistency detection result and SPE permission signal, and generation and the long-pending operation result of output logic, as J1/V5 byte index signal.As J1/V5 byte index signal is " 1 " (H level), means that then the data at this time slot of multiplexed data are J1/V5 bytes.

Above-mentioned pointer processing unit 12 is by to the position of the public SPE lead byte recognition unit 97A (consistency detection unit 98 and AND door 99) of all channels with the lead byte (J1/V5 byte) of the VC4/VC3/VC2/VC12 in the serial mode identification multiplexed data (STM-1 frame), so that each channel (signal of TU level) is handled.

Therefore, do not need to provide the consistency detection unit 199 as shown in figure 49 that equates with a plurality of numbers of channel (63 channels that TU12 is arranged at most in the STM-1 frame), AND door 200, now with pointer value holding unit 201 and skew counting unit 201 ', thereby can reduce unit scale, power consumption, the distribution number between the functional block of this pointer processing apparatus 8B etc. to the utmost.

The explanation of the variation of (b-2 ') TU pointer processing unit

Figure 26 is the block diagram of a kind of variation of the above-mentioned TU pointer processing unit 82B of expression.TU pointer processing unit 82B shown in Figure 26 except that structure shown in Figure 4, also has mapping set point registers group 100 and setup unit 101.

Mapping set point registers group 100 is set in each channel of TU3/TU2/TU12 of multiplexed data (STM-1 frame) with what kind of signal specification shines upon.Selected cell (the signal specification is selected circuit) 101 utilizes by address-generation unit 10 and distributes to the signal specification of the address of each channel from above-mentioned mapping set point registers group 100 channels that selection is considered, and with serial mode output (multiplexed) map information.The detailed structure of mapping set point registers group 100 will describe with reference to Figure 30 below.

The TU pointer processing unit 82B of this variation is by the signal specification of each channel of mapping set point registers group 100 and selected cell 101 identification multiplexed datas, and with information providing pointer extracting unit 11, pointer processing unit 12 and RAM control unit 13, even exist the different frame of signal specification (channel), also can carry out pointer extraction and pointer processing according to the signal specification with a public circuit thereby in multiplexed data, mix.

For this reason, pointer extracting unit 11, for example, as shown in figure 27, have TU3 H1 byte extraction timing generation unit 102, TU2 V1 byte extraction timing generation unit 103, TU12 V1 byte extraction timing generation unit 104, TU3 H2 byte extraction timing generation unit 105, TU2 V2 byte extraction timing generation unit 106, TU12 V2 byte extraction timing generation unit 107 and selection circuit 108 and 109.

The H1 byte extracts regularly the timing that generation unit 102 produces the H1 byte that extracts TU3.The V1 byte extracts regularly the timing that generation unit 103 produces the V1 byte that extracts TU2.The V1 byte extracts regularly the timing that generation unit 104 produces the V1 byte that extracts TU12.

The H2 byte extracts regularly the timing that generation unit 105 produces the H2 byte that extracts TU3.The V2 byte extracts regularly the timing that generation unit 106 produces the V2 byte that extracts TU2.The V2 byte extracts regularly the timing that generation unit 107 produces the V2 byte that extracts TU12.

Select circuit 108 to select regularly the output (the V1 byte that the V1 byte that the H1 byte that is used for TU3 extracts timing signal, be used for TU2 extracts timing signal, be used for TU12 extracts timing signal) of generation unit 102,103 or 104 according to the multiplexed map information of supplying with by selected cell 101, and with its output.Select circuit 109 to select regularly the output (the V2 byte that the V2 byte that the H2 byte that is used for TU3 extracts timing signal, be used for TU2 extracts timing signal, be used for TU12 extracts timing signal) of generation unit 105,106 or 107 in the same way according to the multiplexed map information of supplying with by selected cell 101, and with its output.

Because adding the time slot of VC4 frame multiplexed TU3 pointer byte, TU2 pointer byte and TU3 pointer byte differs from one another, so above-mentioned pointer extracting unit 11 receives the multiplexed map information of being supplied with by mapping set point registers group 100 and selected cell 101 (the signal specification of each channel of multiplexed data), and extract regularly and the H2/V2 byte is switched between extracting regularly in the H1/V1 byte, thereby extract pointer according to the signal size with serial mode according to this signal specification.

Mix situation about existing with different signal specifications in order to adapt to each channel, the pointer processing unit 12 of this variation, as shown in figure 28, have TU3 with SS-place value holding unit 110, TU2 with SS-place value holding unit 111, TU12 with SS-place value holding unit 112, TU3 with maximum pointer value holding unit 113, the maximum pointer value holding unit 114 that is used for TU2, TU12 with maximum pointer value holding unit 115,

select circuit

116 and 117 and comparing unit 118.

SS-place value holding unit 110 keeps the reception desired value (" 10 ") of the SS position of TU3.SS-place value holding unit 111 keeps the reception desired value (" 00 ") of the SS position of TU2.SS-place value holding unit 112 keeps the reception desired value (" 10 ") of the SS position of TU12.

Maximum pointer value holding unit 113 keeps the maximum (" 764 ") of TU3 pointer value.Maximum pointer value holding unit 114 keeps the maximum (" 427 ") of TU2 pointer value.Maximum pointer value holding unit 115 keeps the maximum (" 139 ") of TU12 pointer value.

Select circuit 116 according to the desired value that is chosen in the SS position of the TU3/TU2/TU12 that keep in SS-place value holding unit 110,111 or 112 by the multiplexed map information that shines upon set point registers group 100 and selected cell 101 supplies, and with its output.Select circuit 117 according to the maximum that is chosen in the pointer value of the TU3/TU2/TU12 that keep in maximum pointer value holding unit 113,114 or 115 by the multiplexed map information that shines upon set point registers group 100 and selected cell 101 supplies in the same way, and with its output.

Comparing unit 118 compares pointer value that receives and the pointer value of being selected by selection circuit 117, and when the reception pointer value greater than by the pointer value of selecting circuit 117 to select the time, output " 1 " is as the pointer value detection signal that transfinites, or exports " 0 " as normal value except that above-mentioned situation.

Above-mentioned pointer processing unit 12 receives the information of the signal specification of relevant each channel from mapping set point registers group 100 and selected cell 101, as reception pointer value (being below 764 or 764 under the TU3 situation, being below 427 or 427 under the TU2 situation, being below 139 or 139 under the TU12 situation) in the range of normal value of signal specification, then produce the reception desired value of SS position, handle thereby carry out aforesaid pointer according to the signal specification with serial mode according to this signal specification.

As concrete example, SS place value by each signal specification decision as shown in table 1 is different, select the SS position corresponding so select circuit 116 according to multiplexed map information with the signal specification, and for example the inconsistent detecting unit in SS position as shown in figure 11 28 detects inconsistent as between the SS position of selected SS place value that receives desired value and reception.

After the pointer value effective range of pressing each signal specification of decision shown in the table 2, reception pointer value shown in Figure 14 transfinites detecting unit 35 according to the mapping set information select finger value scope of being supplied with by selection circuit 117, and switch, transfinite reception (promptly according to what selected pointer value detected pointer value then, in this case, suppose that comparing unit shown in Figure 28 118 is included in the reception pointer value and transfinites in the detecting unit 35).

Mix situation about existing with different signal specifications in order to adapt to each channel, the RAM control unit 13 of this variation, for example, as shown in figure 29, regularly generation unit 119, TU2 visit regularly generation unit 121 and select circuit 122 with RAM with RAM visit timing generation unit 120, TU12 with the RAM visit to have TU3.

The visit timing that each RAM visit timing generation unit 119～121 produces RAM14 (or RAM21 and RAM22).RAM visit regularly generation unit 119 produces the RAM visit timing that is used for TU3.RAM visit regularly generation unit 120 generations is used for the TU2RAM visit regularly.RAM visit regularly generation unit 121 produces the RAM visit timing that is used for TU12.

RAM visit timing generation unit 119,120 that the multiplexed map information signal of selecting circuit 122 bases to be supplied with by mapping set point registers group 100 and selected cell 101 is selected or 121 output (the RAM visit timing signal that is used for TU3/TU2/TU12), and with its output.

Therefore, RAM control unit 13 receives the information of the signal specification of relevant each channel from mapping set point registers group 100 and selected cell 101, and according to signal specification generation RAM visit timing signal, thereby write/read according to the data (information sets) of signal specification control to RAM14.

Above-mentioned TU pointer processing unit 82B (pointer processing apparatus 8B) selects the mapping set point registers group 100 of the channel considered according to the channel address that is produced by address-generation unit 10, thereby each channel of TU3/TU2/TU12 that always can discern multiplexed data with what kind of signal specification shines upon.Therefore, exist, also can carry out pointer and handle with a public circuit even different signal specifications is mixed.

Under the situation of the STM-1 frame being carried out the pointer processing, what for example do not need to provide respectively that as shown in figure 50 the number with maximum 87 channels equates is used to carry out the pointer extraction/treatment circuit 202～204 that pointer extracts and pointer is handled, handle (maximum 3 channels), pointer extraction and the pointer of TU2 are handled (maximum 21 channels), reached pointer extraction and the pointer of TU12 are handled (maximum 63 channels), therefore comprising pointer extraction and pointer TU3.For example carried out the data that pointer handles by the signal specification by parallel/205 pairs of serial (P/S) converting units and select to handle and multiplexed and output again, just becoming there is no need.Point out that in passing the reference numbering 206 among Figure 50 0 is represented serial () S/P converting units, is used for multiplexed data is separated into the data of each signal specification.

Figure 30 is the block diagram of the detailed structure of above-mentioned mapping set point registers group 100 of expression and selected cell 101.As shown in figure 30, as the data of STM-1 frame are handled, then shine upon set point registers group 100 and have 3 (being used for 3 channels) TU3/TUG3 set point registers (TU3/TUG3#1～#3) 123 and each TU3/TUG3 set point register 123 is provided with 21 (being used for 21 channels) TU2/TUG2 of total (set point register 124 of TU2/TUG2#1～#7) of 7.Select circuit 101 to have signal specification recognition unit 125A.

Whether 123 storages of TU3/TUG3 set point register are set at the information of TU3 or TUG3 about the TUG3 that deposits (mapping) in the VC4 frame.For example, are " 1 " as the value of set point register 123, then TU3 is multiplexed in the TUG3 frame.Value as set point register 123 is " 0 ", and then TU2 or TU12 are multiplexed in the TUG3 frame.

Whether 124 storages of TU2/TUG12 set point register are set at the information of TU2 or TUG12 about the TUG2 that shines upon in TUG3.For example, are " 1 " as the value of set point register 124, then TU2 is multiplexed in the TUG2 frame.Value as set point register 124 is " 0 ", and then TU12 is multiplexed in the TUG2 frame.

Signal specification recognition unit 125A is according to the signal specification that is stored in the set point channel that identification is considered in each

set point register

123 and 124, and produce and output is used for the TU3/TU2/TU12 setting signal of address-generation unit 10, with shown in Figure 6 similar, its function realizes with following each parts: the address counter 16 of selecting circuit 125～127,1-input inversion formula AND door 128, full input inversion formula AND door 129 and being used for the address counter 15 of TUG3 and being used for TUG2.

Select circuit 125 to select the information of the TU3/TUG3 set point register 123 corresponding with the channel of indicating by the count value of the address counter that is used for TUG3 15 of address-generation unit 10.Select circuit 126 to select the information of the TU2/TUG2 set point register 124 corresponding with the channel of indicating by the count value of the address counter 16 that is used for TUG2.Select circuit 127 to select the information of the TU2/TUG2 set point register 124 corresponding with the channel of indicating by the count value of the address counter 15 that is used for TUG3.

In the TU pointer processing unit 82B with said structure of this variation, by the set point (data " #1 ", " #2 " or " #3 ") of selecting circuit 125 according to the count value selection TU3/TUG3 set point register 123 of the address counter 15 that is used for TUG3, and produce the TU3 setting signal.Only when TU selected signal to be " 1 ", this TU3 setting signal represented that the channel of being considered is TU3.

Select circuit 126 to select to select one by the count value of selecting circuit 127 bases to be used for the address counter 15 of TUG3 arbitrarily at selected these 3 signals then by 3 from the data #1～#7 of 7 registers supplies of TU2/TUG2 set point register 124 (corresponding to TUG3#1, TUG3#2 and TUG3#3) according to the count value of TUG2 address counter 16.

After this, ask for the inversion signal of TU3 setting signal and the logic product of the output signal of selecting circuit 127 by AND door 128, to produce the TU2 setting signal.Point out in passing, this TU2 setting signal, only when for " 1 ", the channel that expression is considered is TU2.

Then, ask for the logic product of inversion signal with the inversion signal of selecting circuit 127 output signals of TU3 setting signal by AND door 129, thereby produce the TU12 setting signal.Point out that in passing only when this TU12 setting signal was " 1 ", the channel that expression is considered was TU12.Above-mentioned signal specification recognition unit 125A judges whether the channel of being considered is shone upon with TU3 by TU3/TUG3 set point register 123.As this channel is not with the TU3 mapping, and then signal specification recognition unit 125A judges that whether this channel is shone upon with TU2 or TU12 by TU2/TUG2 set point register 124, thereby can discern the signal specification of this channel.

By above-mentioned processing, can be according to the setting data of 24 registers of total of 3 TU3/TUG3 set point registers 123 and 21 TU2/TUG2 set point registers 124 data to maximum 63 channel identification TU levels multiplexed among the VC4.

In order to discern the signal specification of channel multiplexed among the VC4, do not need to provide 207,21 channels of TU3 set point register of 3 channels shown in Figure 51 (1)～51 (c) for example TU2 set point register 208, and the TU12 set point register 209 of 63 channels amount to the individual register of 87 (3+21+63).

In above-mentioned TU pointer processing unit 82B, the register number is reduced about 1/3rd.Can further reduce unit scale, power consumption, the distribution number between functional block of this pointer processing apparatus 8B etc.

Figure 31 is the block diagram of structure that the pointer processing unit 12 of SPE lead byte (J1/V5 byte) recognition function in this variation is noticed in expression.Pointer processing unit 12 shown in Figure 31, as being offset counting unit 97 as shown in figure 25, have TU3 with offset counter 130, TU2 with offset counter 131, be used for the offset counter 132 of TU12 and select circuit 133A mix situation about existing with different signal specifications so that adapt to each channel.

TU3 counts with the offset pointer value of 130 couples of TU3 of offset counter.TU2 counts with the offset pointer value of 131 couples of TU2 of offset counter.The offset pointer value that is used for 132 couples of TU12 of offset counter of TU12 is counted.

Select circuit 133A according to the TU3 setting signal/TU2 setting signal/TU12 setting signal selection of aforesaid signal specification recognition unit 125 generations and the count value of output offset counter 130,131 or 132.Here, select the function of circuit 133A to realize with AND door 133～135 and OR door 136.

Promptly, above-mentioned TU pointer processing unit 82B (pointer processing apparatus 8B) is by the signal specification of each channel of mapping set point registers group 100 and selected cell 101 identification multiplexed datas, and with information providing pointer extracting unit 11, pointer processing unit 12 and RAM control unit 13, thereby can carry out pointer extraction and pointer processing according to the signal specification with a public circuit.For this reason, state TU pointer processing unit 82B and have offset counter 130～132, as the offset counter that provides for each signal specification, according to mapping set information (TU3/TU2/TU12 setting signal) gated counter of supplying with by mapping set point registers group 100 130,131 or 132 count value, with the lead byte of identification SPE.

In having the pointer processing unit 12 of said structure (SPE lead byte recognition unit 97A), ask for the logic product of the output of TU3 setting signal and offset counter 130 by AND door 133, ask for the logic product of the output of TU2 setting signal and offset counter 131 by AND door 134, and ask for the logic product of the output of TU12 setting signal and offset counter 132 by AND door 135.

Then, detect in each operation result (output of OR door 136) of the logic product of trying to achieve and the existing consistency of using between the pointer value that allows signal to read according to SPE by consistency detection unit 98 from RAM89 with these 3 AND doors 133～135, and by the output of AND door 99 trying to achieve a consensus property detecting units 98 and the logic product of SPE permission signal, thereby produce and output J1/V5 byte index signal.

Promptly, pointer processing unit 12 is according to logic product of being tried to achieve by the AND door 133～135 that constitutes selection circuit 133A and the logic and the switching skew count value corresponding with the setting signal specification of trying to achieve with the OR door, and selected skew count value compared with pointer value with existing, even thereby different signal specifications mix to exist, also can discern the lead byte of SPE reliably.

Therefore, do not need to provide for example TU3 shown in Figure 52 (a) that equates with each number of channel with SPE lead byte (j1 byte) identification circuit 210, TU2 shown in Figure 52 (b) with SPE lead byte (V5 byte) identification circuit 211 and the SPE lead byte that is used for TU12 (V5 byte) identification circuit 212 shown in Figure 52 (c), thereby can reduce the unit scale, power consumption, the distribution number between functional block etc. of this pointer processing apparatus 8B to the utmost.

Point out in passing, in Figure 52 (a)～52 (c), with reference to numbering the existing pointer value holding unit of using that 213A, 213C and 213E represent to be used for TU3, TU2 respectively, reach TU12.With reference to numbering the skew counting unit that 213B, 213D and 213F represent to be used for TU3, TU2 respectively, reach TU12,213～215 expression consistency detection unit, and 216～218 expression AND doors.

Figure 32 is the block diagram of structure that the pointer processing unit 12 of the pointer change function in this variation is noticed in expression.Pointer processing unit 12 shown in Figure 32 has the RAM141 and the AND door 142 that are used to change pointer that writes number of words counter 139, read out word counter 140, has the ES memory function.

Write row (word) number that writes data indication RAM141 in 139 couples of RAM141 of number of words counter.The number of words that 140 pairs of data of reading from RAM141 of read out word counter are indicated RAM141.

Pointer processing unit 12 with said structure will write the count value of number of words counter 139 and channel address addition at receiver side, to produce the address that writes to RAM141, in addition with the count value of read out word counter 140 and the channel address addition of transmitter side, to produce from the address that RAM141 reads.

SPE according to transmitter side allows signal, the J1/V5 byte index signal of the receiver side that will produce by the SPE lead byte recognition unit 97A shown in Figure 31 (or Figure 25), with the multiplexed data (VCn: wherein n is 2,3,4 or 12) that receives, for example write in as shown in figure 33 the zone by the above-mentioned RAM141 that writes the address indication with the serial mode order.Point out in passing, not necessarily always data are remained in the RAM141 according to order shown in Figure 33.

Allow signal (reading the timing of side) according to SPE at transmitter side, above-mentioned each data of RAM141 that will write are successively from being read by above-mentioned zone of reading the address indication, the J1/V5 byte index signal of use in these data, and allow the logic product of signal, thereby produce the J1/V5 byte index signal that is used to send multiplexed data by the SPE that the public AND door 142 of all channels is asked for this J1/V5 byte index signal and transmitter side.Utilize this signal can be identified in the lead byte of the SPE of transmitter side.

Promptly, above-mentioned pointer processing unit 12 will indicate the SPE data and the information bit (J1/V5 byte index signal) (with serial mode) of the SPE lead byte of input multiplexed data to write in the RAM141, and read the data that write RAM141 by the timing of reading side (with serial mode), so that from the value identification SPE bit preamble of the sense information position of indication SPE lead byte.

Therefore, do not need shown in Figure 53, to provide respectively the SPE lead byte identification circuit 219A that is used to ask for that equates with the number of channel of the multiplexed data that should handle to discern the SPE lead byte that the change pointer is used from ES memory 220 J1/V5 byte index signal of reading and the logic product that sends SPE permission signal.Even each channel exists with different signal specification mixing in multiplexed data, also can handle all channels, thereby can reduce unit scale, power consumption, the distribution number between functional block of this pointer processing apparatus 8B etc. to the utmost with a public circuit.

Figure 34 is the above-mentioned block diagram that writes the structure of number of words counter 139 (or read out word counter 140) of expression.The number of words counter 139 that writes shown in Figure 34 has 3 TU3 and (is used for the 14A of 3 channel: TU3#1～TU3#3) and selects circuit 152 with counting unit.TU3 has 1 TU3/TU2 with each counting unit 14A to be shared counting unit (TU3/TU2#1) 14B, 6 and is used for TU2 (the counting unit 14C of TU2#1～TU2#7) and select circuit 151.

As shown in figure 34, the TU3 of a channel with counting unit 14A in, TU3/TU2 share counting unit 14B have TU3/TU2 sharing E S number of words counter 145, TU3 with decoding circuit 146, the decoding circuit 148 that is used for TU2, AND

door

147 and 149, reach OR door 150.Each TU2 has TU2 ES number of words counter 143 and TU2 decoding circuit 144 with counting unit 14C

Use among the counting unit 14C at each TU2, TU2 counts with the ES number of words of 143 couples of TU2 of ES number of words counter, and TU2 deciphers with the maximum of the ES number of words of 144 couples of TU2 of decoding circuit.For example, be 12 as the ES number of words of TU2, then TU2 deciphers with the count value " 11 " of ES number of words counter 143 with 144 couples of TU2 of decoding circuit.Signal after this decoding as the signal of packing into, is packed into " 0 " in ES number of words counter 143 at TU2, thereby made TU2 become the 12 system counters that from " 0 " to " 11 " counts usefulness with ES number of words counter 143.

Share among the counting unit 14B at TU3/TU2, TU3 deciphers with the maximum of the ES number of words of 146 couples of TU3 of decoding circuit, TU2 deciphers with the maximum of the ES number of words of 148 couples of TU2 of decoding circuit, AND door 147 is asked for the TU3 output signal of decoding circuit 146 and the logic product of above-mentioned TU3 setting signal, AND door 149 is asked for the output signal of the decoding circuit 148 that is used for TU2 and the logic product of above-mentioned TU2 setting signal, and OR door 150 ask for AND

door

147 and 149 output signal logic and, and export this disjunction operation result as the signal of packing into to TU3/TU2 sharing E S number of words counter 145.

The ES number of words of 145 couples of TU3 of TU3/TU2 sharing E S number of words counter or TU2 is counted.The switching mode that the ES number of words counting operation to TU3 of TU3/TU2 sharing E S number of words counter 145 reaches the ES number of words counting operation of TU2 is to switch the incoming timing of the signal of being supplied with by OR door 150 of packing into according to above-mentioned TU3 setting signal and TU2 setting signal.

As for example, be 18 as the ES number of words of TU2, then TU3 deciphers with the count value " 17 " of 146 pairs of these counters 145 of decoding circuit, and TU2 deciphers with the count value " 11 " of 148 pairs of these counters 145 of decoding circuit simultaneously.Use each decoded signal, ask for the logic product of this decoded signal and TU3 setting signal or TU2 setting signal by the AND

door

147 or 149 of correspondence.As the TU3 setting signal is " 1 " (this moment, the TU2 setting signal was " 0 "), and the signal that obtains after then being deciphered with 146 pairs of count values of decoding circuit " 17 " by TU3 becomes the signal of packing into, pack into " 0 " in counter 145.Therefore, when being set at TU3, this counter 145 constitutes the counter that ES number of words " 18 " to TU3 (from " 0 " to " 17 ") is counted.

As the TU2 setting signal is " 1 " (this moment, the TU3 setting signal was " 0 "), and the signal that obtains after then being deciphered with 148 pairs of count values of decoding circuit " 11 " by TU2 becomes the signal of packing into, pack into " 0 " in counter 145.Therefore, when being set at TU2, this counter 145 constitutes the counter that ES number of words " 11 " to TU2 (from " 0 " to " 11 ") is counted.

For the setting that switches in TU3 mapping constantly and the count value of TU2 between setting constantly, above-mentioned write number of words counter 139 have TU3 with decoding circuit 146 and TU2 with decoding circuit 148, respectively the count value of TU3 and the count value of TU2 are deciphered.This writes number of words counter 139 and selects to be used for decoding circuit 146 or the TU2 output signal of decoding circuit 148 of TU3 according to the signal specification, and adopts this output signal as the signal of packing into to counter 145.Therefore, the number of words counter 139 (with reference to Figure 32) that writes of RAM141 can be used as a public counter use when TU3 mapping and TU2 mapping.

Select circuit 151 from the count value of 7 channels, promptly 1 TU3/TU2 shares the output (count value) of counting unit 14B and 6 TU2 with selection the output (count value) of counting unit with export a count value.Selection circuit 151 has the function of always selecting TU3/TU2 to share the output of counting unit 14B when being set at TU3.Selection circuit 152 is selected from the output (count value) of TU3 with counting unit 14A (selecting circuit 151) of 3 channels and is exported one.

Have the writing in the number of words counter 139 (or read out word counter 140) of said structure, signal specification as the TU level of shining upon in the VC4 frame is TU3, then the TU3 setting signal of supplying with from signal specification recognition unit 125A (with reference to Figure 30) becomes " 1 ", thereby will write number of words counter 139 and be set at TU3.Therefore, share the counter works that counter 145 conducts among the counting unit 14B are counted the ES number of words at TU3/TU2, each count value of this counter 145 (to being used for 3 channels of TU3#1～TU3#3) is exported as ES number of words count value with serial mode by selector 151 and 152.

Signal specification as the TU level of shining upon in the VC4 frame is TU2, and then the TU2 setting signal of supplying with from signal specification recognition unit 125A (with reference to Figure 30) becomes " 1 ", thereby will write number of words counter 139 and be set at TU2.Therefore, the counter works that counter 145 in the shared counting unit 14B of TU3/TU2 and each TU2 count the ES number of words of TU2 with counting unit 143 conducts, each count value of this counter 145 (to being used for 3 channels of TU3#1～TU3#3), by selector 151 and 152 with serial mode output count value as the ES number of words, and with each TU3 (count value of TU2#1～TU2#7) (amounts to 3 * 7=21 channel) is exported as ES number of words count value with serial mode by passing through selector 151 and 152 with 7 channels of ES number of words counting unit 14A.

Above-mentioned pointer processing unit 12 (pointer processing apparatus 8B) has decoding circuit 144,146 and 148, be used for according to the maximum of counter 145 being switched in the TU level signal specification (TU3/TU2) of multiplexed data (VC4 frame) mapping, therefore, even different signal specifications, be that TU3 and TU2 mix existence in multiplexed data, also can count the ES number of words with the public number of words counter 139 (or read out word counter 140) that writes.

Therefore, the TU3 that does not need to provide 3 channels shown in Figure 54 (a) with ES word counter 222, thereby can reduce the unit scale, power consumption, the distribution number between functional block etc. of this pointer processing apparatus 8B with the TU2 of

ES word counter

221,21 channels shown in Figure 54 (b) to the utmost.

For the signal that adapts to all TU levels (TU3/TU2/TU12) mixes situation about existing, the above-mentioned number of words counter 139 (or read out word counter 140) that writes, for example, as shown in figure 35, have 3 TU3 with counting unit 16A (being used for 3 channels) and select circuit 172.TU3 has 1 TU3/TU2/TU12 with each counting unit 16A to be shared counting unit 161 (TU3/TU2#1/TU2#1), 6 and is used for TU2/TU12 and shares counting unit 166 (TU2#2～TU2#7) and select circuit 171.

As shown in figure 35, use among the counting unit 16A at the TU3 of a channel, the shared counting unit 161 of TU3/TU2/TU12 has TU3/TU2/TU12 shared cell 163, is used for the ES number of words counter 164 and 165 of TU12, reaches and select circuit 162, therefore, each TU2/TU12 share counting unit 166 and have TU2/TU12 shared cell 168 and 170, be used for TU12 ES number of words counter 169 and 170, and select circuit 167.

Share in the counting unit 161 at TU3/TU2/TU12, the ES number of words of 163 couples of TU2 of TU3/TU2/TU12 shared cell or TU12 is counted.The counting operation of the ES number of words of the TU3/TU2/TU12 of TU3/TU2/TU12 shared cell 163 (maximum of counter) switches according to above-mentioned TU3 setting signal, TU2 setting signal and TU12 setting signal.

Specifically, TU3/TU2/TU12 shared cell 163, as shown in figure 36, have TU3/TU2/TU12 sharing E S number of words counter 153, TU3 with decoding circuit 146, TU2 with decoding circuit 148, the decoding circuit 155 that is used for TU12, AND door 147,149 and 157, and OR door 159.Identical at counting unit 14B on principle with shown in Figure 34, TU3/TU2/TU12 shared cell 163 is according to TU3 setting signal, TU2 setting signal and TU12 setting signal, respectively after the decoding that will obtain by decoding circuit 146,148 and 155 signal with the signal of doing counter 153 of packing into, thus when being set at TU3 the maximum of count value, when being set at TU2 count value maximum and switch between the maximum of count value when being set at TU12.

Respectively being used for the ES number of words counter 164 of TU12 and the ES number of words of 165 couples of TU12 counts.Select circuit 162 from TU3/TU2/TU12 shared cell 163 and be used for the ES number of words counter 164 of TU12 and 165 output is selected and exported one of them.Select circuit 162 to have the function of when being set at TU3 by the TU3 setting signal or being set at TU2, always selecting the output of TU3/TU2/TU12 shared cell 163 by the TU2 setting signal.

Share in the counting unit 166 at each TU2/TU12, the ES number of words of 168 couples of TU2 of TU2/TU12 shared cell or TU12 is counted, it switches according to above-mentioned TU2 setting signal and TU12 setting signal to the counting operation of the ES number of words of TU2 with to the counting operation of the ES number of words of TU12.

For this reason, specifically, for example, as shown in figure 37, TU2/TU12 shared cell 168 has TU2/TU12 sharing E S number of words counter 154, TU2 with decoding circuit 144, the decoding circuit 156 that is used for TU12, AND door 149 and 158, and OR door 160.In this case, according to TU2 setting signal and TU12 setting signal, signal switches between the count value maximum during count value maximum when TU2 sets and TU12 setting thus mutually with the signal of doing counter 154 of packing into after the decoding that will be obtained by decoding circuit 144 and 156 respectively.

The ES number of words counter 169 and 170 that is used for TU12, similar with above-mentioned counter 164 and 165, be respectively applied for the ES number of words of TU12 is counted.Select circuit 167 from TU2/TU12 shared cell 168 and be used for the ES number of words counter 169 of TU12 and 1705 output is selected and exported one of them.Select circuit 167 to have the function of when being set at TU2, always selecting the output of TU2/TU12 shared cell 168 by the TU2 setting signal.

Promptly, the number of words counter 139 (or read out word counter 140) that writes shown in Figure 35 has a kind of like this structure, promptly the ES number of words counter 143 of TU2 shown in Figure 34 and TU3/TU2 sharing E S number of words counter 145 further is provided for the control system that the ES number of words when being set at TU12 is counted.For example, as the ES number of words when being set at TU12 is 10, then when being set at TU12, count value " 9 " is deciphered by each decoding circuit 155 and 156 (with reference to Figure 37) that is used for TU12, and will decipher the back signal as to the signal of packing into of each counter 153 and 154, thereby make each counter 153 and 154 constitute the counter that ES number of words " 10 " to TU12 (from " 0 " to " 9 ") is counted.

Above-mentioned selection circuit 171 is selected and is exported one of them from the output (count value) of above-mentioned counter 161 and 166.Select circuit 171 to have the function of when being set at TU3, always selecting the output of counting unit 161 by the TU3 setting signal.Select circuit 172 from the TU3 of 3 channels with the output selection of counting unit 16A with export one of them.

As shown in figure 35 have the writing in the number of words counter 139 (or read out word counter 140) of said structure, when the signal specification of the TU level of shining upon in the VC4 frame is TU3, the TU3 setting signal of supplying with from signal specification recognition unit 125A (with reference to Figure 30) becomes " 1 ", thereby the counter works that counter 153 conducts in the TU3/TU2/TU12 shared cell 163 are counted the ES number of words of TU3.

At this moment owing to select circuit 162 and 171 to be set to TU3, so always select the output of TU3/TU2/TU12 shared cell 163 and the output of counting unit 161, and pass through to select circuit 172 with the count value of count value output as the ES number of words of TU3 with serial mode.

When the signal specification of the TU level of shining upon in the VC4 frame is TU3, to write number of words counter 139 by the TU2 setting signal and be set at TU2, thereby make the counter 153 in the TU3/TU2/TU12 shared cell 163 reach the counter 154 of the TU2/TU12 shared cell 168 in each counting unit 166 as the counter works that the ES number of words of TU2 is counted.

At this moment owing to select circuit 162 and 167 to be set to TU2, so always select the output of the TU2/TU12 shared cell 168 of the output of TU3/TU2/TU12 shared cell 163 and each counting unit 166, and with serial mode by selecting circuit 172 with the count value of count value output as the ES number of words of TU2.

Signal specification as the TU level of shining upon in the VC4 frame is TU12, then will write number of words counter 139 and be set at TU12, thereby make the counter 153 in the TU3/TU2/TU12 shared cell 163 reach the counter 154 of the TU2/TU12 shared cell 168 in each counting unit 166 as the counter works that the ES number of words of TU12 is counted by the TU12 setting signal.

Then, select the output of TU3/TU2/TU12 shared cell 163 (TU2/TU12 shared cell 168) and the output of each counting unit 164 and 165 (169 and 170) successively by selection circuit 162 (172), thereby export the ES number of words count value of TU12 by selecting circuit 171 and 172 with serial mode.

Above-mentioned pointer processing unit 12 (pointer processing apparatus 8B) have TU3 with decoding circuit 146, be used for the decoding circuit 148 of TU2 and be used for the decoding circuit 156 of TU12, respectively the count value of TU3, the count value of TU2 and the count value of TU12 are deciphered, press the signal specification and select the output signal of decoding circuit 146,148 or 156, and adopt the signals selected signal of packing into that is used as counter 153, even thereby TU3/TU2/TU12 mapping, also can write number of words counter 139 (or read out word counter 140) and use as a public counter.Therefore, pointer processing unit 12 can be operated the hybrid combining ((1+27) * (1+27) * (1+27)) of all TU level signals with amounting to the individual counter in 63 (=(3+3 * 6) * 3).

Therefore, the TU3 that does not need to provide 3 channels shown in Figure 54 (a) for example with ES number of words counter 222, the ES number of words counter 223 that is used for TU12 of 63 channels shown in Figure 54 (c), thereby can reduce unit scale, power consumption, the distribution number between functional block of this pointer processing apparatus 8B etc. with ES number of words counter 221, the TU2 of 21 channels shown in Figure 54 (b) to the utmost.

(b-3) explanation of AU4 pointer processing unit

Figure 38 is the block diagram of structure that the pointer processing apparatus 8B of AU pointer processing unit 81B shown in Figure 3 is noticed in expression.As shown in figure 38, AU pointer processing unit 81B has AU4 pointer detecting unit 174, ES memory cell 175, ES and writes number of words counter 176, pulse generator (PG) 177, ES read out word counter 178 and phase comparison unit 179.

Above-mentioned AU4 pointer detecting unit 174 detects AU4 pointer according to the received frame signal and the clock of transmission line trackside from the multiplexed data that receives according to the timing signal that is produced by pulse generator 177 the SDH transmission system, so that change the processing of AU4 pointer, the processing etc. of j1 byte index signal of position that produces VC4 and allow Signal Processing, produces the SPE lead byte (j1 byte among the POH) of indication VC4 according to the clock of transmission line trackside.

EA memory cell 175 is to be used for the memory of transfering clock.Clock according to the transmission line trackside will write ES memory cell 175 by the multiplexed data (comprising that VC4 allows signal, j1 byte index signal) that AU4 pointer detecting unit 174 receives, and read from the ES memory cell, thereby make the multiplexed data transfering clock of reception according to the clock of device side.

ES writes the clock operation of number of words counter 176 according to the transmission line trackside, will receive the operation that multiplexed data writes ES memory cell 175 to the clock by transmitter side thus and control.ES read out word counter 178 is according to the clock operation of device side, will write the operation that the reception multiplexed data of ES memory cell 175 reads to the clock by device side thus and control.

ES is write the count value of number of words counter 176 to phase comparison unit 179 and the count value of ES read out word counter 178 compares, to detect the phase difference between the two, and by ES read out word counter 178 according to this phase difference control read operation, receive multiplexed data in the time of thus and fill control (phase place adjustment control).

In having the AU pointer processing unit 81B of said structure, AU4 pointer detecting unit 174 conversion AU4 pointers produce VC4 and allow signal and j1 byte index signal, then the data in the VC4 zone are write ES memory cell 175.ES writes the clock operation of number of words counter 176 according to the transmission line trackside, so that according to the clock of transmission line trackside these data are write ES memory cell 175.

On the other hand, because ES read out word counter 178 is according to the clock operation of device side, so the clock by device side is read data from ES memory cell 175, at this moment, phase comparison unit 179 compares the clock phase (count value of counter 178) of device side and the clock phase (count value of counter 176) of transmitter side, and comparative result supplied with ES read out word counter 178, fill the transfer of control and clock thus.

To supply with TU pointer processing unit 181 through the data after the oversampling clock transfer processing, the clock signal of use device side is carried out the TU pointer processing of change TU pointer as described later in this processing unit 181.

In above-mentioned AU pointer processing unit 81B, the count value detected phase that writes number of words counter 176 and ES read out word counter 178 from ES is poor, filling control, thereby in ES storage origin 75, data clock is transferred to the clock of device side from the clock of transmission line trackside.As the shake of considering clock when the number of words of decision ES memory and drift etc., then only need to consider a channel of AU4 pointer.

As illustrating with reference to Figure 67, for the shake that absorbs clock and the influence of drift, as by TU pointer processing unit 245 ' transfering clock, then the number of words of ES memory must equal all numbers of channel.In contrast, present embodiment can reduce unit scale and the power consumption of this pointer processing apparatus 8B to the utmost.

In Figure 38, the TU pointer processing unit 82B that its structure is simplified by various functions has: TU pointer processing unit 181 is used for detecting (extraction) TU pointer (H1/V1 byte, H2/V2 byte, H3/V3 byte); ES memory cell 182 is used to change pointer; And TU pointer calculating insertion unit 183, be used for calculating and inserting (filling control and treatment) TU pointer.Point out that in passing the clock that data is write or read all by device side from ES memory cell 182 carries out.

For example, as shown in figure 39, above-mentioned ES memory cell 182, fill controlled function and the identical filling control unit 182A of above-mentioned AU pointer processing unit 81B as it, has frame counter 82A-1, phase comparison unit 82A-2, SPE allows signal generation unit 82A-3 and RAM82A-4, wherein, to compare by writing number of words counter 139 phase place that writes the side count value that produces and the phase place of reading the side count value that produces by read out word counter 140 with reference to Figure 32～37 are described as preamble by phase comparison unit 82A-2, thereby produce filling control signal (bear/just filling request signal) according to the phase difference between count value.

Specifically, above-mentioned phase comparison unit 82A-2 deducts and reads the side count value from writing the side count value.As the result who subtracts each other bears, and then phase comparison unit 82A-2 produces and just filling request signal.As the result who subtracts each other is positive, and then phase comparison unit 82A-2 produces and negatively fills request signal, thereby described later transmission pointer value keeps and upgrades the phase place of adjusting multiplexed data in handling.

Just filling request signal of Chan Shenging and the negative request signal of filling are write in the zone of RAM82A-4 of address ram (channel address) indication that is produced by address-generation unit 10 (with reference to Fig. 4) successively in a manner described, produce the signal that transmitter side allows signal as allowing at SPE among the signal generation unit 82A-3 in addition.SPE permission signal generation unit 82A-3 allows signal according to the output generation transmitter side SPE that just above-mentioned/negative filling request signal reaches by the frame counter 82A-1 of transmitter side frame signal operation.

Above-mentioned number of words counter 139 and the read out word counter 140 of writing is configured to adapt to as preamble and mixes situation about existing with reference to the described unlike signal specification in Figure 32～37.But, be not mix to exist as the unlike signal specification, that is, as in advance known processed be the signal of TU frame, then use corresponding with this signal specification counter that number of words is counted just enough.

Above-mentioned TU pointer calculates and inserts unit 183, as the functional unit that calculates and insert the TU pointer, has structure transmission pointer value maintenance/updating block 182B as shown in figure 40 and pointer byte insertion unit 182C shown in Figure 41.

As shown in figure 40, above-mentioned transmission pointer value maintenance/updating block 182B has address-generation unit 82B-1, RAM control unit 82B-2, pointer value is calculated offset counter 82B-3, is used to keep sending the RAM82B-4 of pointer value and send pointer value upgrade control unit 82B-5.In addition, send pointer value renewal control unit 82B-5 and have consistency detection unit 82B-6, selector 82B-7, adder-subtracter 82B-8 and inverse gate 82B-9, point out in passing that address-generation unit 82B-1 and RAM control unit 82B-2 have respectively and address-generation unit shown in Figure 4 10 and RAM control unit identical functions.

In sending pointer value maintenance/updating block 182B, should insert the transmission pointer value that sends multiplexed data by RAM control unit 82B-2 writes successively by channel address generation unit 82B-1) in the zone of the RAM82A-4 of the channel address indication that produced, then, the transmission pointer value of inserting unit 182C as shown in figure 41 pointer byte is read it.When reading, send pointer value upgrade control unit 82B-5 according to supply with by filling control unit 182A as preamble with reference to Figure 39 just described/the negative request signal of filling will send pointer value and upgrade (fill and control).

Specifically, in sending pointer value renewal control unit 82B-5, consistency detection unit 82B-6 is according to the consistency of transmission J1/V5 index signal detection between the count value of transmission pointer value (sense data) of reading from RAM82B-4 and offset counter 82B-3 of reading from RAM141 shown in figure 32.As the two unanimity, then will select circuit 82B-7 to switch to RAM82B-4, so that select sense data (transmission pointer value) by the RAM82B-4 supply.

Inconsistent as the two, then will select circuit 82B-7 to switch to offset counter 82B-3, so that select the skew count value as sending pointer value.By inverse gate 82B-9 with the testing result of consistency detection unit 82B-6 anti-phase be the NDF detection signal, and remain in the RAM82B-4 with sending pointer value, then, when reading, the pointer byte that outputs to as shown in figure 41 as NDF transmission request signal inserts unit 182C.

When receiving when just filling request signal, to add "+1 " by the transmission pointer value of selecting circuit 82B-7 to select by adder-subtracter 82B-8, and, add " 1 " by adder-subtracter 82B-8, and write RAM82BB-4 as new transmission pointer value when receiving when just filling request signal.As both not receiving the positive negative filling request signal of also not receiving, then adder-subtracter 82B-8 makes and selects the output of circuit 82B-7 directly to pass through, and this transmission pointer value is not upgraded.

After this; according to supply with by filling control unit 182A just/negatively fill request signal (with reference to Figure 39), send request signal (with reference to Figure 40), shift AIS status signal (with reference to Figure 22) that protected location 81A supplies with by alarm condition and wait and above-mentioned transmission pointer value is inserted the transmission multiplexed data of reading from RAM141, and output conduct transmission multiplex signal according to the frame signal of transmitter side by sending NDF that pointer value maintenances/updating block 182B supplies with.Point out that in passing pointer byte inserts unit 182C and carries out the processing of following (1)～(5):

(1), inserts all I positions (with reference to Figure 64) of sending pointer value in positive byte of padding district, inserts H1/V1 byte and H2/V2 byte and insert byte of padding when receiving when just filling request signal;

(2) negative when filling request signal when receiving, insert all D positions (with reference to Figure 64) of sending pointer value in negative byte of padding district (being the H3/V3 byte), insert H1/V1 byte and H2/V2 byte and insert the SPE signal;

(3) when receiving NDF transmission request signal, allow indication to insert N position (with reference to Figure 64) NDF;

(4) when receiving the AIS status signal (when the AIS status signal is " 1 ") sends pointer bytes with all and is set at " 1 ";

(5) except that the situation of above-mentioned (1)～(4), NDF is forbidden indication insertion N position.

The explanation of the variation of (b-3 ') AU4 pointer processing unit

Figure 42 is the block diagram of the variation of expression AU4 pointer processing unit 81B.AU4 pointer processing unit 81B shown in Figure 42 except that structure shown in Figure 38, also has AU4 pointer calculating/insertion unit 184, is used for calculating and insert the AU4 pointer according to transmit frame signals.In Figure 42,, be used for sending the STM-1 frame according to the clock generating of transmit frame signals and device side with reference to numbering 185 indicating impulse generators (PG).

In having the AU4 pointer processing unit 81B of said structure, ES memory cell 175 is carried out as preamble with reference to described filling control and treatment of Figure 38 and clock transfer processing.In addition, read the VC4 data according to the transmission STM-1 frame that produces by pulse generator 185 from ES memory cell 175, AU4 pointer calculating/insertion unit 184 calculates the AU4 pointer and is inserted into the VC4 data, then, these data of having inserted the AU4 pointer is supplied with TU pointer processing unit 82B.

By monitoring the AU4 pointer value treatment state from the data detection memory cell 175 of the AU4 pointer of more correcting one's mistakes (for example, whether inserting the state of filler pulse) at an easy rate.For example, as any problem takes place in pointer is handled, then thus apace problem identificatioin occur in the processing of AU4 pointer or occur in the processing of TU pointer so that this problem is handled.

As preamble with reference to Figure 160 in the described pointer processing apparatus 243, since AU4 pointer processing unit 244 ' in the AU4 pointer is carried out terminal processes, even so monitor AU4 pointer processing unit 244 ' dateout, also be difficult to check and fill state of a control etc.

According to present embodiment, have as shown in Figure 3 the pointer processing apparatus 8B of AU4 pointer calculating/insertion unit 81B and have and select circuit 83B, be used for selecting and the output of output AU4 pointer processing unit 81B ' or the output of pointer processing unit 82B according to the mode initialization signal of supplying with from the outside as shown in figure 43.The pulse generator 177 and 185 shown in Figure 42, ES number of words counter 178 and phase comparison unit 179 in Figure 43, have been omitted.

In pointer processing apparatus 8B shown in Figure 43, by selecting circuit 83B to export selectively wherein by AU4 pointer processing unit 81B ' insertion AU4 pointer or by the data behind the TU pointer processing unit 82B insertion TU pointer according to the mode initialization signal.

As cross-coupled unit is VC4, then by mode initialization signal select more the to correct one's mistakes data of AU4 pointer.As cross-coupled unit is VC3/VC2/VC1, then by mode initialization signal select more the to correct one's mistakes data of TU pointer, and with its output.

At the cross connection device 8D (with reference to Fig. 3) that is arranged in this pointer processing apparatus 8B back one-level, cross-connection unit (hardware) 226 can be with VC4/VC3/VC2/VC12) be that a unit carries out corresponding interconnection by public mode to the data of more the correct one's mistakes data of AU4 pointer and the TU pointer of more correcting one's mistakes and handles, thereby can further reduce the unit scale of cross connection device 8D.

(b-4) other

As have the AU4 pointer processing unit 81B that in (b-3) item, illustrates, then pointer processing apparatus 8B can adopt general device as TU pointer processing unit 82B.As have the TU pointer processing unit 82B that in (b-2) item, illustrates, then pointer processing apparatus 8B can adopt general device as TU4 pointer processing unit 81B.Above-mentioned pointer processing apparatus 8B not necessarily always has AU4 pointer processing unit 81B and TU pointer processing unit 82B simultaneously, but can only have the TU pointer processing unit 82B of explanation in (b-2) item, used as carrying out the isolated plant that the TU pointer is handled.

(b-5) the integrally-built explanation of POH terminal processes device

Figure 56 is the block diagram of major part structure of the line termination device 306 that is suitable for of POH terminal processes device of the expression embodiment of the invention.Shown in Figure 56, line termination device 306 has current using system 1003A and back-up system 1003B, and each system has SOH terminal processes unit 1004, AU pointer processing unit 1005, TU pointer processing unit 1006, elastic storage (ES) memory cell 1007, POH terminal processes unit (POH terminal processes device) 1008 and passage and switches the insertion unit 1009 of reporting to the police.Last 1 SOH terminal processes unit 1004, AU pointer processing unit 1005, TU pointer processing unit 1006, POH terminal processes unit 1008 correspond respectively to SOH/POH terminal processes unit 8A shown in Figure 3, AU4 pointer processing unit 81B, TU pointer processing unit 82B, POH terminal processes unit 8C.

In the line termination device shown in Figure 56 306, when detecting the various warning of in the SDH terminal system, stipulating by POH terminal processes unit 1008, the warning message of TIM, UNEQ in the various alarm detection information, SLM is sent to passage switch to report to the police and insert unit 1009, (μ-COM) 1010 in addition BIPPM to be notified microcomputer.When receiving this notice, microcomputer 1010 usefulness softwares are handled this warning, then passage are switched to report to the police and insert the insertion that unit 1009 setting passages switchings are reported to the police.More precisely, microcomputer 1010 is that the TU channel of ALL " 1 " carries out signal sets to the detection of its TIM, SLM, UNEQ, the every warning of BIPPM.

When in cross connection device 1011, detecting fault, current using system 1003A is switched to back-up system 1003B.

Figure 57 is the block diagram of structure that the line termination device 306 of TU pointer processing unit 1006 and POH terminal processes unit 1008 is noticed in expression.Shown in Figure 57, TU pointer processing unit 1006 has TU pointer serial process unit 1061 and TU pointer timing generation unit 1062.As described later, the J1/V5 byte timing signal that TU pointer serial process unit 1061 produces, by TU pointer regularly the TU address signal (TUAD) that produces of generation unit 1062 and mapping signal etc. is used when handling by POH terminal processes unit 1008.

For this reason, TU pointer serial process unit (list pointer processing unit) 1061 has pointer extracting unit 1061-1, pointer processing unit 1061-2, RAM (random access memory) control unit 1061-3, RAM1061-4, and shown in Figure 58, TU pointer regularly generation unit 1062 has address-generation unit 1062-1.

In above-mentioned TU pointer timing generation unit 1062, address-generation unit 1062-1, according to the frame signal that produces by means of detection, produce the address (channel address) of each channel (multiplexed data) of distributing to TU level multiplexed in STM-1 frame (VC4 signal) to the frame synchronization mode in the SOH that is included in the STM-1 frame (A1 and A2 byte).According to present embodiment, in the processing of being undertaken by POH terminal processes unit 1008, use the address information (TUAD) of TU channel address as the TU channel that is used for differentiating the VC4 signal.

In TU pointer serial process unit 1061, pointer extracting unit 1061-1 extracts the pointer byte (comprising H1/V1 byte and H2/V2 byte at least) of each channel from multiplexed data with serial mode.Pointer processing unit 1061-2 analyzes pointer according to the multiplexed data of being supplied with by pointer extracting unit 1061-1 with serial mode, and detects the pointer state or the change pointer of each channel.

RAM control unit 1061-3 produces control signal, is used for controlling writing/to read the operation of RAM1061-4 with serial mode to the result of each channel by what pointer processing unit 1061-2 obtained.RAM1061-4 remains on the dateout of pointer processing unit 1061-2 in the zone of being indicated by the channel address to each channel of address-generation unit 1062-1 supply.

In Figure 58, with reference to numbering 1100 ' expression mapping set point registers group, and with reference to label 1101 ' expression selected cell.Mapping set point registers group 1100 ' be used for is set in the signal specification that each channel of TU3/TU2/TU12 of multiplexed data (STM-1 frame) sets.Each channel is distributed in selected cell 1101 ' utilization by address-generation unit 1062-1 address choice is by the signal specification of the respective channels of mapping set point registers group 1100 ' supply with, and with serial mode (multiplexed and) output map information.Mapping set point registers group 1100 ' and selected cell 1101 ' detailed structure will be below with reference to Figure 61 explanation.

In having the TU pointer processing unit 1006 of said structure, according to the permission write signal that produces by RAM control unit 1061-3 (detection of reception pointer byte regularly), will write according to address by the information sets that pointer extracting unit 1061-1 and pointer processing unit 1061-2 produce by the indicated RAM1601-4 of the address ram (channel address) of address-generation unit 1062-1 generation.

Pointer processing unit 1061-2 reads the information sets of former frame according to the permission read output signal that is produced by RAM control unit 1061-3 from RAM1601-4, and utilizes the information sets of each channel of reading to carry out the pointer processing with serial mode.

Figure 59 is the block diagram of the above-mentioned address-generation unit 1062-1 detailed structure of expression.Shown in Figure 59, address-generation unit 1062-1, similar with address-generation unit 10 shown in Figure 6, have the address counter 1015 that is used for TUG3, the address counter 1016 that is used for TUG2, TU12 address counter 1017, AND door (logic integrated circuit) 1018,1-input inversion formula AND door 1019 and address conversioning unit 1020.

The multiplexed TUG3 number (number of channel) (multiplexed maximum 3 channels) of 1015 pairs of STM-1 frames of address counter (ternary counter) that is used for TUG3 is counted.The number of channel (multiplexed maximum 7 channels) that is used for 1016 couples of TUG2 that the TUG3 frame is multiplexed of address counter (septenary counter) of TUG2 is counted.The number of channel (multiplexed maximum 3 channels) that is used for the multiplexed TU12 of 1017 pairs of TUG2 frames of address counter (ternary counter) of TU12 is counted.Each address counter 1015～1017 is by the frame signal initial value of packing into.

In this case, shown in Figure 59, the carry output (CO) of address counter 1015 is connected with the carry input (CI) of address counter 1016, in addition, the carry output of address counter 1016 is connected in the carry input of address counter 1017, therefore, constitute one 63 system counter.The output of 1015～1017 these 3 address counters is used as the address ram (channel address) of RAM1061-4.

AND door (logic product computing circuit) 1018, and when TU pointer processing unit 1006 is not set at the TU12 pattern by the TU12 setting signal as described later (, when the TU12 setting signal is the L level), the output of address counter 1017 is converted to " 0 ".1-input inversion formula AND door 1019, only when TU pointer processing unit 1006 is set at the TU3 pattern by the TU3 setting signal as described later (, only when the TU3 setting signal is the H level) is converted to " 0 " with the output of address counter 1016.

Desired addition processing is carried out in the address output of 1020 pairs of each counters 1015～1017 of address conversioning unit, to produce an address conversion signal, is used for preventing to produce the invalid address at RAM1014.

Address-generation unit 1062-1 switches the combination (only counter 1015, counter 1015 sum counters 1016 or 1015～1017 all counters) according to the counter 1015～1017 of TU2 mode initialization signal and the work of TU3 mode initialization signal, producing for example address that is used for RAM1014 in combination shown in Figure 33, thereby in RAM1014, TU3, TU2 and TU12 are used public channel address.

So even mix the frame (VC4/VC3/VC2/VC12) that exists the unlike signal specification in any combination in the STM-1 frame, also (with reference to Fig. 7) uses an address-generation unit 1062-1 to adapt to neatly as previously mentioned.

The channel address of Chan Shenging carries out address transition by address conversioning unit 1020 in a manner described, thereby can obtain the wherein compressed address outputs in all invalid addresses (with reference to the address space of Figure 10).Therefore, the address wire with RAM1061-4 converts 6 to from 7.Should export as TU channel address (TUAD) and be used for above-mentioned POH terminal processes unit 1008.

Promptly, the POH terminal processes unit 1008 of present embodiment uses a public TU address that is produced by the address-generation unit 1062-1 of TU pointer processing unit 1006 with serial mode, therefore, just eliminated and be produced as the necessity of carrying out the required TU address signal of POH-byte serial terminal processes according to VC3/VC2/VC12 respectively.

Therefore, do not need to install respectively the circuit that is used to produce the TU resistance that equates with the respective channels number, and do not need to discern the special processing of each TU channel.This will help to reduce the scale and the amount of saving energy of circuit significantly.

Secondly, Figure 60 is the block diagram of the structure of the expression pointer processing unit 1061-2 that notices SPE lead byte (J1/V5 byte) recognition function.Pointer processing unit 1061-2 shown in Figure 60 has RAM1089 ' and SPE lead byte recognition unit 1097A.

SPE lead byte recognition unit 1097A is used to discern j1 byte (lead byte of VC3 signal) or the V5 byte (lead byte of VC2/VC12) as the SPE lead byte, shown in Figure 60, it have skew counting unit 1097 ', consistency detection unit 1098 ' and AND circuit 99 '.

Skew counting unit 1097 ', illustrated with reference to Figure 149～156 as preamble, be that initial opportunity is by counting the lead byte of retrieval SPE to the offset pointer value of SPE with frame signal.Consistency detection unit 1098 ' according to allow as the SPE that allows read output signal input now with pointer value be offset counting unit 1097 ' the skew count value between consistency.AND circuit 1099 ' calculating SPE allows signal and logic product by the consistency detection result of consistency detection unit 1098 ' record, thereby produces and export a SPE lead byte (J1/V5 byte) position indicative signal.

Promptly, SPE lead byte recognition unit 1097A have the skew counting unit 1097 that is used to retrieve the SPE lead byte ', read the existing pointer value of using from RAM1089 ', and by SPE allow signal with to the skew count value with now discern the lead byte position of SPE with the consistency detection result's of pointer value logic product.

In having the pointer processing unit 1061-2 of said structure, allow signal to read according to SPE and remain on the interior existing pointer value of use of RAM1089 ', in addition, being offset counting unit 1097 ' with frame signal is to begin initial opportunity the offset pointer value of SPE is counted.Consistency detection unit 1098 ' then detect from RAM1089 ' read existing with pointer value be offset counting unit 1097 ' count value whether consistent.

AND circuit 1099 ' calculating consistency detection result and SPE allow the logic product of signal, and generation and the long-pending operation result of output logic, as J1/V5 byte index signal.Here, when J1/V5 byte index signal is " 1 " (H level), then the data at this time slot of multiplexed data are J1/V5 bytes.In the processing of being undertaken by above-mentioned TU pointer processing unit 1006, use above-mentioned J1/V5 byte index signal and SPE to allow signal.

Figure 61 is the block diagram of structure that the TU pointer processing unit 1006 of signal specification recognition function is noticed in expression.As suppose the data of the TU pointer processing unit 1006 treatment S TM-1 frames shown in Figure 61,3 TU3/TUG3 set point registers of then above-mentioned mapping set point registers group 1100 ' have (TU3/TUG#3 #1～#3) 1123 and each TU3/TUG3 set point register 1123 is provided with 21 (being used for 21 channels) TU2/TUG2 of total (set point register 112 of TU2/TUG2#1～#7) of 7.Above-mentioned selected cell 1101 ' have signal specification recognition unit 1125A.

Whether 1123 storages of TU3/TUG3 set point register are set at the information of TU3 or TUG3 about the TUG3 that deposits (mapping) in the VC4 frame.For example, when the value of set point register 1123 is " 1 ", mean that TU3 is multiplexed in the TUG3 frame.When the value of set point register 1123 is " 0 ", mean that TU2 or TU12 are multiplexed in the TUG3 frame.

Whether 1124 storages of TU2/TUG12 set point register are set at the information of TU2 or TUG2 about the TUG2 that shines upon in TUG3.For example, when the value of set point register 1124 is " 1 ", mean that TU2 is multiplexed in the TUG2 frame.When the value of set point register 1124 is " 0 ", mean that TU12 is multiplexed in the TUG2 frame.

Signal specification recognition unit 1125A discerns the signal specification of correlated channels according to the set point that is stored in each set point register 1123 and 1124, and produces and export the TU3/TU2/TU12 setting signal that is used for address-generation unit 1062-1.Shown in Figure 61, the function of signal specification recognition unit 1125A realizes with following each parts: the address counter 1016 that select circuit 1125～1127,1-input inversion formula AND circuit 1128, full input inversion formula AND circuit 1129, is used for the address counter 101 of TU3 and is used for TUG2, similar shown in these parts and Figure 59.

Select circuit 1125 to select the information of the TU3/TUG3 set point register 1123 corresponding with the channel of indicating by the count value of the address counter that is used for TUG3 1015 of address-generation unit 1062-1.Each selects circuit 1126 to select the information of the TU2/TUG2 set point register 1124 corresponding with the channel of being indicated by the count value of the address counter 1016 that is used for TUG2.Select circuit 1127 to select the information of the TU2/TUG2 set point register 1124 corresponding with the channel of indicating by the count value of the address counter 1015 that is used for TUG3.

In having the TU pointer processing unit 1006 of said structure, select the set point (data #1, #2 or #3) of circuit 1125, to produce the TU3 setting signal according to the count value selection TU3/TUG3 set point register 1123 of the address counter 1015 that is used for TUG3.This TU3 setting signal, only when for " 1 ", the channel that indication is relevant is TU3.

3 data of selecting circuit 1126 to select 7 registers (being used for TUG3#1, TUG3#2 or TUG3#3) of TU2/TUG2 set point register 1124 respectively according to the count value of the address counter 1016 that is used for TUG2 " #1, #2 ... or #7 ", and select circuit 1127 to select these 3 of selecting signal according to the count value that is used for the address counter 1015 of TUG3.

AND circuit 1128 is asked for the inversion signal of TU3 setting signal and the logic product of the output signal of selecting circuit 1127, to produce the TU2 setting signal.Here, this TU2 setting signal, only when for " 1 ", the channel that indication is relevant is TU2.

AND circuit 1129 is asked for the logic product of inversion signal with the inversion signal of selecting circuit 1127 output signals of TU3 setting signal, thereby produces the TU12 setting signal.Here, only when this TU12 setting signal was " 1 ", the channel that indication is relevant was TU12.In the processing of being undertaken by POH terminal processes unit 1008 as described later, use above-mentioned each TU setting signal as the mapping setting signal.

Figure 62 is the block diagram of structure of the POH terminal processes unit 1008 of expression present embodiment.Shown in Figure 62, above-mentioned POH terminal processes unit (serial POH terminal processes unit) 1008 has regularly generation unit 1021, J1/J2 byte terminal processes unit 1022, B3/V5 byte terminal processes unit 1023, C2/V5 byte terminal processes unit 1024 and G1/V5 byte terminal processes unit 1025.

Regularly generation unit (POH timing signal serial generation unit) 1021 SPE of net load Data Position that receives J1V5TP signal (J1/V5 byte index signal), the indication TU data of indication TU data lead bytes from TU pointer processing unit 1006 allow signal (SPEEN), be used to differentiate the mapping signal of TU signal specification (TU3/TU2/TU12) and wherein the TU data be used for being created in to the POH terminal processes of TU and adjust needed various timing signals in the phase place by multiplexed VC4 data.

That is, regularly generation unit 1021 is included in the j1 byte in the multiplex signal (VC4 signal) or the timing signal of V5 byte location and the type information (map information) of multiplex signal according to indication and is created in the POH timing signal that uses when handling in each terminal processes unit 1022～1025 with serial mode.Regularly generation unit 1021 can produce the POH timing signal required to public each the terminal processes unit of TU channel 1022～1025 with serial mode.

J1/J2 byte terminal processes unit 1022 carries out terminal processes (detection of LOM, CRC and TIM) with serial mode to the j1 byte and the J2 byte that are included in the multiplex signal.B3/V5 byte terminal processes unit 1023 carries out terminal processes and the BIPPM of above-mentioned B3 byte and V5 byte is carried out terminal processes the BIP that is included in B3 byte in the multiplex signal and V5 byte with serial mode.

C2/V5 byte terminal processes unit (UNEQ/SLM serial terminal processing unit) 1024 carries out terminal processes with serial mode to being included in the C2 byte in the multiplex signal and the UNEQ of V5 byte, and with serial mode the SLM of above-mentioned C2 byte and V5 byte carried out terminal processes.G1/V5 byte terminal processes unit (FEBE/FERF serial terminal processing unit) 1025 carries out terminal processes with serial mode to being included in the G1 byte in the multiplex signal and the FEBE of V5 byte, and the FEBEPM of above-mentioned G1 byte and V5 byte is carried out terminal processes with serial mode, in addition, also the FERF of above-mentioned G1 byte and V5 byte is carried out terminal processes with serial mode.

Above-mentioned each POH terminal processes unit 1022～1025 mainly has POH terminal operation processing unit 1026 and memory 1027 shown in Figure 63.

1026 pairs of POH terminal operation processing units are wherein with multiplex signal (the VC4 signal: maximum 3 channels in TU3 of the channel of the multiplexed TU3/TU2/TU12 of serial mode, maximum 21 channels in TU2, maximum 63 channels in TU12) carrying out the POH terminal operation handles.According to present embodiment, 1026 pairs of above-mentioned each channels of POH terminal operation processing unit are public.

The operating result of 1026 pairs of each channels of memory cell 1027 storage POH terminal operation processing units.Read and the write operation of memory cell 1027 can be according to the TU channel address of being supplied with by above-mentioned TU pointer processing unit 1006 that is used to read, the TU channel address that is used to write, and allow write signal (WEN) to control neatly.

When the VC4 signal being carried out the processing of POH terminal operation, each terminal processes unit 1022～1025 utilizes the stored informations relevant with respective channels that are stored in the memory cell 1027 to carry out the POH terminal operation in POH terminal operation processing unit 1026 and handles, and resulting POH terminal operation result is stored in the memory block that is used for respective channels in the memory cell 1027.Therefore, can carry out the POH terminal operation to the VC4 signal with serial mode and handle, and the signal on need not each channel that be VC3, VC2 and VC12 with this VC4 Signal Separation.

Figure 64 is the block diagram of the structure of expression POH terminal operation processing unit 1026 and memory cell 1027.Shown in Figure 64, POH terminal operation processing unit 1026 has serial process unit 1026-1 and has triggering (FF) the circuit 1026-2 that starts terminal, and memory cell 1027 has RAM data holding unit 1027-1 that is made of RAM and the FF data holding unit 1027-2 that is made of the FF circuit.

In POH terminal operation processing unit 1026, serial process unit 1026-1 carries out terminal processes with serial mode to the POH byte.For example, 1022 couples of J1 in J1/J2 byte terminal processes unit and J2 byte are carried out terminal processes, 1023 couples of B3 in B3/V5 byte terminal processes unit and V5 byte are carried out terminal processes, 1024 couples of C2 in C2/V5 byte terminal processes unit and V5 byte are carried out terminal processes, and 1025 couples of G1 in G1/V5 byte terminal processes unit and V5 byte are carried out terminal processes

FF circuit (latch units) 1026-2, when serial process unit 1026-1 carries out POH-byte terminal operation when handling, be used for the data (operating result) of the respective channels that temporary transient storage (maintenance) reads from memory cell 1027 and be used to handle the POH byte data of VC4 data.

When FF circuit 1026-2 regularly latchs the data that remain in the memory cell 1027 according to POH and is used to handle the POH byte data of VC4 data, regularly supply with the required data of serial process unit 1026-1 according to this POH, so that serial process unit 1026-1 only operates where necessary.That is, FF circuit 1026-2 has reduced the operation frequency of serial process unit 1026-1, thereby lowers the power consumption of this unit.

In memory cell 1027, RAM data holding unit 1027-1 keeps class data such as alarm and protection progression information relevant with TU channel (0-62 channel).For example; shown in Figure 65 (a)～65 (t); read the data that the TU channel of the correspondence that should handle with serial mode is read from RAM data holding unit 1027-1 in the address according to RAM, and write address and RAM according to RAM and allow write signal that the alarm and protection progression information relevant with TU channel (0-62 channel) etc. of carrying out serial process is write RAM data holding unit 1027-1.According to present embodiment, only when reading and writing RAM data holding unit 1027-1, just import the ram clock signal, so that reduce the operation frequency of RAM data holding unit 1027-1, thereby lower the power consumption of this unit.

FF data holding unit 1027-2 remains on the alarm bit of TU channel (0-62 channel) in the FF circuit.Shown in Figure 65 (a)～65 (t), read address and FF according to FF and read the alarm bit of regularly reading the TU channel that to handle with serial mode, and write the address and FF allows write signal to write the alarm bit of the TU channel that carried out serial process according to FF.

Below, will be divided into every detailed description regularly generation unit 1021, J1/J2 byte terminal processes unit 1022, B3/V5 byte terminal processes unit 1023, C2/V5 byte terminal processes unit 1024 and G1/V5 byte terminal processes unit 1025.

(b-6) the regularly explanation of generation unit 1021

Figure 66 is the block diagram of the structure of the above-mentioned timing generation unit 1021 of expression.Make the timing generation unit 1021 that shows have SPE count value holding unit (RAM) 1028, SPE count value initialization unit 1029, SPE count value addition control unit 1030, timing signal for generating processing unit 1031 and FF circuit 1032 as Figure 66.

SPE count value holding unit 1028 keeps the SPE that is tried to achieve by 1030 pairs of each TU channels of SPE count value addition control unit to count additive value.SPE count value holding unit 1028 is a kind of memory cell that can read and write flexibly, the data of each TU channel that it kept can be supplied with SPE count value initialization unit 1029.SPE count value initialization unit 1029 receives the J1V5 timing signal of the leading position (position of J1/V5 byte) of the VC3/VC2/VC12 signal among the indication VC4, is used for the SPE count value is carried out initialization.

SPE count value addition control unit 1030 is according to by SPE count value initialization unit 1029 signal supplied the SPE count value being carried out addition control.Signal, mapping signal (in-phase signal of indication VC signal type), SPE that timing signal for generating processing unit 1031 receives from SPE count value initialization unit 1029 allow signal (SPEEN) and TU address signal (TUAD), are used to be created in each terminal processes unit 1022～1025 (with reference to Figure 62) employed following listed various POH timing signals when handling.

J1 timing signal (J1TP): the signal of indication j1 byte position;

B3 timing signal (B3TP): the signal of indication B3 byte location;

C2 timing signal (C2TP): the signal of indication C2 byte location;

G1 timing signal (G1TP): the signal of indication G1 byte location;

V5 timing signal (V5TP): the signal of indication V5 byte location;

J1J2 timing signal (J1J2TP): the signal of indication J1 and J2 byte location;

C2V5 timing signal (C2V5tP): the signal of indication C2 and V5 byte location;

G1V5 timing signal (G1V5TP): the signal of indication G1 and V5 byte location;

J1J2 allows write signal (J1J2WEN): indicate its J1 and J2 byte to carry out the signal of the timing that writes data of terminal processes;

J1J2RAMCLK signal: the operation clock signal that in J1/J2 byte terminal processes unit 1022, is used for RAM;

The BIPWEN signal: indication writes the signal of the timing of BIP2/BIP8 operating result;

The BIPPMWEN signal: the signal of the timing that writes data of BIPPM addition process had been carried out in indication;

BIPPMRAMCLK signal: be used for operation clock signal as described later at the BIPPM of B3/V5 byte terminal processes unit 1023 maintenance RAM 1058-1;

The C2V5WEN signal: the signal of the timing that writes data of UNEQ/SLM terminal processes had been carried out in indication;

C2V5RAMCLK signal: be used for operation clock signal as described later at the RAM of C2/V5 byte terminal processes unit 1024;

The G1V5WEN signal: the signal of the timing that writes data of FERF terminal processes had been carried out in indication;

G1V5RAMCLK signal: be used for operation clock signal as described later at the RAM of G1/V5 byte terminal processes unit 1025;

The TU address signal that is used to read: the signal that the terminal processes result that will be before the one-period corresponding TU channel that carries out the POH terminal processes of indication carries out reads;

The TU address signal that is used to write: indication will be carried out the signal that the TU channel data of POH terminal processes writes;

SPE allows signal (SPEEN): the signal that the SPE by will input allows the phase delay of signal to obtain;

The SPE count value writes TU address signal (CNTTUAD): the SPE count value that appointment will be carried out the TU channel of SPE count value addition control is write the signal of fashionable used address;

The SPE count value allows write signal (CNTEN): indication will be carried out the signal that the signal of SPE count value addition control writes; And

FEBEPMRAMCLK: be used for operation clock signal as described later at the FEBEPM of G1/V5 byte terminal processes unit 1025 maintenance RAM 1093-2;

FF circuit 1032 utilizes the phase delay of the SPE count value that a clock signal will obtain by the preceding single treatment (last cycle) that SPE count value holding unit 1028 is supplied with, so as to adjusting the incoming timing to SPE count value initialization unit 1029.

In having the timing generation unit 1021 of said structure, for example, according to the timing shown in Figure 67 (a)～Figure 67 (q), each channel is remained on the information (SPE count value) about SPE leading position (j1 byte/V5 byte) in the multiplex signal in (reading/write) SPE count value holding unit 1028 by SPE count value initialization unit 1029 and SPE count value addition control unit 1030, and upgrade successively, thereby by the public timing signal for generating processing unit 1031 of all TU channels is created in the various POH timing signals that adopted when each terminal processes unit 1022～1025 is handled with serial mode.Therefore, can realize above-mentioned serial process with open-and-shut structure.

Specifically, above-mentioned timing generation unit 1021, shown in Figure 68, have expense counter (OHCTR) RAM holding unit 1028 ', phase-shift unit 1032 ', expense counter serial process unit 1033.In addition, timing generation unit 1021, as above-mentioned timing signal for generating processing unit 1031, also has POH timing signal for generating unit 1034, the bald facies unit 1035 of POH timing signal, LOM keeps RAM operation control unit 1036, frame number (FRNO) keeps RAM operation control unit 1037, BIP2 keeps RAM operation control unit 1038, signal mark (SL) keeps RAM operation control unit 1039, FERF keeps RAM operation control unit 1040, receive desired value (EXP1/2) and keep RAM operation control unit 1041, BIPPM keeps RAM operation control unit 1042, and FEBEPM keeps RAM operation control unit 1043.

Above-mentioned expense counter serial process unit 1033 is corresponding to the part that is made of the SPE count value initialization unit 1029 shown in Figure 66, SPE count value addition control unit 1030 and FF circuit 1032.In the corresponding RAM of one of expense counter RAM holding unit 1028 ' will remain on and the count value of SPE shown in Figure 66 holding unit 1028 by the count value that expense counter serial process unit 1033 is supplied with.

Figure 69 be the above-mentioned phase-shift unit 1032 of expression ' the block diagram of detailed structure.Shown in Figure 69, the phase place of each signal [TUDT (TU data), TU address signal, SPE allow signal, J1V5 timing signal, mapping signal (VC3TUG/VC2VC12)] of phase-shift unit 1032 ' will be supplied with by TU pointer processing unit 1006 postpones the value of being scheduled to respectively.For this reason, the FF circuit 1032 that phase-shift unit 1032 ' have constitutes with predetermined progression respectively is used for by above-mentioned each phase of input signals of a clock signal delay of master clock (C1～C8).

The phase-shift unit 1032 with said structure ' in, the SPE of the net load Data Position of the TU address signal of the TU data of VC4 signal, indication TU channel, indication TU data allow the Qian Dao position of signal, indication TU data the J1V5 timing signal, be used to discern the phase place of each signal such as mapping signal of TU3/TU2/TU12, FF circuit 1032 by predetermined progression moves predetermined value respectively, and uses in serial process of being undertaken by expense counter serial process unit 1033 and POH terminal processes.

At this moment, specifically, phase-shift unit 1032 ' in, 7 clock signals of FF circuit 1032 usefulness of 7 grades (phase place of mobile TU data of C1 → C7), thus produce TU address signal (TUDTC7) with phase place C7.1～8 clock signal of FF circuit 1032 usefulness of 8 grades moves the phase place of TU data, thereby produces TU address signal (TUDTC1-8) with phase place C1-C8 respectively.

7 clock signals of FF circuit 1032 usefulness of 7 grades move the phase place that SPE allows signal, allow signal (SPEENC7) thereby produce SPE with phase place C7.Meanwhile, 3 clock signals of FF circuit 1032 usefulness of the 1st～3rd level move the phase place that SPE allows signal, allow signal (SPEENC3) thereby produce SPE with phase place C3.

3 clock signals of FF circuit 1032 usefulness of 3 grades move the phase place of J1V5 timing signal and mapping signal (VC3TUG/VC2VC12), thereby all produce J1V5 timing signal (J1V5TPC3) and mapping signal (VC3TUGC3/VC2VC12C3) with phase place C3.

Figure 70 is the above-mentioned expense counter RAM holding unit 1028 of expression ' and the block diagram of the detailed structure of expense counter serial process unit 1033.Shown in Figure 70, expense counter RAM holding unit 1028 ' have expense counter RAM1028 '-1 and be used for the negater that the polarity of input signal is anti-phase 1028 '-2.Expense counter serial process unit 1033 has FF circuit 1033-1, zero byte control unit (1-input inversion formula AND circuit) 1033-2, TU3 detecting unit (1-input inversion formula AND circuit) 1033-3, TU2 detecting unit (1-input inversion formula AND circuit) 1033-4, TU12 detecting unit (1-input inversion formula AND circuit) 1033-5, maximum setup unit 1033-6, maximum detection unit 1033-9, count value adder unit 1033-12, and count value initialization control unit (1-input inversion formula AND circuit) 1033-13.

Expense counter RAM holding unit 1028 ' in, expense counter RAM1028 '-1 be used to keep with the processing byte of SPE data in the relevant information in residing position from as the j1 byte of the 0th byte and V5 byte counting the time.The operation of expense counter RAM1028 '-1 be the signal that will obtain after anti-phase by negater 1028 '-2 as the SPE permission signal (SPEENC3) that writes the address, will supply with phase place C3 as the TU address signal of reading the address, will supplying with phase place C2 by the TU address signal (TUADC1) of above-mentioned phase-shift unit 1032 ' supply with phase place C1 as write the permission signal and with master clock as ram clock.

In expense counter serial process unit 1033, the information (count value) that the temporary transient maintenance of FF circuit 1033-1 is read from expense counter RAM1028 '-1.Zero byte control unit 1033-2, when the leading position J1V5 timing signal (J1V5TPC3) of TU data was indicated in input, controlling and making count value was 0.Signal (OHCTRC3) according to carrying out control is created in the various POH timing signals that use in the POH terminal processes.

It is TU3 that TU3 detecting unit 1033-3 is used to detect the TU channel that should handle, and its function adopts the AND circuit (logic integrated circuit) of the logic product of the inversion signal of asking for above-mentioned VC3TUGC3 and VC2VC12C3 to realize.It is TU2 that TU2 detecting unit 1033-4 is used to detect the TU channel that should handle, and its function adopts the AND circuit realization of the inversion signal of asking for above-mentioned VC3TUGC3 and the logic product of VC2VC12C3.

It is TU12 that TU12 detecting unit 1033-5 is used to detect the TU channel that should handle, and its function adopts the AND circuit realization of the inversion signal of asking for above-mentioned VC3TUGC3 and the logic product of the inversion signal of VC2VC12C3.

Maximum setup unit 1033-6 selects the maximum of count value according to the setting of TU3/TU2/TU12.Here, reach in the output by AND circuit 1033-7 and (logic and circuit) the 1033-8 selection of OR circuit and output and above-mentioned TU3 detecting unit 1033-3, TU2 detecting unit 1033-4 and TU12 detecting unit 1033-5 the H level the corresponding maximum [TU3:2FC (hex), TU2:1AB (hex), TU12:08B (hex)] of any one output.

Whether maximum detection unit 1033-9 detects by the count value after the zero byte control unit 1033-2 control consistent with the maximum of being set by maximum setup unit 1033-6, and its function adopts EXOR circuit ("or" else circuit) 1033-10 and OR circuit 1033-11 to realize.When maximum detection unit 1033-9 detects maximum, mean that SPE is last byte, thereby the SPE byte of next same TU channel is j1 byte or V5 byte, is the lead byte of TU data.

Count value adder unit 1033-12 will add 1 by the count value after the zero byte control unit 1033-2 control.Because as mentioned above when maximum detection unit 1033-9 detects maximum, the next SPE that should handle is j1 byte or V5 byte, is the lead byte of TU data, is controlled to be 0 of indication j1 byte or V5 byte so count value initialization control unit 1033-13 should remain on the count value of expense counter RAM1028 '-1.

Expense counter serial process unit 1033 with said structure can produce needed expense (SPE) count value when the various PON timing signal of timing signal for generating processing unit 1031 generations with serial mode.

Figure 71 is the block diagram of the detailed structure of the POH timing signal for generating unit 1034 shown in expression Figure 68.POH timing signal for generating unit 1034 shown in Figure 71 has with each several part:

Testing circuit (DEC) 1034-1: detect 0 of (decoding) SPE count value (OHCTRC3);

Testing circuit (DEC) 1034-2: detect 85 of (decoding) SPE count value (OHCTRC3);

Testing circuit (DEC) 1034-3: detect 170 of (decoding) SPE count value (OHCTRC3);

Testing circuit (DEC) 1034-4: detect 255 of (decoding) SPE count value (OHCTRC3);

Testing circuit (DEC) 1034-5: detect 107 of (decoding) SPE count value (OHCTRC3);

Testing circuit (DEC) 1034-6: detect 35 of (decoding) SPE count value (OHCTRC3);

TU3 testing circuit (1-input inversion formula AND circuit) 1034-7: the TU channel that detection should be handled is TU3;

TU2 testing circuit (1-input inversion formula AND circuit) 1034-8: the TU channel that detection should be handled is TU2;

TU12 testing circuit (1-input inversion formula AND circuit) 1034-9: the TU channel that detection should be handled is TU12;

J1 state detection unit (AND circuit) 1034-10: the TU channel that detection should be handled is in the 0th byte of TU3;

B3 state detection unit (AND circuit) 1034-11: the TU channel that detection should be handled is in the 85th byte of TU3;

C2 state detection unit (AND circuit) 1034-12: the TU channel that detection should be handled is in the 170th byte of TU3;

G1 state detection unit (AND circuit) 1034-13: the TU channel that detection should be handled is in the 255th byte of TU3;

V5 state detection unit (AND circuit) 1034-14: the TU channel that detection should be handled is in the 0th byte of TU2/TU12;

TU2J2 state detection unit (AND circuit) 1034-15: the TU channel that detection should be handled is in the 107th byte of TU2;

TU12J2 state detection unit (AND circuit) 1034-16: the TU channel that detection should be handled is in the 35th byte of TU12;

J2 state detection unit (OR circuit) 1034-17: the J2 state that detects TU12J2 is to be detected by above-mentioned TU2J2 state detection unit 1034-15, or is detected by TU12J2 state detection unit 1034-16;

J1 timing signal for generating unit (AND circuit) 1034-18: ask for the output signal of above-mentioned J1 state detection unit 1034-10 and the logic product that SPE allows signal, to produce the signal of indication j1 byte position;

B3 timing signal for generating unit (AND circuit) 1034-19: ask for the output signal of above-mentioned B3 state detection unit 1034-11 and the logic product that SPE allows signal, to produce the signal of indication B3 byte location;

C2 timing signal for generating unit (AND circuit) 1034-20: ask for the output signal of above-mentioned C2 state detection unit 1034-12 and the logic product that SPE allows signal, to produce the signal of indication C2 byte location;

G1 timing signal for generating unit (AND circuit) 1034-21: ask for the output signal of above-mentioned G1 state detection unit 1034-13 and the logic product that SPE allows signal, to produce the signal of indication G1 byte location;

V5 timing signal for generating unit (AND circuit) 1034-22: ask for the output signal of above-mentioned V5 state detection unit 1034-14 and the logic product that SPE allows signal, to produce the signal of indication V5 byte location;

J2 timing signal for generating unit (AND circuit) 1034-23: ask for the output signal of above-mentioned J2 state detection unit 1034-17 and the logic product that SPE allows signal, to produce the signal of indication J2 byte location;

J1J2 timing signal for generating unit (OR circuit) 1034-24: the signal that produces indication j1 byte or J2 byte location;

B3V5 timing signal for generating unit (OR circuit) 1034-25: the signal that produces indication B3 byte or V5 byte location;

C2V5 timing signal for generating unit (OR circuit) 1034-26: the signal that produces indication C2 byte or V5 byte location; And

G1V5 timing signal for generating unit (OR circuit) 1034-27: the signal that produces indication G1 byte or V5 byte location.

Above-mentioned each timing signal for generating unit 1034-18～1034-23 asks for input signal and SPE allows the reason of the logic product of signal to be, for the detection position that prevents each byte be not according to the timing of the SPE data of TU by corresponding detecting unit 1034-10,1034-11 ... or 1034-17 determine (promptly, prevent to produce timing signal by the timing of mistake), thus can produce various timing signals by accurate timing all the time.

Above-mentioned POH timing signal for generating unit 1034, as described later, can be created in various POH timing signals required in the terminal processes of being undertaken (signals of indication J1, B3, C2, G1, byte locations such as V5, J2) with serial mode by each terminal processes unit 1022～1025 (with reference to Figure 62).

Figure 72 is the block diagram of the detailed structure of the POH timing signal phase-shifting unit 1035 shown in expression Figure 68.Shown in Figure 72, POH timing signal phase-shifting unit 1035 has FF circuit 1035-1～1035-8, be used for each input signal of clock signal delay with master clock, so as to moving the phase place of the various POH timing signals that produced by above-mentioned POH timing signal for generating unit 1034, the phase potential energy that the POH timing signal is had adapts to the POH terminal processes of being undertaken by each terminal processes unit 1022～1025.

For example, the phase place C3 of J1 timing signal (J1TPC3) with 5 clock signal delays, thereby makes this J1 timing signal (J1TPC3) become J1TPC8 by 5 grades of FF circuit 1035-1.The phase place C3 of B3 timing signal (B3TPC3) with 5 clock signal delays, thereby makes this B3 timing signal (B3TPC3) become B3TPC8 by 5 grades of FF circuit 1035-2.The phase place C3 of C2 timing signal (C2TPC3) with 5 clock signal delays, thereby makes this C2 timing signal (C2TPC3) become C2TPC8 by 5 grades of FF circuit 1035-3.

The phase place C3 of V5 timing signal (V5TPC3), J12 timing signal (J12TPC3), B3V5 timing signal (B3V5TPC3), C2V5 timing signal (C2V5TPC3) and G1V5 timing signal (G1V5TPC3) etc., respectively by 5 grades of FF circuit 1035-4～1035-8 with 2～5 clock signal delays, thereby become V5TPC5-C8, J12TPC5-C8, B3V5TPC5-C8, C2V5TPC5-C8 and G1V5TPC5-C8.

Figure 73 is the block diagram that the LOM shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1036.Shown in Figure 73, LOM keeps RAM operation control unit 1036 to have operating clock shielding generation unit (OR circuit) 1036-1, FF circuit 1036-2, clock screen unit (1-input inversion formula OR circuit) 1036-3 and negater 1036-4.

Operating clock shielding generation unit 1036-1 produces each the J12 timing signal (J1TPC5-C8) that is used for by J1/J2 byte terminal processes unit 1022 produces after by 1035 phase shifts of above-mentioned POH timing signal phase-shifting unit as described later and catches the clock shielding of reading the address that LOM is kept RAM1050-1 (with reference to Figure 86) from J12TPC5, catch the clock shielding that writes the address that LOM is kept RAM1050-1 from J12TPC6, and the clock that writes data of catching LOM maintenance RAM1050-1 from J12TPC7 shields.

FF circuit 1036-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1036-1 of master clock.Clock screen unit 1036-3 utilizes the clock shielding of being supplied with by FF circuit 1036-2 that master clock is shielded, and LOM is kept to produce RAM1050-1's read or write required clock pulse edge (LOMCK).Negater 1036-4 is anti-phase with the polarity of J12TPC8, keeps the negative polarity of RAM1050-1 to allow write signal (XLOMWEN) to produce to LOM.

Above-mentioned LOM keeps RAM operation control unit 1036 can utilize by the clock pulse edge (LOMCK) that produces as upper type and allows write signal (XLOMWEN) to keep RAM1050-1 by best fixed cycle operator LOM.

Figure 74 is the block diagram that the FRNO shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1037.Shown in Figure 74, FRNO keeps RAM operation control unit 1037, keep RAM operation control unit 1036 similar with above-mentioned LOM, have operating clock shielding generation unit (OR circuit) 1037-1, FF circuit 1037-2, clock screen unit (1-input inversion formula OR circuit) 1037-3 and negater 1037-4.

Operating clock shielding generation unit 1037-1 produce be used for by J1/J2 byte terminal processes unit 1022 as described later at the J12 timing signal (J12TPC3) that is produced by above-mentioned POH timing signal for generating unit 1034 and each the J12 timing signal (J1TPC5-C8) that produces after by 1035 phase shifts of above-mentioned POH timing signal phase-shifting unit from J12TPC5 catch to FRNO keep RAM1051-1 (with reference to Figure 87) the clock-disabling of reading the address, from J12TPC6 catch to FRNO keep the writing address of RAM1051-1 clock-disabling, and catch the clock-disabling that FRNO is kept the data writing of RAM1051-1 from J12TPC7.

FF circuit 1037-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1037-1 of master clock.Clock screen unit 1037-3 utilizes the clock shielding of being supplied with by FF circuit 1037-2 that master clock is shielded, and FRNO is kept to produce RAM1051-1's read or write required clock pulse edge (FRNOCK).Negater 1037-4 is anti-phase with the polarity of J12TPC8, keeps the negative polarity of RAM1051-1 to allow write signal (XFRNOWEN) to produce to FRNO.

Above-mentioned FRNO keeps RAM operation control unit 1037 can utilize by the clock pulse edge (FRNOCK) that produces as upper type, allow write signal (XFRNOWEN) to keep RAM1051-1 by best fixed cycle operator FRNO.

Secondly, Figure 75 is the block diagram that the BIP2 shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1038.Shown in Figure 75, the BIP2 of present embodiment keeps RAM operation control unit 1038, keep RAM operation control unit 1037 similar with above-mentioned FRNO, have operating clock shielding generation unit (OR circuit) 1038-1, FF circuit 1038-2, clock screen unit (1-input inversion formula OR circuit) 1038-3 and negater 1038-4.

Operating clock shielding generation unit 1038-1 produces the SPE that is used for by B3/V5 byte terminal processes unit 1023 produces after by 1035 phase shifts of above-mentioned POH timing signal phase-shifting unit as described later and allows signal (SPEENC5-C8) to catch the clock shielding of reading the address that BIP2 is kept RAM1054-1 (with reference to Figure 110) from SPEENC5, catch the clock shielding that writes the address that BIP2 is kept RAM1054-1 from SPEENC6, and the clock that writes data of catching BIP2 maintenance RAM1054-1 from SPEENC7 shields.

FF circuit 1038-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1037-1 of master clock.Clock screen unit 1038-3 utilizes the clock shielding of being supplied with by FF circuit 1038-2 that master clock is shielded, and BIP2 is kept to produce RAM1054-1's read or write required clock pulse edge (BIPCK).Negater 1038-4 is anti-phase with the polarity of SPEENC8, keeps the negative polarity of RAM1054-1 to allow write signal (XBIPWENC8) to produce to BIP2.Therefore, above-mentioned BIP2 keeps RAM operation control unit 1038 can utilize by the clock pulse edge (BIPCK) that produces as upper type, allow write signal (XBIPOWENC8) to keep RAM1054-1 by best fixed cycle operator BIP2.

Figure 76 is the block diagram that the SL shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1039.As shown in the figure, the SL of present embodiment keeps RAM operation control unit 1039, keep RAM operation control unit 1038 similar with above-mentioned BIP2, have operating clock shielding generation unit (OR circuit) 1039-1, FF circuit 1039-2, clock screen unit (1-input inversion formula OR circuit) 1039-3 and negater 1039-4.

Operating clock shielding generation unit 1039-1 produces the C2V5 timing signal (C2V5TPC5-C8) that is used for by C2/V5 byte terminal processes unit 1024 produces after by 1035 phase shifts of above-mentioned POH timing signal phase-shifting unit as described later and catches the clock shielding of reading the address that SL is kept RAM1072-1 (with reference to Figure 129) from C2V5C5, catch the clock shielding that writes the address that SL is kept RAM1072-1 from C2V5TPC6, and the clock that writes data of catching SL maintenance RAM1072-1 from C2V5TPC7 shields.

FF circuit 1039-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1039-1 of master clock.Clock screen unit 1039-3 utilizes the clock shielding of being supplied with by FF circuit 1039-2 that master clock is shielded, and SL is kept to produce RAM1072-1's read or write required clock pulse edge (SLCK).Negater 1039-4 is anti-phase with the polarity of C2V5TPC8, keeps the negative polarity of RAM1072-1 to allow write signal (XSLWENC8) to produce to SL.

Above-mentioned SL keeps RAM operation control unit 1039 can utilize by the clock pulse edge (SLCK) that produces as upper type, allow write signal (XSLWENC8) to keep RAM1072-1 by best fixed cycle operator SL.

Figure 77 is the block diagram that the FERF shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1040.Shown in Figure 77, the FERF of present embodiment keeps RAM operation control unit 1040, keep RAM operation control unit 1039 similar with above-mentioned SL, have operating clock shielding generation unit (OR circuit) 1040-1, FF circuit 1040-2, clock screen unit (1-input inversion formula OR circuit) 1040-3 and negater 1040-4.

Operating clock shielding generation unit 1040-1 produces the G1V5 timing signal (G1V5TPC5-C8) that is used for by G1/V5 byte terminal processes unit 1025 produces after by 1035 phase shifts of above-mentioned POH timing signal shift unit as described later and catches the clock shielding of reading the address that FERF is kept RAM1096-1 (with reference to Figure 141) from G1V5TPC5, catch the clock shielding that writes the address that FERF is kept RAM1096-1 from G1V5TPC6, and the clock that writes data of catching FERF maintenance RAM1096-1 from G1V5TPC7 shields.

FF circuit 1040-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1040-1 of master clock.Clock screen unit 1040-3 utilizes the clock shielding of being supplied with by FF circuit 1040-2 that master clock is shielded, and FERF is kept to produce RAM1096-1's read or write required clock pulse edge (FERFCK).Negater 1040-4 is anti-phase with the polarity of G1V5TPC8, keeps the negative polarity of RAM1096-1 to allow write signal (XFERFWENC8) to produce to FERF.

Above-mentioned FERF keeps RAM operation control unit 1040 can utilize by the clock pulse edge (FERFCK) that produces as upper type, allow write signal (XFERFWENC8) to keep RAM1096-1 by best fixed cycle operator FERF.

Figure 78 is the block diagram that the reception desired value shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1041.Shown in Figure 78, the reception desired value of present embodiment maintenance RAM operation control unit 1041 has the desired value of reception and reads request detection unit (OR circuit) 1041-1, EXP1 desired value read operation clock shielding generation unit (1-input inversion formula AND circuit) 1041-2, EXP2 desired value read operation clock shielding generation unit (AND circuit) 1041-3, the EXP1 desired value is set accessing operation clock shielding generation unit (1-input inversion formula AND circuit) 1041-4, the EXP2 desired value is set accessing operation clock shielding generation unit (AND circuit) 1041-5, EXP1 clock shielding generation unit (OR circuit) 1041-6, EXP2 clock shielding generation unit (OR circuit) 1041-7, FF circuit 1041-8 and 1041-9, EXP1 clock screen unit (1-input inversion formula OR circuit) 1041-10, EXP2 clock screen unit (1-input inversion formula OR circuit) 1041-11, EXP1 allows to write generation unit (1-input inversion formula AND circuit) 1041-12 and EXP2 allows to write generation unit (NAND circuit) 1041-13.

Receive desired value and read the timing that request detection unit (OR circuit) 1041-1 detects the signal mark take over period prestige value of the reception desired value of the channels track data of reading J1 or J2 byte and C2 or V5 byte.EXP1 desired value read operation clock shielding generation unit 1041-2, the highest significant position of reading the address when the reception desired value of as described later REXPADC5 (with reference to Figure 95) is during for " 0 ", generation is used to catch the clock shielding of reading the address that EXP1 keeps RAM1048-1 (with reference to Figure 95), so that keep RAM1048-1 to read the reception desired value from EXP1.

EXP2 desired value read operation clock shielding generation unit (AND circuit) 1041-3, the highest significant position of reading the address when the reception desired value of REXPADC5 is during for " 1 ", generation is used to catch the clock shielding of reading the address that EXP2 keeps RAM1048-2, so that keep RAM1048-2 to read the reception desired value from EXP2.The EXP1 desired value is set accessing operation clock shielding generation unit 1041-4, when setting the reception desired value by software (microcomputer 1010 :) or reading the set content with reference to Figure 56, as the highest significant position at the MEXPAD of the read/write address of this software side is " 0 ", then produce the clock shielding that is used for EXP1 maintenance RAM1048-1, so that keep RAM1048-1 to read or write to EXP1.

The EXP2 desired value is set accessing operation clock shielding generation unit 1041-5, when receiving desired value by software set or reading the set content, highest significant position as above-mentioned MEXPAD is " 1 ", then produce the clock shielding that is used for EXP2 maintenance RAM1048-2, so that keep RAM1048-2 to read/write to EXP2.

EXP1 clock shielding generation unit 1041-6 ask for by above-mentioned EXP1 desired value read operation clock shielding generation unit 1041-2 and EXP1 desired value set the clock shielded signal that accessing operation clock shielding generation unit 1041-4 produces logic and.EXP2 clock shielding generation unit 1041-7 ask for by above-mentioned EXP2 desired value read operation clock shielding generation unit 1041-3 and EXP2 desired value set the clock shielded signal that accessing operation clock shielding generation unit 1041-5 produces logic and.

FF circuit 1041-8 is with the output (shielding of EXP1 clock) of the above-mentioned EXP1 clock shielding of a clock signal delay of master clock generation unit 1041-6.FF circuit 1041-9 is with the output (shielding of EXP2 clock) of the above-mentioned EXP2 clock shielding of a clock signal delay of master clock generation unit 1041-7.

EXP1 clock screen unit 1041-10 utilizes the output (shielding of EXP1 clock) of FF circuit 1041-8 that master clock is shielded, and to be produced as read/write data (EXP1) is remained on required clock pulse edge (EXP1CK) in the EXP1 maintenance RAM1048-1.EXP2 clock screen unit 1041-11 utilizes the output (shielding of EXP2 clock) of FF circuit 1041-9 that master clock is shielded, and to be produced as read/write data (EXP2) is remained on required clock pulse edge (EXP2CK) in the EXP2 maintenance RAM1048-2.

EXP1 allows to write generation unit 1041-12, when writing take over period prestige value by software, highest significant position as above-mentioned MEXPAD is " 0 ", then produces the permission write signal (XEXP1WEN) that EXP1 is kept RAM1048-1, keeps RAM1048-1 so that data are write EXP1.EXP2 allows to write generation unit 1041-13, when writing take over period prestige value by software, highest significant position as above-mentioned MEXPAD is " 1 ", then produces the permission write signal (XEXP2WEN) that EXP2 is kept RAM1048-2, keeps RAM1048-2 so that data are write EXP2.

Therefore, above-mentioned reception desired value keeps RAM operation control unit 1041 can produce above-mentioned clock pulse edge (EXP1CK and EXP2CK) and allows write signal (XEXP1WEN and XEXP2WEN), thereby keeps RAM1048-1 and EXP2 to keep RAM1048-2 by best fixed cycle operator EXP1.

Figure 79 is the block diagram that the BIPPM shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1042.Shown in Figure 79, the BIPPM of present embodiment keeps RAM operation control unit 1042, keep RAM operation control unit 1039 similar with the SL shown in Figure 76, have operating clock shielding generation unit (OR circuit) 1042-1, FF circuit 1042-2, clock screen unit (1-input inversion formula OR circuit) 1042-3 and negater 1042-4.

Operating clock shielding generation unit 1042-1 produces the B3V5 timing signal (B3V5TPC5-C8) that is used for by B3/V5 byte terminal processes unit 1023 produces after by 1035 phase shifts of above-mentioned POH timing signal shift unit as described later and catches the clock shielding of reading the address that BIPPM is kept RAM1058-1 (with reference to Figure 112) from B3V5C5, catch the clock shielding that writes data that BIPPM is kept the clock that writes the address of RAM1058-1 to shield and BIPPM kept RAM1058-1 from the B3V5TPC7 seizure from B3V5TPC6, in addition, also produce the clock shielding of reading the count value address of BIPPM from the BIPPM software notice request signal capture of supplying with by software side.

FF circuit 1042-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1042-1 of master clock.Clock screen unit 1042-3 utilizes the clock shielding of being supplied with by FF circuit 1042-2 that master clock is shielded, and BIPPM is kept to produce RAM1058-1's read or write required clock pulse edge (BIPPMCK).Negater 1042-4 is anti-phase with the polarity of B3V5TPC8, keeps the negative polarity of RAM1058-1 to allow write signal (XBIPPMWEN) to produce to BIPPM.

Therefore, above-mentioned BIPPM keeps RAM operation control unit 1042 can utilize by the clock pulse edge (BIPPMCK) that produces as upper type, allow write signal (XBIPPMWEN) to keep RAM1058-1 by best fixed cycle operator BIPPM.

Figure 80 is the block diagram that the FEBEPM shown in expression Figure 68 keeps the detailed structure of RAM operation control unit 1043.Shown in Figure 80, the FEBEPM of present embodiment keeps RAM operation control unit 1043, keep RAM operation control unit 1042 similar with above-mentioned BIPPM, have operating clock shielding generation unit (OR circuit) 1043-1, FF circuit 1043-2, clock screen unit (1-input inversion formula OR circuit) 1043-3 and negater 1043-4.

Operating clock shielding generation unit 1043-1 produces the G1V5 timing signal (G1V5TPC5-C8) that is used for by G1/V5 byte terminal processes unit 1025 produces after by 1035 phase shifts of above-mentioned POH timing signal shift unit as described later and catches the clock shielding of reading the address that FEBEPM is kept RAM1093-1 (with reference to Figure 139) from G1V5C5, catch the clock shielding that writes data that FEBEPM is kept the clock that writes the address of RAM1093-1 to shield and FEBEPM kept RAM1093-1 from the G1V5TPC7 seizure from G1V5TPC6, in addition, also produce the clock shielding of reading the count value address of FEBEPM according to the FEBEPM software notice request signal capture of supplying with by software side.

FF circuit 1043-2 is with the output (clock shielding) of a clock signal delay operating clock shielding generation unit 1043-1 of master clock.Clock screen unit 1043-3 utilizes the clock shielding of being supplied with by FF circuit 1043-2 that master clock is shielded, and FEBEPM is kept to produce RAM1093-1's read or write required clock pulse edge (FEBEPMCK).Negater 1043-4 is anti-phase with the polarity of G1V5TPC8, keeps the negative polarity of RAM1093-1 to allow write signal (XFEBEBIPPMWEN) to produce to FEBEPM.

Therefore, above-mentioned FEBEPM keeps RAM operation control unit 1043 can utilize by the clock pulse edge (FEBEPMCK) that produces as upper type, allow write signal (XFEBEMWEN) to keep RAM1058-1 by best fixed cycle operator FEBEPM.

Below, brief description is the whole operation of generation unit 1021 regularly.Here, for example supposition by the timing shown in Figure 81 (a)～81 (h) with TU data (be the j1 byte of VC3 herein), TUAD, SPEEN, J1V5TP, VC3TUG, reach VC2VC12 be input to phase-shift unit 1032 ', the each several part of expense counter serial operation unit 1033 is pressed shown in Figure 82 (a)～82 (p) and is operated.

In timing signal for generating processing unit 1031, the each several part of POH timing signal for generating unit 1034 is for example pressed operation shown in Figure 83 (a)～82 (t), produces various POH timing signals with serial mode.LOM keeps the each several part of RAM operation control unit 1036, for example press shown in Figure 84 (a)～84 (f) operation, be used to control with generation LOM is kept the clock pulse edge (LOMCK) of the writing of RAM1050-1/read operation and allows write signal (XLOMWEN).Point out that in passing the numbering in the circle shown in Figure 82～84 [Figure 70-3., Figure 70-4. wait] corresponds respectively in corresponding each figure the signal with the indication of the numbering in the circle.

According to the PON terminal processes unit 1008 of present embodiment, regularly generation unit 1021 can be created in by needed various POH timing signals in the POH terminal processes that each public terminal processes unit 1022～1025 of all TU channels is carried out with serial mode.Therefore, do not need to install the circuit that is used to produce various POH timing signals that equates with the respective channels number, thereby can reduce circuit scale and power consumption to the utmost.

(b-7) explanation of J1/J2 byte terminal processes unit 1022

Figure 85 is the block diagram of the structure of the J1/J2 byte terminal processes unit 1022 shown in expression Figure 62.Shown in Figure 85, in the J1/J2 of present embodiment byte terminal processes unit 1022, POH terminal operation processing unit 1022 shown in Figure 63 is configured to J1/J2 byte serial terminal processes unit 1026A, be used for the J1 and the J2 byte that are included in the VC4 signal being carried out terminal processes with serial mode, and the memory cell shown in Figure 63 1027 is configured to memory cell 1027A, be used for also institute's canned data to be supplied with J1/J2 byte serial terminal processes unit 1026A to the operating result that each TU channel carries out by J1/J2 byte serial terminal processes unit 1026A.

Above-mentioned J1/J2 byte serial terminal processes unit 1026A has multi-frame pattern serial detecting unit 1044, multi-frame string row control unit 1045, LOM serial detecting unit 1046, CRC serial detecting unit 1047, receives desired value holding unit 1048 and TIM serial detecting unit 1049.Memory cell 1027A has LOM holding unit 1050, frame number (FRNO) holding unit 1051, reaches alarm bit holding unit 1052.

In J1/J2 byte serial terminal processes unit 1026A, multi-frame pattern serial detecting unit 1044 detects the multi-frame pattern of J1 and J2 byte with serial mode.Multi-frame string row control unit (multi-frame pattern count Serial Control unit) 1045 is with the multi-frame number of serial mode control J1 and J2 byte.LOM serial detecting unit 1046 detects the LOM of J1 and J2 byte with serial mode.

CRC serial detecting unit 1047 detects the CRC of J1 and J2 byte with serial mode.Receive the reception desired value of desired value holding unit 1048 by the channels track signal that keeps administrative staff to write or read from software side.TIM serial detecting unit 1049 detects the TIM of J1 and J2 byte with serial mode according to the reception desired value that keeps in receiving desired value holding unit 1048.

In memory cell 1027A, the result (operating result) that 1050 maintenances of LOM holding unit are undertaken by 1044 pairs of each TU channels of multi-frame pattern serial detecting unit can also be supplied with the stored information of one-period (frame) preceding storage multi-frame pattern serial detecting unit 1044 in addition.The result that 1051 maintenances of FRNO holding unit are undertaken by 1045 pairs of each TU channels of multi-frame string row control unit can also be supplied with the stored information of one-period (frame) preceding storage multi-frame string row control unit 1045 in addition and receive desired value holding unit 1048.

The result that 1052 maintenances of alarm bit holding unit are undertaken by LOM serial detecting unit 1046, CRC

serial detecting unit

1047 and 1049 pairs of each TU channels of TIM serial detecting unit can also be supplied with LOM serial detecting unit 1046, CRC serial detecting unit 1047 and TIM serial detecting unit 1049 with the stored information of one-period (frame) preceding storage in addition.

Promptly, said memory cells 1027A storage is by multi-frame pattern serial detecting unit 1044, multi-frame string row control unit 1045, LOM serial detecting unit 1046, the operating result that 1049 pairs of each TU channels of CRC serial detecting unit 1047 and TIM serial detecting unit carry out, the stored information of one-period (frame) preceding storage can also be supplied with multi-frame pattern serial detecting unit 1044 in addition, multi-frame string row control unit 1045, LOM serial detecting unit 1046, CRC serial detecting unit 1047 and TIM serial detecting unit 1049

J1/J2 byte terminal processes unit 1022 by to the public J1/J2 byte serial terminal processes unit 1026A of all channels with serial mode to be included in the j1 byte in the VC3-POH235 and be included in VC2-POH236 and VC12-POH237 (being included in the digital stage multiplex signal lower) than the multiplex signal that comprises j1 byte in the J2 byte carry out terminal processes, thereby can obtain such as various warning messages such as LOM, CRC, TIM with a J1/J2 byte serial terminal processes unit 1026A.

Hereinafter, describe above each several part in detail.

Figure 86 is the block diagram of the detailed structure of above-mentioned multi-frame pattern serial detecting unit 1044 of expression and LOM holding unit 1050.Shown in Figure 86, multi-frame pattern serial detecting unit 1044 has the FF circuit 1044-1 of tape starting terminal (corresponding to the FF circuit 1026-1 shown in Figure 64) separately, 1044-2 and 1044-3, zero continuous counter adder unit 1044-4, zero continuous counter reset unit (1-input inversion formula AND circuit) 1044-5, decoding circuit (DEC) 1044-6～1044-8, the multi-frame bit preamble detects information reset unit (1-input inversion formula AND circuit) 1044-9, the multi-frame bit preamble detects information setting unit (OR circuit) 1044-10, frame number correct detection unit (AND circuit) 1044-11 and multi-frame mode detection unit (AND circuit) 1044-12.LOM holding unit 1050 has LOM and keeps RAM1050-1.

The LOM of LOM holding unit 1050 keeps RAM1050-1 to keep the result of being undertaken by multi-frame pattern serial detecting unit 1044 (promptly, for detect by J1 and the indication of J2 byte as LOM, warning such as CRC and TIM information necessary), its operation is that the TU address signal (TUADC6) that will be supplied with by phase-shift unit 1032 ' (with reference to Figure 69) of timing generation unit 1021 is as reading the address, with TUADC7 as writing the address, and will by the LOM of timing generation unit 1021 keep XLOMWENC8 that RAM operation control unit 1036 supplies with as allow write signal and with LOMCK as ram clock.

According to present embodiment, LOM holding unit 1050-1 for example keeps 21 data as follows.When remaining on these data in the LOM holding unit 1050-1 not necessarily according to order as follows.

Position sequence number 3-0: with the MSB position of J1/J2 byte is the relevant information of number of times of " 0 " continuously;

Position sequence number 4: the multi-frame bit preamble detects information;

Position sequence number 7-5:LOM protected level;

Position sequence number 14-8:CRC-7 operation result information;

The inconsistent detection information of CRC of sequence number 15:1 multi-frame front side, position;

The inconsistent detection information of CRC of sequence number 16:2 multi-frame front side, position;

Position sequence number 17: receive expectation and put inconsistent detection information;

Position sequence number 20-18:TIM protection progression information.

In multi-frame pattern serial detecting unit 1044, FF circuit 1044-1, according to the timing signal (J12TPC7: produce) of the indication J1/J2 byte location that produces by timing generation unit 1021, the 4th to the 0th data in the sense data (RLOMDTC7) that keeps supplying with by LOM holding unit 1050-1 by the POH timing signal shift unit shown in Figure 72 1035.FF circuit 1044-2 is according to the data of the MSB position of the data (TUDTC7) of the J1/J2 byte of above-mentioned timing signal (J12TPC7) maintenance VC4 data.The result that FF circuit 1044-3 keeps LOM alarm bit (RLOMC7), promptly obtains before the frame according to above-mentioned timing signal.

Zero continuous counter adder unit 1044-4 is to add 1 on " 0 " the continuous counter information (count value) of " 0 " at the continuous how many times in MSB position of indication J1/J2 byte.This information is 4 information, and when count value " 15 " when adding 1, its count value is gone back to " 0 ".

The reason of doing like this is owing to 16 [15 the tracking data bytes having CRC byte (1) as lead byte: with reference to Figure 162] of multi-frame by the J1/J2 byte constitute, wherein only the CRC byte is " 1 ", and the MSB position of all the other tracking data bytes all is " 0 ", and the delegation MSB position that detects the J1/J2 byte is just enough for " 1,000 0,000 0,000 0000 ".

Zero continuous counter reset unit 1044-5 when FF circuit 1044-2 keeps expression to detect data " 1 " as the CRC byte of multi-frame lead byte, resets to " 0 " with above-mentioned " 0 " read-around ratio information.The data (" 0 " read-around ratio information) of having carried out above-mentioned processing write the 0th to the 3rd of above-mentioned LOM holding unit 1050-1.

Decoding circuit (" 0 " decoding unit) 1044-6 detects " 0 " (that is, to " 0 " decoding) that " 0 " read-around ratio information of having handled is meant the leading position of the frame pattern of giving instructions in reply.It is to indicate the J1/J2 byte that should handle to be positioned at " 14 " (that is, to " 14 " decoding) of the 14th byte of tracking data that decoding circuit (" 14 " decoding unit) 1044-7 detects " 0 " the read-around ratio information of having carried out processing.It is to indicate the J1/J2 byte that should handle to be positioned at " 15 " (that is, to " 15 " decoding) of the 15th byte of tracking data that decoding circuit (" 15 " decoding unit) 1044-8 detects " 0 " read-around ratio information of having handled.

The multi-frame bit preamble detects information reset unit 1044-9, when detecting the leading position of multi-frame pattern, the lead byte detection information of last multi-frame pattern is resetted.The multi-frame bit preamble detects information setting unit 1044-10, when keeping " 1 " and detecting " 0 " read-around ratio information of having handled after the bit preamble not being " 0 " in FF circuit 1044-2, detects the bit preamble of current multi-frame.

Frame number correct detection unit 1044-11, when the asynchronous warning of multi-frame pattern (LOM) takes place (when RLOMC7 is the H level), detecting multi-frame bit preamble detection information (output information of FF circuit 1044-1) and having handled " 0 " read-around ratio information really is " 14 ", thereby the delegation MSB position that detects the J1/J2 byte is " 1,000 0,000 0,000 0000 ", and produce a frame number correction request information (FRONOSETC8), so that to handling as the J1/J2 byte in the next frame of the 15th byte of tracking data byte.

Multi-frame mode detection unit 1044-1 2 detects multi-frame bit preamble detection information (output information of FF circuit 1044-1) and " 0 " read-around ratio information (output information of decoding circuit 1044-8) is " 15 ", thereby the delegation MSB position that detects the J1/J2 byte is " 1,000 0,000 0,000 0000 ", so that detect multi-frame pattern (MEPATDETC8).

Delegation MSB position with frame pattern serial detecting unit 1044 detection J1/J2 bytes of said structure is " 10,000,000 0,000 0000 ", keep RAM1050-1 to read " 0 " read-around ratio information and multi-frame bit preamble detection information successively from LOM simultaneously, thereby detect so that the public mode of all TU channels is carried out serial to the multi-frame pattern of J1/J2 byte (channels track data).

Figure 87 is the block diagram of the detailed structure of expression multi-frame string row control unit 1045 and FRNO holding unit 1051.Shown in Figure 87, multi-frame string row control unit 1045 has FF circuit (corresponding to the FF circuit 1026-2 shown in Figure 64) 1045-1, FF circuit 1045-2 and 1045-3, the frame number control unit 1045-4 of tape starting terminal and deciphers mediocre (DEC) 1045-5 and 1045-6, FRNO holding unit 1051 have FRNO and keep RAM1051-1.

It is the information (hereinafter, regarding frame number information as) of J1/J2 byte that the FRNO of FRNO holding unit 1051 keeps RAM1051-1 to be used to keep indicating the byte of multi-frame.For example, according to present embodiment, FRNO maintenance RAM1051-1 can keep 4 (position sequence number 3 to 0) frame number information shown in Figure 88.

FRNO keeps the operation of RAM1051-1 be TU address signal (TUADC4) that phase-shift unit 1032 ' (with reference to the Figure 69) by timing generation unit 1021 supplied with as read the address, with TUADC7 as write the address, and the XFRNOWENC8 that will keep RAM operation control unit 1037 (with reference to Figure 74) supply by the FRNO of timing generation unit 1021 as the permission write signal and with FRNOCK as ram clock.Timing according to the J2 byte of j1 byte that detects TU3 or TU2/TU12, where read next J1/J2 byte from FRNO holding unit 1051 is positioned at, and, next J1/J2 byte is positioned at where write FRNO holding unit 1051 according to the timing of the J2 byte of j1 byte that detects TU3 or TU2/TU12.

As the relation between frame number information and the tracking frame, for example, " 0 " indication CRC byte of frame number information, " 1 " of frame number information is " 15 " the 1st to the 15th byte of indicators track data byte respectively extremely, and " 0 " of frame number information extremely " 15 " remain in the FRNO maintenance RAM1051-1 with the relation shown in Figure 90.

In multi-frame string row control unit 1045, FF circuit 1045-1 keeps being kept by FRNO the 3rd to the 0th data of the sense data of RAM1051-1 supply according to the timing signal (J12TPC5: produced by the POH timing signal phase-shifting unit shown in Figure 72 1035) of indication J1/J2 byte location.

The frame number information that FF circuit 1045-2 is kept by FF circuit 1045-1 with a clock signal delay of master clock.The frame number information that FF circuit 1045-3 is further kept by FF circuit 1045-2 with a clock signal delay of master clock.When the frame number correction request signal (FRNOSETC8) that provides as the frame number correct detection unit 1044-11 by the multi-frame pattern serial detecting unit 1044 shown in Figure 86 was " 1 ", frame number control unit 1045-4 was " 15 " with the frame number information updating.

The count value that decoding circuit (" 0 " decoding unit) 1045-5 detects frame number information is " 0 ", produces to represent that the J1/J2 byte that should handle is the signal (CRCTRPC8) of CRC byte.The count value that decoding circuit (" 15 " decoding unit) 1045-6 detects frame number information is " 15 ", produces J1/J2 byte that expression should handle and is the 15th byte that is positioned at tracking data, is the signal (FRNO15TPC8) of the last byte of multi-frame.

Multi-frame string row control unit 1045 with said structure keeps RAM1051-1 to read the above-mentioned frame number information of former frame successively from FRNO, with the frame number information updating of current multi-frame, thereby so that the public mode of all TU channels is carried out Serial Control to the multi-frame number.

Figure 91 is the block diagram of the detailed structure of the LOM serial detecting unit 1046 shown in expression Figure 85.Shown in Figure 91, the LOM serial detecting unit 1046 of present embodiment has the FF circuit 1046-1 and the 1046-2 of tape starting terminal separately; LOM protection progression adder unit 1046-3; decoding circuit (DEC) 1046-4 and 1046-5; add 1 state detection unit ("or" else circuit) 1046-6; LOM detects 7 grades of detecting units (AND circuit) 1046-7; LOM eliminates 3 grades of detecting units (AND circuit) 1046-8; state transitions generation detecting unit (OR circuit) 1046-9; LOM protection progression information reset unit 1046-10; state transitions unit ("or" else circuit) 1046-11 and Bypass Control unit (selector) 1046-12.

FF circuit 1046-1 keeps being kept by the LOM shown in Figure 86 the 7th to the 5th data (LOM protected level information) of the sense data (RLOMDTC7) of RAM1050-1 supply according to the timing signal (J12TPC7: supplied with by the POH timing signal phase-shifting unit shown in Figure 72 1035) of indication J1/J2 byte location.FF circuit 1046-2 according to above-mentioned timing signal (J12TPC7) keep LOM alarm bit (RLOMC7), promptly to the result of former frame.

LOM protection progression adder unit 1046-3 adds 1 in the LOM protected level information (count value) that keeps RAM1050-1 to read from LOM.Decoding circuit (" 6 " decoding unit) 1046-4 detects for " 6 " the count value of the LOM protected level information of being read.Decoding circuit (" 2 " decoding unit) 1046-5 detects for " 2 " the count value of the LOM protected level information of being read.

Add 1 state detection unit 1046-6 and be used for detecting the situation that (when RLOMC7 is " 0 ") detects the multi-frame pattern when LOM takes place, (when MFPATDETC8 is " 0 ") do not detect the multi-frame pattern when LOM does not take place.LOM detects 7 grades of detecting unit 1046-7, continue 6 multi-frames and be used to detect when above and add 1 state and recur 7 situations more than the multi-frame when decoding circuit 1046-4 detects non-multi-frame mode state, add 1 state so that detect, and further detect 1 state that adds that in current multi-frame, takes place, thereby detect LOM.

LOM eliminates 3 grades of detecting unit 1046-8, when 2 of decoding circuit 1046-5 continuous detecting more than the multi-frame add 1 state and current multi-frame take place add 1 state the time, be used to detect and add 1 state and recur the above situation of 3 multi-frames, thereby LOM is eliminated.LOM detection that state transitions generation detecting unit 1046-9 detection is carried out in 7 grades of detecting unit 1046-7 of LOM detection or 3 grades of detecting unit 1046-8 of LOM elimination or the elimination state of LOM.

LOM protection progression information reset unit 1046-10 does not detect and adds 1 state and state transitions generation detecting unit 1046-9 and detect when state transitions takes place when adding 1 state detection unit 1046-6, and LOM protected level information is reset to " 0 ".State transitions unit 1046-11, when state transitions generation detecting unit 1046-9 detects the generation state transitions, the polarity of the alarm bit of LOM is anti-phase, thereby with state from state transitions that LOM takes place to the nonevent state of LOM, or the state transitions that LOM never takes place is to the state that LOM takes place.

For LOM being upgraded when the 15th byte of the tracking data of J1/J2 byte; only when handling the 15th byte; Bypass Control unit 1046-12 will write LOM by the result that above-mentioned LOM protection progression information reset unit 1046-10 carries out and keep RAM1050-1, will write alarm bit holding unit 1052 by the result that state transitions unit 1046-11 carries out in addition.During byte beyond the 15th byte, Bypass Control unit 1046-12 will not do any processing and write LOM to keep RAM1050-1 and alarm bit holding unit 1052 from the information that LOM keeps RAM1050-1 and alarm bit holding unit 1052 to read.

LOM serial detecting unit 1046 with said structure keeps RAM1050-1 and alarm bit holding unit 1052 to read LOM protection progression information and LOM alarm bit (state information that expression LOM takes place or do not take place) successively respectively from LOM; and according to the information of reading current multi-frame is carried out LOM and upgrade processing, so that so that the public mode of all TU channels is carried out serial process to LOM.

Figure 92 is the block diagram of the detailed structure of the CRC serial detecting unit 1047 shown in expression Figure 85.Shown in Figure 92, the CRC serial detecting unit 1047 of present embodiment has the FF circuit 1047-1～1047-3 of tape starting terminal separately; CRC operating result reset unit (AND circuit) 1047-4; the CRC data are inserted unit (80hex inserts the unit) 1047-5; CRC operating unit 1047-6; inconsistent detecting unit 1047-7; protected level numerical control system unit 1047-8; crc error detects 3 grades of detecting unit 1047-9; crc error is eliminated 3 grades of detecting unit 1047-10; state transitions generation detecting unit (OR circuit) 1047-11; state transitions unit ("or" else circuit) 1047-12 and Bypass Control unit (selector) 1047-13.

FF circuit 1047-1 keeps being kept by the LOM shown in Figure 86 the 16th to the 8th the data (the inconsistent detection information of CRC that records before the inconsistent detection information of the CRC that records before CRC operation result information, 1 multi-frame, 2 multi-frames) of the sense data (RLOMDTC7) of RAM1050-1 supply according to the timing signal (J12TPC7: supplied with by the POH timing signal phase-shifting unit shown in Figure 72 1035) of indication J1/J2 byte location.

FF circuit 1047-2 keeps the J1/J2 byte data (TUDTC7) of TU data according to above-mentioned timing signal (J12TPC7).FF circuit 1047-3 keeps CRC alarm bit (RCRCC﹠amp according to above-mentioned timing signal (J12TPC7); ), promptly to the result of former frame.CRC operating result reset unit 1047-4 when the J1/J2 byte that should handle is the CRC byte, will reset from the CRC operating result to last multi-frame that LOM keeps RAM1050-1 to read.

CRC data insertion unit 1047-5 is 80hex with the data rewrite of CRC byte.According to the 80hex that the data of being inserted unit 1047-5 rewriting CRC byte by the CRC data are tried to achieve, protected level numerical control system unit 1047-8 utilizes generator polynomial X7+X3+1 that the 1st to the 15th byte is carried out the CRC-7 operation.Operating result is write LOM keep RAM1050-1.

Inconsistent detecting unit 1047-7 detects inconsistent between the 2nd to the 8th the crc value of the result of the CRC operation of last multi-frame and CRC byte.Protected level numerical control system unit 1047-8 controls, and makes the output signal of inconsistent detecting unit 1047-7 become the 15th data that keep RAM1050-1 at LOM, and will move to the 16th from the 15th the data that LOM keeps RAM1050-to read.

When the inconsistent detection information of CRC that records before inconsistent detection information of the known CRC that records before 1 frame when not having crc error of the testing result of carrying out from inconsistent detecting unit 1047-7 and 2 frames all showed the inconsistent detection of CRC, crc error detected 3 grades of detecting unit 1047-9 and detects 3 of consistent continued presences of CRC more than the multi-frame.When the inconsistent detection information of CRC that records before inconsistent detection information of CRC that is recording before 1 frame when existing crc error when the testing result of carrying out from inconsistent detecting unit 1047-7 is known and 2 frames shows all that CRC is consistent and detects, crc error is eliminated 3 grades of detecting unit 1047-10 and is detected 3 of consistent continued presences of CRC more than the multi-frame, so that this crc error is eliminated.

State transitions generation detecting unit 1047-11 will be eliminated the detection or the elimination of the crc error that 3 grades of detecting unit 1047-10 carry out by 3 grades of detecting unit 1047-9 of error detection or crc error.State transitions unit 1047-12, when state transitions generation detecting unit 1047-11 detects the generation state transitions, the polarity of the alarm bit of crc error is anti-phase, thereby with state from the state transitions that has crc error to the non-existent state of crc error, or from the non-existent state transitions of crc error to the state that has crc error.

In order only crc error to be upgraded when the CRC of the J1/J2 byte byte; only when handling the CRC byte; Bypass Control unit 1047-13 will be write LOM by the result that protected level numerical control system unit 1047-8 carries out and keep RAM1050-1, will write alarm bit holding unit 1052 by the result that state transitions unit 1047-12 carries out in addition.During byte beyond the CRC byte, Bypass Control unit 1047-13 will not do any processing and write LOM to keep RAM1050-1 and alarm bit holding unit 1052 from the information that LOM keeps RAM1050-1 and alarm bit holding unit 1052 to read.

The inconsistent detection information of CRC and the CRC alarm bit (the expression crc error exists or non-existent state information) that record before the inconsistent detection information of CRC that records before the CRC-7 operation result information that CRC serial detecting unit 1047 with said structure keeps RAM1050-1 and alarm bit holding unit 1052 to read respectively successively recording before the 1 above-mentioned multi-frame from LOM, 1 multi-frame, 2 multi-frames, and according to above-mentioned information current multi-frame is carried out CRC and operate (renewal crc error), thereby so that the public mode of all TU channels is carried out serial process to CRC.

Point out in passing; CRC serial detecting unit 1047 shown in Figure 92; for example; shown in Figure 93; can have CRC protection progression adder unit 1047-14; decoding circuit 1047-15; add 1 state detection unit ("or" else circuit) 1047-16; 3 grades of detecting units of detection/elimination (AND circuit) 1047-17 and protection progression reset unit (1-input inversion formula AND circuit) 1047-18 are to replace above-mentioned protected level numerical control system unit 1047-8; crc error detects 3 grades of detecting unit 1047-9; crc error is eliminated 3 grades of detecting unit 1047-10 and state transitions generation detecting unit (OR circuit) 1047-11.

In this case, will remain on the inconsistent detection information of CRC that LOM keeps recording before the inconsistent detection information of CRC that records before 1 multi-frame in the RAM1050-1 and 2 multi-frames as representing CRC unanimity/inconsistent CRC protection progression information that occurs in sequence how many times.

CRC protection progression adder unit 1047-14 adds 1 in the CRC protection progression information that keeps RAM1050-1 to read from LOM.Decoding circuit (" 2 " decoding unit) 1047-15 detects for " 2 " CRC protection progression information.Adding 1 state detection unit 1046-6 is used for detecting when have crc error by inconsistent detecting unit 1047-7 detection consistency and detects inconsistent situation by inconsistent detecting unit 1047-7 when not having crc error.

3 grades of detecting unit 1047-17 of detection/elimination detect the generation of crc error detection/elimination state.Protection progression reset unit 1047-18 is used for protecting progression information to reset CRC.

Above-mentioned CRC serial detecting unit 1047, similar with the CRC serial detecting unit 1047 shown in Figure 92, also can detect CRC with serial mode.

Figure 94 is the block diagram of the detailed structure of the TIM serial detecting unit 1049 shown in expression Figure 85.Shown in Figure 94; the TIM serial detecting unit 1049 of present embodiment has the FF circuit 1049-1～1049-4 of tape starting terminal separately; inconsistent detecting unit 049-5; inconsistent detection indicating member (OR circuit) 1049-6; inconsistent detection indication reset unit (1-input inversion formula AND circuit) 1049-7; add 1 state detection unit ("or" else circuit) 1049-8; TIM protection progression adder unit 1049-9; decoding circuit 1049-10 and 1049-11; TIM detects 7 grades of detecting units (AND circuit) 1049-12; TIM eliminates 3 grades of detecting units (AND circuit) 1049-13; state transitions generation detecting unit (OR circuit) 1049-14; TIM protection progression information reset unit (1-input inversion formula AND circuit) 1049-15, state transitions unit ("or" else circuit) 1049-16 and Bypass Control unit (selector) 1049-17.

FF circuit 1049-1 keeps being kept by LOM the 20th to the 17th the data (receiving inconsistent detection information of desired value and TIM protection progression information) of the sense data (RLOMDTC7) of RAM1050-1 supply according to the timing signal (J12TPC7: supplied with by the POH timing signal phase-shifting unit shown in Figure 72 1035) of indication J1/J2 byte location.FF circuit 1049-2 according to above-mentioned timing signal (J12TPC7) keep uncle TU according to J1/J2 byte data (TUDTC7).

The reception desired value (REXPDTR:7 position) of the FF circuit 1049-3 J1/j2 byte that maintenance should be handled according to above-mentioned timing signal (J12TPC7).FF circuit 1049-4 according to above-mentioned timing signal (J12TPC7) keep TIM alarm bit (RTMC7), promptly to the result of former frame.

Inconsistent detecting unit 1049-5 detects inconsistent between 7 of above-mentioned reception desired value and J1/J2 byte the 2nd to the 8th.Inconsistent detection indicating member 1049-6 produces and is representing at the reception tracking data of present frame and the inconsistent signal between the above-mentioned explanation desired value, and its function is realized by EXOR circuit 1049-5A and OR circuit 1049-5B.

Inconsistent detection indication reset unit 1049-7, when the CRC byte is positioned at the multi-frame leading position, will need with the inconsistent detection indication of the CRC byte that receives the desired value comparison and keep the inconsistent detection indication reset of the last multi-frame that RAM1050-1 reads from LOM.Add 1 state detection unit 1049-8, be used to detect the inconsistent detection when TIM does not take place, the reception value carried out, TIM detected state, and when TIM takes place, consistently detecting of carrying out of reception value, TIM eliminated state.

TIM protection progression adder unit 1049-9 adds 1 on TIM protection progression information.Decoding circuit (" 6 " decoding unit) 1049-10 detects for " 6 " the count value of the TIM protected level information of being read.Decoding circuit (" 2 " decoding unit) 1046-11 detects for " 2 " the count value of the TIM protected level information of being read.

TIM detects 7 grades of detecting unit 1049-12, when detecting, above-mentioned decoding circuit 1049-10 adds 6 multi-frames of 1 state continuous detecting when above, be used to detect and add 1 state and recur the above situation of 7 multi-frames, and further detect and add 1 state so that detect TIM at present frame.TIM eliminates 3 grades of detecting unit 1049-13, when above-mentioned decoding circuit 1049-11 detect when TIM takes place, add 1 state 2 more than the multi-frame and further current multi-frame also take place add 1 state the time, be used to detect and add 1 state and recur the above situation of 3 multi-frames, thereby TIM is eliminated.

TIM detection that state transitions generation detecting unit 1049-14 detection is carried out in above-mentioned 7 grades of detecting unit 1049-12 of TIM detection or 3 grades of detecting unit 1049-13 of TIM elimination or the elimination state of TIM.TIM protection progression information reset unit 1049-15, when add 1 state detection unit 1049-8 do not detect add 1 state and (or) detect when state transitions takes place by state transitions generation detecting unit 1049-14, TIM protected level information is reset to " 0 ".

State transitions unit 1049-16, when state transitions generation detecting unit 1049-14 detects the generation state transitions, the polarity of the alarm bit of TIM is anti-phase, thereby with state from state transitions that TIM takes place to the nonevent state of TIM, or the state transitions that TIM never takes place is to the state that TIM takes place.

For TIM being upgraded when the 15th byte of the tracking data of J1/J2 byte; only when handling the 15th byte; Bypass Control unit 1049-17 will write LOM by the result that above-mentioned TIM protection progression information reset unit 1049-115 carries out and keep RAM1050-1, will write alarm bit holding unit 1052 by the result that state transitions unit 1049-16 carries out in addition.During byte beyond the 15th byte, Bypass Control unit 1049-17 will not do any processing and write LOM to keep RAM1050-1 and alarm bit holding unit 1052 from the information that LOM keeps RAM1050-1 and alarm bit holding unit 1052 to read.

TIM serial detecting unit 1049 with said structure keeps RAM1050-1 and alarm bit holding unit 1052 to read TIM protection progression information and TIM alarm bit (state information that expression TIM takes place or do not take place) successively respectively from LOM; and upgrade the TIM protection progression information of current multi-frame, thereby so that the public mode of all TU channels is carried out serial process to TIM.

Figure 95 is the block diagram of the detailed structure of the reception desired value holding unit 1048 shown in expression Figure 85.Shown in Figure 95, the reception desired value holding unit 1048 of present embodiment has the 1st and receives desired value (EXP1) maintenance RAM1048-1, the 2nd receives desired value (EXP2) keeps RAM1048-2, signal mark (SL) receives desired value MSB position holding unit (FF circuit) 1048-3～1048-5, MSB position software notice selected cell 1048-6, receive desired value software notice selected cell (selector) 1048-7, SL receives desired value and reads address control unit (1-input inversion formula AND circuit) 1048-8, FF circuit 1048-9 and 1048-10, decoding circuit 1048-11～1048-13, MSB position selected cell 1048-14 and reception desired value selected cell (selector) 1048-15.

EXP1 keeps RAM1048-1, when the multiplex signal that receives is the STM-1 frame, is used to keep the reception desired value of signal mark of each TU channel of 0-62ch and the reception desired value on the 1st to the 7th of each tracking data.EXP1 keep the operation of RAM1048-1 be with the reception desired value by timing generation unit 1021 keep XEXP1WEN that RAM operation control unit 10041 (with reference to Figure 78) supply with as allow write signal and with EXP1CK as ram clock.It is characterized in that, for example, shown in Figure 96, SL is received desired value [EXP1: signal mark (SL) and channels track data (TRC)] write corresponding address (MEXPAD is described further below) district successively with 7.

The the 8th to the 15th byte of the tracking data on each TU channel of EXP2 maintenance RAM1048-2 maintenance 0-62ch.EXP2 keep the operation of RAM1048-2 be equally with the reception desired value by timing generation unit 1021 keep XEXP1WEN that RAM operation control unit 1041 (with reference to Figure 78) supply with as allow write signal and with EXP2CK as ram clock.It is characterized in that for example, shown in Figure 97,7 (EXP1:TEC) SL being received desired value write corresponding address (MEXPAD) district successively.

According to present embodiment, in the relation of above-mentioned address ram (MEXPAD), frame number and TU interchannel, shown in Figure 100.

In RAM, only have usually the 512nd address below the address owing to its specification.Therefore, in order to obtain to keeping all to receive 1024 required addresses of desired value, the reception desired value holding unit 1048 of present embodiment has 2 RAM that are used for keeping receiving desired value.According to present embodiment, shown in Figure 99 and 101, the MSB position of the address contents of RAM1048-1 and 1048-2 is used for the reading/write of control (handover access) RAM1048-1 and 1048-2 (about its operation timing, can with reference to Figure 98).If there is its capacity to be enough to keep all to receive the RAM of desired value, then only just enough certainly with a RAM, there is no need to install 2 above-mentioned RAM.

SL receives the MSB position that TU channel SL that desired value MSB position holding unit 1048-3 is used to keep 0ch receives desired value.SL receives the MSB position that SL that desired value MSB position holding unit 1048-4 is used to keep the TU channel of 1ch receives desired value.SL receives the MSB position that SL that desired value MSB position holding unit 1048-5 is used to keep the TU channel of 2ch receives desired value.

That is, in receiving desired value holding unit 1048, when the multiplex signal of input is TU3, need be because SL is received desired value with 8, so the EXP1 of 7 bit architectures keeps the figure place of RAM1048-1 not enough as mentioned above.Therefore, the 8th of the reception desired value of above-mentioned each SL reception desired value MSB position holding unit 1048-3～1048-5 maintenance TU3.Point out in passing, to each EXP1 keep RAM1048-1, EXP2 keep RAM1048-2 and SL receive desired value MSB position holding unit 1048-3～1048-5 the reception desired value setting and read set information from these unit, undertaken by software side.

The SL that MSB position software notice selected cell 1048-6 selects software to read the TU channel of 0ch-2ch receives the time of desired value setting content, and its function is realized by AND circuit 1048-6A～1048-6C and OR circuit 1048-6D.Receive desired value software notice selected cell 1048-7 and keep RAM1048-1 and EXP2 to keep RAM1048-2 to read setting content, and suitably select the data that keep RAM1048-1 or EXP2 to keep RAM1048-2 to read from EXP1 according to the MSB of the address signal (MEXPAD) of the indication Writing/Reading address of supplying with by software by the reception desired value of software set from EXP1.

SL receives desired value and reads address control unit 1048-8, when reading when being used to carry out SL that SLM handles and receiving desired value, timing signal (J12TPC5: supplied with by the POH timing signal shift unit shown in Figure 72 1035) according to indication C2/V5 byte location is controlled, shielding, be " 0 " thereby make this frame number information from the frame number information (FRNODTC5) that above-mentioned FRNO holding unit 1051 (FRNO keeps RAM1051-1: with reference to Figure 87) is read.

4 positions of the TU address signal of being controlled (TUADC5) and 6 positions constitute 10 reception desired value and read address (REXXPADC5).Read the address when reading when SL receives desired value under above-mentioned control, 10 receive desired value and read 4 of the high positions of address and become " 0000 ", and 4 positions of this TUAD of the TU channel that should handle according to indication and 6 positions are read SL and received desired value.

FF circuit 1048-9 receives the phase place that desired value is read the address with 10 of clock signal delays of master clock.FF circuit 1048-10 further postpones the phase place that 10 reception desired values are read the address with a clock signal of master clock.

Decoding circuit (" 0 " decoding unit) 1048-11 reads the address to 10 reception desired values and detects for " 0 ".Decoding circuit (" 1 " decoding unit) 1048-12 reads the address to 10 reception desired values and detects for " 1 ".Decoding circuit (" 2 " decoding unit) 1048-13 reads the address to 10 reception desired values and detects for " 2 ".

MSB position selected cell 1048-14 selects its function of reading of the SL reception desired value setting content of the TU channel of 0ch-2ch is realized by AND circuit 1048-14A～1048-14C and OR circuit 1048-14D.Receive desired value selected cell 1048-15 and receive desired values according to 10 and read 9 of address and keep RAM1048-1 and EXP2 to keep RAM1048-2 to read the reception desired value, and receive desired values according to 10 and read the MSB position of address and select this position of reading to receive desired value from EXP1.The output signal that receives 7 positions of desired value selected cell 1048-15 constitutes channels track Data Receiving desired value (REXPDTC7), and notifies above-mentioned TIM serial process unit 1049 as tracking data reception desired value.In addition, will be by 8 signals that the output signal of MSB position selected cell 1048-14 and above-mentioned 7 output signal additions are tried to achieve, notice will be later with reference to the SLM detecting unit of the C2/V5 byte terminal processes unit 1024 of Figure 105 explanation, receive desired value (RFXPSLC7) as SL.

The reception desired value holding unit 1048 with said structure of present embodiment can keep with serial mode and supply required various reception desired values in the processing of being undertaken by TIM serial process unit 1049 and C2/V5 byte terminal processes unit 1024 each TU channel in software side.

Figure 102 is the block diagram of the detailed structure of the alarm bit holding unit 1052 shown in expression Figure 85.Shown in Figure 102, the alarm bit holding unit 1052 of present embodiment has TIM alarm bit holding unit 1052-1, CRC alarm bit holding unit 1052-2, LOM alarm bit holding unit 1052-3, alarm bit writes address control unit (1-input inversion formula OR circuit) 1052-4, allow to write generation unit [decoding circuit (DEC)] 1052-5, alarm bit is read address control unit (1-input inversion formula OR circuit) 1052-6, read and select generation unit (DEC) 105 2-7, TIM selected cell (selector) 1052-8, CRC selected cell (selector) 1052-9, LOM selected cell (selector) 1052-10, the circuit handover information is read and is selected generation unit (DEC) 1052-11, circuit handover information selected cell (selector) 1052-12, the software notice is read and is selected generation unit 1052-13 and software notice to read selected cell (selector) 1052-14.

TIM alarm bit holding unit 1052-1 is by the TIM alarm bit of the TU channel of 63 FF circuit 1052A maintenances 0 to 62ch.CRC alarm bit holding unit 1052-2 is by the CRC alarm bit of the TU channel of 63 FF circuit 1052B maintenances 0 to 62ch.LOM alarm bit holding unit 1052-3 is by the LOM alarm bit of the TU channel of 63 FF circuit 1052C maintenances 0 to 62ch.

Alarm bit writes address control unit 1052-4, when alarm bit writes regularly (J12TPC8) for " 1 ", and the content (TUADC8) of output TU channel, and when J12TPC8 is " 0 ", itself output signal is controlled to be 63 (" 111111 ").

Allow to write generation unit 1052-5, when the output signal that writes address control unit 1052-4 when alarm bit is 0 to 62, produce 0 to 62ch respectively and be used for the permission write signal that each alarm bit keeps FF circuit 1052A～1052C, and it is supplied with keep WTIMC8, WCRCC8, WLOMC8, promptly handle the FF circuit 1052A～1052C of the alarm signal that obtains behind TIM, CRC, the LOM of TU channel respectively.When the output signal that writes address control unit 1052-4 when alarm bit is 63, because this is not the timing that writes alarm bit, so do not produce the permission write signal.

Alarm bit is read address control unit 1052-6, when alarm bit is read regularly (J12TPC7) for " 1 ", and the content (TUADC7) of the TU channel that output should be handled, and when J12TPC8 is " 0 ", itself output signal is controlled to be 63 (" 111111 ").Read and select generation unit 1052-7, when the output signal of reading address control unit 1052-6 when alarm bit is 0 to 62, to 0 to 62ch produce be used to read alarm bit read the selection signal.When the output signal of reading address control unit 1052-6 when alarm bit is 63,, do not read the selection signal so do not produce because this is not the timing of reading alarm bit.

TIM selected cell 1052-8, according to by read select that generation unit 1052-7 produces read the selection signal, read the alarm bit of the TIM of the TU channel that should handle.CRC selected cell 1052-9, according to by read select that generation unit 1052-7 produces read the selection signal, read the alarm bit of the CRC of the TU channel that should handle.LOM selected cell 1052-10, according to by read select that generation unit 1052-7 produces read the selection signal, read the alarm bit of the LOM of the TU channel that should handle.

The circuit handover information read select generation unit 1052-11 to produce to be used for 0 to 62ch TU channel read the selection signal.Circuit handover information selected cell 1052-12 is according to read the alarm bit of selecting reading of generation unit 1052-11 generation to select signal to read TIM by the circuit handover information.Software notice read select generation unit 1052-13 to produce to be used for 0 to 62ch TU channel read the selection signal.The software notice is read selected cell 1052-14 according to the alarm bit of selecting signal to read TIM of reading of being read selection generation unit 1052-13 generation by the software notice, and with TIM alert notice software.

Alarm bit holding unit 1052 with said structure can be reported to the police thereby produce TIM with serial mode so that the public mode of TU channel is kept for example various warning messages such as TIM, CRC, LOM.

Be briefly described the integrated operation of J1/J2 byte terminal processes unit 1022 now with said structure.For example, as by the timing shown in Figure 103 (a)～103 (h) with TU data (being the j1 byte of VC3 here), TUAD, SPEEN, J1V5TP, VC3TUG and VC2VC12 be input to phase-shift unit 1032 ', then the each several part of multi-frame pattern serial detecting unit 1044 shown in Figure 86 and LOM holding unit 1050 will be according to the fixed cycle operator shown in Figure 104 (a)～104 (1).

At this moment, the each several part of LOM serial detecting unit 1046 shown in multi-frame string row control unit 1045 shown in Figure 87 and FRNO holding unit 1051, Figure 91 and the CRC serial detecting unit 1047 shown in Figure 92, for example according to the fixed cycle operator shown in Figure 105 (a)～105 (n), and the reception desired value holding unit 1048 shown in the TIM serial detecting unit 1049 shown in Figure 94 and Figure 95 will be according to the fixed cycle operator shown in Figure 106 (a)～106 (k), thereby is created in the reception desired value of SL required in the processing of being undertaken by C2/V5 byte terminal processes unit 1024.

Therefore, the each several part of the alarm bit holding unit 1052 shown in Figure 102 for example will be according to the fixed cycle operator shown in Figure 107 (a)～107 (n), thereby each TU channel is produced the alarm bit of TIM with serial mode.

In the POH of present embodiment terminal processes unit 1008, the public J1/J2 byte terminal processes unit 1022 of all TU channels is carried out to the terminal processes of j1 byte and to the terminal processes of J2 byte with serial mode, detect the multi-frame pattern of multiplex signals in addition as mentioned above by J1/J2 byte terminal processes unit 1022, thereby do not need to install respectively the circuit that with the corresponding TU number of channel being used for of equating j1 byte is carried out the circuit of terminal processes and the J2 byte is carried out terminal processes.

Therefore, present embodiment can help to reduce to the utmost the scale and the power consumption of the circuit (device) of POH terminal processes unit 1008 significantly.

Specifically, this J1/J2 byte terminal processes unit 1022 can obtain for example various warning messages such as LOM, CRC, TIM to all TU channel public lands with serial mode, thereby does not need to prepare respectively to be used to detect the circuit of LOM, the circuit of detection CRC, the circuit of detection TIM etc.This can reduce the scale and the power consumption of device to the utmost.

(b-8) explanation of B3/V5 byte terminal processes unit 1023

Figure 108 is the block diagram that is illustrated in the structure of the B3/V5 byte terminal processes unit 1023 that illustrated with reference to Figure 62 in the preamble.Shown in Figure 108, B3/V5 byte terminal processes unit 1023 has BIP2 error serial detecting unit 1053, BIP2 holding unit 1054, BIP8 error serial detecting unit 1055, BIPPM count value initialization unit 1056, BIPPM serial process unit 1057, BIPPM holding unit 1058 and PMRAM address control unit 1059.

BIP2 error serial detecting unit (BIP2 serial operation processing unit) 1053 carries out BIP2 operation with serial mode to VC2 in the multiplex signal and VC12 according to the BIP2 error that obtained before one-period, to detect the BIP2 error.The BIP2 operating result that 1054 maintenances of BIP2 holding unit are undertaken by 1053 pairs of each TU channels of BIP2 error serial detecting unit in addition, is also supplied with stored information (the BIP2 operating result that obtained before one-period) BIP2 error serial detecting unit 1053.

BIP8 error serial detecting unit (BIP8 serial operation processing unit) 1055 carries out the BIP8 operation with serial mode to VC3, to detect the BIP8 error.BIPPM count value initialization unit 1056 is controlled according to the PM reset signal of being supplied with by software side, with the count value initialization of BIPPM.The output (BIP2 error or BIP8 error) of BIP2 error serial detecting unit 1053 or BIP8 error serial detecting unit 1055 is selected in BIPPM serial process unit 1057, and carries out the phase add operation according to selected BIP error signal with serial mode.

That is, for example, shown in Figure 109, BIPPM serial process unit 1057 has: BIP error selected cell 1057A is used to select from the BIP error signal of BIP2 error serial detecting

unit

1053 or 1055 outputs of BIP8 error serial detecting unit; And BIPPM serial addition unit 1057B, be used for carrying out the phase add operation according to the BIP error signal of selecting by BIP error selected cell 1057A.

The operating result (BIPPM) that BIPPM holding unit 1058 is undertaken by 1057 pairs of each the TU channels in BIPPM serial process unit in addition, is also supplied with stored information (BIPPM that obtained before one-period) BIPPM serial process unit 1057.PMRAM address control unit 1059 produces the address ram that is used for the address ram of BIPPM holding unit 1058 and is used for the FEBEPM holding unit 1093 (with reference to Figure 135 and 139) of G1/V5 byte terminal processes unit 1025 as described later according to the PM reset signal of being supplied with by software side.

Promptly, in above-mentioned B3/V5 byte terminal processes unit 1023, POH terminal operation processing unit 1026 shown in Figure 63 is configured to B3/V5 byte serial terminal processes unit 1026B, be used for operating being included in the B3 byte in the VC4 signal and the BIP of V5 byte with serial mode, and the BIPPM of B3 byte and V5 byte carried out terminal processes, in addition, also the memory cell shown in Figure 63 1027 is configured to memory cell 1027B, be used to store the operating result that each TU channel is carried out by B3/V5 byte serial terminal processes unit 1026B, canned data can be supplied with B3/V5 byte serial terminal processes unit 1026B simultaneously.

Therefore, B3/V5 byte terminal processes unit 1023 can detect the BIP error that should detect to all TU channel public lands in the POH terminal processes to each TU channel with unlike signal specification with serial mode.For this reason, dispose above-mentioned various piece as follows particularly.

Figure 110 is the block diagram of the detailed structure of expression BIP2 error serial detecting unit 1053, BIP2 holding unit 1054.Shown in Figure 110, BIP2 error serial detecting unit 1053 has FF circuit 1053-1 and 1053-2, BIP2 operating value reset unit (1-input inversion formula AND circuit) 1053-3, odd bits BIP2 operating unit ("or" else circuit) 1053-4, even bit BIP2 operating unit ("or" else circuit) 1053-5, BIP2 operation comparing unit 1053-6 and the BIP2 error detection unit 1053-7 of tape starting terminal separately, and BIP2 holding unit 1054 has BIP2RAM1054-1.

The BIP2 of BIP2 holding unit 1054 keeps RAM1054-1 to keep the BIP2 operating result that the V5 byte is carried out, its operation be TU address signal (TUADC6) that phase-shift unit 1032 ' (with reference to the Figure 69) by timing generation unit 1021 supplied with as read the address, with TUADC7 as write the address, and the XBIP2WENC8 that will keep 1038 supplies of RAM operation control unit by the BIP2 of timing generation unit 1021 as the permission write signal and with BIP2CK as ram clock.

BIP2 holding unit 1054-1 keeps 2 data, wherein, the result of odd number BIP2 operational processes is held in place in the memory block of sequence number " 1 ", and the result of even number BIP2 operational processes is held in place in the memory block of sequence number " 0 ".

In BIP2 error serial detecting unit 1053, FF circuit 1053-1 keeps keeping the 1st and the 0th of sense data that RAM1054-1 supplies with by BIP2 according to the timing signal (SPEENC7) of the net load position of indication TU, and FF circuit 1054-2 keeps the net load data of VC4 data according to above-mentioned timing signal.To export as SPEDTC8 by the signal that FF circuit 1054-2 keeps.

BIP2 operating value reset unit 1053-3 shields the BIP2 operational processes result who reads from BIP2 holding unit 054-1 according to the timing signal (V5TPC8) of the V5 byte of the leading position that is positioned at the BIP2 operating space, resets with the operating value with last BIP2 operating space.Odd bits BIP2 operating unit 1053-4 calculates from " different " logic (EXOR) of the the the 1st, the 3rd, the 5th and the 7th of BIP2 holding unit 1054-1 odd number BIP2 operational processes result who reads and the net load that is kept by FF circuit 1053-2, and result of calculation is write from the 1st of BIP2 maintenance RAM1054-1.

Even bit BIP2 operating unit 1053-5 calculates the the the 2nd, the 4th, the 6th and the 8th " different " logic (EXOR) that keeps RAM1054-1 odd number BIP2 operational processes result who reads and the net load that is kept by FF circuit 1053-2 from BIP2, and result of calculation is write from the 0th of BIP2 holding unit 1054-1.

BIP2 operation comparing unit 1053-6 will keep the 1st and the 2nd of RAM1054-1 BIP2 operational processes result who reads and the net load that is kept by FF circuit 1053-2 to compare from BIP2, and when comparative result when being inconsistent, output " 1 ", its function is realized by EXOR circuit 1053-6A shown in Figure 85 and OR circuit 1053-6B.

The output of BIP2 error detection unit 1053-7 output BIP2 operation comparing unit 1053-6 is as the BIP2 error.But above-mentioned BIP2 operation comparing unit 1053-6 always compares with 22, thereby exports invalid comparative result in the moment that is not the V5 byte by BIP2 operation comparing unit 1053-6.Therefore, BIP2 error detection unit 1053-7 can extract the suitable comparative result of BIP2 operation by the timing signal (V5TPCK) of V5 byte.

The BIP2 error serial detecting unit 1053 with said structure of present embodiment keeps RAM1054-1 to read the BIP2 error of former frame successively from BIP2, and according to sense information present frame is carried out BIP2 and operate, BIP2 control information is upgraded, thereby detected so that the public mode of all TU channels is carried out serial to the BIP2 error.

Figure 111 is the block diagram of the detailed structure of the BIP8 error serial detecting unit 1055 shown in expression Figure 108.Shown in Figure 111, the BIP8 error serial detecting unit 1055 of present embodiment has BIP8 operating value holding unit (FF circuit) 1055-1～1055-3, BIP8 operating result holding unit (FF circuit) 1055-4～1055-6, decoding circuit (DEC) 1055-7～1055-9, BIP operating value selected cell (selector) 1055-10, BIP8 operating value reset unit (1-input inversion formula AND circuit) 1055-11, BIP operating unit ("or" else circuit) 1055-12, the BIP8 operating value allows to write generation unit (AND circuit) 1055-13, the BIP8 operating result allows to write generation unit (AND circuit) 1055-14, BIP8 operating result selected cell (selector) 1055-15, BIP8 operation comparing unit 1055-16 and BIP8 error detection unit (AND circuit) 1055-17.

BIP8 operating value holding unit 1055-1 is used to keep the BIP8 operating result to each the net load data on the TU channel of 0ch.BIP8 operating value holding unit 1055-2 keeps the BIP8 operating result to each the net load data on the TU channel of 1ch.BIP8 operating value holding unit 1055-3 keeps the BIP8 operating result to each the net load data on the TU channel of 2chh.

BIP8 operating result holding unit 1055-4 is used to keep the BIP8 operating result to the j1 byte of the j1 byte of the TU channel of 0ch and next frame.BIP8 operating result holding unit 1055-5 is used to keep the BIP8 operating result to the j1 byte of the j1 byte of the TU channel of 1ch and next frame.BIP8 operating result holding unit 1055-6 is used to keep the BIP8 operating result to the j1 byte of the j1 byte of the TU channel of 2ch and next frame.

The TU channel (TUADC8) of decoding circuit (" 0 " decoding unit) 1055-7 alignment processing detects for " 0 ".The TU channel (TUJADC8) of decoding circuit (" 1 " decoding unit) 1055-8 alignment processing detects for " 1 ".The TU channel (TUADC8) of decoding circuit (" 2 " decoding unit) 1055-9 alignment processing detects for " 2 ".

BIP operating value selected cell 1055-10 selects one according to the detection signal of being supplied with by above-mentioned decoding circuit 1055-7,1055-8,1055-9 in the BIP8 operating value of being supplied with by above-mentioned BIP8 operating value holding unit (FF circuit) 1055-1～1055-3.BIP8 operating value reset unit 1055-11 shields the BIP8 operating value of reading from BIP8 operating value holding unit 1055-1,1055-2,1055-3 according to the timing (J1TUPC8) of the j1 byte of the leading position that is positioned at the BIP8 operating space, resets with the operating result with last BIP8 operating space.

BIP8 operating unit 1055-12 calculates the BIP8 operating result SPEDTC8 that resetted by above-mentioned BIP8 operating value reset unit 1055-11, promptly carries out " different " logics (EXOR) of the net load data of BIP8 operation.The BIP8 operating value allows to write generation unit 1055-13 and produces a signal, and the BIP8 operating value that is used for carrying out the BIP8 operation by BIP8 operating unit 1055-12 writes corresponding BIP8 operating value holding unit 1055-1,1055-2,1055-3.

The BIP8 operating result allows to write timing (J1TUPC8) the generation signal (permission write signal) of generation unit 1055-14 according to the j1 byte of the leading position of indication BIP8 operating space, and the BIP8 operating value that is used for remaining in BIP8 operating value holding unit 1055-1～1055-3 writes BIP8 operating result holding unit 1055-4～1055-6 respectively.

BIP8 operating result selected cell 1055-15 selects the operating result of BIP8 according to the detection signal of being supplied with by decoding circuit 1055-7,1055-8 or 1055-9.BIP8 operation comparing unit 1055-16 detects inconsistent between the BIP8 operating result of being selected by BIP8 operating result selected cell 1055-15 and net load data, and its function is by EXOR circuit 1055-16A and OR circuit 1055-16B realization.

The output of BIP8 error detection unit 1055-17 output BIP8 operation comparing unit 1055-16 is as BBIP8 error (BIP8ERRC8).But, because above-mentioned BIP8 operation comparing unit 1055-16 always compares 8, so invalid comparative result is exported in the timing of BIP8 operation comparing unit 1055-16 beyond the B3 byte constantly, therefore, BIP8 error detection unit 1055-17 only extracts and exports the suitable result of BIP8 operation according to the timing signal (B3TPCK) of B3 byte.

The BIP8 error serial detecting unit 1055 with said structure of present embodiment can accurately detect and export BIP8 control information at any time.

Figure 112 is the BIPPM serial detecting unit 1057 shown in expression Figure 108 and the block diagram of BIPPM holding unit 1058 detailed structure.Shown in Figure 112, BIPPM serial detecting unit 1057 has FF circuit 1057-1, error count value initialization control unit (1-input inversion formula AND circuit) 1057-2, BIP error detection unit (OR circuit) 1057-3 and the BIPPM adder unit 1057-4 of tape starting terminal, and BIPPM holding unit 1058 has BIPPM maintenance RAM1058-1.

The BIPPM of BIPPM holding unit 1058 keeps RAM1058-1 to keep BIP error count value and should notify the BIPPM count value of software, and its operation is as the address of reading on the counting face with address signal (RPMADC6), with address signal (WPMADC7) as the address that writes on the counting face, (XBIPPMWENC8) conduct that will be kept RAM operation control unit 1042 (with reference to Figure 79) to supply with by the BIP of timing generation unit 1021 allows write signal, with address signal (BIPPMRAD) as reading the address and will keep clock (BIPPMCK) that RAM operation control unit 1042 supplies with as ram clock on the notice face by BIP.Point out that in passing above-mentioned address signal (RPMADC6, WPMADC7 and BIPPMRAD) is provided by PMRAM address control unit 1059.

Keep among the RAM1058-1 at above-mentioned BIPPM, for example, shown in Figure 114, the PM count value of regularly reading BIP2/8 according to the detection of the V5 byte of the B3 byte of TU3 or TU2/TU12, and according to the request of reading (μ COM Read) of software side PM count value notice software with this BIP2/8, in addition, regularly write the updating value of the PM count value of BIP2/8 according to the detection of the V5 byte of the B3 byte of TU3 or TU2/TU12.

In BIPPM, for to counting at the BIP error amount that takes place between the PM reset signal and before the signal of position, next PM mansion, notifying software with count value, must between the PM reset signal, carry out error count and notifications count value, for this reason, must keep the count value of error and the count value that maintenance should be notified.

Therefore, for example, shown in Figure 116, the BIPPM of present embodiment keeps RAM1058-1 to have low plane [address 0 (00 _HEX) to 63 (3F _HEX)] and high plane [address 64 (40 _HEX) to 127 (7F _HEX)], be designated as the notice face (PM result keeps face) that is used for the counting face that the BIP error is counted and is used to notify the count value of BIP respectively.When input PM reset signal, the effect of above-mentioned 2 faces as counting face and notice face is changed each other.According to present embodiment, the mutual conversion of 2 faces for example, shown in Figure 115 and 117, can be undertaken by the polarity of MSB position of conversion address ram.

For example, shown in Figure 113, BIPPM keeps RAM1058-1 to keep 13 data, wherein, BIP error count value is remained on position sequence number 12～0 on the counting face, and the BIPPM count value is remained on position sequence number 12～0 on the notice face.

The BIPPM serial detecting unit 1057 with said structure of present embodiment can keep RAM1058-1 to read the BIPPM of former frame successively from BIPPM, and according to the BIPPM of the information updating present frame of reading, detect the BIPPM public with serial mode to all TU channels, BIPPM is remained on BIPPM keep in the RAM1058-1, and with this BIPPM notice software side.

Figure 118 is the block diagram of the detailed structure of the PMRAM address control unit 1059 shown in expression Figure 108.Shown in Figure 118, the PMRAM address control unit 1059 of present embodiment has counting face holding unit (the FF circuit of tape starting terminal) 1059-1, negater 1059-2 and FF circuit 1059-3～1059-6.

Counting face holding unit 1059-1 produces expression as the high plane of the above-mentioned BIPPM maintenance RAM1058-1 of counting face or the signal (PM counts address signal) of low plane.When input PM reset signal, counting face holding unit 1059-1 catches with the polarity of the output signal of itself signal of trying to achieve after anti-phase, thereby the effect of low plane and high plane is changed mutually.

For example, when the output signal of counting face holding unit 1059-1 for " 0 " and will hang down plane as the counting face with high plane as in the notice face during with PM reset signal input counting face holding unit 1059-1, in the face of counting holding unit 1059-1, capture " 1 " that the polarity of output signal that should counting face holding unit 1059-1 by negater 1059-2 is tried to achieve after anti-phase.Therefore, the output signal of counting face holding unit 1059-1 becomes " 1 " after PM resets, thereby with each face conversion, make low plane be used as the notice face, and high plane is used as the counting face.

The phase place of the PM season address signal that FF circuit 1059-3 is produced by counting face holding unit 1059-1 with a clock signal delay of master clock.The FEBEPM that the output (RPMADC6) of FF circuit 1059-3 is kept RAM1058-1 as BIPPM and will illustrate below keeps the address of reading on the counting face of RAM1093 (with reference to Figure 135 and 139).

The PM that FF circuit 1059-4 is supplied with by FF circuit 1059-3 with a clock signal delay of master clock counts the phase place of address signal.Keep RAM1058-1 and FEBEPM to keep the address that writes on the counting face of RAM1093 as BIPPM the output of FF circuit 1059-4.

FF circuit 1059-5 is with a clock signal delay BIPPM Notify Address of the master clock phase place of [indication being used to read 7 signals that obtain after output signal (1) addition of address signal (MBIPPMRAD:6 position) and negater 1059-2 of TU channel of the BIPPM that supplies with from software side].The output (BIPPM Notify Address) of FF circuit 1059-5 is kept the address of reading on the notice face of RAM1058-1 as BIPPM.

FF circuit 1059-6 is with a clock signal delay FEBEPM Notify Address of the master clock phase place of [indication being used to read 7 signals that obtain after output signal (1) addition of address signal (FEBEPMRAD:6 position) and negater 1059-2 of TU channel of the FEBEPM that supplies with from software side].The output (BEFEPM Notify Address) of FF circuit 1059-6 is kept the address of reading on the notice face of RAM1093 as FEBE.

The PMRAM address control unit 1059 with said structure of present embodiment is changed each BIPP M according to the timing of the best and is kept RAM1058-1 and FEBEPM to keep counting face and the notice face of RAM1093, thereby can be at any time with accurate BIPPM and FEBEPM notice software side.

Figure 119 is the block diagram of the detailed structure of the BIPPM count value initialization control unit 1056 shown in expression Figure 108.Shown in Figure 119, BIPPM count value initialization control unit 1056 has FF circuit 1056-1,1056-2 and 1056-8, timing control unit (1-input inversion formula OR circuit) 1056-3, read/write signal generation unit [decoding circuit (DEC)] 1056-4, allows to write generation unit (OR circuit) 1056-5, BIPPM count value initialization request signal holding unit (FF circuit) 1056-6 and BIPPM count value initialization request signal selected cell (selector) 1056-7.

FF circuit 1056-1 and 1056-2 are with the phase place of a clock signal delay PM reset signal of master clock.By the above-mentioned phase place adjustment that postpones the PM reset signal by FF circuit 1056-1 and 1056-2 the control of the conversion of each face of being carried out according to this PM reset signal by PMRAM address control unit 1059 is regularly reached initialized control timing to the BIPPM count value of being undertaken by BIPPM count value initialization control unit 1056.

The timing of timing control unit 1056-3 control BIPPM count value initialization request signal.For example, when signal that BIPPM handles is carried out in indication for " 1 ", the content (TUADC7) of the TU channel that timing control unit 1056-3 output should be handled, and when above-mentioned timing signal (B3V5TPC7) is " 0 " is controlled to be 63 (being shown " 111111 " with binary form) with itself output signal.

Read/write signal generation unit 1056-4, when the output signal of timing control unit 1056-3 is 0 any value in 62, to 0 to 62 respective channels produce be used to read BIPPM count value initialization request signal selection signal (supplying with BIPPM count value initialization request signal selected cell 1056-7), and produce permission write signal to BIPPM count value initialization request signal holding unit 1056-6.When the output signal of timing control unit 1056-3 was 63, this was not to carry out the timing that BIPPM handles, thereby did not produce to read and select signal and allow write signal.

Allow to write generation unit 1056-5, when by FF circuit 1056-5 input PM reset signal, make all permission write signals be to 0 to 62ch " 1, and when not importing the PM reset signal, by the output signal of previous status output read/write signal generation unit 1056-4.BIPPM count value initialization request signal holding unit 1056-6 keeps the BIPPM count value initialization request signal to 0 to 62ch TU channel, and its function is realized by 63 FF circuit 1056-6A.

In BIPPM count value initialization request signal holding unit 1056-6, for example, utilization will become " 1 " to the permission write signal of all channels by the PM reset signal that FF circuit 1056-2 supplies with, thereby make FF circuit 1056-6A become " 1 " to the data of all channels, that is, all channels are write FF circuit 1056-6A simultaneously with " 1 " by the PM reset signal.

When the timing signal (B3V5TPC7) of the back input B3/V5 byte that resets at PM, by by timing control unit 1056-3, read/write signal generation unit 1056-4 and allow to write processing that generation unit 1056-5 carries out and make the permission write signal of the channel that its BIPPM count value should handle become " 1 ".Owing at this moment do not import the PM reset signal,, thereby " 0 " write the FF circuit 1056-6A that is used to answer processing channel so the input data of each FF circuit 1056-6A are " 0 ".Therefore, by the 1st B3/V5 timing signal (B3V5TPC7) BIPPM count value initialization request signal is eliminated.

That is, after PM resets, only read BIP error count value by the counting face of the 1st B3/V5 timing signal after the initialization.

BIPPM count value initialization request signal selected cell 1056-7 reads BIPPM count value initialization request signal to 0 to 62ch selectively according to the output signal of read/write signal generation unit 1056-4.FF circuit 1056-8 is with the phase place of the output signal of a clock signal delay BIPPM count value initialization request signal selected cell 1056-7 of master clock, thereby the phase place of the output signal of BIPPM count value initialization request signal selected cell 1056-7 is adjusted into phase place used when carrying out reset processing by BIPPM serial process unit 1057.

The BIPPM count value initialization control unit 1056 with said structure of present embodiment can produce at any time by the timing of the best according to the PM reset signal and be used for the initialized reset signal of BIPPM count value (BIPPMCTRRSTC8), thereby BIPPM serial process unit 1057 is accurately operated.

Be briefly described the integrated operation of B3/V5 byte terminal processes unit 1023 now with said structure.For example, as press timing input TU data (V5 byte), TUAD, SPEEN, J1V5TP, VC3TUG and the VC2VC12 shown in Figure 120 (a)～120 (f), then the each several part of BIP2 error serial detecting unit 1053 shown in Figure 110 and BIP2 holding unit 1054 will be according to the fixed cycle operator shown in Figure 121 (a)～121 (o).

At this moment, the each several part of the BIPPM count value initialization control unit 1056 shown in the PMRAM address control unit 1059 shown in Figure 118 and Figure 119, for example according to the fixed cycle operator shown in Figure 123 (a)～123 (q) [or Figure 124 (a)～124 (o)], the each several part that makes BIPPM serial detecting unit 1057 shown in Figure 112 and BIPPM holding unit 1058 is handled thereby with serial mode each TU channel is carried out BIPPM for example according to the fixed cycle operator shown in Figure 122 (a)～122 (n).

The POH terminal processes unit 1008 of present embodiment can be by the public B3/V5 byte terminal processes unit 1023 of all channels is carried out the BIP terminal (operation) of B3 byte is handled the BIP terminal processes that reaches the V5 byte with serial mode.Therefore, do not need to install being used for of equating with the respective channels number carry out the BIP terminal processes to B3 byte and V5 byte circuit.This can reduce the scale and the power consumption of device to the utmost.

Specifically, B3/V5 byte terminal processes unit 1023 is to detect the BIP2 error that should detect in the POH terminal processes that each channel that has the unlike signal specification is usually carried out to the public mode of all channels.Therefore, do not need to install the circuit that for example being used to of equating with the respective channels number detect the circuit of BIP8 error and be used to detect the BIP2 error.This can further reduce the scale and the power consumption of device to the utmost.

Above-mentioned B3/V5 byte terminal processes unit 1023 (with reference to Figure 109), for example, shown in Figure 125, can have BIP2 serial operation processing unit 1053A and 1053B, BIP8 serial operation processing unit 1055, TU3 serially adds method unit (the 1st BIPPM serially adds the method unit) 1057C with BIPPM, TU2/TU12 serially adds method unit (2BIP PM serially adds the method unit) 1057D and 1057E with BIPPM, TU3 BIPPM holding unit (the 1st memory cell) 1058A, TU2/TU12 BIPPM holding unit (the 2nd memory cell) 1058B and 1058C and BIPPM selected cell 1057F, handle and the processing of BIP2 serial terminal by the BIP8 serial terminal, try to achieve BIP error signal (BIPPM) one by one, and export each BIPPM selectively.

BIPPM can be tried to achieve with serial mode with simple structure in B3/V5 byte terminal processes unit 1023 shown in Figure 125.If do not require and specifically use the BIPPM holding unit 1058A～1058C public to all signal specifications, then said structure is extremely effective.When constituting this device, help to improve flexibility and versatility.

(b-9) explanation of C2/V5 byte terminal processes unit 1024

Figure 126 is the block diagram that is illustrated in the structure of the C2/V5 byte terminal processes unit 1024 that illustrated with reference to Figure 62 in the preamble.Shown in Figure 126, C2/V5 byte terminal processes unit 1024 has UNEQ detecting unit 1071, SL holding unit 1072, SLM detecting unit 1073 and alarm bit holding unit 1074.

UNEQ detecting unit 1071 detects from being included in UNEQ indication (the signal mark: SL) of interior C2 byte of multiplex signal (VC4 data) and V5 byte with serial mode.SL holding unit (UNEQ data holding unit) 1072 storages are supplied with stored information UNEQ detecting unit 1071 in addition by the testing result that 1071 pairs of each channels of UNEQ detecting unit obtain.

SLM detecting unit 1073 detects from being included in the detected mismatch of C2/V5 byte (SLM) in the VC4 data.Alarm bit holding unit (SLM data holding unit) 1074 maintenances are supplied with stored information SLM detecting unit 1073 in addition by each testing result that 1073 pairs of each channels of SLM detecting unit obtain.

In C2/V5 byte terminal processes unit 1024, POH terminal operation processing unit 1026 shown in Figure 63 is configured to UNEQ serial terminal processing unit 1026C, be used for the UNEQ that is included in the C2/V5 byte in the VC4 data being carried out terminal processes with serial mode, and be configured to SLM serial terminal processing unit 1026D, be used for the SLM of above-mentioned C2 byte/V5 byte is carried out terminal processes, and the memory cell shown in Figure 63 1027 is configured to memory cell 1027C, be used to store the operating result that each channel is carried out by UNEQ serial terminal processing unit 1026C, in addition canned data is supplied with UNEQ serial terminal processing unit 1026C, and be configured to memory cell 1027D, be used to store the operating result that each channel is carried out by SLM serial terminal processing unit 1026D, in addition canned data supplied with SLM serial terminal processing unit 1026D.

Therefore, above-mentioned C2/V5 byte terminal processes unit 1024 can carry out serial with the SLM that the public mode correspondence of all channels is detected and detects in the POH terminal processes that each channel that has the unlike signal specification is usually carried out.

Specifically, for example, shown in Figure 127, above-mentioned UNEQ detecting unit 1071 has: C2UNEQ indication serial detecting unit 1075, and whether be used for detecting the C2 byte with serial mode is the UNEQ indication; V5UNEQ indication serial detecting unit 1076, whether be used for detecting the V5 byte with serial mode is the UNEQ indication; UNEQ indicates selected cell 1077, is used to select the UNEQ from detecting

unit

1075 or 1076 outputs to indicate detection signal; And UNEQ serial detecting unit 1078, be used for indicating detection signal to detect the UNEQ of C2/V5 byte with serial mode according to the UNEQ that selects by UNEQ indication selected cell 1077.

On the other hand, for example, shown in Figure 128, above-mentioned SLM detecting unit 1073 has: C2 mismatch serial detecting unit 1081 is used for detecting the mismatch that records in the C2 byte with serial mode; V5 mismatch serial detecting unit 1082 is used for detecting the mismatch that records in the V5 byte with serial mode; Mismatch selected cell 1083 is used to select from detecting unit 1081 or the 1082 detection of mismatch signals of exporting; And SLM serial detecting unit 1084, be used for detecting C2/V5 byte SLM with serial mode according to the detection of mismatch signal of selecting by mismatch selected cell 1083.

Below, will be elaborated to UNEQ detecting unit 1071, SL holding unit 1072, SLM detecting unit 1073 and alarm bit holding unit 1074.

Figure 129 is the block diagram of the detailed structure of expression UNEQ serial detecting unit 1071 and SL holding unit 1072.Shown in Figure 129; UNEQ serial detecting unit 1071 has the FF circuit 1071-1～1071-3 of each tape starting terminal; UNEQ protection progression adder unit 1071-4; decoding circuit (DEC) 1071-5～1071-7; eliminate progression selected cell (selector) 1071-8; SL district control unit (AND circuit) 1071-9; UNEQ indication detecting unit 1071-10; add 1 state detection unit ("or" else circuit) 1071-11; UNEQ detects 4 grades of detecting units (1-input inversion formula AND circuit) 1071-12; UNEQ eliminates detecting unit (AND circuit) 1071-13; state transitions generation detecting unit (OR circuit) 1071-14; UNEQ protection progression information reset unit 1071-15 and state transitions unit ("or" else circuit) 1071-16, and SL holding unit 1072 has SL maintenance RAM1072-1.

The SL of SL holding unit 1072 keeps RAM1072-1 to keep the protection progression information of UNEQ and SLM, its operation be TU address signal (TUADC6) that phase-shift unit 1032 ' (with reference to the Figure 69) by timing generation unit 1021 supplied with as read the address, with TUADC7 as write the address, and the XSLWENC8 that will keep RAM operation control unit 1039 (with reference to Figure 76) supply by the SL of timing generation unit 1021 as the permission write signal and with SLCK as ram clock.

The SL of present embodiment keeps RAM1072-1 to keep 6 data, and wherein UNEQ protects in the memory block of progression information stores sequence number 2 to 0 on the throne, and in the memory block of SLM protection progression information stores sequence number 5 to 3 on the throne.

In UNEQ serial detecting unit 1071, the FF circuit 1071-1 timing signal of C2/V5 byte location (C2V5TPC7) as indicated keeps SL to keep the 2nd to the 0th the data (UNEQ protection progression information) of the sense data of RAM1072-1.FF circuit 1071-2 keeps the data (TUDTC7) of the C2/V5 byte of VC4 data according to above-mentioned timing signal (C2V5TPC7).FF circuit 1071-3 according to above-mentioned timing signal (C2V5TPC7) keep the UNEQ alarm bit, promptly to the result of former frame.

UNEQ protection progression adder unit 1071-4 adds 1 in the count value of the UNEQ protected level information that keeps RAM1072-1 to read from SL.Decoding circuit (" 3 " decoding unit) 1071-5 detects for " 3 " the count value of the UNEQ protected level information of being read.Decoding circuit (" 4 " decoding unit) 1071-6 detects for " 4 " the count value of the UNEQ protected level information of being read.Decoding circuit (" 5 " decoding unit) 1071-7 detects for " 5 " the count value of the UNEQ protected level information of being read.

Because for eliminating the different of the progression that UNEQ adopted and TU2/TU12 among the TU3, promptly in TU3, adopt 6 grades and in TU2/TU12, adopt 5 grades, so eliminate progression selected cell 10721-8 selects decoding circuit 1071-7 according to the timing signal of the C2 byte of the UNEQ that is used for detecting TU3 output signal.Because the SL district of C2 byte is different with the V5 byte, all 8 that are the C2 byte all is the signal mark of TU3, and the 5th to the 7th of V5 byte is the signal mark of TU2/TU12, so when the data in remaining on FF circuit 1071-2 were the C2 byte, SL district control unit 1071-9 did not control, and the data in remaining on FF circuit 1071-2 are when being the V5 byte, then control, with the 1st to the 4th and the 8th bit mask, so that " 0 " is replaced by in its each position.

UNEQ indication detecting unit 1071-10 detects that to carry out 8 of the signal controlled by SL district control unit 1071-9 all be the situation of " 0 ".Add 1 state detection unit 1071-11 and detect the situation that when UNEQ takes place, does not detect the UNEQ indication or when UNEQ does not take place, detect the UNEQ indication.UNEQ detects 4 grades of detecting unit 1071-12, when by adding 1 state and be used to discern situation about adding more than 1 state continuous detecting, 4 frames when not detecting UNEQ more than decoding circuit 1071-5 continuous detecting 3 frames, and further 1 state that adds that detects in present frame, so that detect UNEQ.

UNEQ eliminates detecting unit 1071-13, when from by the output signal continuous detecting 4 of eliminating decoding circuit 1071-6 that progression selected cell 10721-8 selects or 1071-7 or more than 5 frames add 1 state the time, be used to discern 1 state continuous detecting, 5 frames or the above situation of 6 frames of adding, and further 1 state that adds that detects in present frame, so that UNEQ is eliminated.

State transitions generation detecting unit 1071-14 is used to detect the state that UNEQ is detected or eliminates.UNEQ protection progression information reset unit 1071-15; in adding 1 state detection unit 1071-11, do not detect and add 1 state and state transitions generation detecting unit 1071-14 detects when state transitions takes place; UNEQ protected level information is reset to " 0 ", and its output signal (count value) is write in the SL maintenance RAM1072-1.

State transitions unit 1071-16, when state transitions generation detecting unit 1071-14 detects the generation state transitions, the polarity of the alarm bit of UNEQ is anti-phase, thereby produce a signal, be used to indicate from state transitions that UNEQ takes place to the nonevent state of UNEQ, or the state transitions of the state transitions of UNEQ to the state that UNEQ takes place never takes place.

The UNEQ serial detecting unit 1071 of present embodiment keeps RAM1072-1 to read the UNEQ of former frame successively from SL, so that the UNEQ with present frame upgrades according to the information of reading, thereby so that the public mode of all TU channels is carried out the serial detection and notified software side with UNEQ UNEQ.

Figure 130 is the block diagram of the detailed structure of the SLM serial detecting unit 1073 shown in expression Figure 126.Shown in Figure 130, SLM serial detecting unit 1073 of the present invention has the FF circuit 1073-1～1073-4 of each tape starting terminal; SLM protection progression adder unit 1073-5; decoding circuit (DEC) 1073-6 and 1073-7; SL district control unit (AND circuit) 1073-8; inconsistent detecting unit 1073-9; add 1 state detection unit ("or" else circuit) 1073-10; SLM detects 7 grades of detecting units (1-input inversion formula AND circuit) 1073-11; SLM eliminates 3 grades of detecting units (AND circuit) 1073-12; state transitions generation detecting unit (OR circuit) 1073-13; SLM protection progression information reset unit 1073-14 and state transitions unit ("or" else circuit) 1073-15.

FF circuit 1073-1 keeps keeping data (SLM protection progression information: RSLDTC7) on the 5th to the 3rd of sense data that RAM1072-1 supplies with by SL according to the timing signal (C2V5TPC7) of indication C2/V5 byte location.FF circuit 1073-2 keeps the C2/V5 byte data (TUDTC7) of VC4 data according to above-mentioned timing signal (C2V5TPC7).

FF circuit 1073-3 keeps the reception desired value (REXPSLC7) of the signal mark read from above-mentioned reception desired value holding unit 1048 (with reference to Figure 85 and 95) according to above-mentioned timing signal (C2V5TPC7).FF circuit 1073-4 keeps the SLM of former frame is detected the result data of handling (RSLMC7) according to above-mentioned timing signal (C2V5TPC7).

SLM protection progression adder unit 1073-5 adds 1 in the count value of the SLM protection progression information that keeps RAM1072-1 to read from SL.Decoding circuit (" 6 " decoding unit) 1073-6 detects for " 6 " the count value of the SLM protected level information of being read.Decoding circuit (" 2 " decoding unit) 1071-7 detects for " 2 " the count value of the SLM protected level information of being read.

Because the SL district in the TU3 is different with the SL district in the TU2/TU12, all 8 that are the C2 byte all is the signal mark of TU3, and the 5th to the 7th of V5 byte is the signal mark of TU2/TU12, so, when the data in remaining on FF circuit 1073-3 were the C2 byte, SL district control unit 1073-8 did not control.When the data in remaining on FF circuit 1073-3 are the V5 byte, then control, with the 1st to the 4th and the 8th bit mask, so that " 0 " is replaced by in its each position.

Inconsistent detecting unit 1073-9 detects at 8 that have been shielded by SL district control unit 1073-8 and receives inconsistent between data and the SL reception desired value.When the reception value of SL with receive desired value consistent and when SLM takes place and when the reception value of SL inconsistent and when SLM not taking place, add 1 state detection unit 1073-10 detection and add 1 state with the reception desired value.

SLM detects 7 grades of detecting unit 1073-11, when by adding 1 state and be used to discern situation about adding more than 1 state continuous detecting, 7 frames when not detecting SLM more than decoding circuit 1073-6 continuous detecting 6 frames, and further 1 state that adds that detects in present frame, so that detect SLM.SLM eliminates 3 grades of detecting unit 1073-12, when by more than decoding circuit 1073-7 continuous detecting 2 frames add 1 state and when detecting SLM, be used to discern situation about adding more than 1 state continuous detecting, 3 frames, and further detect 1 state that adds in present frame, so that SLM is eliminated.

State transitions generation detecting unit 1073-13 is used to detect the state that SLM is detected or eliminates.SLM protection progression information reset unit 1073-14 does not have detection to add 1 state in adding 1 state detection unit 1073-10 and state transitions generation detecting unit 1073-13 detects when state transitions takes place, and SLM protected level information is reset to " 0 ".State transitions unit 1073-15, when state transitions generation detecting unit 1073-13 detects the generation state transitions, the polarity of the alarm bit of SLM is anti-phase, thereby with state from state transitions that SLM takes place to the nonevent state of SLM, or the state of the state transitions of SLM to generation SLM never takes place, and its output signal (WSLMC8) is write alarm bit holding unit 1074.

For example, shown in Figure 131, above-mentioned alarm bit holding unit 1074 has UNEQ alarm bit holding unit 1074-1, SLM alarm bit holding unit 1074-2, alarm bit writes address control unit (1-input inversion formula OR circuit) 1074-3, allow to write generation unit [decoding circuit (DEC)] 1074-4, alarm bit is read address control unit (1-input inversion formula OR circuit) 1074-5, read and select generation unit [decoding circuit (DEC)] 1074-6, UNEQ selected cell (selector) 1074-7, SLM selected cell (selector) 1074-8, the circuit handover information is read and is selected generation unit [decoding circuit (DEC9)] 1074-9, UNEQ circuit handover information is read selected cell (selector) 1074-10, SLM circuit handover information is read selected cell (selector) 1074-11, the software notice is read and is selected generation unit (selector) 1074-12, UNEQ software notice reads selected cell (selector) 1074-13 and SLM software notice is read selection generation unit (selector) 1074-14.

UNEQ alarm bit holding unit 1074-1 is with the UNEQ alarm bit of the TU channel of 63 FF circuit 1074-1A maintenances 0 to 62ch.SLM alarm bit holding unit 1074-2 is with the SLM alarm bit of the TU channel of 63 FF circuit 1074-2A maintenances 0 to 62ch.

Alarm bit writes address control unit 1074-3, when the indication alarm bit writes timing signal (C2V5TPC8) regularly for " 1 ", the content (TUADC8) of the TU channel that output should be handled, and the output signal of itself is controlled to be 63 (" 111111 ") when " 0 " when above-mentioned timing signal (C2V5TPC8).

Allow to write generation unit 1074-4, the output signal that writes address control unit 1074-3 when above-mentioned alarm bit is 0 in 62 during arbitrary value, produce being used to keep the FF circuit 1074-1A of alarm bit and the permission write signal of 1074-2A 0 to 62ch, so that will carry out FF circuit 1074-1A and the 1074-2A that alarm signal (WUNEQC8, WSLMC8) that UNEQ and SLM handle writes the TU channel alarm bit that maintenance handled.When the output signal that writes address control unit 1074-3 when alarm bit is 63, because this is not the timing that writes alarm bit, so do not produce the permission write signal.

Alarm bit is read address control unit 1074-5, when the indication alarm bit is read timing signal (C2V5TPC8) regularly for " 1 ", the content (TUADC7) of the TU channel that output should be handled, and the output signal of itself is controlled to be 63 (" 111111 ") when " 0 " when above-mentioned timing signal (C2V5TPC8).

Read and select generation unit 1074-6, when the output signal of reading address control unit 1074-5 when above-mentioned alarm bit is 0 to 62, select to be used to read the signal of 0 to 62ch alarm bit.When the output signal of reading address control unit 1074-5 when above-mentioned alarm bit is 63, because this is not the timing of reading alarm bit, so do not produce the permission write signal.

UNEQ selected cell 1074-7 basis is by reading the alarm bit of selecting reading of generation unit 1074-6 generation to select signal to read the UNEQ of the TU channel that should handle.SLM selected cell 1074-8 basis is by reading the alarm bit of selecting reading of generation unit 1074-6 generation to select signal to read the SLM of the TU channel that should handle.

The circuit handover information read select generation unit 1074-9 to produce to be used for 0 to 62ch TU channel read the selection signal.UNEQ circuit handover information is read selected cell 1074-10 and is read the UNEQ alarm bit according to read the selection signal of reading of selecting generation unit 1074-9 to produce by the circuit handover information.SLM circuit handover information is read selected cell 1074-11 and is read the SLM alarm bit according to read the selection signal of reading of selecting generation unit 1074-9 to produce by the circuit handover information.

Software notice read select generation unit 1074-12 to produce to be used for 0 to 62ch TU channel read the selection signal.UNEQ software notice is read selected cell 1074-13 and is selected signal to read UNEQ to report to the police according to read reading of selecting that generation unit 1074-12 produces by the software notice, and with this UNEQ alert notice software side.SLM software notice is read selected cell 1074-14 and is selected signal to read SLM to report to the police according to read reading of selecting that generation unit 1074-12 produces by the software notice, and with this SLM alert notice software side.

The SLM serial detecting unit 1073 with said structure of present embodiment, read the SLM alarm bit of former frame successively from above-mentioned alarm bit holding unit 1074, so that the SLM warning of present frame is upgraded according to the information of reading, thereby so that the public mode of all TU channels is carried out the serial detection and notified software side with SLM UNEQ.

Below, be briefly described the integrated operation of C2/V5 byte terminal processes unit 1024 with said structure.For example, as press the timing shown in Figure 132 (a)～132 (f) and import TU data (C2 byte), TUAD (" 0 "), SPEEN and J1V5TP, then the each several part of the alarm bit holding unit 1074 shown in the SLM detecting unit 1073 shown in the UNEQ detecting unit 1071 shown in Figure 104, Figure 130 and Figure 131 will be according to the fixed cycle operator shown in Figure 132 (g)～132 (z) and 132 (α), thereby with serial mode each TU channel is carried out UNEQ terminal processes (the UNEQ indication detects and UNEQ software notice) and SLM terminal processes (the SLM indication detects and SLM software is notified)

As mentioned above, the POH terminal processes unit 1008 of present embodiment can be by the public C2/V5 byte terminal processes unit 1024 (UNEQ serial terminal processing unit) of all channels is carried out to the UNEQ terminal processes of C2 byte and to the UNEQ terminal processes of V5 byte with serial mode.Therefore, do not need to install being used for of equating with the respective channels number carry out the UNEQ terminal processes to C2 byte and V5 byte circuit.This can reduce the scale and the power consumption of device to the utmost.

Specifically, C2/V5 byte terminal processes unit 1024 is by the UNEQ indication of the public UNEQ detecting unit 1071 of all channels being carried out should carry out in the POH terminal processes to each channel of having the unlike signal specification usually.Therefore, do not need to install the circuit that is used to indicate UNEQ that equates with the respective channels number.This can reduce the scale and the power consumption of device to the utmost.

The POH terminal processes unit 1008 of present embodiment can be by the public C2/V5 byte terminal processes unit 1024 (SLM serial terminal processing unit) of all channels is carried out to the SLM terminal processes of C2 byte and to the SLM terminal processes of V5 byte with serial mode.This can further reduce the scale and the power consumption of device.

Specifically, C2/V5 byte terminal processes unit 1024 detects with the SLM that the public mode of all channels is carried out should carry out in the POH terminal processes to each channel of having the unlike signal specification usually.Therefore, do not need to install the circuit that is used to detect SLM that equates with the respective channels number.This can reduce the scale and the power consumption of device to the utmost.

Above-mentioned C2/V5 byte terminal processes unit 1024 (with reference to Figure 127), shown in Figure 133, can have C2UNEQ indication serial detecting unit 1075A, V5UNEQ indication

serial detecting unit

1076A and 1076B, TU3 UNEQ serial detecting unit (the 1st UNEQ serial detecting unit) 1078A, TU2/TU12 UNEQ serial detecting unit (the 2nd UNEQ serial detecting unit) 1078B and 1078C, TU3 UNEQ holding unit (the 1st memory cell) 1072A, TU2/TU12 UNEQ holding unit (the 2nd memory cell) 1072B and 1072C and UNEQ data selection unit 1077A, carry out one by one the UNEQ indication of C2 byte is handled and the UNEQ indication of V5 byte is handled with serial mode, and export each UNEQ indication selectively.

Therefore, UNEQ can be indicated with serial mode with simple structure in the C2/V5 byte terminal processes unit 1024 shown in Figure 133.If do not require and specifically use UNEQ holding unit 1072A～1072C that public being used to keeps UNEQ to indicate to all signal specifications, then said structure is effectively, helps to improve flexibility and versatility when constituting this device significantly.

Above-mentioned C2/V5 byte terminal processes unit 1024 (with reference to Figure 128), shown in Figure 134, can have C2 mismatch serial detecting unit 1081A, V5 mismatch

serial detecting unit

1082A and 1082B, TU3 SLM serial detecting unit (the 1st SLM serial detecting unit) 1084A, TU2/TU12 SLM serial detecting unit (the 2nd SLM serial detecting unit) 1084B and 1084C, TU3 SLM holding unit (the 1st memory cell) 1074A, SLM holding unit (the 2nd memory cell) 1074B and 1074C and the SLM data selection unit 1083A that are used for TU2/TU12, carry out one by one the SLM detection of C2 byte is handled and the SLM detection of V5 byte is handled with serial mode, and export each SLM data selectively.

Therefore, the C2/V5 byte terminal processes unit 1024 shown in Figure 134 can detect SLM with serial mode with simple structure.If do not require the SLM holding unit 1074A～1074C that specifically uses to all signal specifications public being used to keep the SLM data, then said structure is extremely effective, helps to improve flexibility and versatility when constituting this device significantly.

(b-10) explanation of G1/V5 byte terminal processes unit 1025

Figure 135 is the block diagram that is illustrated in the structure of the G1/V5 byte terminal processes unit 1025 that illustrated with reference to Figure 62 in the preamble.Shown in Figure 135, the G1/V5 byte terminal processes unit 1025 of present embodiment has FEBE detecting unit 1091, FEBEPM serial process unit 1092, FEBEPM holding unit 1093, FEBEPM count value initialization control unit 1094, FERF serial process unit 1095, FERF holding unit 1096 and alarm bit holding unit 1097.

FEBE detecting unit 1091 detects with serial mode and is included in the interior G1 byte of multiplex signal (VC4 data) and the FEBE of V5 byte.FEBEPM serial process unit 1092 carries out phase add operation with serial mode to the count value of FEBEPM according to the FEBBE detection signal of being supplied with by FEBE detecting unit 1091.

(count value) addition result that 1093 storages of FEBEPM holding unit are undertaken by 1092 pairs of each channels in FEBEPM serial process unit is supplied with FEBEPM serial process unit 1092 with the stored information of itself in addition.The addition result initialization that FEBEPM count value initialization control unit 1094 will be undertaken by FEBEPM serial process unit 1092 according to the PM reset signal.

FERF serial process unit 1095 carries out terminal processes with serial mode to being included in the G1 byte in the VC4 data and the FERE of V5 byte.Each result (FERF) who handles that FERF holding unit (FERF data holding unit) 1096 storages (maintenance) are undertaken by 1095 pairs of each channels in FERF serial process unit in addition, also supplies with FERF serial process unit 1095 with the stored information of itself.Each result's (FERF alarm bit) who handles that alarm bit holding unit (FERF data holding unit) 1097 storages (maintenance) are undertaken by 1095 pairs of each channels in FERF serial process unit, in addition, also the stored information of itself is supplied with FERF serial process unit 1095.

Promptly, in G1/V5 byte terminal processes unit 1025, just the POH terminal operation processing unit 1026 shown in Figure 63 is configured to FEBE serial terminal processing unit 1026E, be used for carrying out terminal processes to being included in the G1 byte in the VC4 data and the FEBE and the FEBEPM of V5 byte with serial mode, and be configured to FERF serial terminal processing unit 1026F, be used for the FERF of above-mentioned G1 byte and V5 byte is carried out terminal processes, and the memory cell shown in Figure 63 1027 is configured to memory cell 1027E, be used to store the operating result that each channel is carried out by FEBE serial terminal processing unit 1026E, in addition canned data is supplied with FEBE serial terminal processing unit 1026E, and be configured to memory cell 1027F, be used to store the operating result that each channel is carried out by FERF serial terminal processing unit 1026F, in addition canned data supplied with FERF serial terminal processing unit 1026F.

Above-mentioned G1/V5 byte terminal processes unit 1025 can carry out serial with FEBE, FEBEPM, the FERF that the public mode correspondence of all channels is detected and detect in the POH terminal processes to each channel of having the unlike signal specification usually.

Specifically, for example, shown in Figure 136, above-mentioned FEBE detecting unit 1091 has: G1FEBE serial detecting unit 1098 is used for the FEBE with serial mode detection G1 byte; V5FEBE serial detecting unit 1099 is used for the FEBE with serial mode detection V5 byte; FEBE selected cell 1100 is used to select from detecting unit 1098 or the 1099 FEBE detection signals of exporting; And FEBEPM detecting unit 1092 has FEBEPM serial addition unit 1101, is used for serial mode FEBEPM being carried out the phase add operation according to the FEBE detection signal of being selected by FEBE selected cell 1100.

Above-mentioned FERF serial process unit 1095 has: G1FERF indication serial detecting unit 1102 is used for detecting the byte G1 that indicates FERF with serial mode; V5FERF indication serial detecting unit 1103 is used for detecting the byte V5 that indicates FERF with serial mode; The FERF indication detects selected cell 1104, is used for the FERF indication detection signal from detecting

unit

1102 or 1103 outputs; And FERF serial detecting unit 1106, be used for according to indicate the FERF indication detection signal that detects selected cell 1104 selections to detect the FERF of above-mentioned G1 byte or V5 byte with serial mode by FERF.

To describe above-mentioned FEBE detecting unit 1091, FEBEPM serial process unit 1092, FEBEPM holding unit 1093, FEBEPM count value initialization control unit 1094, FERF serial process unit 1095, FERF holding unit 1096 and alarm bit holding unit 1097 below in detail.

Figure 138 is the block diagram of the detailed structure of expression FEBE detecting unit 1091.Shown in Figure 138, the FEBE detecting unit 1091 of present embodiment has FF circuit 1091-1, the G1 byte FEBE detecting unit 1091-2 of tape starting terminal and the selector 1091-3 of the FEBE selected cell 1100 of conduct shown in Figure 136.

FF circuit 1091-1 keeps the data (TUDTC7) on the 1st to the 4th of G1/V5 byte of VC4 data according to the timing signal (G1V5TPC7) of the timing of indication G1/V5 byte.The content that G1 byte FEBE detecting unit 1091-2 detects 4 of the high positions of the G1/V5 byte data that is kept by FF circuit 1091-1 is 1 to 8 situation.

Selector 1091-3 selects the FEBBE of G1 byte or the FEBE of V5 byte according to timing signal (V5TPIC8).In handling, uses performance monitoring (PM) output signal (FEBE) of selector 1091-3.As the zone of FEBE, high-order 4 content is the FEBE code (with reference to Figure 169) in the G1 byte, is to detect FEBE at 1 to 8 o'clock in the content of this code.In the V5 byte, the 3rd is the FEBE code (with reference to Figure 171) in the V5 byte, detects FEBE when the content of this code is " 1 ".

In having the FEBE detecting unit 1091 of said structure, as press the timing shown in Figure 145 (a)～145 (f) and import TU data (G1 byte), TUAD (" 0 "), SPEEN and J1V5TP, then the each several part of FEBE detecting unit 1091 will be according to the fixed cycle operator shown in Figure 145 (g)～145 (m), and the FEBE[that exports the G1 byte selectively is with reference to Figure 145 (j)] or the FEBE[of V5 byte with reference to Figure 145 (k)], so that FEBE is supplied with the FEBEPM detecting unit 1092 public to all channels with serial mode.

Figure 139 is the block diagram of the detailed structure of above-mentioned FEBEPM serial process unit 1092 of expression and FEBEPM holding unit 1093.Shown in Figure 139, FEBEPM serial process unit 1092 has FF circuit 1092-1, FEBE count value initialization control unit (1-input inversion formula AND circuit) 1092-2 and the FEBEPM adder unit 1092-3 of tape starting terminal, and FEBEPM holding unit 1093 has FEBEPM maintenance RAM1093-1.

The FEBEPM of FEBEPM holding unit 1093 keeps RAM1093-1 to keep FEBE error count value and should notify the FEBEPM count value of software.About FEBEPM, similar with BIPPM, in order to count and before next PM reset signal, to notify software, must count and between the PM reset signal, notify software error amount with count value with count value to occurring in FEBE value between the PM reset signal.For this reason, must keep the count value of error and the count value that should notify.

Therefore, the FEBEPM of present embodiment keeps RAM1093-1 to have 2 faces, promptly low plane [address 0 (00 _HEX) to 63 (3F _HEX)] and high plane [address 64 (40 _HEX) to 127 (7F _HEX)], its effect is designated as the notice face (PM result keeps face) that is used for the counting face that FEBE is counted and is used to notify the count value of FEBEPM respectively.In this case, above-mentioned 2 faces can be changed mutually by the polarity of MSB position (PM) of conversion address ram.

FEBEPM keep the operation of RAM1093-1 be with RPMADC6 as on the counting face read the address, with WPMADC7 as on the counting face write the address,, with XFEBEPMWENC8 (with reference to Figure 80) as allow write signal, with FEBEPMRAD as on the notice face read the address and with FEBEPMCK (with reference to Figure 80) as ram clock.

According to present embodiment, FEBEPM keeps RAM1093-1 to keep 13 data, wherein the FEBE count value is remained on the counting face, and the FEBEPM count value is remained on the notice face.

In FEBEPM serial process unit 1092, FF circuit 1092-1 from the count value that FEBEPM keeps the counting face of RAM1093-1 to read FEBE, remains on 12nd to 0th with data according to indication G1/V5 timing signal (G1V5TPC7) regularly.FEBE count value initialization control unit 1092-2 when carrying out the 1st FEBEPM serial process behind the PM signal, resets the FEBBE count value of reading.

FEBEPM adder unit 1092-3 was being undertaken by FEBE count value initialization control unit 1092-2 adding 1 on the FEBE count value of control when detecting FEBE,, and its output signal write the counting face that FEBEPM keeps RAM1093-1.When not detecting FEBE, in FEBEPM adder unit 1092-3, do not carry out addition process, but the FEBE count value that will undertaken controlling by FEBE count value initialization control unit 1092-2 is exported by previous status.

In having the FEBEPM serial process unit 1092 of said structure, similar with FEBE detecting unit 1091, for example as pressing timing input TU data (G1 byte), TUAD (" 0 "), SPEEN and the J1V5TP shown in Figure 145 (a)～145 (f), then the each several part of FEBEPM serial process unit 1092 will be according to the fixed cycle operator shown in Figure 145 (n)～145 (x).

Promptly, FEBEPM serial process unit 1092 is read the FEBEPM (count value) of former frame successively from above-mentioned FEBEPM holding unit 1093, so that the FEBEPM with present frame upgrades according to the information of reading, thereby so that the public mode of all TU channels is carried out the serial terminal processing and notified software side with FEBEPM FEBE.

Figure 140 is the block diagram of the detailed structure of expression FEBEPM count value initialization control unit 1094.Shown in Figure 140, the FEBEPM count value initialization control unit 1094 of present embodiment has FF circuit 1094-1,1094-2 and 1094-8, timing control unit (1-input inversion formula OR circuit) 1094-3, read/write signal generation unit [decoding circuit (DEC)]] 094-4, allow to write generation unit (OR circuit) 1094-5, FEBEPM count value initialization request signal holding unit (FF circuit) 1094-6 and FEBEPM count value initialization request signal selected cell (selector) 1094-7.

FF circuit 1094-1 is with the phase place of a clock signal delay PM reset signal (FEBEPM count value initialization request signal) of master clock.The phase place of the PM reset signal after FF circuit 1094-2 postpones to be postponed by FF circuit 1094-1 so that a clock signal of master clock is further.

The timing of timing control unit 1094-3 control FEBEPM count value initialization request signal.For example, when timing signal (G1V5TPC7) that FEBEPM handles is carried out in indication for " 1 ", the content (TUADC7) of the TU channel that timing control unit 1094-3 output should be handled, and when above-mentioned timing signal (G1V5TPC7) is " 0 ", itself output signal is controlled to be 63 (" 111111 ").

Read/write signal generation unit 1094-4, when the output signal of timing control unit 1056-3 is 0 respective value in 62, to the channel in 0 to 62 produce be used to read FEBEPM count value initialization request signal the selection signal and allow write signal.When the output signal of timing control unit 1094-3 is 63,, thereby does not produce the selection signal that is used to read and allow write signal because this is not to carry out the timing that FEBEPM handles.

Allow to write generation unit 1094-5, when importing the output signal of FF circuit 1094-2 (when the PM reset signal is " 1 "), making all the permission write signals to 0 to 62ch is " 1.When not importing the PM reset signal, allow to write the output signal of generation unit 1094-5 by previous status output read/write signal generation unit 1094-4.

FEBEPM count value initialization request signal holding unit 1094-6 will remain on 63 FF circuit 1094-6A to the FEBEPM count value initialization request signal of 0 to 62ch TU channel, wherein, utilization will become " 1 " to the permission write signal of all channels by the PM reset signal that FF circuit 1094-2 supplies with, make input data become " 1 " simultaneously, thereby all channels are set simultaneously with FEBEPM count value initialization request signal all channels to FF circuit 1094-6A.

When the timing signal (G1V5TPC7) of the back input G1/V5 byte that resets at PM, by by timing control unit 1094-3, read/write signal generation unit 1094-4 and allow to write processing that generation unit 1094-5 carries out and make the permission write signal of the channel that its FEBEPM count value should handle become " 1 ".Owing at this moment do not import the PM reset signal,, thereby " 0 " write the FF circuit 1094-6A that is used to answer processing channel so the input data of coming from FF circuit 1094-2 are " 0 ".

Promptly, in FEBEPM count value initialization request signal holding unit 1094-6, FEBEPM count value initialization request signal is eliminated by the timing of the 1st G1/V5 byte in the PM back that resets, thereby the FEBE count value initialization that after PM resets, can only will read from the counting face of FEBEPM holding unit 1093-1 by the timing of the 1st G1/V5.

FEBEPM count value initialization request signal selected cell 1094-7, according to the output signal of read/write signal generation unit 1094-4 read remain in the FF circuit 1094-6A to 0 to 62ch FEBEPM count value initialization request signal.FF circuit 1056-8 is with the phase place of the output signal of a clock signal delay FEBEPM count value initialization request signal selected cell 1094-7 of master clock, thereby the phase place of the output signal of FEBEPM count value initialization request signal selected cell 1094-7 is adjusted into the phase place that can be used for reset processing.

In having the FEBEPM count value initialization control unit 1094 of said structure, as press the timing shown in Figure 145 (a)～145 (f) and import TU data (G1 byte), TUAD (" 0 "), SPEEN and J1V5TP, then the each several part of FEBEPM count value initialization control unit 1094 will be according to the fixed cycle operator shown in Figure 146 (g)～146 (q), according to the PM reset signal, TU address signal and G1/V5 timing signal produce at any time by the timing of the best and are used for the initialized reset signal of FEBEPM count value (FEBEPMCTRRSTC8), thereby can make FEBEPM serial process unit 1092 in institute's accurately operation if having time.

As mentioned above, the POH terminal processes unit 1008 of present embodiment can be by the public G1/V5 byte terminal processes unit 1025 of all channels is carried out to the FEBE of G1 byte and FEBEPM terminal processes and to the FEBE and the FEBEPM terminal processes of V5 byte with serial mode.This can reduce the scale and the power consumption of device to the utmost.

Specifically, G1/V5 byte terminal processes unit 1025 is by the terminal processes of the public FEBE detecting unit 1091 of all channels and FEBEPM serial process unit 1092 being carried out should be in to the POH terminal processes of each channel of having the unlike signal specification usually FEBE and FEBEPM be carried out.Therefore, do not need to install the circuit of the terminal processes that being used for of equating with the respective channels number carry out FEBE and FEBEPM.This can reduce the scale and the power consumption of device to the utmost.

Figure 141 is the block diagram of the detailed structure of expression FERF serial detecting unit 1095 and FERF holding unit 1096.Shown in Figure 141; FERF serial detecting unit 1095 has the FF circuit 1095-1～1095-3 of each tape starting terminal; FERF protection progression adder unit 1095-4; decoding circuit (DEC) 1095-5; FERF selected cell (selector) 1095-6; add 1 state detection unit ("or" else circuit) 1095-7; FERF detects and eliminates 10 grades of detecting units (AND circuit) 1095-8; FERF protection progression information reset unit (1-input inversion formula AND circuit) 1095-9 and 1095-10SL district, state transitions unit ("or" else circuit) control unit (AND circuit) 1071-9; UNEQ indication detecting unit 1071-10, and FERF holding unit 1096 has FERF maintenance RAM1096-1.

The FERF of FERF holding unit 1096 keep RAM1096-1 keep the protection progression information of FERF, its operation be with by TU address signal (TUADC6) as read the address, with TUADC7 as write address and XFERFWENC8 (keeping 1040 generations of RAM operation control unit) by the FERF shown in Figure 77 as the permission write signal and with FERFCK as ram clock.According to present embodiment, FERF keeps RAM1096-1 to keep 4 data (FERF protection progression information).

In FERF serial detecting unit 1095, the data that FF circuit 1095-1 is read by FERF maintenance 1096-1 according to timing signal (G1V5TPC7) maintenance of indication G1/V5 byte location (FERF protection progression information).FF circuit 1095-2 keeps the 5th and the 8th of data (TUDTC7) of the G1/V5 byte of VC4 data according to above-mentioned timing signal (G1V5TPC7).FF circuit 1095-3 keeps result (FERF alarm bit: FERFC7) to the FERF of the former frame supplied with by alarm bit holding unit 1097 according to above-mentioned timing signal (G1V5TPC7).

FERF protection progression adder unit 1095-4 adds 1 in the count value of the FERF protection progression information that keeps RAM1096-1 to read from FERF.Decoding circuit (" 9 " decoding unit) 1095-5 protects the count value of progression information to detect for " 9 " to the FERF that is read.FERF selected cell 1095-6, the FERF position when FERF position when selection is handled TU3 or selection are handled TU2/TU12.

Here, the 5th of the G1 byte is the interior FERF position (with reference to Figure 169) of TU3, and the least significant bit of V5 byte (the 8th) is the FERF position (with reference to Figure 171) in the TU2/TU12.When in the V5 byte, detecting FERF, use the timing signal (V5TPC8) of V5 byte, select the 8th as the FERF position.

Add 1 state detection unit 1095-7 be used for detecting when FERF takes place, detect the FERF position for the situation of " 0 " and when FERF does not take place when the FERF position be the situation of " 1 ".10 grades of detecting unit 1095-8 of FERF detection elimination are used to detect 1 state that adds by more than above-mentioned decoding circuit 1095-5 continuous detecting 9 frames, and further 1 state that adds that in present frame, detects that detects, thereby discern 1 state that adds more than continuous detecting 10 frames, so that detect or eliminate FERF.

FERF protection progression information reset unit 1095-9; do not detect and add 1 state and when detect eliminating 10 grades of detecting unit 1095-8 the state that detects or eliminate is detected when adding 1 state detection unit 1095-8, the count value of FERF protected level information is reset to " 0 " by FERF.State transitions unit 1095-10, the polarity of the alarm bit of FERF is anti-phase when detecting when state transitions takes place, thereby with state from state transitions that FERF takes place to the nonevent state of FERF, or the state transitions that FERF never takes place is to the state that FERF takes place.

In the FERF serial process unit 1095 with said structure of present embodiment, as press timing input TU data (G1 byte), TUAD (" 0 "), SPEEN and the J1V5TP shown in Figure 147 (a)～147 (f), then the each several part of FERF serial process unit 1095 will be according to the fixed cycle operator shown in Figure 147 (g)～147 (s).

Promptly; FERF serial process unit 1095 from FERF holding unit 1096 (FERF keeps RAM1096-1) and alarm bit holding unit 1097 read successively to former frame result (FERF protected level information and FERF alarm bit); so that the FERF with present frame upgrades according to the information of reading, thereby, the public mode of all TU channels handles so that being carried out serial terminal to FERF.

Figure 142 is the block diagram of the detailed structure of the above-mentioned alarm bit holding unit 1097 of expression.Shown in Figure 142, the alarm bit holding unit 1097 of present embodiment has FERF alarm bit holding unit 1097-1, alarm bit writes address control unit (1-input inversion formula OR circuit) 1097-2, allow to write generation unit [decoding circuit (DEC)] 1097-3, alarm bit is read address control unit (1-input inversion formula OR circuit) 1097-4, read and select generation unit [decoding circuit (DEC)] 1097-5, FERF selected cell (selector) 1097-6, the software notice is read and is selected generation unit [decoding circuit (DEC)] 1097-7 and FERF software notice to read selected cell (selector) 1097-8.

FERF alarm bit holding unit 1097-1 is by the FERF alarm bit of the TU channel of 63 FF circuit 1097-1A maintenances 0 to 62ch.Alarm bit writes address control unit 1097-2, when the indication alarm bit writes timing signal (G1V5TPC8) regularly for " 1 ", the content (TUADC8) of output TU channel, and when above-mentioned timing signal (G1V5TPC8) is " 0 ", itself output signal is controlled to be 63 (" 111111 ").

Allow to write generation unit 1097-3, when the output signal that writes address control unit 1097-2 when alarm bit is 0 respective value in 62, produce the permission write signal that is used for any one FF circuit 1097-1A to 0 to 62ch respectively, the alarm signal (WFERFC8) of carrying out the FERF processing is write the FF circuit 1097-1A of the TU channel of having handled.When the output signal that writes address control unit 1097-2 when alarm bit is 63, because this is not the timing that writes alarm bit, so do not produce the permission write signal.

Alarm bit is read address control unit 1097-4, when the timing signal that is used to read alarm bit (G1V5TPC7) is " 1 ", the content (TUADC7) of the TU channel that output should be handled, and the output signal of itself is controlled to be 63 (" 111111 ") when " 0 " when above-mentioned timing signal (G1V5TPC8).

Read and select generation unit 1097-5, when the output signal of reading address control unit 1097-4 when alarm bit is 0 respective value in 62, to any channel in 0 to 62ch produce be used to read alarm bit read the selection signal.When the output signal of reading address control unit 1097-4 when alarm bit is 63,, do not read the selection signal so do not produce because this is not the timing of reading alarm bit.

FERF selected cell 1097-6, according to by read select that generation unit 1097-5 produces read the selection signal, read the alarm bit of the FERF of the TU channel that should handle.Software notice is read and is selected generation unit 1097-7 to produce to be used to select the alarm bit of any one TU channel of 0 to 62ch read the selection signal.The software notice is read selected cell 1097-8 according to the alarm bit of selecting signal to read FERF of reading of being read selection generation unit 1097-7 generation by the software notice, and with FERF alert notice software.

The alarm bit holding unit with said structure 1097 of present embodiment keeps to the public FERF alarm bit of TU channel and selectively with its output, thus with serial mode with FERF alert notice software.

As mentioned above, the POH terminal processes unit 1008 of present embodiment can be by the public G1/V5 byte terminal processes unit 1025 of all channels is carried out to the terminal processes of G1 byte and to the terminal processes of V5 byte with serial mode.This can reduce the scale and the power consumption of device to the utmost.

Specifically, G1/V5 byte terminal processes unit 1025 is by the terminal processes of the public FERF serial process unit 1095 of all channels being carried out should carry out FERF in to the POH terminal processes of each channel of having the unlike signal specification usually.Therefore, do not need to install the circuit that is used to carry out the FERF terminal processes that equates with the respective channels number.This can reduce the scale and the power consumption of device to the utmost.

Above-mentioned G1/V5 byte terminal processes unit 1025 (with reference to Figure 136), shown in Figure 143, can have G1FEBE serial detecting unit 1098A, V5FEBE serial detecting unit 1099A and 1099B, TU3 FEBEPM serial addition unit (the 1st FEBEPM serial addition unit) 1101A, TU2/TU12 FEBEPM serial addition unit (the 2nd FEBEPM serial addition unit) 1101B and 1101C, TU3 FEBEPM holding unit (the 1st memory cell) 1093A, TU2/TU12 FEBE holding unit (the 2nd memory cell) 1093B and 1093C and FEBE selected cell 1077A, carry out respectively to the FEBE of G1 byte and FEBEPM terminal processes and to the terminal processes of the FEBE and the FEBEPM of V5 byte with serial mode, and selectively each FEBEPM is outputed to software side.

Therefore, the G1/V5 byte terminal processes unit 1025 shown in Figure 143 can carry out terminal processes to FEBE and FEBEPM with serial mode with simple structure.If do not require the FEBEPM holding unit 1093A～1093C that specifically uses to all signal specifications public being used to keep FEBEPM, then said structure is extremely effective, helps to improve flexibility and versatility when constituting this device significantly.

Above-mentioned G1/V5 byte terminal processes unit 1025 (with reference to Figure 137), for example, shown in Figure 144, can have G1FERF serial detecting unit 1102A, V5FERF

serial detecting unit

1103A and 1103B, TU3 FERF serial detecting unit (the 1st FERF serial detecting unit) 1106A, TU2/TU12 FERF serial detecting unit (the 2nd FERF serial detecting unit) 1106B and 1106C, TU3 FERF holding unit (the 1st memory cell) 1096A, TU2/TU12 FERF holding unit (the 2nd memory cell) 1096B and 1096C and SLM data selection unit 1104A, carry out one by one to the terminal processes of the FERF of G1 byte and to the terminal processes of the FERF of V5 byte with serial mode, and selectively each FERF data is outputed to software side.

Therefore, the G1/V5 byte terminal processes unit 1025 shown in Figure 144 can carry out the FERF terminal processes with serial mode with simple structure.If do not require the FERF holding unit 1096A～1096C that specifically uses to all signal specifications public being used to keep the FERF data, then said structure is extremely effective, helps to improve flexibility and versatility when constituting this device significantly.

The POH terminal processes unit 1008 of present embodiment can carry out the POH terminal processes with serial mode, and the multiplex signal that sends need not be separated into signal on each channel in the SDH transmission system, thereby do not need to install the circuit that is used for the POH terminal processes that equates with the number of channel multiplexed in multiplex signal.This can reduce (circuit) scale and the power consumption of device to the utmost.

(b-11) other

Above-mentioned example is illustrated with an example, in this embodiment TU pointer processing unit 1006 and POH terminal processes unit 1008 is applied to line termination device 306, so as to constituting pointer/POH terminal processes device.But the present invention is not limited to this example.As another kind of scheme, also can only POH terminal processes unit be installed on line termination device 306, constitute the device that is specifically designed to the POH terminal processes.

Claims

1. pointer processing apparatus in the SDH transmission system, it comprises:

Address-generation unit is used for address assignment is given each channel of the multiplexed data of being imported;

The pointer extracting unit is used to extract the pointer byte that comprises H1/V1 byte and H2/V2 byte at least;

The pointer processing unit is used to carry out desired pointer and handles;

RAM, be used to keep each information sets of in the zone of the address indication that produces for each channel by above-mentioned address-generation unit, obtaining by above-mentioned pointer extracting unit or above-mentioned pointer processing unit, that is: the information sets of representing with the pointer byte of each channel of extracting from above-mentioned multiplexed data, by the pointer byte that receives make pointer action begin required information sets and begin as this pointer action after the information sets that obtains of result; And

The RAM control unit is used to control the order to the writing of above-mentioned RAM/read operation, handles thereby with serial mode above-mentioned multiplexed data is carried out pointer.

2. the pointer processing apparatus in the SDH transmission system according to claim 1, it is characterized in that: above-mentioned RAM is divided into 1RAM and 2RAM, wherein, above-mentioned 1RAM keeps the information sets by the indication of the H1/V1 byte in the above-mentioned reception pointer byte, and above-mentioned 2RAM keep by the information sets of the indication of the H2/V2 byte in the above-mentioned reception pointer byte, make above-mentioned pointer action begin required information sets and begin as this pointer action after the information sets that obtains of result.

3. the pointer processing apparatus in the SDH transmission system according to claim 1, it is characterized in that: above-mentioned pointer processing unit has the 1st pointer converting unit, be used to compress reception the H1/V1 byte figure place and its figure place is compressed after information remain in the above-mentioned RAM.

4. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing unit comprises:

The 1st pointer converting unit, be used to compress reception the H1/V1 byte figure place and its figure place has been compressed after information remain in the above-mentioned RAM; And

The 2nd pointer converting unit, information after its figure place that is used for producing according to above-mentioned multiplexed data, by above-mentioned the 1st pointer converting unit is compressed, by the information sets of the H2/V2 byte representation of above-mentioned reception pointer byte, make above-mentioned pointer action begin required information sets and begin as pointer action after result's information sets, produce pointer processing control signals and pointer result according to the timing of extracting the H2/V2 byte from above-mentioned multiplexed data, and these information sets are remained in the RAM4.

5. the pointer processing apparatus in the SDH transmission system according to claim 1, it is characterized in that: above-mentioned pointer processing apparatus extracts the information signal of the pointer value of each channel of indication from above-mentioned multiplexed data, and will remain in the above-mentioned RAM except that the low-order bit the MSB of above-mentioned information signal, above-mentioned pointer processing apparatus also has latch cicuit, position of MSB of the above-mentioned information signal that obtains when can be used for keeping signal specification when above-mentioned each channel of multiplexed data for TU3, and will be by the signal that obtains after the address value of distributing to above-mentioned each channel of TU3 the is deciphered control signal that writes and read with the above-mentioned latch cicuit of opposing.

6. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing apparatus comprises:

The consistency detection unit is used to detect the consistency between the reception pointer value of pointer value that receives and former frame and the consistency detection result is remained in the above-mentioned RAM as an information;

The pointer value converting unit that transfinites, when receiving the pointer byte of expression invalid information, be used for remain on pointer value in the above-mentioned RAM be converted to certain value that exceeds the pointer value scope and will change after information remain in the above-mentioned RAM; And

Normal 3 continuous consistent detecting units that receive of pointer value, by to the consistency detection result's that represents to keep in the above-mentioned RAM signal and the logic product computing that the consistency detection result between the pointer byte value of prior pointer value and reception carries out, detect 3 continuous consistent receptions of normal pointer value.

7. the pointer processing apparatus in the SDH transmission system according to claim 1, it is characterized in that: above-mentioned pointer processing unit has the LOP detecting unit, be used to detect the LOP state, above-mentioned LOP state detection unit has counting control unit, be used for allowing the NDF of reception, null pointer reception, former frame to allow the count value of reception information and former frame, the continuous reception number of times of NDF permission or the continuous reception number of times of null pointer counted according to a predetermined truth table according to NDF.

8. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing unit comprises:

The LOP detecting unit, be used to detect the LOP state, above-mentioned LOP detecting unit has counting control unit, be used for allowing the NDF of reception, null pointer reception, former frame to allow the count value of reception information and former frame, the continuous reception number of times of NDF permission or the continuous reception number of times of null pointer counted according to a predetermined truth table according to NDF; And

INC/DEC reception result recognition unit is used to discern the result that INC/DEC receives;

Above-mentioned INC/DEC reception result recognition unit has: the INC/DEC detecting unit is used for detecting INC or DEC from the reception pointer byte; And the filling control with n system counting unit suppresses the unit, is used for allowing and INC/DEC receives the back and receives by INC/DEC image duration at n and suppress to fill control at NDF, thereby prevents to receive the memory slip that causes continuously by INC/DEC; And above-mentioned pointer processing unit remains on the reception result of the count results of said n system counting unit and INC or DEC and is used to discern in the RAM of INC/DEC reception result, so that utilize the reception result that remains on the INC/DEC in the above-mentioned RAM, the count value of said n system counting unit and the result who receives by the NDF permission that above-mentioned LOP detecting unit obtains, the result that identification INC/DEC receives.

9. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing unit has alarm condition and shifts protected location;

This alarm condition shifts protected location and has: have the counting control unit of tally function, be used to carry out alarm condition as m level protective circuit and shift; And the RAM that is used to protect alarm condition to shift, store up the count value of this counting control unit at this memory ram; And; when receiving that alarm condition diverts the aim signal; above-mentioned pointer is handled processing unit and is counted with this counting control unit; if and do not receive the alarm condition signal that diverts the aim; then with the count resets of this counting control unit; when the count value of above-mentioned counting control unit reaches maximum; transfer to alarm condition; and before receiving warning elimination condition; the count value that will reach its peaked this counting control unit remains on and above-mentionedly is used to protect in the RAM that alarm condition shifts, and whether reaches maximum according to this count value with box lunch when the above-mentioned RAM that is used to protect alarm condition to shift reads above-mentioned count value and judges whether a relevant channel is in alarm condition.

10. the pointer processing apparatus in the SDH transmission system according to claim 1, it is characterized in that: above-mentioned pointer processing unit has the existing pointer value holding unit of using, and is used to keep the existing pointer value of using except that the reception pointer value of each channel that hardware in fact working;

The above-mentioned pointer value holding unit of now using will be used to keep existing with in the RAM of pointer value except that above-mentioned now remaining on the low-order bit the MSB of pointer value; It has latch cicuit, when the signal specification of above-mentioned each channel of multiplexed data is TU3, is used to latch position of MSB; And will write and read the control signal of usefulness with the above-mentioned latch cicuit of opposing by the signal that obtains after the address value of a channel distributing to TU3 is deciphered.

11. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing unit comprises:

Now use the pointer value holding unit, be used to keep the existing pointer value of using except that the reception pointer value of each channel that hardware in fact working; And

SPE lead byte recognition unit is used to discern j1 byte or V5 byte as the lead byte of above-mentioned SPE; Above-mentioned SPE lead byte recognition unit has skew counting unit, be used to retrieve the lead byte of above-mentioned SPE, and now read the existing pointer value of using with the pointer value holding unit from above-mentioned, so that by SPE being allowed signal and, discerning the position of the lead byte of SPE in skew count value and this logic product computing of now carrying out with the consistency detection result between the pointer value.

12. the pointer processing apparatus in the SDH transmission system according to claim 1, it also comprises: mapping set point registers group, and each channel of TU3/TU2/TU12 that is used for being set in above-mentioned multiplexed data with what kind of signal specification shines upon; And the signal specification is selected circuit, be used for selecting from above-mentioned mapping set point registers group the signal specification of a correlated channels according to the address of distributing to each channel by above-mentioned address-generation unit, select circuit to discern the signal specification of above-mentioned each channel of multiplexed data so that utilize above-mentioned mapping set point registers group and above-mentioned signal specification, wherein above-mentioned pointer terminal processes device is to above-mentioned pointer extracting unit, above-mentioned pointer processing unit and above-mentioned RAM control unit provide and the relevant information of above-mentioned signal specification, thereby carry out pointer extraction and pointer processing by a public circuit according to the signal specification.

13. the pointer processing apparatus in the SDH transmission system according to claim 12, it also comprises: 3 TU3/TUG3 set point registers and each above-mentioned TU3/TUG3 set point register established 21 TU2/TUG2 set points of total register of 7 TU2/TUG2 set point registers, as above-mentioned mapping set point registers group; And signal specification recognition unit, be used to judge whether a correlated channels is to be shone upon with above-mentioned TU3 by above-mentioned TU3/TUG3 set point register, and when this channel be not during with above-mentioned TU3 mapping, judge whether this channel is to be shone upon with above-mentioned TU2 or above-mentioned TU12 by above-mentioned TU2/TUG2 set point register, thus the signal specification of identification channel.

14. the pointer processing apparatus in the SDH transmission system according to claim 1 is characterized in that: above-mentioned pointer processing unit comprises:

Now use the pointer value holding unit, be used to keep the existing pointer value of using except that the reception pointer value of each channel that hardware in fact working;

SPE lead byte recognition unit with skew counting unit, be used to retrieve the lead byte of SPE, above-mentioned SPE lead byte recognition unit is now read the existing pointer value of using with the pointer value holding unit from above-mentioned, in order to by SPE being allowed signal and discerning the position of the lead byte of SPE in skew count value and this logic product computing of now carrying out with the consistency detection result between the pointer value;

Mapping set point registers group, each channel of TU3/TU2/TU12 that is used for being set in above-mentioned multiplexed data with what kind of signal specification shines upon; And

Signal specification selected cell, be used for selecting from above-mentioned mapping set point registers group the signal specification of a correlated channels according to the address of distributing to each channel by above-mentioned address-generation unit, so that utilize above-mentioned mapping set point registers group and signal specification to select circuit to discern the signal specification of above-mentioned each channel of multiplexed data, and utilize the information that provides to above-mentioned pointer extracting unit, above-mentioned pointer processing unit and above-mentioned RAM control unit to carry out pointer extraction and pointer processing according to the signal specification by a public circuit;

Wherein above-mentioned pointer terminal processes device has the offset counter that is used for each signal specification, selects the count value of above-mentioned offset counter according to the mapping set information of supplying with from above-mentioned mapping set point registers group, so that discern the lead byte position of above-mentioned SPE.

15. the pointer processing apparatus in the SDH transmission system according to claim 11, it is characterized in that: above-mentioned pointer processing unit has the RAM with ES memory function that is used to switch pointer, the information bit of the lead byte of SPE data that will obtain from the multiplexed data of being imported and indication SPE writes the above-mentioned RAM that is used to switch pointer, and read, so that the value identification SPE leading position of the information bit of the SPE lead byte of reading from indication by the data that the timing of reading side will write above-mentioned RAM in order to switch pointer.

16. the pointer processing apparatus in the SDH transmission system according to claim 15, it also comprises: the Writing/Reading counter, be used to control the RAM that above-mentioned switching pointer is used with above-mentioned ES memory function, above-mentioned Writing/Reading counter has TU3 decoding circuit and TU2 decoding circuit, respectively the count value of TU3 and the count value of TU2 are deciphered, purpose is a switch count value between the setting constantly of the setting moment of TU3 mapping and TU2 mapping;

This pointer terminal processes device is characterised in that: above-mentioned pointer processing apparatus is selected the output of above-mentioned decoding circuit according to the signal specification, used as the signal of packing into of above-mentioned counter, thus with the Writing/Reading counter of the above-mentioned RAM that is used to switch the above-mentioned ES memory function of having of pointer when TU3 mapping and the TU2 mapping as a public counter use.

17. the pointer processing apparatus in the SDH transmission system according to claim 15, it also comprises: the Writing/Reading counter is used to control the RAM with above-mentioned ES memory function that above-mentioned switching pointer is used; And above-mentioned read/write counter have TU3 with decoding circuit, TU2 with decoding circuit and TU12 decoding circuit, respectively the count value of TU3, the count value of TU2 and the count value of TU12 are deciphered, purpose is a switch count value between the setting moment of the setting moment of the setting moment that TU3 shines upon, TU2 mapping and TU12 mapping

This pointer terminal processes device is characterised in that: above-mentioned pointer processing apparatus is selected the output signal of above-mentioned each decoding circuit according to the signal specification, used as the signal of packing into of above-mentioned counter, thereby the Writing/Reading counter of above-mentioned RAM with above-mentioned ES memory function is used as a public counter when TU3, TU2 and the TU12 mapping.

18. the pointer processing apparatus in the SDH transmission system, it comprises:

AU4 pointer processing unit is used for the AU4 pointer is handled; And

TU pointer processing unit is used for after by above-mentioned AU4 pointer processing unit processes the TU pointer being handled;

Above-mentioned AU4 pointer processing unit comprises: AU4 pointer detecting unit, be used to change the AU4 pointer, and allow the signal of the j1 byte position of signal and indication VC4POH according to the clock generating VC4 of transmission line trackside, and be used to transmit the ES memory of clock, above-mentioned AU4 pointer processing unit is used to control an ES who is written to above-mentioned ES memory according to the clock operation of above-mentioned transmission line trackside and writes counter, according to the clock of device side, operation is used to control the ES read-out counter of reading simultaneously;

This pointer terminal processes device is characterised in that: above-mentioned pointer processing apparatus is filled control by detection at the phase difference that above-mentioned ES writes count value between counter and the above-mentioned read-out counter, so that signal is transferred to the clock of device side from the clock of transmission line trackside, and according to the clock of said apparatus side, the signal that its clock has been shifted at above-mentioned TU pointer processing unit carries out the TU pointer to be handled.

19. the pointer processing apparatus in the SDH transmission system according to claim 18, it is characterized in that: above-mentioned AU4 pointer processing unit has AU4 pointer calculating/insertion unit, be used for calculating the AU4 pointer and inserting this AU4 pointer, and will supply with above-mentioned TU pointer processing unit by the data behind the above-mentioned AU4 pointer calculating/insertion unit insertion AU4 pointer according to transmit frame signals.

20. the pointer processing apparatus in the SDH transmission system according to claim 19, it also comprises the selection circuit, be used for according to setting model selection, and send this selected signal by more the correct one's mistakes signal of AU4 pointer or of above-mentioned AU4 pointer processing unit by the above-mentioned TU pointer processing unit signal of TU pointer of more correcting one's mistakes.

21. the pointer processing apparatus in the SDH transmission system according to claim 18 is characterized in that: above-mentioned TU pointer processing unit has:

Address-generation unit is used for each channel allocation address to multiplexed data;

The pointer processing unit is used to carry out desired pointer and handles;

RAM, be used to keep each information sets of in the zone of the address indication that each channel is produced by above-mentioned address-generation unit, obtaining by above-mentioned pointer extracting unit or above-mentioned pointer processing unit, that is: the information sets of representing with the pointer byte of each channel of extracting from above-mentioned multiplexed data, by the pointer byte that receives make pointer action begin required information sets and begin as this pointer action after the information sets that obtains of result; And

The RAM control unit is used to control the order to the writing of above-mentioned RAM/read operation.

22. the POH terminal processes device in the SDH transmission system is used for its information multiplexed multiplex signal on a plurality of channels that sends in the SDH transmission system is carried out the POH terminal processes, this device comprises:

The POH terminal operation processing unit public to all channels is used for that this multiplex signal is carried out the POH terminal operation and handles; And

The memory cell that can read and write flexibly is used to store the operating result that each channel is carried out by above-mentioned POH terminal operation processing unit;

Above-mentioned POH terminal processes device, when above-mentioned multiplex signal being carried out the processing of POH terminal operation, carrying out the POH terminal operation by above-mentioned POH terminal operation processing unit use in the stored information relevant with respective channels of said memory cells stored handles, and the above-mentioned POH terminal operation result that will obtain is stored in the respective channels memory block of said memory cells, just can carry out the POH terminal operation to above-mentioned multiplex signal and handles thereby above-mentioned multiplex signal need not be separated to each channel.

23. the POH terminal processes device in the SDH transmission system according to claim 22, it also comprises latch units, is used for temporary transient POH byte data of storing stored information relevant with respective channels of reading from said memory cells and the above-mentioned multiplex signal that should handle when being carried out the processing of POH terminal operation by above-mentioned POH terminal operation processing unit.

24. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to J1/J2 byte serial terminal processes unit, be used for the j1 byte and the J2 byte that are included in the above-mentioned multiplex signal being carried out terminal processes with serial mode, and

The said memory cells storage is supplied with institute's canned data above-mentioned J1/J2 byte serial terminal processes unit in addition by the operating result that above-mentioned J1/J2 byte serial terminal processes unit carries out each channel.

25. the POH terminal processes device in the SDH transmission system according to claim 24 is characterized in that: above-mentioned J1/J2 byte serial terminal processes unit comprises:

Multi-frame pattern serial detecting unit is used for detecting with serial mode the multi-frame pattern of above-mentioned j1 byte and J2 byte;

Multi-frame pattern count Serial Control unit is used for controlling with serial mode the multi-frame number of above-mentioned j1 byte and J2 byte;

LOM serial detecting unit is used for detecting with serial mode the LOM of above-mentioned j1 byte and J2 byte;

CRC serial detecting unit is used for detecting with serial mode the CRC of above-mentioned j1 byte and J2 byte; And

TIM serial detecting unit is used for detecting with serial mode the TIM of above-mentioned j1 byte and J2 byte;

Wherein the said memory cells storage is supplied with institute's canned data above-mentioned multi-frame pattern serial detecting unit, above-mentioned multi-frame pattern count Serial Control unit, above-mentioned LOM serial detecting unit, above-mentioned CRC serial detecting unit and above-mentioned TIM serial detecting unit in addition by the operating result that above-mentioned multi-frame pattern serial detecting unit, above-mentioned multi-frame pattern count Serial Control unit, above-mentioned LOM serial detecting unit, above-mentioned CRC serial detecting unit and above-mentioned TIM serial detecting unit carry out each channel.

26. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to B3/V5 byte serial terminal processes unit, be used for carrying out to the terminal processes of the BIP that is included in B3 byte in the above-mentioned multiplex signal and V5 byte and to the terminal processes of the BIPPM of above-mentioned B3 byte and V5 byte with serial mode, and

The said memory cells storage is supplied with institute's canned data above-mentioned B3/V5 byte serial terminal processes unit in addition by the operating result that above-mentioned B3/V5 byte serial terminal processes unit carries out each channel.

27. the POH terminal processes device in the SDH transmission system according to claim 26 is characterized in that: above-mentioned B3/V5 byte serial terminal processes unit comprises:

BIP operation serial process unit is used for serial mode above-mentioned multiplex signal being carried out the BIP8 operation;

BIP2 operation serial process unit is used for serial mode above-mentioned multiplex signal being carried out the BIP2 operation;

BIP error selected cell is used to select from above-mentioned BIP8 operation serial process unit or the BIP error signal of BIP2 operation serial process unit output; And

BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being selected by above-mentioned BIP error selected cell; And

Wherein the said memory cells storage is supplied with institute's canned data above-mentioned BIPPM serial addition unit in addition by the operating result that above-mentioned BIPPM serial addition unit carries out each channel.

28. the POH terminal processes device in the SDH transmission system according to claim 26 is characterized in that: above-mentioned B3/V5 byte serial terminal processes unit comprises:

BIP8 operation serial process unit is used for serial mode above-mentioned multiplex signal being carried out the BIP8 operation;

The 1st BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being supplied with by above-mentioned BIP8 operation serial process unit;

BIP2 operation serial process unit is used for serial mode above-mentioned multiplex signal being carried out the BIP2 operation; And

The 2nd BIPPM serial addition unit is used for serial mode BIPPM being carried out add operation according to the BIP error signal of being supplied with by above-mentioned BIP2 operation serial process unit; And

The BIPPM selected cell is used to select from above-mentioned the 1st BIPPM operation serial addition unit or the BIPPM of 2BIPPM adder unit output; And

Wherein said memory cells has: the 1st memory cell, be used to store the operating result that is undertaken by above-mentioned the 1st BIPPM serial addition unit, and provide stored information to above-mentioned the 1st BIPPM serial addition unit in addition; And the 2nd memory cell, be used to store the operating result that is undertaken by above-mentioned the 2nd BIPPM serial addition unit, in addition institute's canned data is supplied with above-mentioned the 2nd BIPPM serial addition unit.

29. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to UNEQ serial terminal processing unit, is used for carrying out terminal processes to being included in the C2 byte in the above-mentioned multiplex signal and the UNEQ of V5 byte with serial mode; And

Wherein the said memory cells storage is supplied with institute's canned data above-mentioned UNEQ serial terminal processing unit in addition by the operating result that above-mentioned UNEQ serial terminal processing unit carries out each channel.

30. the POH terminal processes device in the SDH transmission system according to claim 29 is characterized in that: above-mentioned UNEQ serial terminal processing unit comprises:

C2UNEQ indication serial detecting unit is used for detecting above-mentioned C2 byte with serial mode and whether indicates UNEQ;

V5UNEQ indication serial detecting unit is used for detecting above-mentioned V5 byte with serial mode and whether indicates UNEQ;

UNEQ indicates selected cell, is used to select the UNEQ by above-mentioned C2UNEQ indication serial detecting unit or the output of above-mentioned V5UNEQ indication serial detecting unit to indicate detection signal; And

UNEQ serial detecting unit is used for according to the UNEQ of the UNEQ indication detection signal of being selected by above-mentioned UNEQ indication selected cell with serial mode indication C2 byte and V5 byte; And

Wherein the said memory cells storage is supplied with institute's canned data this UNEQ serial detecting unit in addition by the operating result that above-mentioned UNEQ serial detecting unit carries out each channel.

31. the POH terminal processes device in the SDH transmission system according to claim 29 is characterized in that: above-mentioned UNEQ serial terminal processing unit comprises:

UNEQ indicates selected cell, is used to select the UNEQ by above-mentioned the 1st UNEQ serial detecting unit or the output of above-mentioned 2UNEQ serial detecting unit to indicate detection signal; And

Wherein said memory cells has: the 1st memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 1st UNEQ serial detecting unit, and in addition institute's canned data is supplied with above-mentioned 1UNEQ serial detecting unit; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 2nd UNEQ serial detecting unit, in addition institute's canned data is supplied with above-mentioned the 2nd UNEQ serial detecting unit.

32. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to SLM serial terminal processing unit, is used for carrying out terminal processes to being included in the C2 byte in the above-mentioned multiplex signal and the SLM of V5 byte with serial mode; And

The said memory cells storage is supplied with institute's canned data above-mentioned SLM serial terminal processing unit in addition by the operating result that above-mentioned SLM serial terminal processing unit carries out each channel.

33. the POH terminal processes device in the SDH transmission system according to claim 32 is characterized in that: above-mentioned SLM serial terminal processing unit comprises:

C2 mismatch serial detecting unit is used for detecting the mismatch that detects in above-mentioned C2 byte with serial mode;

V5 mismatch serial detecting unit is used for detecting the mismatch that detects in above-mentioned V5 byte with serial mode;

The detection of mismatch selected cell is used to select the detection of mismatch signal by above-mentioned C2 mismatch serial detecting unit or the output of above-mentioned V5 mismatch serial detecting unit; And

SLM serial detecting unit is used for indicating the SLM of above-mentioned C2 byte and V5 byte with serial mode according to the detection of mismatch signal of being selected by above-mentioned detection of mismatch selected cell; And,

The said memory cells storage is supplied with institute's canned data this SLMQ serial detecting unit in addition by the testing result that above-mentioned SLM serial detecting unit carries out each channel.

34. the POH terminal processes device in the SDH transmission system according to claim 32 is characterized in that: above-mentioned SLM serial terminal processing unit comprises:

The 1st SLM serial detecting unit is used for basis is detected above-mentioned C2 byte with serial mode by the detection of mismatch signal of above-mentioned C2 mismatch serial detecting unit supply SLM;

The 2nd SLM serial detecting unit is used for basis is detected above-mentioned V5 byte with serial mode by the detection of mismatch signal of above-mentioned V5 mismatch serial detecting unit supply SLM; And

The SLM selected cell is used to select the SLM by above-mentioned the 1st SLM serial detecting unit or the output of above-mentioned the 2nd SLM serial detecting unit; And,

Said memory cells has: the 1st memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 1st SLM serial detecting unit, and in addition institute's canned data is supplied with to above-mentioned the 1st SLM serial detecting unit; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 2nd SLM serial detecting unit, in addition institute's canned data is supplied with above-mentioned the 2nd SLM serial detecting unit.

35. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to FEBE serial terminal processing unit, is used for carrying out to the terminal processes of the FEBE that is included in G1 byte in the above-mentioned multiplex signal and V5 byte and to the terminal processes of the FEBEPM of above-mentioned G1 byte and V5 byte with serial mode; And,

The said memory cells storage is supplied with institute's canned data above-mentioned FEBE serial terminal processing unit in addition by the operating result that above-mentioned FEBE serial terminal processing unit carries out each channel.

36. the POH terminal processes device in the SDH transmission system according to claim 35 is characterized in that: above-mentioned FEBE serial terminal processing unit comprises:

G1FEBE serial detecting unit is used for detecting with serial mode the FEBE of above-mentioned G1 byte;

V5FEBE serial detecting unit is used for detecting with serial mode the FEBE of above-mentioned V5 byte;

The FEBE selected cell is used to select the FEBE detection signal by above-mentioned G1FEBE serial detecting unit or the output of above-mentioned V5FEBE serial detecting unit; And

FEBEPM serial addition unit is used for serial mode FEBEPM being carried out add operation according to the FEBE detection signal of being selected by above-mentioned FEBE selected cell; And,

The said memory cells storage is supplied with institute's canned data above-mentioned FEBEPM serial addition unit in addition by the operating result that above-mentioned FEBEPM serial addition unit carries out each channel.

37. the POH terminal processes device in the SDH transmission system according to claim 35 is characterized in that: above-mentioned FEBE serial terminal processing unit comprises:

The FEBEPM selected cell is used to select the FEBEPM by above-mentioned the 1st FEBEPM serial addition unit or the output of above-mentioned 2FEBEPM serial addition unit; And,

The said memory cells storage is supplied with institute's canned data above-mentioned FEBEPM serial addition unit in addition by the result that FEBEPM serial addition unit carries out addition to each channel.

38. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: above-mentioned POH terminal operation processing unit is configured to FERF serial terminal processing unit, is used for carrying out terminal processes the FERF that is included in G1 byte in the above-mentioned multiplex signal and V5 byte with serial mode; And,

The said memory cells storage is supplied with institute's canned data above-mentioned FERF serial terminal processing unit in addition by the operating result that above-mentioned FERF serial terminal processing unit carries out each channel.

39. according to the described POH terminal processes device in the SDH transmission system of claim 38, it is characterized in that: above-mentioned FERF serial terminal processing unit comprises:

G1FERF indicates the serial detecting unit, is used for detecting with serial mode the G1 byte of above-mentioned indication FERF;

V5FERF indicates the serial detecting unit, is used for detecting with serial mode the V5 byte of above-mentioned indication FERF;

The FERF indication detects selected cell, is used to select to be indicated by above-mentioned G1FERF indication serial detecting unit or above-mentioned V5FERF the FERF indication detection signal of serial detecting unit output; And

FERF serial detecting unit is used for indicating detection signal to detect the FERF of G1 byte and V5 byte with serial mode according to the FERF that detects the selected cell selection by above-mentioned FERF indication; And,

The said memory cells storage is supplied with institute's canned data this FERF serial detecting unit in addition by the testing result that above-mentioned FERF serial detecting unit carries out each channel.

40. according to the described POH terminal processes device in the SDH transmission system of claim 38, it is characterized in that: above-mentioned FERF serial terminal processing unit comprises:

The 1st FERF serial detecting unit is used for indicating detection signal to detect the FERF of above-mentioned G1 byte with serial mode according to the FERF that is supplied with by above-mentioned G1FERF indication serial detecting unit;

V5FERF indication serial detecting unit is used for detecting the above-mentioned V5 byte of indicating FERF with serial mode;

The 2nd FERF serial detecting unit is used for indicating detection signal to detect the FERF of above-mentioned V5 byte with serial mode according to the FERF that is supplied with by above-mentioned V5FERF indication serial detecting unit; And

FERF indicates selected cell, is used to select the FEFERF by above-mentioned the 1st FERF serial detecting unit or the output of above-mentioned the 2nd FERF serial detecting unit to indicate; And,

Said memory cells has: the 1st memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 1st FERF serial detecting unit, and in addition institute's canned data is supplied with above-mentioned 1FERF serial detecting unit; And the 2nd memory cell, be used to store the testing result of each channel being carried out by above-mentioned the 2nd FERF serial detecting unit, in addition institute's canned data is supplied with above-mentioned 2FERF serial detecting unit.

41. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: it also comprises POH timing signal serial generation unit, is used for being created in the POH timing signal that uses when handling in the above-mentioned POH terminal operation processing unit with serial mode according to the timing signal of j1 byte of indicating above-mentioned multiplex signal and V5 byte location and the type information of above-mentioned multiplex signal.

42. according to the described POH terminal processes device in the SDH transmission system of claim 41, it is characterized in that: above-mentioned POH timing signal serial generation unit comprises:

The count value initialization unit, the timing signal by receiving above-mentioned j1 byte in the above-mentioned multiplex signal of indication and V5 byte location is with the initialization of SPE count value;

Count value addition control unit is used for according to by above-mentioned count value initialization unit signal supplied above-mentioned SPE count value being carried out addition control;

The memory cell that can read and write flexibly is used to keep the SPE by above-mentioned count value addition control unit is tried to achieve each channel to count additive value, will supply with this count value initialization unit to the maintenance data of each channel in addition; And

POH timing signal for generating unit is used for the POH timing signal that uses when being created in above-mentioned POH terminal operation processing unit by the type information of above-mentioned count value initialization unit signal supplied and above-mentioned multiplex signal and handling.

43. the POH terminal processes device in the SDH transmission system according to claim 22, it is characterized in that: it also comprises address-generation unit, produces the address information of each channel be used to differentiate above-mentioned multiplex signal.

44. the POH terminal processes device in the SDH transmission system according to claim 22 is characterized in that above-mentioned POH terminal operation processing unit comprises:

J1/J2 byte serial terminal processes unit is used for serial mode the j1 byte and the J2 byte that are included in this multiplex signal being carried out terminal processes;

B3/V5 byte serial terminal processes unit is used for carrying out to the terminal processes of the BIP that is included in B1 byte in the above-mentioned multiplex signal and V5 byte and to the terminal processes of the BIPPM of above-mentioned B1 byte and V5 byte with serial mode;

UNEQ/SLM serial terminal processing unit is used for carrying out terminal processes to the UNEQ that is included in C2 byte in this multiplex signal and V5 byte with serial mode, and carries out terminal processes to the SLM of above-mentioned C2 byte and V5 byte with serial mode; And

FEBE/FERF serial terminal processing unit, be used for carrying out terminal processes to being included in the G1 byte in this multiplex signal and the FEBE of V5 byte with serial mode, and the FEBEPM of above-mentioned G1 byte and V5 byte carrying out terminal processes with serial mode, the FERF to G1 byte and V5 byte carries out terminal processes in addition; And,

The operating result that the said memory cells storage is carried out each channel by above-mentioned J1/J2 byte serial terminal processes unit, above-mentioned B3/V5 byte serial terminal processes unit, above-mentioned UNEQ/SLM serial terminal processing unit and above-mentioned FEBE/FERF serial terminal processing unit, in addition, also institute's canned data is supplied with above-mentioned J1/J2 byte serial terminal processes unit, above-mentioned B3/V5 byte serial terminal processes unit, above-mentioned UNEQ/SLM serial terminal processing unit and above-mentioned FEBE/FERF serial terminal processing unit.