JPH1032469A - Sawtooth wave generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set output voltage to be constant and to always maintain change width to be constant even if deflection frequency changes by changing rise voltage per sample pulse in accordance with the period of a sawtooth wave signal. SOLUTION: Constant voltage is supplied to the input terminal 13 of a sample/hold circuit 1 from a constant voltage input circuit 3 and the sample pulse SP is supplied to a logic input terminal 15. When it comes to a sample period, the holding capacitor 20 of an integrated circuit for sample/hold 6 is charged by input voltage. When it becomes a holding period, SP is phase-inverted by an invertor 31, output voltage is supplied to an integrated circuit for operation circuit 23 and the voltage of an output terminal 26 rises. When a switching element 21 is turned on by a reset pulse RP from outside, the charge of the capacitor 20 is discharged and the voltage of the integrated circuit 23 becomes zero. Thus, the sawtooth wave signal of a prescribed period is outputted whenever RP is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sawtooth wave generating circuit used in a television receiver, a CRT monitor and the like.

[0002]

2. Description of the Related Art For example, television receivers and CRTs
In the monitor, a sawtooth deflection signal is used to change the electron beam of the cathode ray tube. Conventionally, as a sawtooth wave generation circuit for generating a sawtooth wave signal, a configuration using a charge and discharge circuit of a resistor and a capacitor, a configuration using a variable constant voltage source to charge a capacitor at a constant voltage, and a configuration using a Miller integration circuit Etc. are known.

In these conventional sawtooth wave generating circuits, the level of the sawtooth wave signal increases with the passage of time and is reset to 0 in synchronization with the synchronization signal. Therefore,
The sawtooth signal is determined by the deflection frequency. The circuit constants are set so that a sawtooth signal having a predetermined amplitude is obtained at the used deflection frequency.
However, even if the circuit constant is set so that a predetermined amplitude is obtained at a certain frequency, if the frequency changes, the amplitude of the sawtooth signal changes.

On the other hand, the deflection frequency used in a television receiver or a CRT monitor varies widely, and in the case of a television receiver, the deflection frequency differs depending on the television system.
In the case of a monitor, the deflection frequency is switched according to the resolution of the display screen.

When the deflection frequency changes in this way, it is necessary to adjust circuit constants at each frequency or to replace parts in order to obtain a sawtooth signal having a constant amplitude at any deflection frequency. And it is necessary to provide a plurality of sawtooth-wave generating circuits corresponding to each frequency to selectively operate the circuits, which is very inconvenient.

In a deflection circuit using an oscillation circuit in which an oscillation cycle is determined based on a time constant determined from a capacitance of a capacitor and a resistance value of a resistor, the capacitance of the capacitor must be accurately defined. There was a problem that was difficult.

On the other hand, digital amplitude data representing the waveform of a deflection signal to be output is recorded in a memory such as a ROM, and the amplitude data in the memory is read out and D / A converted to obtain a deflection signal having a desired waveform. It has been proposed to obtain In this digital deflection signal generating circuit, an address counter is generally driven by a clock pulse, an output of the address counter is supplied as an address signal of a memory, and the contents of the memory are read.

When changing the frequency of the deflection signal in the digital deflection signal generating circuit, the address interval is changed according to the deflection frequency. However, when the deflection frequency is controlled by changing the address interval in this way, the linearity of the output deflection signal waveform may be impaired. Hereinafter, the reason will be described.

In a digital deflection signal generating circuit, data representing an output voltage is discretely stored in an address memory as shown in FIG. Now
Assuming that the memory is accessed at the address interval indicated by reference numeral A1, the value of the data read from the memory increases at a constant width as indicated by reference numeral D1. Therefore, the slope of the sawtooth wave obtained by D / A conversion of the data read from the memory becomes one straight line as shown by the dotted line. On the other hand, in order to increase the deflection frequency, the symbol A
As shown by 2, when the address interval is extended,
The increment of the value of the data read from the memory becomes non-uniform for each access. For this reason, the slope of the sawtooth wave obtained by D / A converting the data read from the memory becomes a bent line as shown by a broken line. Note that the symbol A
1. The time intervals for accessing the memories A2 are the same. Since the rate of change of the output voltage corresponds to the scanning speed of the bright spot on the display screen, the scanning speed of the portion where the slope of the sawtooth wave is gentle is slow, and the scanning speed of the portion where the slope is sharp is fast. Become. For this reason, there is a problem that a portion where the scanning speed is low becomes bright, and a portion where the scanning speed is high becomes dark, thereby causing a shading of the image.

[0010]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a sawtooth wave generating circuit which can maintain the amplitude of a sawtooth signal constant even when the deflection frequency changes, and which is excellent in linearity. The task is to provide.

[0011]

SUMMARY OF THE INVENTION A saw-tooth wave generating circuit according to the present invention samples a constant input voltage for each pulse of a sample pulse having a period sufficiently short with respect to the period of a saw-tooth wave signal to be output. A sample / hold circuit for charging a capacitor based on a voltage obtained by adding the constant input voltage and the previously sampled voltage to hold an output voltage, and a reset pulse synchronized with a period of a sawtooth signal to be output. A reset circuit for discharging the charge of the capacitor of the / hold circuit; and a control circuit for changing the constant voltage value in accordance with the period of the sawtooth signal to be output.

Further, the present invention is characterized in that the sampling pulse is a signal synchronized with a horizontal deflection signal, and the reset pulse is a signal synchronized with a vertical deflection signal.

[0013]

FIG. 1 is a circuit diagram showing an embodiment of a saw-tooth wave generating circuit according to the present invention.

A sample / hold circuit 1 and an operational amplifier circuit 2 having a high input impedance are connected in cascade, and the sample / hold circuit 1 is connected to a variable constant voltage source 4 of a constant voltage input circuit 3 via a resistor 5. Input signal is supplied. The output voltage of the variable constant voltage source 4 can be switched according to the television system, as described later.

The sample / hold circuit 1 includes a sample / hold integrated circuit 6 such as LF198 manufactured by National Semiconductor. FIG.
FIG. 2 is a circuit diagram showing an internal configuration of the sample / hold integrated circuit 6, which includes a pre-stage operational amplifier 7a, a limiter 8, a switching element 9, a post-stage operational amplifier 7b, a comparator 10, resistors 11, 12 and the like. An input terminal 13 and an offset terminal 14 are derived from the first-stage operational amplifier 7a, a logical input terminal 15 and a logical reference terminal 16 are derived from the comparator 10, and an output terminal 17 is derived from the output side of the second-stage operational amplifier 7b. A hold capacitor terminal 18 is led out through the resistor 12 from the side. In the circuit shown in FIG. 1, the offset terminal 14 is not used.

The input terminal 13 of the sample / hold integrated circuit 6 is connected to the constant voltage input circuit 3 and to the output terminal 17 via a resistor 19, the logic reference terminal 16 is grounded, and the hold capacitor A hold capacitor 20 is connected between the terminal 18 and the ground. A switching element 21 that is turned on by a reset pulse is connected in parallel with the resistor 19.

An output terminal 17 of the sample / hold integrated circuit 6 is connected to an arithmetic circuit integrated circuit 23 through a resistor 22.
, The negative input terminal 24 is connected to an output terminal 26 via a resistor 25, the positive input terminal 27 is grounded, and the output terminal 2
6 is connected to the input terminal 13 of the sample / hold integrated circuit 6 via a resistor 28. Further, an enable terminal 29 is derived from the arithmetic circuit integrated circuit 23.

A sample pulse supply terminal 30, to which a sample pulse having a period sufficiently shorter than the period of the sawtooth signal to be output, is supplied, is directly connected to the logic input terminal 15 of the sample / hold integrated circuit 6. At the same time, it is connected to the enable terminal 29 of the arithmetic circuit integrated circuit 23 via the inverter 31.

Next, the operation of the sawtooth wave generating circuit will be described.

Input terminal 13 of sample / hold circuit 1
3A, a constant voltage input signal as shown in FIG. 3A is supplied from the constant voltage input circuit 3, and an output as shown in FIG. A sample pulse SP having a period sufficiently shorter than the period of the power sawtooth signal is supplied. The sample pulse SP is
It consists of a sample period t1 and a hold period t2. In the sample period t1 of the sample pulse SP, the switching element 9 of the sample / hold integrated circuit 6 is turned on, and as shown in FIG. 3C, the hold capacitor 20 connected to the hold capacitor terminal 18 changes the input voltage e. Charged to ₁ .

Next, when the sample pulse SP reaches the hold period t2, the switching element 9 of the sample / hold integrated circuit 6 is turned off, and the voltage of the capacitor 20 is maintained. Since the phase of the sample pulse SP is inverted by the inverter 31 and supplied to the enable terminal 29 of the arithmetic circuit integrated circuit 23, during the hold period t2 of the sample pulse SP, the arithmetic circuit integrated circuit 2
3 is enabled, the output voltage of the sample / hold integrated circuit 6 is supplied to the arithmetic circuit integrated circuit 23, and the output voltage of the output terminal 26 of the arithmetic circuit integrated circuit 23 is e ₂
Becomes

Next, the sample pulse SP is the sample period t1 again, Similarly, the input voltage e ₁ from the constant voltage input circuit 3 is supplied to an input terminal 13 of the sample / hold integrated circuit 6. At this time, the output voltage e _{2 of} the arithmetic circuit integrated circuit 23 is also supplied to the input terminal 13 via the resistor 28. Therefore, the voltage of the input terminal 13 when the second sample pulse SP is supplied becomes e ₁ + e ₂ .
Here, assuming that the resistance of the resistor 19 is R ₂ , the resistance of the resistor 22 is R ₃ , the resistance of the resistor 25 is R ₄ , and the resistance of the resistor 28 is R _5. , R ₂ = R ₃ = R ₄
= With R _5, is set the sample / hold circuit 1 and the gain of the operational amplifier 2, respectively 1. As a result, e ₁ = e ₂ , and the second sample pulse S
When P is supplied the output of the sample / hold integrated circuit 6 becomes 2e _1.

Similarly, the input signal and the sample pulse S
Each time P is supplied, the sample / hold integrated circuit 6
The output voltage rises by e _1, arithmetic circuit for an integrated circuit 23
Be delayed a half cycle increases one by e ₁ of the output voltage.

Here, the maximum value or amplitude of the intended sawtooth wave is E, the repetition period of the sawtooth wave is T,
Assuming that the period of the sample pulse SP is t and the input voltage is e ₁ , the number n of samples is represented by n = T / t (1), and the output voltage E is E = e ₁ · n = e ₁ · (T / t) (2)

The number of sample pulses SP corresponding to the period T
Is supplied, the reset pulse RP is supplied to the switching element 21 from the outside, and the switching element 21 is turned on. As a result, the gain of the sample / hold integrated circuit 6 becomes 0, and the charge stored in the capacitor 20 is rapidly discharged through the output impedance of the sample / hold integrated circuit 6, and the arithmetic circuit integrated circuit The output voltage of 23 also becomes 0.

By repeating the above operation, a saw-tooth wave having a period T and a maximum output voltage E as shown in FIG. 4 can be generated. At this time, the sample pulse SP
Is sufficiently short with respect to the period of the sawtooth wave signal to be output, so that the slope portion of the sawtooth wave has a sufficiently smooth waveform.

FIG. 5 is a circuit diagram showing an example in which the above sawtooth wave generating circuit is applied to a deflection circuit of a television receiver compatible with multiple systems. Here, a television receiver capable of reproducing both an NTSC video signal and a PAL video signal will be described as an example.

A video signal of the NTSC system or the PAL system is supplied to a sync separation circuit 32, where a vertical sync signal V and a horizontal sync signal H included in the video signal are separated. The vertical synchronizing signal V and the horizontal synchronizing signal H
3 and the reset pulse generation circuit 34 generates a reset pulse in synchronization with the vertical synchronization signal V.
The sample pulse generation circuit 35 generates a sample pulse in synchronization with the horizontal synchronization signal H. Further, the vertical synchronizing signal V and the horizontal synchronizing signal H are supplied to a system determining circuit 36 to determine the television system. In addition, NTSC
In the PAL system, the vertical deflection frequency is 60 Hz and the horizontal deflection frequency is 15.75 kHz. In the PAL system, the vertical deflection frequency is 50 Hz and the horizontal deflection frequency is 15.625 kHz. By detecting, the system of the supplied video signal can be determined.

The sample pulse and the reset pulse are supplied to a sawtooth wave generating circuit 38 having a circuit configuration as shown in FIG. The output of the type discriminating circuit 36 is supplied to a voltage control circuit 37, and the output voltage of the variable constant voltage source 4 shown in FIG. 1 is controlled according to the type.

From the sawtooth wave generating circuit 38, FIG.
As shown in (d), a saw-tooth wave signal having a period T that increases by a voltage e _{1 for} each sample pulse is output. The output of the saw-tooth wave generation circuit 38 is supplied to a low-pass filter 39, and a harmonic component included in the saw-tooth wave signal is removed.
The output of the low-pass filter 39 is amplified by the deflection circuit 40 and supplied to the deflection coil.

In a television receiver compatible with multiple systems, the deflection frequency differs depending on the system of the received television signal. For example, regarding the vertical deflection frequency, N
The TSC system is 60 Hz, whereas the PAL system is 50 Hz. That is, the period T of the sawtooth signal changes to 1/60 seconds and 1/50 seconds depending on the television system.

Here, as can be seen from the equation (2), the ratio T between the repetition period T of the sawtooth wave and the period t of the sample pulse SP.
/ T is fixed, the output voltage E is equal to the input voltage e
Proportional to ₁ . In this embodiment, the repetition period T of the sawtooth wave corresponds to the vertical deflection period, and the sample pulse SP
Corresponds to the horizontal deflection cycle, and the vertical deflection cycle and the horizontal deflection cycle are determined by each television system.
Is constant. Therefore, the television system is determined by the system determination circuit 36, and the voltage control circuit 3
The output voltage E of the variable constant voltage source 4 is controlled by the control unit 7, so that the output voltage E can be constant regardless of the period T of the sawtooth signal.

FIG. 6 is an explanatory diagram showing the principle of generation of a sawtooth signal in the NTSC system and the PAL system. However,
Here, for the sake of simplicity, it is assumed that interlace scanning is not performed.

In the case of the NTSC system, since the vertical deflection frequency is 60 Hz, the period of the sawtooth signal to be output is 1/60 second. The number of horizontal scanning lines is 525.
Since this is a book, the number of sample pulses per vertical cycle is 525. Here, assuming that the voltage of the target sawtooth signal is E, the increase voltage per sample pulse is E / 525. Therefore, by setting the input voltage e _1N to E / 525 by the voltage control circuit 37, a saw-tooth wave signal whose output voltage is E can be obtained.

In the case of the PAL system, since the vertical deflection frequency is 50 Hz, the period of the sawtooth signal to be output is 1/50 second. The number of horizontal scanning lines is six.
Since there are 25 pulses, the number of sample pulses per vertical cycle is 625. Here, the voltage of the sawtooth signal is N
Assuming that E is the same as in the TSC system, the increase voltage per sample pulse is E / 625. Therefore, by setting the input voltage e _1P to E / 625 by the voltage control circuit 37, a saw-tooth wave signal whose output voltage is E can be obtained. That is, by setting the values of the input voltages e _1N and e _1P so as to satisfy the condition of e _1N = E / 525 e _1P = E / 625, the sawtooth signal can be obtained regardless of the difference in the deflection frequency. The voltage can be kept constant.

[0036]

According to the sawtooth wave generating circuit of the present invention,
By changing the rising voltage per one sample pulse in accordance with the period of the sawtooth signal, the output voltage of the sawtooth signal can be made constant regardless of the period of the sawtooth signal. Therefore, even if the deflection frequency changes, the deflection width can always be kept constant.

[Brief description of the drawings]

[0037]

FIG. 1 is a circuit diagram showing an embodiment of a sawtooth wave generating circuit according to the present invention.

[0038]

FIG. 2 is a circuit diagram showing an internal configuration of a sample / hold integrated circuit.

[0039]

FIG. 3 is a waveform chart for explaining the operation of the sawtooth wave generation circuit.

[0040]

FIG. 4 is a waveform chart for explaining the operation of the sawtooth wave generation circuit.

[0041]

FIG. 5 is a circuit diagram showing an example in which a sawtooth wave generating circuit is applied to a deflection circuit of a television receiver compatible with multiple systems.

[0042]

FIG. 6 is an explanatory diagram showing the principle of generation of a sawtooth signal in the NTSC system and the PAL system.

[0043]

FIG. 7 is an explanatory diagram showing a principle of generating a sawtooth signal in a digital deflection signal generating circuit.

[0044]

[Explanation of symbols]

1: sample / hold circuit, 2: operational amplifier circuit, 3:
Constant voltage input circuit, 4 ... Variable constant voltage source, 5 ... Internal resistance, 6
... Integrated circuit for sample / hold, 7a... Front-stage operational amplifier, 7b.
... Input terminal, 14 ... Offset terminal, 15 ... Logic input terminal, 16 ... Logic reference terminal, 17 ... Output terminal, 18 ... Hold capacitor terminal, 19 ... Resistor, 20 ... Hold capacitor, 21 ... Switching element, 22 ... Resistance Container, 2
3: Integrated circuit for arithmetic circuit, 24: negative input terminal, 25:
Resistor, 26 output terminal, 27 positive input terminal, 28
Resistor, 29: enable terminal, 30: sample pulse supply terminal, 31: inverter, 32: synchronization separation circuit, 3
3: Synchronous control circuit, 34: Reset pulse generating circuit, 3
5 ... Sample pulse generation circuit, 36 ... Method discrimination circuit, 3
7: voltage control circuit, 38: sawtooth wave generation circuit, 39: low-pass filter, 40: deflection circuit

Claims (2)

[Claims] 1. A voltage obtained by sampling a constant input voltage for each pulse of a sample pulse having a period sufficiently shorter than a period of a sawtooth signal to be output, and adding the constant input voltage and a previously sampled voltage. A reset circuit for discharging a charge of the capacitor of the sample / hold circuit by a reset pulse synchronized with a period of a sawtooth signal to be output; A control circuit for changing the value of the constant voltage in accordance with the cycle of the sawtooth signal to be output. 2. The method according to claim 1, wherein the sampling pulse is a signal synchronized with a horizontal deflection signal, and the reset pulse is a signal synchronized with a vertical deflection signal.
A saw-tooth wave generating circuit as described.