JPH1032336A - Resonance-tunnel field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resonance-tunnel field-effect transistor, which can readily form the unitary body together with a silicon-based material system. SOLUTION: In a resonance-tunnel field-effect transistor 10, which is formed of silicon-based material system and includes a first conducting contact 24, a second conducting contact 30 and a control contact 26, a resonance-tunnel device 14 is arranged on the second conducting contact 30 of a field effect transistor 12 in the movable shape, and a contact 40, which can be externally accessed, is determined. The resonance tunnel device 14 can be formed of the silicon-based material or the III-V based material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to resonant tunnel devices, and more particularly to resonant tunnel field effect transistors.

[0002]

BACKGROUND OF THE INVENTION Various resonant tunneling devices have been constructed or proposed in the literature. Examples of such structures include resonant tunneling emitter transistors;
Electron transistors; and quantum well resonant tunnel base transistors. One important issue is that all of these structures are peak-to-va
lley) low current ratio. These structures also
Difficult to make contact without generating an unacceptable amount of leakage current between contacts (eg, base, collector or gate, source, drain).

[0003] Resonant tunnel devices have the potential to replace conventional transistors in some applications, such as logic circuits. Logic circuits and their uses are well known in the art. Generally, a special logic circuit includes a plurality of elements or members such as a transistor, a diode, and a resistor. Also,
It is generally very difficult to integrate these various members on a single semiconductor chip because of different conditions.

[0004] By employing a resonant tunneling device, the logic circuit can be miniaturized. At present, a major problem with resonant tunneling devices is that they are made of exotic material systems that cannot be combined with conventional techniques.

[0005] Therefore, there is a need to provide a resonant tunneling field effect transistor that can be coupled with existing techniques.

[0006]

It is an object of the present invention to provide a new and improved resonant tunneling field effect transistor.

It is another object of the present invention to provide a new and improved resonant tunneling field effect transistor that can be easily integrated with silicon-based material systems. It is a further object of the present invention to provide a resonant tunneling field effect transistor that provides a high peak-to-valley current ratio.

[0008]

BRIEF SUMMARY OF THE INVENTION Briefly stated, in accordance with a preferred embodiment, provided to achieve the desired objects of the present invention are those formed of a silicon-based material system,
A resonant tunneling field effect transistor including a field effect transistor including a first conductive contact, a second conductive contact, and a control contact. A resonant tunneling device is operatively disposed over the second conductive contact of the field effect transistor to define an externally accessible contact.

In one specific embodiment, a resonant tunnel
The device is formed of a silicon-based material system.

[0010] In another specific embodiment, the resonant tunneling device is formed of a III-V based material system. There is also a ramp region between the III-V based resonant tunneling device and the silicon-based field effect transistor, which ramps the silicon-based field effect transistor to the III-V based resonant transistor. Lattice matching with the tunnel device.

[0011] These and other individual objects and advantages will be readily apparent to those skilled in the art from the following detailed description, taken in conjunction with the accompanying drawings.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. Through multiple figures,
The same reference numbers indicate corresponding elements. First, look at FIG. 1, which shows a resonant tunneling field effect transistor (generally designated by reference numeral 10). The resonance tunnel field effect transistor 10 includes a field effect transistor 12 formed of a silicon-based material system and a resonance tunnel transistor.
Device 14. In this particular embodiment, field effect transistor 12 is a conventional metal oxide semiconductor field effect transistor (MOSF) having a silicon substrate 16.
ET), and a source 18 and a drain 20 are formed in the substrate. Source 18 and drain 20 are formed by applying a dopant material to a particular region of substrate 16 and separated by a channel region 22 using conventional techniques such as diffusion or buried. In this example,
The source 18 and the drain 20 have N-type conductivity,
Substrate 16, especially channel region 22, is P-type conductive. A drain electrode 24 is formed over the drain 20 and a gate electrode 26 is formed over the channel region 22 from which a silicon dioxide layer 28 is formed.
Separated by

Instead of an electrode providing an external contact with the source 18, a resonant tunneling device 14 is formed on the source 18. Therefore, in this specific embodiment, the drain 20, source 18 and gate 22 are each
They are conductive contacts (drain, source) and control contacts and operate as a conventional MOSFET. However, it should be understood that the resonant tunneling field effect transistor 10 is not limited to a particular type of field effect transistor, but may use any field effect transistor, for example, a heterojunction field effect transistor. This will be immediately apparent from the following example.

A resonant tunneling device 14 is operatively disposed on the source 18 of the field effect transistor 12 and defines externally accessible contacts. In this particular embodiment, the resonant tunneling device 14 comprises:
Formed in a silicon-based material system. In particular,
The conductive layer 30 having the first conductivity is disposed on the substrate 16 on which the source 18 is mounted, and the pair of quantum well layers 32, 3
4 is disposed on the conductive layer 30 and separated by the barrier layer 36, and another conductive layer 38 having the second conductivity is provided.
Are arranged on the quantum well layer 34 and the quantum well layer 3
2 and 34 and the barrier layer 36 are sandwiched between the conductive layers 30 and 38.

The conductive layer 38 is heavily doped with p dopants to form p ++ conductivity, while the conductive layer 30 is heavily doped with n dopants to form n ++ dopants. Source electrode 40
Is formed on the conductive layer 38 to provide an external contact for the resonant tunneling device 14, ie, the field effect transistor 1
Two external contacts are provided. In the specific embodiment shown, the quantum well layers 32, 34 are formed of GeSi and the conductive layers 3
0, 38 are formed of Si.

Turning now to FIG. 2, the conduction band (represented by line 42) and the valence band (represented by line 44) of the resonant tunneling device 14 are shown. Starting from the right, conductive layer 3
A band gap of zero is shown with the quantum well layer 32 adjacent. The quantum well 32 is separated from the quantum well 34 by a barrier layer 36, and the conductive layer 38 is adjacent to the quantum well 34 on the left. As shown, the resonant tunneling device 14 is biased to shift the energy band downward, as in FIG. 2, to allow carriers to flow in a manner well known to those skilled in the art.

Referring to FIG. 3, there is shown another embodiment of a resonant tunneling field effect transistor, generally designated 10 '. Resonant tunnel field effect transistor 10 ′
Although there are two or three notable differences, similar elements are generally similar to the resonant tunneling field effect transistor 10 and therefore include similar elements, including those with the same prime number added to indicate a new embodiment. It is shown as having. The difference is that a pair of Ge monolayers 46 and 48 are included, and are respectively accommodated in the GeSi quantum well layers 32 ′ and 34 ′. The addition of monolayers 46 and 48 is effective in increasing the peak-to-valley ratio of the device.

A further embodiment of a resonant tunneling field effect transistor, generally designated 50, is shown in FIG. Resonant tunnel field effect transistor 50 is a field effect transistor 52 formed of a silicon-based material system.
And a resonant tunneling device 54 formed of a III-V material system.

In this particular embodiment, field effect transistor 52 is a conventional heterostructure field effect transistor (HFET) having a silicon substrate 56, on which a channel 58 and a supply layer 60 are formed, respectively. You. The channel 58 and the supply layer 60 are formed by a conventional technique such as evaporation or epitaxial growth. The conductive contacts 62, 64 and the control contact 66 are operatively coupled to the channel 58. Resonant tunnel device 54 is operatively disposed over conductive contact 64 of field effect transistor 52 to define an externally accessible contact.

In this embodiment, the conductive contacts are provided in the supply layer 60.
A drain electrode 68 formed on
It includes the surface of the supply layer 60 located below the device 54.
The control contact 66 is a gate electrode 70 formed on the supply layer 60 and separated from the supply layer by an insulating layer 72, the drain electrode 68 and the resonant tunneling device 54.
And placed in between. In this example, channel 58
Is formed of a strained GeSi material, which preferably has a Ge _x Si _1-x ratio. The supply layer 60 is silicon.

Here, the resonant tunneling field effect transistor 50 is not limited to a specific HFET, but may be any HFE.
Note that T can be employed. For example, strain Si
An HFET having a channel and a relaxed GeSi coating can be employed. Also, conventional FETs or MOSFETs can be employed in combination with resonant tunneling devices formed from III-V material systems.

Resonant tunnel device 54 includes barrier layer 7
Resonance tunnel layers 78, 80 disposed on both sides of
And a quantum well layer 72 sandwiched between the barrier layers 74 and 76 so that the barrier layers 74 and 76 are sandwiched between the resonant tunnel layers 78 and 80. In this specific embodiment, the quantum well layer 72 is formed of GaSb, the barrier layers 74 and 76 are formed of AlSb,
8, 80 are formed of InAs.

A graded region 82 is located between the resonant tunneling device 54 and the field effect transistor 52 to couple the silicon-based heterojunction field effect transistor to the III-V based resonant tunneling device and the grating. Align. The graded region 82 includes the heterojunction field effect transistor 52, the GaAs layer 86 disposed on the graded GeSi layer 84, and the graded InGaAs layer 88 disposed on the GaAs layer 86. Inclined GeSi layer 8
4 is graded from a heterojunction field effect transistor 52 substantially close to pure Si to a GaAs layer 86 substantially close to pure Ge. Inclined InGaAs layer 88
From the GaAs approximation (proximate) GaAs layer 86,
A gradient is applied to the InAs approximation InAs barrier layer 78.

Substantially pure G in graded GeSi layer 84
e changes the lattice constant to about 5.66 °, which is
Very close to that of s (5.653 °). On the other hand, Si
(5.43 °) indicates a lattice mismatch (latt) of 4% with GaAs.
ice mismatch). Growing GaAs directly on Si can roughen the surface morphology and degrade the layer / interface quality of the resonant tunneling device. The roughening is caused by mismatch strain.
) And three-dimensional growth resulting from different lattice symmetry. GeSi gradient layer 84
By adopting GaAs, GaAs can be grown on without being coarse.

Accordingly, a new and improved resonant tunneling field effect transistor in combination with existing technology has been disclosed. Also, the new and improved resonant tunneling field effect transistor can be easily integrated with silicon-based material systems. This resonant tunneling field effect transistor also provides a relatively high peak-to-valley current ratio.

While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art.
Therefore, it is to be understood that this invention is not limited to the particular forms shown. Also, the appended claims are intended to cover all modifications that do not depart from the spirit and scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a simplified cross-sectional view of an embodiment of a resonant tunneling field effect transistor according to the present invention.

FIG. 2 is an energy band diagram of a resonance tunnel region of the structure shown in FIG. 1 in a state where a bias is applied.

FIG. 3 is a simplified cross-sectional view of another embodiment of a resonant tunneling field effect transistor according to the present invention.

FIG. 4 is a simplified cross-sectional view of yet another embodiment of a resonant tunneling field effect transistor according to the present invention.

[Explanation of symbols]

 10, 10 'Resonant tunnel field effect transistor 12, 12' Field effect transistor 14, 14 'Resonant tunnel device 16, 16' Silicon substrate 18, 18 'Source 20, 20' Drain 22, 22 'Channel region 24, 24' Drain electrode 26, 26 'Gate electrode 28, 28' Silicon dioxide layer 30, 30 'Conductive layer 32, 32', 34, 34 'Quantum well layer 36 Barrier layer 38, 38' Conductive layer 40, 40 'Source electrode 42 Conduction Band 44 valence band 46,48 monolayer 50 resonant tunneling field effect transistor 52 field effect transistor 54 resonant tunneling device 58 channel 60 supply layer 62 conductive contact 66 control contact 68 drain electrode 70 gate electrode 72 quantum well layer 74,76 Barrier layer 78,80 resonance tons Flannel layer 82 Slant region 84 Slant GeSi layer 86 GaAs layer 88 Slant InGaAs layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Herbert Golonkin 8623, South Kachina Drive, Tempe, Arizona, USA (72) Inventor Baymond Kay Sui 3339, East Tanglewood Drive, Phoenix, Arizona, USA

Claims (4)

[Claims] 1. A resonant tunneling field effect transistor formed of a silicon-based material system and having a first conductive contact (20, 24), a second conductive contact (18, 30), and a control contact (26). Field effect transistor (1)
And 2) a resonant tunnel operatively disposed on the second conductive contact (18, 30) of the field effect transistor (12) to define an externally accessible contact (40). A transistor characterized by being constituted by a device (14); 2. A resonant tunneling field effect transistor, comprising: a silicon-based material system, comprising a first conductive contact (20, 24), a second conductive contact (18, 30) and a control contact (26). Including field effect transistors (1
And 2) a silicon base operatively disposed on the second conductive contact (18, 30) of the field effect transistor (12) to define an externally accessible contact (40). A resonant tunneling device (14). 3. A resonant tunneling field-effect transistor comprising: a first conductive contact (20 ', 24') and a second conductive contact (18 ', 3') formed of a silicon-based material system.
0 ') and a field effect transistor (12') including a control contact (26 '); and a form operable on said second conductive contact (18', 30 ') of said field effect transistor (12'). Arranged in
A silicon-based resonant tunneling device (14 ') defining an externally accessible contact (40'), wherein said resonant tunneling device (14 ') comprises a first
Said field-effect transistor (12 ') having conductivity
And a second conductive layer (38 ') having a second conductivity, between which the first and second quantum well layers (32', 30 ') are disposed. 34 '), and the second quantum well layer (34') is provided with a barrier layer (3 ').
6 ') and separated from the first quantum well layer (32') by the first and second quantum well layers (32 ', 3').
4 ') includes a monolayer (46, 48) housed therein, wherein the first and second quantum well layers (32', 34 ') are each formed of GeSi, and 46,4
8) is made of Ge, and the first and second conductive layers (3
0 ', 38') comprises a silicon-based resonant tunneling device (14 ') formed of Si. 4. A resonant tunneling field effect transistor formed of a silicon-based material system and including a first conductive contact (68), a second conductive contact (64) and a control contact (70). (52); the second conductive contact (6) of the field effect transistor (52);
4) a resonant tunneling device (54) operatively disposed thereon to define externally accessible contacts;
Wherein said resonant tunneling device (54) comprises I
A resonant tunneling device (54) formed of a II-V based material system; and a graded region (8) disposed between the resonant tunneling device (54) and the field effect transistor (52).
2) wherein said graded region (82) comprises said silicon-based field effect transistor (52)
A transistor, characterized by a sloped region (82) lattice-matched to the IV-based resonant tunneling device.