JPH1032241A - Manufacture of semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate fine processing of a trench groove width and restrain progress of crystal defects due to stress concentration, by forming a first insulating film having a first groove on a semiconductor substrate, forming a polycrystalline film or an amorphous film on the lateral surface of the first groove, and then forming a second groove substantially matched with the first groove. SOLUTION: A silicon oxide film 14 is formed on the front and back sides of a dielectric isolation substrate 10 in which an upper silicon substrate 11 and a lower silicon substrate 12 are connected via an insulating film 13, and a silicon oxide film 15 is formed on the oxide film 14. Then, the oxide films 14, 15 are etched to form a groove 15a, and a polysilicon film is deposited on the inner surface of the groove 15a and on the oxide film 15. Then, the polysilicon film 16 is anisotropically etched to leave a polysilicon film 16a only on the lateral surfaces of the oxide films 14, 15. Subsequently, the substrate 11 is anisotropically etched until the insulating film 13 is reached, thus forming a trench groove 11a. This trench groove 11a is matched with the groove 15a, and the groove width is narrowed by the amount of the film 16a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device and a method for forming a trench in a dielectric isolation substrate or the like.

[0002]

2. Description of the Related Art In a power IC using a dielectric separation substrate, elements constituting a circuit are separated by a dielectric, so that a power IC having a high withstand voltage can be realized. Further, since no parasitic element is formed between the elements, a highly reliable I
C can be realized.

In a dielectric isolation power IC, the separation between the substrate and the device is performed by an insulating film provided in the middle of the dielectric separation substrate, and the separation between the devices is performed by a trench. Conventionally, this trench was formed as follows (see FIG. 8).

[0004] First, a dielectric isolation substrate 50 in which an upper silicon substrate 51 and a lower silicon substrate 52 are connected via an insulating film 53 is thermally oxidized to form a silicon oxide film 54. A thick silicon oxide film 55 is formed by a CVD method. Then, the silicon oxide films 54 and 55 are patterned by reactive ion etching to form a groove 55a (a). Next, the upper silicon substrate 51 is etched by RIE using the patterned silicon oxide films 54 and 55 as a mask to form a trench 51a (b). After removing the silicon oxide films 54 and 55, a silicon oxide film 56 is formed by thermal oxidation, and a polysilicon film 57 is buried in the trench where the silicon oxide film 56 is formed (c).

[0005]

In the above conventional method,
There were the following problems. First, there is a problem with miniaturization of the trench groove width. The trench is filled by depositing a polysilicon film. Therefore, as the width of the trench is narrower, thinner polysilicon can be deposited and flattening becomes easier, so that the cost can be reduced. However, it is necessary to use an expensive device for miniaturization, and as a result, it has been difficult to reduce the cost.

Second, there is a problem of generation of crystal defects. When the oxidation is performed as shown in FIG. 8C after the formation of the trench, stress is concentrated at a portion where the surface of the upper silicon substrate 51 intersects with the side surface of the trench, and a crystal defect occurs at this location. . When the plane orientation of the substrate is (100), the crystal defects travel in the (111) direction and reach the element region, resulting in deterioration of element characteristics. Therefore, conventionally, as shown in FIG. 9, by forming a deep trench 51a inside a shallow trench 51b, a convex portion is formed in a region sandwiched between the shallow trench 51b and the deep trench 51a. Some methods have been used to concentrate stress. However, in this case, since it is necessary to form the shallow trench 51b and the deep trench 51a, there arises a problem that the trench must be etched twice.

Third, there is a problem of unevenness in the depth and shape of the trench. The surface of the dielectric isolation substrate has a tendency to warp in a convex shape.
As shown in FIG. 0, since the bottom surface of the dielectric separation substrate 50 does not completely adhere to the wafer chuck 61 of the RIE apparatus, the central portion of the dielectric separation substrate 50 floats from the wafer chuck 61. For this reason, the cooling effect is different between the central portion of the dielectric isolation substrate 50 and the peripheral portion of the dielectric isolation substrate 50, and the temperature of the central portion of the dielectric isolation substrate 50 rises.
As shown in FIG. 1, the central portion of the trench 51a has a so-called bowing shape which is expanded. Further, as shown in FIG. 10, the peripheral portion of the dielectric isolation substrate 50 is in close contact with the wafer chuck by the pawl 62, so that charging by plasma is likely to occur, thereby increasing the etching rate and increasing the depth of the trench groove. Variations are likely to occur.

In order to solve the above problem, an electrostatic chuck has recently been adopted. In this electrostatic chuck, the dielectric separation substrate is brought into close contact with the chuck by static electricity, and even a warped substrate can be brought into close contact with the chuck. Therefore, the above problem can be solved temporarily by using an electrostatic chuck. However, the use of the electrostatic chuck has caused a new problem. This is because, when the dielectric isolation substrate is covered with an oxide film, the electric charge charged on the dielectric isolation substrate by the plasma is not discharged, so that the dielectric isolation substrate is attracted to the electrostatic chuck and the dielectric isolation substrate is attracted. Is not able to be detached from the chuck.

A first object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can easily reduce the width of a trench groove and can suppress the progress of crystal defects due to stress concentration. It is in.

A second object of the present invention is to solve the problem of non-uniformity of the depth and shape of the trench, and to easily stabilize the substrate when performing plasma etching using an electrostatic chuck. An object of the present invention is to provide a method for manufacturing a semiconductor device which can be separated from an electric chuck.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film having a first groove on a semiconductor substrate; Forming a polycrystalline film or an amorphous film on a side surface of the semiconductor device, and forming a second groove in the semiconductor substrate substantially matching the first groove in which the polycrystalline film or the amorphous film is formed. And the second
Forming a second insulating film on the surface of the groove and on the surface of the polycrystalline film or the amorphous film; and forming a buried film in the second groove in which the second insulating film is formed. And

Since the polycrystalline film or the amorphous film is formed on the side surface of the first groove, the width of the second groove (trench groove) is larger than that of the first groove. Alternatively, the width can be reduced by the amount of the amorphous film, and the miniaturization of the trench can be easily performed. Further, since stress is concentrated on the polycrystalline film, stress on the semiconductor substrate can be reduced, and generation and progress of crystal defects can be suppressed.

In the manufacturing method, an impurity may be introduced into the polycrystalline film or the amorphous film, and the impurity may be diffused into the semiconductor substrate. In this case, a getter effect can be expected due to the diffused impurities, and the device characteristics can be improved.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: mounting a semiconductor substrate having a conductive film formed on a rear surface side on an electrostatic chuck of an etching apparatus; Forming a groove in the semiconductor substrate, and separating the semiconductor substrate having the groove from the electrostatic chuck by making the potential of the electrode of the electrostatic chuck substantially equal to the potential of the conductive film. .

Since the anisotropic etching is performed using the electrostatic chuck, the depth and shape of the trench can be made uniform, and a conductive film is provided on the back side of the semiconductor substrate to attach the semiconductor substrate to the electrostatic chuck. Since the potential of the electrode of the electrostatic chuck is equal to the potential of the conductive film when the semiconductor substrate is separated from the semiconductor substrate, the semiconductor substrate can be easily separated from the electrostatic chuck.

Further, according to a method of manufacturing a semiconductor device according to a third aspect of the present invention, by combining the above two manufacturing methods, it is possible to achieve miniaturization of a trench groove and to suppress generation and progress of crystal defects. In addition, the depth and shape of the trench can be made uniform, and the semiconductor substrate can be easily separated from the electrostatic chuck.

As the conductive film formed on the lower surface side of the semiconductor substrate, it is most preferable to use the same polycrystalline film or amorphous film formed on the upper surface side from the viewpoint of easiness of the manufacturing process. .

According to a fourth aspect of the present invention, there is provided a semiconductor device, comprising: a groove formed in a semiconductor substrate; a polycrystalline film or an amorphous film formed in a portion of the semiconductor substrate surface in contact with the groove;
An insulating film formed on the surface of the groove and the surface of the polycrystalline film or the amorphous film; and a buried film formed in the groove in which the insulating film is formed. Since stress is concentrated on the polycrystalline film and stress on the semiconductor substrate can be reduced, generation and progress of crystal defects in the semiconductor substrate can be suppressed.

[0019]

1 to 3 are cross-sectional views of a manufacturing process according to an embodiment of the present invention.
The manufacturing method will be described according to (i). First, the upper silicon substrate 11 and the lower silicon substrate 12 are
3 (using a silicon oxide film), a dielectric isolation substrate 10 (semiconductor substrate) is prepared, and a silicon oxide film 14 (first insulating film) is formed on the front and back surfaces of the dielectric isolation substrate 10 by thermal oxidation. Then, a thick silicon oxide film 15 (first insulating film) is formed on the silicon oxide film 14 by the CVD method (a).

Next, the silicon oxide films 14 and 15 are
Etching is selectively performed by IE to form a groove 15a (first groove) (b). Next, a polysilicon film 16 (polycrystalline film, conductive film) is deposited on the inner surface of the groove 15a and on the silicon oxide film 15, and then the polysilicon film 16 is deposited.
Then, an n-type or p-type impurity is implanted (c).

Next, the polysilicon film 1 is formed by RIE.
6 is anisotropically etched to form silicon oxide films 14 and 15
The polysilicon film 16a is left only on the side surface of. Since the polysilicon film 16a is formed inside the groove 15a in this manner, the width of the groove 15a is reduced by the size of the polysilicon film 16a (d).

Subsequently, the upper silicon substrate 11 is anisotropically etched by RIE until it reaches the insulating film 13,
A trench 11a (second groove) is formed. The trench 11a thus formed is formed in the polysilicon film 1
6a is aligned with the groove 15a formed on the side wall, and the groove width is reduced by the polysilicon film 16a (e).

Here, the RIE step in the steps (d) and (e) will be described in more detail. FIG.
Shows the main part of the plasma etching apparatus 20 used in the RIE process. Reference numeral 21 denotes an electrostatic chuck for mounting and adsorbing the substrate 10, and an electrode 22 is embedded in the electrostatic chuck 21. A power supply 23 is connected between the electrodes 22 so that a DC voltage is applied to the electrodes 22. In addition, a conductive lift pin 24 is connected to the electrode 22, and the lift pin 24 is movable in the vertical direction. Although not shown, a cooling liquid flows inside the electrostatic chuck 21 to cool the electrostatic chuck 21 to a constant temperature.

After the step (c) is completed, the dielectric isolation substrate 10 (more precisely, the silicon oxide film 1) shown in FIG.
The dielectric isolation substrate 10 on which the dielectric films 4 and 15 and the polysilicon film 16 are formed is referred to as a dielectric isolation substrate on which these films are formed for convenience. ) Is mounted on the electrostatic chuck 21 shown in FIG. When a voltage of several hundred volts is applied to the electrode 22 embedded in the electrostatic chuck 21, the dielectric separation substrate 10 is attracted to the electrostatic chuck 21 by static electricity.

After the dielectric separation substrate 10 is fixed on the electrostatic chuck 21 in this manner, when an etching gas is introduced into the chamber of the plasma etching apparatus 20 and a high-frequency electric field is applied, the etching gas is turned into plasma and becomes RI.
E is performed. In the RIE step, first, the polysilicon film 16 is etched to leave the polysilicon film 16a on the side surfaces of the silicon oxide films 14 and 15, and then the upper silicon substrate 11 is etched until it reaches the insulating film 13 to form the trench groove 11a. Form.

At the time of RIE, since the dielectric separation substrate 10 is attracted to the electrostatic chuck 21 by static electricity, even if the dielectric separation substrate 10 is warped, the central portion of the substrate is floated as in the conventional case. That is, the entire surface of the dielectric isolation substrate 10 is uniformly cooled. Therefore, a trench groove having excellent uniformity in depth and shape can be formed. 4A, the lift pins 24 are kept apart from the electrostatic chuck 22 until the RIE ends after the dielectric separation substrate 10 is mounted on the electrostatic chuck 21.

Since electrons in the plasma are injected into the dielectric isolation substrate 10 during RIE, the dielectric isolation substrate 10 is in a charged state when RIE is completed. Therefore, even after the application of the voltage to the electrode 22 is stopped, the dielectric separation substrate 10 is attracted to the electrostatic chuck 21 by static electricity.
It is in a state where it is difficult to leave from. Therefore, after the RIE is completed, the lift pins 24 are moved upward to make contact with the back surface of the dielectric isolation substrate 10 as shown in FIG. Since the conductive polysilicon film 16 is formed on the back surface of the dielectric isolation substrate 10 as shown in FIG. 2E, the back surface of the dielectric isolation substrate 10 is The formed polysilicon film 16 and the electrode 22 embedded in the electrostatic chuck 21 have substantially the same potential. As a result, the dielectric separation substrate 10 and the electrostatic chuck 2
1 is eliminated, and the dielectric separation substrate 10 can be easily separated from the electrostatic chuck 21.

As described above, steps (d) and (e)
Is completed, and a trench groove 11a having a groove width reduced by the polysilicon film 16a is formed. In this embodiment, the polysilicon film 16 is used as the conductive film formed on the back surface of the dielectric isolation substrate 10,
The method as shown in FIG.
With respect to the technical idea that the dielectric separation substrate 10 can be easily separated from the electrostatic chuck 21 by eliminating the attraction force between the dielectric chuck 10 and the electrostatic chuck 21, the polysilicon film is not necessarily required. It is only necessary that the film be a conductive film, and for example, a metal film or the like may be used.

After the above step (e) is completed, the silicon oxide films 14 and 15 are removed (f), and the silicon oxide film 17 (the second oxide film 17) is formed on the surfaces of the trench grooves 11a and the polysilicon film 16a by thermal oxidation. (Insulating film). At this time, since the polysilicon film 16a is formed at the intersection of the surface of the upper silicon substrate 11 and the side wall of the trench 11a, stress concentrates on the polysilicon film 16a. Therefore, stress on upper silicon substrate 11 can be reduced, and generation and progress of crystal defects in upper silicon substrate 11 can be suppressed. Also,
By this thermal oxidation step, the impurities in the polysilicon film 16a are activated, and the impurities in the polysilicon film 16a are diffused into the upper silicon substrate 11 so that the diffusion layer 18 is formed.
Is formed. Since the diffusion layer 18 is thus formed, a getter effect can be expected due to the diffused impurities,
The device characteristics can be improved (g).

Next, a polysilicon film 19 is deposited on the entire surface (h), and a polysilicon film 19a (buried film) is buried in the trench groove 11a by a planarization process (i). As described above, a trench isolation structure in which the polysilicon film 19a is buried in the trench groove 11a is formed, thereby separating the elements.

In the manufacturing method shown in FIGS. 1 to 3, an impurity is introduced into the polysilicon film 16 in the step (c), and the impurity is diffused in the thermal oxidation step in the step (g) to diffuse the impurity. 18 is formed, but the polysilicon layer 1
It is not necessary to introduce impurities into 6.

In the above-described manufacturing method, a dielectric isolation substrate is used, but a normal semiconductor substrate may be used instead of the dielectric isolation substrate. The etching method is RIE
However, any method having high anisotropy may be used. For example, reactive ion beam etching using an electron cyclotron (ECR) ion source may be used.

Further, the side on which the first and second grooves are formed does not need to be a polysilicon film, but may be an amorphous silicon film which is an amorphous film. When an amorphous silicon film is used, it can be formed at a lower temperature than when a polysilicon film is formed, thereby facilitating the manufacturing process. These films need not be conductive only from the viewpoint of stress relaxation. Further, the material that can be formed is not limited to a polysilicon film or an amorphous silicon film, and any polycrystalline film or amorphous film can be used regardless of whether it is conductive or not.

Next, an application example of the method for manufacturing a trench described in the above embodiment will be described with reference to FIGS. In these applications, the trench described in the above embodiment is used for separating a circuit portion (element region) and a bonding pad portion in an integrated circuit (semiconductor chip). By separating the element region and the bonding pad by the trench groove, a crack or the like generated by an impact or the like at the time of bonding can be stopped by the trench groove, and the crack or the like can be prevented from reaching the element region. In addition, in the example shown in FIGS.
Components that are substantially the same as or correspond to the components shown in (1) are assigned the same reference numerals, and detailed descriptions thereof are omitted.

FIG. 5 shows a first application example.
5 (A) is a plan view, and FIG. 5 (B) is BB in FIG. 5 (A).
FIG. Reference numeral 30 denotes a semiconductor chip, 31 denotes an element region in which transistors and the like are formed, and 32 denotes a bonding pad. Reference numeral 33 denotes a trench groove region, which is shown in FIG.
Although only the solid line is drawn in FIG. 5A, the configuration is actually the same as that described with reference to FIGS. 1 to 3, and as shown in FIG. 5B, a polysilicon film 19a is embedded in the trench. It has a configuration. In this application example, a trench groove region 33 is formed outside the element region 31 to separate the element region 31 from the bonding pad 32. In this application example, the trench 3 is located between the bonding pads 32.
3, the pn junction isolation may be performed by forming a reverse P-type semiconductor layer, for example, around the N-type semiconductor layer immediately below the bonding pad 32, for example.

FIG. 6 shows a second application example.
6 (A) is a plan view, and FIG. 6 (B) is BB in FIG. 6 (A).
FIG. Components substantially the same as or corresponding to those of the first application example shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this application example, a trench groove 33 is provided around each bonding pad 32 to perform separation between the bonding pads 32 and separation between the bonding pad 32 and the element region 31. Since the trench groove region 33 is provided in this manner, it is not necessary to form a pn junction around the bonding pad 32, and a high breakdown voltage can be achieved without increasing the area of the bonding pad portion.

FIG. 7 shows a third application example.
7A is a plan view, and FIG. 7B is BB in FIG. 7A.
FIG. Components substantially the same as or corresponding to those of the first application example shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this application example, similarly to the second application example shown in FIG. 6, a trench groove region 33 is provided around each bonding pad 32, and an input protection diode (N The mold region is connected to the bonding pad 32 via the electrode 34a, and the P-type region is grounded via the electrode 34b.) By providing the input protection diode in this manner, a surge voltage is absorbed by the diode, and a highly reliable integrated circuit can be formed.

In the application examples of FIGS.
An opening may be formed in the intermediate insulating film 13 and the upper silicon substrate 11 and the lower silicon substrate 12 may be connected via a conductive material in the opening.

In the application examples of FIGS. 5 to 7 described above, the bonding pad 32 and the element region 31 are dielectrically separated by the trench groove region 33, and the bonding pad 32 and the lower silicon The substrate 12 and the intermediate insulating film 13 are dielectrically separated. Therefore, the bonding pad 32 may be subjected to an impact during bonding or the like.
Even if the insulating film 17 immediately below is broken, the bonding pad 3
2 and lower silicon substrate 1 immediately below bonding pad 32
2 can be prevented from being short-circuited. Further, even if a large impact occurs during bonding and a crack is generated, the crack can be prevented from spreading by the trench groove region 33 and the intermediate insulating film 13, and an increase in leak current and the like can be suppressed. In the application examples shown in FIGS. 6 and 7, since the trench groove region 33 is provided around each bonding pad 32, a high breakdown voltage can be achieved without increasing the area of the bonding pad portion.

The configuration shown in the application example of FIGS.
That is, the technical idea is that the bonding pad 32 and the element region 31 are dielectrically separated by the trench groove region 33, and the bonding pad 32 and the lower silicon substrate 12 of the dielectric separation substrate 10 are dielectrically separated by the intermediate insulating film 13. With regard to the above, it is not always necessary to apply the manufacturing method and configuration shown in FIGS. 1 to 3, and for example, a manufacturing method and configuration according to a conventional technique as shown in FIG. 8 may be applied. Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the invention.

[0041]

According to the first aspect of the present invention, since the polycrystalline film or the amorphous film is formed on the side surface of the first groove, the second groove is formed.
Groove width of the first groove can be made smaller than that of the first groove by the amount of the polycrystalline film or the amorphous film. As a result, the second groove can be easily miniaturized. Become. In addition, by concentrating the stress on the polycrystalline film or the amorphous film, the stress on the semiconductor substrate can be reduced, and the occurrence and progress of crystal defects can be suppressed.

According to the second aspect of the present invention, since the semiconductor substrate is mounted on the electrostatic chuck and anisotropic etching is performed,
In addition to making the depth and shape of the groove uniform, a conductive film is formed on the back side of the semiconductor substrate, and the potential of the electrode of the electrostatic chuck and the conductive film are formed when the semiconductor substrate is separated from the electrostatic chuck. And the potential of the semiconductor substrate is made substantially equal, so that the semiconductor substrate can be easily separated from the electrostatic chuck.

According to the invention of claim 3, both effects of the invention of claim 1 and the invention of claim 2 can be obtained. According to the fourth aspect of the present invention, since the stress on the semiconductor substrate can be reduced by concentrating the stress on the polycrystalline film, the generation and progress of crystal defects in the semiconductor substrate can be suppressed.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process according to the embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process according to the embodiment of the present invention.

FIG. 4 shows a part of the embodiment shown in FIGS. 1 to 3 in more detail;

FIG. 5 is a diagram showing a first applied example of the embodiment shown in FIGS. 1 to 3;

FIG. 6 is a diagram showing a second application example of the embodiment shown in FIGS. 1 to 3;

FIG. 7 is a diagram showing a third application example of the embodiment shown in FIGS. 1 to 3;

FIG. 8 is a diagram showing a conventional technique.

FIG. 9 is a diagram showing a conventional technique.

FIG. 10 is a diagram showing a problem of the related art.

FIG. 11 is a diagram showing a problem of the related art.

[Explanation of symbols]

 Reference Signs List 10: dielectric isolation substrate (semiconductor substrate) 11a: trench groove (second groove) 14, 15: silicon oxide film (first insulating film) 15a: first groove 16: polysilicon film (polycrystalline film, 17: silicon oxide film (second insulating film) 19: buried film 20: plasma etching apparatus 21: electrostatic chuck 22: electrode of electrostatic chuck

Claims (4)

[Claims] A step of forming a first insulating film having a first groove on a semiconductor substrate; a step of forming a polycrystalline film or an amorphous film on a side surface of the first groove; Forming a second groove in the semiconductor substrate substantially matching the first groove on which the crystalline film or the amorphous film is formed; and forming a second groove on the surface of the second groove and the polycrystalline film or the amorphous film. Manufacturing a semiconductor device, comprising: forming a second insulating film on a surface of the film; and forming a buried film in a second groove in which the second insulating film is formed. Method. 2. A step of mounting a semiconductor substrate having a conductive film formed on a back surface side on an electrostatic chuck of an etching apparatus; a step of forming a groove in the semiconductor substrate by anisotropic etching; Removing the semiconductor substrate, on which the groove is formed, from the electrostatic chuck by making the potential of an electrode substantially equal to the potential of the conductive film. 3. A step of forming a first insulating film having a first groove on an upper surface of a semiconductor substrate, and a polycrystalline film or an amorphous film on an upper surface side of the semiconductor substrate on which the first insulating film is formed. Forming a conductive film on the lower surface side of the semiconductor substrate, mounting the semiconductor substrate on which the conductive film is formed on an electrostatic chuck of an etching apparatus, and forming the first groove by anisotropic etching Selectively leave the polycrystalline film or the amorphous film on the side surface of the second groove and the second groove substantially aligned with the first groove in which the polycrystalline film or the amorphous film is formed.
Forming the groove on the semiconductor substrate; and setting the potential of the electrode of the electrostatic chuck equal to the potential of the conductive film, and separating the semiconductor substrate on which the second groove is formed from the electrostatic chuck. Forming a second insulating film on the surface of the second groove and on the surface of the selectively left polycrystalline film or amorphous film; and forming the second insulating film. Forming a buried film in the formed second groove. 4. A groove formed in a semiconductor substrate, a polycrystalline film or an amorphous film formed in a portion of the semiconductor substrate surface in contact with the groove, and a polycrystalline film or an amorphous film formed on a surface of the groove and the polycrystalline film or a non-crystalline film. A semiconductor device comprising: an insulating film formed on a surface of a crystalline film; and a buried film formed in a groove in which the insulating film is formed.