JPH10320271A - Microcomputer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer system capable of properly controlling access timing to a memory device. SOLUTION: The microcomputer system for accessing a memory at set access timing is provided with an access time detection circuit 3 for addressing a memory device 2 trying to execute access timing control immediately after turning on a power supply, sampling data on a data bus for a fixed period and detecting an access time by detecting a change in the states of two continuous sampled values from a non-coincident state to a coincident state and an access timing control part 4 for controlling access timing in accordance with the access time detected by the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system having a microprocessor and a memory device such as a ROM and a RAM, and more particularly to a microcomputer system capable of appropriately controlling access timing to a memory device.

[0002]

2. Description of the Related Art The access time of a memory device such as a ROM or a RAM used in a microcomputer system or the like varies depending on products. Therefore, generally, when designing a microcomputer system or the like, a memory device to be used is determined, and access timing to the memory device is set in accordance with the determined memory device. However, in the method of setting the access timing after determining the conditions of the memory device, it is impossible to change to a memory device having a slow access time after commercialization. Therefore, the memory access wait control circuit disclosed in Japanese Patent Application Laid-Open No. 2-83754 realizes different memory access wait times depending on the access time of the memory device by changing the width of the clock related to the memory access wait time. This solves the conventional problem as described above.

[0003]

However, in the prior art disclosed in Japanese Patent Application Laid-Open No. 2-83754, when changing the memory access wait time, the access time cannot be automatically detected, and the clock width cannot be automatically detected. Since the access timing is changed by changing the access timing, there is a problem that a variable range of the access timing is narrow, so that an appropriate access timing cannot be realized depending on a memory device. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the related art and to provide a microcomputer system capable of appropriately controlling access timing to a memory device.

[0004]

In order to solve the above-mentioned problems, according to the present invention, in a microcomputer system for performing memory access at a set access timing, an access time of a memory device is automatically set. An access time detecting means for detecting, and an access timing control means for controlling access timing according to the access time detected by the access time detecting means are provided. According to the second aspect of the present invention, in the above, immediately after power-on, a memory device for which access timing control is to be performed is addressed, and data on the data bus at that time is sampled at a constant cycle to obtain two consecutive sampling values. The access time detecting means is configured to detect that the state has changed from the non-match state to the match state and detect the access time. According to the third aspect of the present invention, in the above, the access timing control means is configured so that an access timing is the next sampling time when two consecutive sampled values change from a mismatched state to a matched state. According to a fourth aspect of the present invention, in the second aspect of the present invention, an access is made when two consecutive sampled values change from a non-coincidence state to a coincidence state and the coincidence state is detected two or more consecutive times. Time or access timing. According to the fifth aspect of the present invention,
5. The microcomputer system according to claim 4, further comprising data bus pull means for selectively pulling up and pulling down the data bus, and immediately after power-on, the data bus is pulled up or pulled down by said data bus pull means for access. When the operation for obtaining the time is started, and when two consecutive sampled values do not become inconsistent, the operation for obtaining the access time is started by changing the data bus pull state to the other state and starting the operation for obtaining the access time again. did. According to a sixth aspect of the present invention, in a microcomputer system for performing memory access at a set access timing, a nonvolatile memory device in which an access time is previously written at a predetermined address of the nonvolatile memory device; Access timing control means for controlling the access timing by reading the written access time. Further, in the invention according to claim 7, in the nonvolatile memory device, an access time is written to a predetermined address of the nonvolatile memory device at the time of manufacture.

[0005]

According to the first aspect of the present invention, the access timing to the memory device is appropriately controlled according to the detected access time.
According to the second aspect of the invention, immediately after the power is turned on, a memory device for which access timing is to be set is accessed, data on the data bus at that time is sampled at a constant cycle, and two consecutive sampled values are in a non-coincidence state. The access time is detected by detecting that a match has been reached from. According to the third aspect of the present invention, in the above, the access timing is set so that the next sampling time when two consecutive sampled values change from a non-coincidence state to a coincidence state. According to the fourth aspect of the present invention, an access time or an access timing is set when two consecutive sampled values change from a non-coincidence state to a coincidence state, and when the coincidence state is detected twice or more consecutively. You. According to the fifth aspect of the present invention, immediately after the power is turned on, the data bus is pulled up or down to start the operation for obtaining the access time, and when two consecutive sampled values do not become inconsistent, the data bus is pulled up. Is changed to the other state, and the operation for obtaining the access time is started again, whereby the access time is obtained. According to the present invention, the access time written in the ROM is read, and the access timing is automatically set according to the access time. According to the seventh aspect of the present invention, the access time of the ROM can be obtained by accessing a predetermined address of the ROM.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram of a first embodiment in which the present invention is applied to a microcomputer system. As shown in the figure, the microcomputer system of this embodiment includes a control unit 1 having a CPU (microprocessor) and the like, and a ROM for detecting an access time.
Or a memory device 2 such as a RAM, a memory device 2
Access time detection circuit 3 for detecting access time
(Access time detection means), an access timing control unit 4 (access timing control means) for setting access timing according to the detected access time, and controlling access to the memory device 2 according to the set access timing, and a power supply for the data bus. A selection switch 5 (data bus pull means) for pulling up to the voltage Vcc or pulling down to the ground (GND) is provided. Note that a configuration without the selection switch 5 is also possible. FIG. 2 shows details of the access time detection circuit 3 of the first embodiment. As shown in the figure, the access time detection circuit 3 includes flip-flops (hereinafter, referred to as F / Fs) 11, 12, F / Fs 11, 1 having an 8-bit configuration, for example.
A mismatch circuit 14, which outputs a signal B of a predetermined width when the coincidence signal A output from the comparator circuit 13 changes from High level (meaning coincidence) to Low level. A flag circuit 15 for storing that a mismatch is detected is provided, a match detection circuit 16 for outputting a signal CMPOK having a predetermined width when a second match is detected, and the like.

As shown in FIG. 3, the access timing control section 4 includes a load signal generation circuit 17 for outputting a load signal F having a predetermined width at the beginning of the read signal RD, an increment counter 18, a decrement counter 19,
A comparison circuit 20 and the like are provided. Note that RDB is an inverted signal of the read signal RD. FIG. 4 is a timing chart of the first embodiment without the selection switch 5, and FIG. 5 is an operation flowchart. Hereinafter, the operation of the first embodiment will be described with reference to FIGS. First, the microcomputer system is turned on (S1). Then, the control unit 1
Addresses the memory device 2 (addresses the access time check address) (see FIG. 4), starts reading (S2), and the RDB signal is Low.
Become a level. When the power is turned on, the control unit 1 outputs a system clock (hereinafter, referred to as a CLK signal), and data on the data bus is set in the F / F 11 by the first CLK signal (S3). Also, the next CL
The data set in F / F11 by the K signal becomes F / F11.
/ F12, and the data on the data bus at that time is set in F / F11 (S4). When the control unit 1 starts reading and the RDB signal, which is an inverted signal of the read signal RD, goes low, the load signal generation circuit 1 in the access timing control unit 4 starts at the beginning.
7, the load signal F is output, whereby the value of the increment counter 18 is set to 0. At this time, since the EN (enable) terminal of the increment counter 18 is at the low level, after the counter value is set to 0, the value of the counter 18 is set to 1 every time the CLK signal becomes high. Increase by one.

In this manner, sampling is performed at a constant period, and two consecutive sampling values set in the F / Fs 11 and 12 are compared by the comparison circuit 13 (S
5). Then, the two sampling values match, and the level of the output signal (signal A) of the comparison circuit 13 is High.
If the signal is at the h level (S5, Yes), the data set in the F / F11 and the data set in the F / F12 are compared by the next CLK, and the comparison circuit 13 which is the result of comparing these two sampled values is compared. Are determined (S6, S4, S5). The value of the data bus is
Re from the addressed address of the memory device 2
It does not change until ad data is output (see FIG. 4). However, after that, Read data
When a appears, at the beginning, two consecutive sampling values have different values (S5, No), and the mismatch detection circuit 14 outputs a positive signal B of a predetermined width. continue,
The next sampling is performed with the next CLK signal (S7),
The comparison with the previous sampling value is performed (S8).
Since the state where Read data appeared has been maintained,
Normally, this comparison result indicates a matching state (S8, Ye
s). Also, this CLK FLAG signal (signal C) is H
It becomes high level, and CMPOK becomes High by a predetermined width.
h level. If the matching state is not indicated due to a variation between bits (a plurality of bit data) (S8, No), the same is repeated in the next sampling (S8 → S9 → S7 → S8). In this way, the count-up of the increment counter 18 is completed, and the FLAG signal continues to be at the High level irrespective of the memory access thereafter. Therefore, the count-up and the load of the increment counter 18 are not performed. Is held as a value larger by one than the count value corresponding to the access time (S10). (When the count value is smaller than the final value of the increment counter 18 by one, Read data appears on the data bus. The value is a count value corresponding to the access time, and S10 in the flowchart is an expression taking this point into account.)

Next, the operation at the time of actual memory read access after the detection of the access time will be described with reference to FIGS. First, when reading is started, the RDB signal goes low. Then, at the beginning, the load signal F becomes Low level by a predetermined width, and the count value held in the increment counter 18 is loaded into the decrement counter 19 by the load signal F. Since then
During the readout period, since the EN terminal is at the low level, the decrement counter 19 is counted down by one each time the CLK signal goes to the high level. When the value becomes 1, the value of G shown in FIG. 1), the output signal H of the comparison circuit 20 becomes High level. The comparison circuit output signal H is output from the control unit 1
Is input to the Ready terminal of the CPU (see FIG. 1), and when the signal H becomes High level, the CPU fetches the Read data on the data bus. As shown in FIG. 4, the access timing T2 is a time shorter than T1 at the time of detecting the access time by t (one clock cycle), but at the time of detecting the access time, the data is at least one clock cycle shorter than T1. Since the read data appears on the bus, the read data appears on the data bus at the access timing T2.
Is appearing. In the above, the value of G input to the comparison circuit 20 may be set to 0. In this case, the access time or access timing is set to be longer by one clock cycle, and the margin of the access timing is increased by that amount. Thus, according to this embodiment, the access time is automatically set, and reading of the memory device 2 is performed at the set access timing.

FIG. 6 is an operation flowchart showing a second embodiment of the present invention. As shown, steps S11 to S19 of this embodiment are the same as steps S11 to S19 of the first embodiment (FIG. 5).
1 to S9, the description is omitted. In the subsequent step S20, the microcomputer system of this embodiment continuously performs another data sampling and compares the data with the data sampled immediately before (S21). Then, when they match again, that is, when they match twice in succession, the count value at the first sampling is set as the count value corresponding to the access time (S22). Thus, according to this embodiment, it is possible to prevent an accidental match due to noise or the like from being erroneously determined as Read data appearing on the data bus.

Next, a third embodiment provided with a selection switch 5 (see FIG. 1) will be described. In the claims, the data bus pull means indicates the selection switch 5. FIG. 7 shows the details of the selection switch 5, and FIG. 8 shows a block diagram of the configuration of the main part of the microcomputer system of this embodiment. As shown in FIG. 7, the selection switch 5 includes two transistors Tr1, Tr2 and an inverter 21.
When power is turned on, the inverter 21
Becomes high level, so that the transistor Tr1 is off and the transistor Tr2 is on. That is, each data line of n bits (n, for example, 8) is in a pull-down state. Less than,
The operation of this embodiment will be described with reference to the operation flow shown in FIG. First, the power is turned on (S31).
As a result, the data line enters a pull-down state (S
32). Hereinafter, steps S33 to S37 are the same as those in the first embodiment (the same as steps S2 to S5 in FIG. 5, and a description thereof will be omitted. If the determination in step S37 is a match (S37, Yes)),
If (FIG. 8) has not reached the timeout (S38,
No), the same comparison is performed with the next sampling value (S3).
9 → S36 → S37) (see FIG. 2). Note that the time-out counter 23 is, for example, clock
It is configured to count up by a signal and output a coincidence signal J when a predetermined number is reached. If two consecutive sampling values do not match before the timeout counter 23 reaches the timeout (S3).
7, No), and thereafter, operate in the same manner as in the first embodiment (see FIG. 5). That is, if the timeout does not occur, the access time is detected in the same manner as in the first embodiment, and the access timing control unit sets the access time of the memory device according to the detected access time.

On the other hand, if the power-on data of the access time check address of the memory device 2 is 0 and there is no change in data before and after Read data appears on the data bus (the data bus is pulled down). Therefore, the value of the data on the data bus before the appearance of Read data is 0), and after a predetermined time, the timeout counter 23 times out (S
38, Yes). Then, the interrupt generation circuit 24 (FIG. 8) generates an interrupt signal K to the CPU 22 in the control unit 1, whereby the CPU 22 sets the switch control signal L output to the selection switch 5 to Low level.
When the switch control signal L goes low, the transistor Tr1 is turned on and the transistor Tr2 is turned off, so that the data bus is pulled up (S40). Hereinafter, step S33 is repeated. Re
Since it is impossible that the read data is 0 and 1, when the data appears on the read data bus, the comparison result in step S 37 becomes inconsistent (S 37, No). It operates as in the embodiment. That is, if the data bus is not pulled up or pulled down, immediately after the power is turned on, the R read from the memory device 2 for detecting the access time is read.
The read data becomes the same as the data value on the data bus before the reading by chance, and in FIG. 5, S5 → S6 →
Although the possibility of continuing the loop of S4 → S5 forever cannot be denied, if switching between pull-up and pull-down is performed as in this embodiment, the Read read from the memory device 2 for access time detection should be performed. d
Even if “ata” is the same value as the data value on the data bus before reading, the data value on the data bus is changed by switching between the pull-up and the pull-down, so that the problem of continuing the loop can be avoided.

In the fourth embodiment of the present invention shown in FIG. 10, when the memory device 2 is a nonvolatile semiconductor, the access time of the memory device 2a is measured at the time of manufacture, and the predetermined address (access time Check time) is recorded in the access time. Then, such a memory device 2a is mounted on the microcomputer system of this embodiment, and when the power is turned on, the control unit 1 reads an access time recorded from a predetermined address of the memory device 2a, and The value N obtained by dividing the time by the clock cycle is stored in the latch 25, and is stored in the latch 25 by the load signal F output from the load signal generation circuit 17 at the beginning of each read from the memory device 2a. The set value N is set in the decrement counter 19. As described above, according to this embodiment, the first time without the access time detecting circuit 3 shown in FIG.
The same effects as those of the embodiment can be realized.

[0014]

As described above, according to the present invention,
According to the first aspect of the present invention, since the access timing to the memory device is appropriately controlled according to the detected access time, it is possible to access the memory device at an appropriate access timing without any trouble for the user. In addition, setting errors by the user can be prevented. According to the second aspect of the present invention, immediately after the power is turned on, the memory device for which access timing is to be set is accessed, and the data on the data bus at that time is sampled at a constant cycle. Since the access time is detected by detecting the change from the mismatched state to the matched state, more appropriate access timing can be realized. According to the third aspect of the present invention, in the above, the access timing is set so that the next sampling time when two consecutive sampled values change from a mismatched state to a matched state becomes the access timing.
The establishment of the read data becomes more reliable. In the invention according to claim 4, two consecutive sampling values are changed from a non-coincidence state to a coincidence state, and the time when the coincidence state is detected two or more times consecutively becomes an access time or an access timing. Since it is set, it is not necessary to judge the access time due to noise or the like.
According to the fifth aspect of the present invention, immediately after the power is turned on, the data bus is pulled up or pulled down to start an operation for obtaining an access time, and when two consecutive sampled values do not become inconsistent, the data bus is turned off. Since the access state is obtained by changing the pull state to the other state and starting the operation for obtaining the access time again, the danger of falling into a permanent loop upon detection of the access time can be prevented. In the invention according to claim 6, the access time written in the ROM is read and the access timing is automatically set according to the access time, so that the effects of claim 1 and the like can be realized more easily. . In the invention according to claim 7, R
By accessing a predetermined address of the OM, the R
OM access time can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microcomputer system according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a microcomputer system showing a first embodiment of the present invention.

FIG. 3 is another circuit diagram of a main part of the microcomputer system showing the first embodiment of the present invention.

FIG. 4 is a timing chart of a main part of a microcomputer system showing a first embodiment of the present invention.

FIG. 5 is an operation flowchart of the microcomputer system showing the first embodiment of the present invention.

FIG. 6 is an operation flowchart of a microcomputer system showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part of a microcomputer system showing a third embodiment of the present invention.

FIG. 8 is a configuration block diagram of a main part of a microcomputer system showing a third embodiment of the present invention.

FIG. 9 is an operation flowchart of a microcomputer system showing a third embodiment of the present invention.

FIG. 10 is a configuration block diagram of a main part of a microcomputer system showing a fourth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control part, 2 ... Memory device, 3 ... Access time detection circuit, 4 ... Access timing control part, 5 ... Selection switch, 13 ... Comparison circuit, 1
4 ... mismatch detection circuit, 15 ... flag circuit, 16
... match detection circuit, 17 ... load signal generation circuit,
18: increment counter, 19: decrement counter, 20: comparison circuit, 23: timeout counter

Claims (7)

[Claims] In a microcomputer system for performing memory access at a set access timing, an access time detecting means for automatically detecting an access time of a memory device, and an access according to the access time detected by the access time detecting means. A microcomputer system comprising: access timing control means for controlling timing. 2. The microcomputer system according to claim 1, wherein immediately after the power is turned on, a memory device for which access timing control is to be performed is addressed, and data on the data bus at that time is sampled at a constant cycle, and two successive samplings are performed. A microcomputer system comprising an access time detecting means for detecting an access time by detecting that a value has changed from a mismatched state to a matched state. 3. The microcomputer system according to claim 2, wherein the access timing control means is configured such that an access timing is a next sampling time when two consecutive sampling values change from a mismatched state to a matched state. Microcomputer system. 4. The microcomputer system according to claim 2, wherein a time when two consecutive sampled values change from a non-coincidence state to a coincidence state and the coincidence state is detected twice or more consecutively is an access time or an access timing. A microcomputer system characterized in that: 5. The microcomputer system according to claim 2, further comprising data bus pull means for selectively performing pull-up and pull-down of a data bus, said data bus pull means being provided immediately after power-on. Means for pulling up or pulling down the data bus to start an operation for obtaining an access time, and when two consecutive sampled values do not become inconsistent, change the data bus pull state to the other state and reset the access time. A microcomputer system wherein an access time is obtained by starting a desired operation. 6. A microcomputer system for performing memory access at a set access timing, wherein a nonvolatile memory device in which an access time is previously written at a predetermined address of the microcomputer, and an access written in the nonvolatile memory device. A microcomputer system comprising: an access timing control unit that reads out time and controls access timing. 7. The nonvolatile memory device according to claim 1, wherein an access time is written to a predetermined address of the nonvolatile memory device during manufacturing.