JPH10319897A - Image magnifying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display an image of VGA the number of lines and the number of pixels per one line of which are 480 and 640 respectively on a screen of a liquid crystal projector which conforms to the SVGA of 600 pixels long and 800 pixels wide without using a frame memory and lowering illuminance. SOLUTION: Image signals are digitalized by an A/D converter 1; written into line memory 2 one line each; the first line and the second line are read out with the double speed of write in the write period of the second line; the data is switched in the order of the first line from the A/D converter, the first line from the line memory, and the second line by a selector 3; two lines are magnified to three lines; and applied to a D/A converter 4. This signal is held by one pixel by one pixel in a sample-and-hold circuit and the first pixel, the fourth pixel, the seventh pixel... are two times each outputted to expand three pixels to four pixels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image enlargement circuit, and more particularly to a VGA (480 horizontal lines, 1 pixel per horizontal line).
640) video is SVGA compatible (vertical 600 pixels, horizontal 800
(Pixel) and a liquid crystal panel using a liquid crystal panel to display the image completely on the screen of the projector.

[0002]

2. Description of the Related Art A VGA image having 480 horizontal lines and 640 pixels per horizontal line is 600 pixels vertically and 80 pixels horizontally.
When displayed on the screen of a 0-pixel SVGA-compatible liquid crystal projector, the size of the image is approximately 64% of the screen area (both horizontal and vertical pixels are approximately 80% of the display area)
Then, the remaining part becomes no image. In order to display this image on the full screen, for example, optically enlarge,
Alternatively, there is a method of performing frequency conversion by calculation, but there is a problem that the brightness of an image is reduced in inverse proportion to the magnification when optically enlarged. There is a problem that a memory or the like is required and the cost increases.

[0003]

SUMMARY OF THE INVENTION In view of the foregoing, the present invention is directed to a projector such as a projector using an SVGA-compatible liquid crystal panel for displaying a VGA image without using a frame memory or the like without a decrease in luminance. It is to enlarge the image so that it is displayed on the full screen.

[0004]

According to the present invention, there is provided a line memory for storing an input video signal, and a selector for switching the input video signal or a video signal read from the line memory. A sample and hold circuit for sampling and holding the video signal from the selector, and a display control unit for controlling the writing and reading of the line memory, the selector, and the sample and hold circuit. The number of horizontal lines is increased by switching the selector. It is another object of the present invention to provide an image enlargement circuit in which the number of pixels in each horizontal line is enlarged by a sample and hold circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an image enlargement circuit according to the present invention,
The input video signal is converted into a digital signal by an A / D converter, and is sequentially written into a line memory by one horizontal line (hereinafter, referred to as a line). During writing, the first line and the second line are sequentially read at twice the speed of writing, and the second line is read.
In the frame No. 2 during writing during the writing of the third line,
The second line and the third line are sequentially read out at twice the speed, and the first line from the A / D converter, the first line from the line memory, and the second line in the first frame via the selector in the first frame. , And in the second frame, the second line from the A / D converter, the second line from the line memory, and the third line, and the two lines are expanded to three lines. I do. The signal from the selector is converted into an analog signal by a D / A converter, and each pixel of each line is sampled and sequentially held by a sample-and-hold circuit, and every three pixels, the first pixel in the first frame Is repeated twice, and in the second frame, the second pixel is continuously output twice, and three pixels are enlarged to four pixels. A signal synchronized with the horizontal synchronization signal input together with the video signal is P
It is generated by the LL circuit, and controls writing and reading of the line memory and switching of the selector via the display control unit (CRTC) to control the sample and hold circuit.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image enlargement circuit according to the present invention; FIG. 1 is a block diagram of a main part of an embodiment of a video enlargement circuit according to the present invention. In the figure, reference numeral 1 denotes an A / D converter, which converts red (R), green (G), and blue (B) video signals into digital signals. Reference numeral 2 denotes a line memory for writing a signal from the A / D conversion unit 1 line by line and performing reading at twice the speed of writing. 3
Is a selector for switching between data from the A / D converter 1 and data from the line memory 2. Reference numeral 4 denotes a D / A converter, which converts a signal from the selector 3 into an analog video signal. Reference numeral 5 denotes a sample-and-hold circuit, which enlarges the number of pixels based on the video signal from the D / A converter 4 and
The required number of pixels are held and output to the liquid crystal panel. 6
Is a PLL circuit that generates a clock synchronized with a horizontal synchronization signal (H-sync) input together with a video signal. Reference numeral 7 denotes a display control unit for controlling a write / read control signal of the line memory 2, a switching signal of the selector 3, a control signal of the sample and hold circuit 5, and a horizontal register of the liquid crystal panel based on a clock from the PLL circuit 6. Clock H-CK,
The clock V-CK for controlling the vertical register is output.

Next, the operation of the image enlargement circuit according to the present invention will be described. A VGA video signal having 480 lines and 640 pixels per line and separated into red (R), green (G) and blue (B) is input to the A / D converter 1 and converted into a digital signal. , One line at a time. This writing is performed by the write CLK from the display control unit 7 shown in FIG. 2, the written signal is read by the read CLK at twice the speed of the write, and the selector 3 outputs the signal from the A / D conversion unit 1. And is input to the D / A converter 4.

When a line (first line of VGA) is written into the line memory 2 as in the example of the first frame shown in FIG. 2 by writing / reading of the line memory 2 and switching of the selector 3, for example. At the same time, the data is output via the selector 3 and then the line written in the line memory 2 is read at double speed. At the same time, the line (second line) is written and the line is read at the same speed. That is, as shown in FIG. 3, one line is output twice in units of two lines, thereby expanding two lines to three lines. In the second frame, the line is written to the line memory 2 and output via the selector 3 at the same time. Subsequently, the line written to the line memory 2 is read at double speed, and at the same time, the line (third line ) Is written, and the line is read at the same speed following the line. When the first frame and the second frame having the increased number of lines are overlapped in this manner, the images of the two frames are integrated as shown in FIG. 3 due to the afterimage effect of the eyes, and the first line L1 of the SVGA is VGA. Line, SV
The second line L2 of the GA is the average value of the VGA lines, the third line L3 is the VGA line, and so on.

The R, G, and B video signals converted to analog by the D / A converter 4 are input to a sample-and-hold circuit 5, where each pixel of each line is sampled by a control signal from a display controller 7, and Then, one pixel is output twice for every three pixels, for example, as a first pixel, a fourth pixel, a seventh pixel,..., Thereby expanding three pixels to four pixels. Then, as shown in FIG. 4, in the first frame, the pixel, pixel, pixel,... Are output twice as described above, and in the second frame, the pixel, pixel, pixel,. When the first frame and the second frame are overlapped, the image of the two frames is integrated as shown in the lower part of FIG. 4 due to the afterimage effect of the eyes, and the first pixel of the SVGA is a VGA.
Pixel, the second pixel is the average value of the VGA pixel and the pixel, and the third to fifth pixels are the VGA pixels
The pixel and the sixth pixel are set to have an average value of the VGA pixel and the pixel, and so on.

The video signal from the sample and hold circuit 5 is sent to a liquid crystal panel. The liquid crystal panel drives a horizontal counter by H-CK from a display control unit 7 to control the display position of each pixel in the horizontal direction. The vertical counter is driven by -CK to control the display position of each line in the vertical direction, whereby the image enlarged to SVGA is displayed on the screen of the liquid crystal projector in the full screen.

[0011]

As described above, according to the image enlargement circuit of the present invention, horizontal lines and pixels are interpolated using the afterimage effect of the eye to enlarge the image, and the VGA image is converted to an SVGA-compatible image. Since the image is displayed on the entire screen of the liquid crystal projector, it can be implemented relatively inexpensively without the need for a frame memory or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an embodiment of an image enlargement circuit according to the present invention.

FIG. 2 is a time chart for expanding the number of lines of the video enlargement circuit according to the present invention.

FIG. 3 is a diagram for explaining an enlargement of the number of lines of a video enlargement circuit according to the present invention.

FIG. 4 is a diagram for explaining the enlargement of the number of horizontal pixels of the video enlargement circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 Line memory 3 Selector 4 D / A conversion part 5 Sample hold circuit 6 PLL circuit 7 Display control part

Claims (7)

[Claims] 1. A line memory for storing an input video signal, a selector for switching to an input video signal or a video signal read from the line memory, and a sample and hold circuit for sampling and holding the video signal from the selector. A display control unit for controlling writing / reading of the line memory, a selector, and a sample hold circuit. The number of horizontal lines is expanded by switching the selector, and each horizontal line is sampled and held by the sample hold circuit. An image enlargement circuit that enlarges the number of pixels. 2. An A / D converter is provided in a stage preceding the line memory to convert a video signal into a digital signal, and a D / A converter is provided in a stage subsequent to the selector to convert a signal from the selector into an analog video signal. 2. The video enlarging circuit according to claim 1, wherein said image enlarging circuit is adapted to convert the image into an image. 3. A PLL circuit for generating a signal synchronized with a horizontal synchronization signal input together with the video signal,
3. The image enlarging circuit according to claim 1, wherein each unit is controlled via the display control unit by a signal from an L circuit. 4. A video signal input to the line memory is sequentially written one horizontal line at a time, and for every two horizontal lines,
The first horizontal line and the second horizontal line are sequentially read at twice the writing speed during the writing of the second horizontal line, and the two horizontal lines are enlarged to three horizontal lines. The video enlarging circuit according to claim 2 or 3. 5. A video signal input to the line memory is sequentially written one horizontal line at a time, and every two horizontal lines,
In the first frame, during the writing of the second horizontal line, the first horizontal line and the second horizontal line are sequentially read at twice the writing speed, and during the writing of the third horizontal line in the second frame. 4. The method according to claim 1, wherein the second horizontal line and the third horizontal line are sequentially read out at twice the writing speed, and the two horizontal lines are enlarged to three horizontal lines. Image magnification circuit. 6. The sample and hold circuit samples and holds each pixel of each horizontal line and sequentially holds the sampled data.
6. The image enlargement circuit according to claim 1, wherein one pixel is output twice for each pixel, and three pixels are enlarged to four pixels. 7. The sampling and holding circuit samples and holds each pixel of each horizontal line and sequentially holds the sampled data.
For each pixel, the first frame is followed by the first pixel for 2
6. The video enlargement circuit according to claim 1, wherein the second pixel is output twice in succession and in the second frame, and three pixels are enlarged to four pixels.