JPH10319063A - Capacitance variation detecting device, and integrator used for the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitance variation detecting device which has a simple structure, dose not require a condition that difference between standard capacity and sensor capacity must be positive, and easily provides capacity ratio of two sensor capacities which are conventionally derived with a complex process, and to provide an integrator adequate to it. SOLUTION: The device consists of an integrator 12 which has one of two kinds of electrostatic capacitance C1, C2 which vary depending on physical quantity and chemical quantity of a detected object as a part of its constant, a selecting circuit 15 which selects one of two kind of electrostatic capacitance C1, C2 depending on value of output voltage of the integrator, and sets it as an element of the integrator, feedback circuits 13, 14 which are placed between an output part and an input part of the integrator, and an output circuit 11 which converts output from the integrator to rectangular wave, and outputs a rectangular wave signal which has duty ratio determined by the ratio of the two kinds of electrostatic capacitance C1, C2 from the output circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection device for detecting or measuring a change in capacitance.

[0002]

2. Description of the Related Art Conventionally, a capacitance type sensor is known as a device for detecting or measuring a change in capacitance.
As an interface circuit for generating a detection signal, an oscillation circuit using a capacitance type sensor as a frequency determining element is often used.

Assuming that the oscillation frequency of this circuit is ω, the capacitance of the sensor is C, and the rate of change of the capacitance is ΔC, the oscillation frequency ω
Changes according to the capacitance C, and the rate of change is expressed as follows.

[0004]

(Equation 1) The oscillation frequency (ω) of an oscillation circuit including a conventional capacitive sensor is determined by the total capacitance (C _S = C _B + ΔC) of the sensor. Here, the electrostatic capacity at C _B is in the reference state where there is a sensor (base capacitance), [Delta] C is the amount of change in electrostatic capacitance. For this reason, when the variation (ΔC) is smaller than the total capacitance (C _S ) of the sensor, the variation of the oscillation frequency is also smaller. This narrows the dynamic range of capacitance measurement, making it difficult to achieve high accuracy. In addition, error factors such as parasitic capacitance and stray capacitance also pose a problem.

[0005] In order to solve such problems,
A differential capacitance inverting integrator having a difference between the capacitance (C _S ) of a detector having a capacitance corresponding to a physical quantity or a stoichiometry of a detection target and a reference capacitance (C _r ) as a part of a constant. And an oscillation circuit for determining an oscillation frequency based on a difference between these electrostatic capacitances has been invented, and a patent application has been filed by the present applicant (Japanese Patent Application Laid-Open No. H08-208,1992). −
No. 62266). The differential-capacitance inverting integrator used in this detection device grounds the input terminal on the (+) side of the operational amplifier and connects a resistor to the input terminal on the (-) side to connect the output terminal of the operational amplifier to the (-). A reference capacitor (C _r ) and a sensor capacitor (C _S ) connected in series to an inverting amplifier (gain = −k) are connected in parallel as feedback elements between the input terminals on the side. With this configuration,
The integrator has a reference capacitance (C _r) and the sensor capacitance (C _S) the difference between (C _S -kC _r) an integrator part of a constant.

[0006]

However, an electrostatic capacitance change amount detecting device including such a differential capacitance inverting integrator is disclosed in US Pat.
Since the feedback element of the differential capacitance inverting integrator includes an inverting amplifier, the configuration becomes complicated and the reference capacitance (C _r )
The difference between the sensor capacitance _{(C S) (C S -kC} r) there has been a problem that does not work if a positive value.

Further, in order to detect a change in capacitance, two sensor capacitance _{^{(C S +, C S -}} ) divided into, one of the sensor capacitance (C _S ⁺⁾ is increased, the other sensor capacity (C _S ^-)
There has also been proposed a method of using two sensors configured to reduce the capacitance ratio of the two sensors. In this case, two analog switches and a second reference capacitance (C _C ) are provided for the two capacitances, and two types of oscillation outputs are generated from the oscillation circuit by a switching signal of the analog switches. The ratio of the oscillation output corresponding to the difference between the two capacitances is detected by dividing the type of oscillation output by the digital signal processing circuit. However, in this method, two sensors capacitance _{^{(C S +, C S -}} ) signal processing for obtaining the capacity ratio is disadvantageously complicated.

An object of the present invention is to simplify the configuration, eliminate the condition that the difference between the reference capacitance and the sensor capacitance must be a positive value, and further reduce the capacitance of the two sensor capacitances conventionally obtained by complicated processing. An object of the present invention is to provide a capacitance change amount detecting device capable of easily obtaining a ratio and an integrator suitable for the device.

[0009]

According to the capacitance change amount detecting apparatus of the present invention, one of two capacitances which change according to a physical quantity and a chemical quantity to be detected is made a part of a constant. An integrator and two in accordance with the value of the output voltage of the integrator.
A selection circuit that selects one of the two capacitances to be an element of an integrator, a feedback circuit provided between an output section and an input section of the integrator, and converts the output of the integrator into a square wave And a rectangular wave signal having a duty ratio determined by a ratio of the two capacitances.

[0010] In a more specific mode, the feedback circuit includes:
It comprises an inverting adder for inverting and adding the output of the integrator, and a comparator for comparing the output of the inverting adder with its own output. The output of this comparator is used as the input of the integrator.

According to another aspect of the present invention, there is provided an integrator in which one of two capacitances that change according to a physical quantity and a chemical quantity of a detection target is a part of a constant, and an output voltage of the integrator. A selection circuit that selects one of the electrostatic capacities according to the value of the integrator and uses it as an element of the integrator; an inverting adder that inverts and adds the output of the integrator; A first comparator for comparing the output of the inverting adder with an output of the first comparator; an output of the first comparator and an output of the second comparator. And an output circuit that takes the exclusive OR of the two and determines the output from the first comparator as an input to the integrator, thereby determining from the output circuit the ratio of the two capacitances. A rectangular wave signal having a pulse width is output.

In the above configuration, the two capacitances are:
It is preferable that one capacitance increases and the other capacitance decreases so that the sum of the two capacitances becomes a constant value.

An integrator according to the present invention comprises: two capacitances that change according to a physical quantity and a chemical quantity of a detection target; and an integration circuit that makes one of the two capacitances a part of a constant. And a selection circuit that selects one of the two capacitances according to the value of the output voltage of the integration circuit and uses it as an element of the integration circuit.

The selection circuit includes, for example, two diodes connected between two capacitances and an output terminal of the integration circuit. In this case, the two diodes are connected in opposite directions, and when the integrator circuit outputs a negative voltage, one of the capacitances is selected. When the integrator circuit outputs a positive voltage, the other diode is selected. It is configured to select the capacitance.

[0015]

In the capacitance change amount detecting device according to the present invention, the selecting circuit selects two values according to the value of the output voltage of the integrator.
Either one of the two capacitances is alternately selected and becomes an integral element. For this reason, since the integrator outputs a vibration waveform corresponding to the ratio of the two capacitances, the output circuit converts the vibration waveform into a rectangular wave to have a duty ratio corresponding to the ratio of the two capacitances. A square wave signal is obtained.

According to another aspect of the present invention, a rectangular wave signal whose pulse width is determined by a ratio of two capacitances that change according to a physical quantity and a chemical quantity of a detection target is obtained.

In the above configuration, when one of the two capacitances increases and the other decreases, the sum of the two capacitances becomes a constant value. Since the frequency of the rectangular wave is constant, subsequent signal processing is facilitated.

Further, according to the integrator of the present invention, one of the two capacitances can be selected as an element of the integration circuit according to the output voltage of the integration circuit.

According to the present invention, a circuit for performing ratiometric signal processing with a simpler configuration is provided as an interface circuit for generating a detection signal from a capacitance type sensor. Although this circuit is basically a relaxation oscillator, the conventional one detects a change in capacitance by frequency, while the present invention detects a change in capacitance by a duty ratio. Therefore, signal processing in the time domain becomes possible, and the measurement is speeded up. The details will be described below.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a differential capacitance type sensor is represented by an equivalent circuit composed of _two capacitances (capacitors) C ₁ and C ₂ connected through a common electrode. In a one-dimensional displacement sensor in which the capacitance changes linearly in response to the displacement x of the detection target, the two capacitances C ₁ , C
₂ is represented by the following equation.

[0021]

(Equation 2) Here, C ₀ is the total capacitance of the detector. on the other hand,
In the differential pressure detecting device, since the distance between the electrodes changes linearly in accordance with the pressure difference x, the capacitances C ₁ and C ₂ are represented by the following equations.

[0022]

(Equation 3) If the change in capacitance is linear as in equation (1),
In either hyperbolic case as in the equation (2), the measured value x detected by the sensor is expressed by the following equation independent of the total value C _{0 of the} capacitance, and changes ratiometrically.

[0023]

(Equation 4) Embodiment 1 FIG. 2 shows a circuit configuration of an apparatus for detecting a change amount of _two capacitances C ₁ and C ₂ . This circuit includes an oscillation circuit 10 and an output circuit 11. The oscillation circuit 10 includes an integrator 12,
It comprises an inverting adder 13 and a comparator 14. Here, the inverting adder 13 and the comparator 14 constitute a feedback circuit,
By feeding back the output of the comparator 14 to the integrator 12, a relaxation oscillation circuit is formed.

The integrator 12 includes an operational amplifier A ₁ and a resistor R
_t , two capacitances C ₁ and C ₂ , and two diodes D ₁ and D _2. The (+) input terminal of the operational amplifier A ₁ is grounded and the (−) input terminal is connected to Resistance R
Connect the _t, and an output terminal of the operational amplifier A ₁ (-) between the side of the input terminal, a feedback element, the capacitance C ₁ is connected to the anode side of the diode D ₁ and the diode cathode of D ₂ it is obtained by constituting a capacitance C ₂ which is connected to the side connected in parallel. Two diodes D
By connecting ₁ and D ₂ in this manner, a selection circuit 15 that selectively switches between the _two capacitances C ₁ and C ₂ is configured. The integrator 12 conducts one of the two diodes D ₁ and D _{2 in} a conductive state by its own output, and electrically connects to _{one of the} capacitances C ₁ and C _2. Generate Note that the diodes D ₁ and D ₂ are ideal, and the voltage drop of the diodes themselves can be ignored. Here, the current flowing through the resistor R _t is I ₁ , the output voltage of the operational amplifier A ₁ is V ₁ ,
The potential at the connection point between the capacitance C ₁ and the diode D ₁ is represented by V _C1 ,
Let V _C2 be the potential at the connection point between the capacitance C ₂ and the diode D ₂ .

The summing amplifier 13 includes an operational amplifier A _2, and resistors _{R 1, R 2, R 3} , operational amplifier A ₂ (+)
The input terminal on the side is grounded, the resistors R ₁ and R ₂ are connected to the input terminal on the (−) side, and the resistor R ₃ is connected between the output terminal of the operational amplifier A _{2 and} the input terminal on the (−) side. It is configured. The other terminal of the resistor R ₁ is connected to the capacitance C ₁ of the integrator 12, the other terminal of the resistor R ₂ is connected to the capacitance C ₂ of the integrator 12. The summing amplifier 13 has a weight (-1) the value of the resistor R _1, R _2, R ₃ by all equal. Also, since the diodes D ₁ and D ₂ of the selection circuit 15 do not become conductive at the same time,
The inverting adder 13 operates as an inverting voltage follower. Here, the operational amplifier A ₂ (-) potential side of the input terminal and V _2.

The comparator 14 comprises an operational amplifier A ₃ and a resistor R
_4, and a R _5. Of the operational amplifier A ₃ (-) while connecting the terminal to the output terminal of the operational amplifier A ₂ of the summing amplifier 13, the resistors R ₄ and R ₅ are connected in series to the output terminal, to ground the resistor R _5. By connecting the connection point of the resistors R ₄ and R ₅ in (+) input terminal of the operational amplifier A _3, comparator 14 operates as a hysteresis comparator having a threshold voltage V _d, V _u. Here, the potential of the input terminal on the (−) side of the operational amplifier A ₃ is set to V ₃ , and the resistance R ₄
And the potential at the connection point of R ₅ and V _4.

The output circuit 11 includes an operational amplifier A ₄ ,
Its (-) while grounding the input terminal side, (+) by connecting the input terminal side to the output terminal of the operational amplifier A ₁ of the integrator 12 converts the signal waveform of the oscillation circuit into a digital signal Output. Here, the digital signal output terminal of the operational amplifier A ₄ and V _5.

The oscillation circuit 10 in FIG.
The positive and negative states of the input V ₄ and output V ₁ voltages
It is divided into four states T _i (i = 1, 2, 3, 4).
3A to 3D show equivalent circuits of the integrator 12 in each state,
FIG. 4 shows the waveform of each part.

In FIG. 3, the T ₁ state is V ₄ = V _u ,
V ₁ > 0. In this state, the diode D ₂
Is conducting, V _C2 = V ₁ , and the capacitance integrated by the integrator 12 is C ₂ . When the output of the comparator 14 is in the H state (V
₄ = In V _u), and when the output V ₁ of the operational amplifier A ₁ is positive, (as shown in a), the electrostatic capacitance C through resistor R _t
Discharge ₂ charge. Charge of the capacitance C ₂ is varied by a current I ₁ flowing through the resistor R _t, the output V ₁ of the operational amplifier A ₁ is reduced. If the initial voltage of the capacitance C ₂ and V _d, the period of T ₁ state is from the time of V ₁ = V _d until V ₁ = 0.

As shown in FIG. 4, the output V ₁ of the operational amplifier A ₁ decreases linearly. This operation is performed by the operational amplifier A ₁
Output V ₁ is becomes 0, until the diode D ₂ is cut (non-conductive) state. T ₁ period of the state is as follows.

T ₁ = C ₂ R _t V _d / V _u (4) When the output V ₁ of the operational amplifier A ₁ decreases to 0 or less,
State is switched from T ₁ to T _2. The moment of state switching, the diode D ₂ is disconnected, the diode D ₁ becomes conductive. In this state, V _C1 = V ₁ , and the capacitance integrated by the integrator 12 is C ₁ . Where V
₄ = _Vu remains. Therefore, the output V ₁ of the operational amplifier A ₁ continuously decreases with time. The duration of this T ₂ state is from the time of V ₁ = 0 until V ₁ = -V _u.

As shown in FIG. 3B, in the T ₂ state,
The integrator 12 is charged with a charge to the capacitance C ₁ through resistor R _t. The output V ₁ of the operational amplifier A ₁ continuously decreases until it reaches the threshold voltage −V _u of the comparator 14. T
_{The two} states are as follows.

T ₂ = C ₁ R _t (5) The period of the T ₂ state is not related to the voltage. Because
This is because the integrator is driven by the threshold voltage of the comparator. Threshold voltage -V _u of the output V ₁ is comparator 14 of the operational amplifier A ₁
Upon reaching, the output V ₄ of the comparator is switched -V _d, and the condition of T ₂ to T _3. In this state, V ₁ <0,
The diode D ₁ is conducting, V _C1 = V ₁ , and the capacitance integrated by the integrator 12 is C ₁ . The integrator 12 discharges the charge of C ₁ through resistor R _t, the output V ₁ of the operational amplifier A ₁ is increased. T ₃ period of state, V ₁ = -V _u
From the time of ( ₁₎ until V ₁ = 0.

As shown in FIG. 3 (c), the integrator 12 in this state will discharge the C _1. This operation continues until the output V ₁ of the operational amplifier A ₁ becomes 0 and the diode D ₁ is turned off. T ₃ period is as follows.

T ₃ = C ₁ R _t V _u / V _d (6) When the output V ₁ of the operational amplifier A ₁ increases and becomes a positive voltage, the state switches from T ₃ to T ₄ . The moment of state switching, the diode D ₁ is disconnected, the diode D ₂ becomes conductive. In this state, V _C2 = V ₁ and the capacitance integrated by the integrator 12 is C ₂ . However, V ₄
= Remains of -V _d. Therefore, the output V ₁ of the operational amplifier A ₁ is gradually increased with time. The duration of this T ₄ state is from the time of V ₁ = 0 until V ₁ = V _d.

As shown in FIG. 3 (d), the integrator 12 in this state to charge the capacitance C _2. Output V ₁ of the operational amplifier A ₁ is increases continuously until it reaches the voltage V _d. The period of T ₄ state is as follows. As in the period T ₂ state, period T ₄ state also does not change the voltage.

T ₄ = C ₂ R _t (7) The oscillation waveform thus obtained is converted into a digital signal V ₅ by the output circuit 11 including the operational amplifier A ₄ . Operational amplifier A ₄ serves to convert the triangle wave oscillation waveform into a rectangular wave. The period of H level of the digital signal V ₅ T _H,
Assuming that the L-level period is T _L , these are given by the following equations.

T _H = T ₁ + T ₄ = C ₂ R _t (V _u + V _d ) / V _u (8) T _L = T ₂ + T ₃ = C ₁ R _t (V _u + V _d ) / V _d . (9) Therefore, the duty ratio D is as follows.

[0039]

(Equation 5) If V _u = V _d, then ε _V = 0, and the duty ratio D exactly represents the capacitance ratio between the _two capacitances C ₁ and C ₂ . The duty ratio D, by gating the RF clock digital signal V ₅ as a gate signal can be easily detected (measured). For example, by providing a counter circuit at the subsequent stage, the duty ratio D can be converted into a numerical value. In addition, this measurement is based on a one-cycle digital signal V
Complete with ₅ outputs. To obtain the analog value may If you put a low-pass filter into a digital signal V _5.

As described above, according to the circuit shown in FIG. 2, high-speed signal processing for differential capacitance detection is possible.

Embodiment 2 In Embodiment 1 described above, the two diodes D ₁ and D ₂ constituting the selection circuit 15 are ideal. However, in an actual circuit, it is often the case that this is not the case. Become. Other causes of the non-linear error include a mismatch between the threshold voltages V _u and V _d of the comparator 14 and a slew rate (sl
ew rate), response delay, and offset voltage of the operational amplifier.

Therefore, as a second embodiment, the capacitance change amount which can remove the error caused by the diodes D ₁ and D ₂ and the non-linear error caused by the mismatch between the threshold voltages V _u and V _d of the comparator 14 can be eliminated. The detection device will be described.

FIG. 6 shows the circuit configuration. This is to remove the error due to mismatch in the threshold voltage V _u and V _d of the comparator 14, focusing on the state of the T ₂ and T ₄ having the period that does not vary by the voltage as described above, in this state It is configured as an interface circuit that extracts only signals. This circuit is configured by changing the comparator 14 in the oscillation circuit 10 of the first embodiment to a first comparator 16, and further adding a second comparator 17 and an output circuit 18.
The first comparator 16 is obtained by modifying the comparator 14 in order to extract the voltage used in the second comparator 17. Therefore, the oscillation circuit 10 is composed of the integrator 12, the inverting adder 13, and the first comparator 16, and the output of the first comparator 16 is fed back to the integrator 12 to constitute a relaxation oscillation circuit. .

The integrator 12 includes an operational amplifier A ₁ and a resistor R
_t , two capacitances C ₁ and C ₂ , and two diodes D ₁ and D _2. The (+) input terminal of the operational amplifier A ₁ is grounded and the (−) input terminal is connected to Resistance R
Connect the _t, and an output terminal of the operational amplifier A ₁ (-) between the side of the input terminal, a feedback element, the capacitance C ₁ is connected to the anode side of the diode D ₁ and the diode cathode of D ₂ It is configured such that the capacitance C ₂ connected to the side is connected in parallel. By connecting the _two diodes D ₁ and D ₂ in this manner, a selection circuit 15 for selecting the _two capacitances C ₁ and C ₂ is configured. The integrator 12 makes one of the two diodes D ₁ and D ₂ conductive by its own output, and is electrically connected to _{one of the} capacitances C ₁ and C ₂ to output the integrated output. Can be generated. Here, the resistance R _t the current flowing through the I1, V ₁ output voltage of the operational amplifier A _1, the capacitance C ₁
The potential of the diode D ₁ of the connection points V _C1, the capacitance C ₂
And the potential of the connection point diode D ₂ and V _C2.

The summing amplifier 13 includes an operational amplifier A _2, and resistors _{R 1, R 2, R 3} , operational amplifier A ₂ (+)
Side input terminal is grounded and R-terminal is
₁ and R ₂ are connected, and a resistor R ₃ is connected between the output terminal of the operational amplifier A _{2 and} the input terminal on the (−) side. The other terminal of the resistor R ₁ integrator 12
Is connected to the capacitance C _1, the other terminal of the resistor R ₂ is connected to the capacitance C ₂ of the integrator 12. Inverting adder 13
Has a weight (−1) by making all the values of the resistors R ₁ , R ₂ and R ₃ equal. Further, since the diodes D ₁ and D ₂ of the selection circuit 15 do not become conductive at the same time, the inverting adder 13 operates as an inverting voltage follower.
Here, the operational amplifier A ₂ (-) potential side of the input terminal and V _2.

The first comparator 16 comprises an operational amplifier A ₃ and resistors R ₄ , R ₅ and R ₆ . Of the operational amplifier A ₃ (-) while connecting the terminal to the output terminal of the operational amplifier A ₂ of the summing amplifier 13, resistor R ₄ to the output terminal, R ₅ and R ₆
The are connected in series, to ground the resistor R _6. Resistance R ₄ and R
By the _fifth connection point is connected to a (+) input terminal of the operational amplifier A _3, a first comparator 16, the threshold voltage V _d, V
_Operates as a hysteresis comparator with _u .
Here, the operational amplifier A ₃ (-) potential of the input terminal V ₃ side, V ₆ the potential of the output terminal of the operational amplifier A _3, resistor R
₄ and the potential at the connection point of R ₅ V _4, the potential at the connection point between the resistors R ₅ and R ₆ and alpha] V _4. The value of α is determined so as to reduce the influence of the power supply voltage. Details will be described later.

The second comparator 17 is constituted by an operational amplifier A _5, the operational amplifier A ₅ (-) input terminal side, while connected to the connection point between the resistor R ₅ and R ₆ of the first comparator 16 , by connecting the input terminal of the (+) side to the output V ₃ of the operational amplifier a ₂ of the summing amplifier 13, and outputs a digital value by comparing the potential of alpha] V ₄ and the output V ₃ of the operational amplifier a _2. Here, the digital signal output terminal of the operational amplifier A ₅ and V _7.

The output circuit 17 outputs an exclusive OR (Exclusiv
e OR) composed of negative and circuit U ₁ (NOT) circuit U _2. The exclusive circuit U _1, and the output V ₆ of the operational amplifier A ₃ of the first comparator, inputs the output V ₇ of the operational amplifier A ₅ of the second comparator, the NOT circuit U ₂ output of U ₁ input. The output of the NOT circuit U ₂ and V _8.

The operation of the oscillation circuit 10 in FIG.
In the following, the second comparator 17 is mainly used.
And the operation of the output circuit 17 will be described.

[0050] FIG. 7 (a) the waveform of the oscillation circuit 10 in FIG. 6, FIG. 7 (b) shows the waveform of the output V ₇ of the second comparator 17.

[0051] Voltage alpha] V ₄ of the first comparator 16, by dividing the output V ₆ of the operational amplifier A ₃ in the resistor R _4, R _5, R _6, is generated between the resistors R ₅ and R _6. The potential of the output V ₃ of the operational amplifier A ₂ of the summing amplifier 13 is increased, alpha
Exceeds V _4, the output V ₇ of the operational amplifier A ₅ of the second comparator 17 becomes H. Potential of V ₃ is reduced to the contrary, at the alpha] V ₄ below, V ₇ becomes L.

Here, a period in which both V ₆ and V ₇ are H is T ₅ , and a period in which both V ₆ and V ₇ are L is T ₆ . Since these two periods T ₅ and T ₆ are in the period of T ₂ and T ₄ in the circuit of FIG. 2, respectively, like T ₂ and T ₄ , in these periods, nonlinear errors are caused by the power supply voltage. Do not cause.

The calculation of the circuit of the second embodiment when an error is included is as follows.

[0054] First, the input bias current of the operational amplifier A ₁ and I _B, the input offset voltage of each operational amplifier V
_off n (n = 1, 3, 4).

[0055] In the T ₅ state that V ₆ and V ₇ is H together,
Current _{(V u -V off1) / R} t -I B flows to the capacitance C _1, V ₃ from _{(αV u -V off4) (V} u -V off3)
Changes to Therefore, T ₅ is

[0056]

(Equation 6) On the other hand, in the T ₆ state V ₆ and V ₇ is L both current _{(-V d -V off1) / R} t -I B flows to the capacitance C _2, V ₃ are, (- alpha] V _d - V _off4 ) to (−V _d −V
_off3 ). Therefore, T ₆ is

[0057]

(Equation 7) Becomes

When the capacitance ratio is obtained from the above equations (12) and (13),

[0059]

(Equation 8) Here, the inside of the curly braces of the two items in the equation (15) is a factor of the nonlinear error. If this can be reduced to 0, the effect of V _u can be eliminated. That is,

[0060]

(Equation 9) Then, the determined value may be used.

As means for taking out the periods of T ₅ and T ₆ , for example, an output circuit 1 for inverting by taking exclusive OR is used.
7 is used. FIG. 8 shows the input V _{6 of the} output circuit 17.
And is a waveform diagram of V ₇ and the output V _8.

Next, a design example will be described.

[0063] A ₁ (model number AD711J): input bias current I _B ~15pA <50pA, the offset voltage _{V off1 ~0.3mV <2.0mV A 3,} A 4 ( Part No. CMP-04): the offset voltage V _off3, V _{off4 to} 0.4mV <1.0
mV, V _d = V _u = 10 V, R ₁ = R ₂ = R ₃ = 1 KΩ, R _t = 25 MΩ α = 0.1 Based on V _u and R _t , the oscillation frequency f at C ₁ = C ₂ = 10 pF = 1 kHz or higher and all errors work with constructive codes. Substituting into equation (12) gives

[0064]

(Equation 10) As a result, despite a simple circuit, the resolution is 0.
Results greater than 1% were obtained.

Experimental Example In the circuit of FIG. 2, LF411 was used as an operational amplifier. For performance evaluation, a detector using a parallel plate capacitor was used. A 30 MHz clock was used to measure the duty ratio.

The capacitances C ₁ and C ₂ are given by x in the equation (2), and have a center electrode sandwiched between two outer electrodes. The total capacitance is C ₀ = 3 pF or 6 pF.

FIG. 9 shows the measurement results when C ₀ = 6 pF. The oscillation frequency is 0.5 KHz when C ₁ = C _2
Rt is adjusted so that Each measured value (plot) is an average of the results of 20 measurements at each position. The position was adjusted on a scale of 10 μm with a screw of a micrometer.

The resolution was evaluated by setting C ₀ = 3 pF.
The evaluation based on the standard deviation is 2 × 10 ⁻³ %, and a change of 60 aF can be detected from the measurement of the duty ratio. These results are consistent with the above evaluation.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of two capacitances of a differential capacitance detector.

FIG. 2 is a circuit diagram of a capacitance change amount detection device according to the present invention.

FIG. 3 is an equivalent circuit diagram in each state of the integrator of the present invention.

FIG. 4 is a waveform chart of each part of the circuit of FIG. 2;

FIG. 5 is a waveform chart of an output circuit of the circuit of FIG. 2;

FIG. 6 is a circuit diagram of another embodiment of the capacitance change amount detection device of the present invention.

FIG. 7 is a waveform chart of each part of the circuit diagram of FIG. 6;

FIG. 8 is a waveform chart of an output circuit of the circuit of FIG. 6;

FIG. 9 is a diagram showing a duty ratio and a displacement of an output signal measured in an experiment.

[Explanation of symbols]

10: oscillation circuit, 11, 18: output circuit, 12: integrator, 13: inverting adder, 14: comparator, 15: selection circuit, 16: first comparator, 17: second comparator, A ₁ , A
₂ , A ₃ , A ₄ , A ₅ ... operational amplifier, C ₁ , C ₂ ... capacitance, D ₁ , D ₂ ... diode, U ₁ ... exclusive OR circuit, U ₂ ... negation circuit.

Claims (6)

[Claims] 1. An integrator having one of two capacitances, which varies according to a physical quantity and a chemical quantity of a detection target, as a part of a constant, and an integrator according to an output voltage value of the integrator. A selection circuit that selects one of the two capacitances to be an element of the integrator, a feedback circuit provided between an output section and an input section of the integrator, An output circuit for converting the signal into a wave, wherein the output circuit outputs a rectangular wave signal having a duty ratio determined by a ratio of the two capacitances. 2. The capacitance change detecting device according to claim 1, wherein the feedback circuit compares an output of the inverting adder with an output of the inverting adder for inverting and adding an output of the integrator. And an output of the comparator as an input of the integrator. 3. An integrator having one of two capacitances, which varies according to a physical quantity and a chemical quantity of a detection target, as a part of a constant, and an integrator according to a value of an output voltage of the integrator. A selection circuit that selects one of the two capacitances to be an element of the integrator, an inverting adder that inverts and adds the output of the integrator, and outputs the output of the inverting adder and its own output. A first comparator for comparison, a second comparator for comparing an output of the inverting adder with an output of the first comparator, and exclusion of an output of the first comparator and an output of the second comparator. An output circuit for inverting by taking a logical OR, and by using an output of the first comparator as an input of the integrator, a pulse determined from the output circuit by a ratio of the two capacitances Output a rectangular wave signal having a width. Amount detecting device. 4. The capacitance change amount detecting device according to claim 1, wherein one of the two capacitances increases while the other decreases. And a capacitance change amount detection device configured so that the sum of the two capacitances is constant. 5. An integration circuit that changes two capacitances according to a physical quantity and a chemical quantity of a detection object, an integration circuit that makes one of the two capacitances a part of a constant, A selector circuit for selecting one of the two capacitances according to the value of the output voltage to be used as an element of the integration circuit. 6. The integrator according to claim 5, wherein said selection circuit comprises two diodes connected between said two capacitances and an output terminal of said integration circuit, and said two diodes are connected. By making the directions opposite to each other, one of the capacitances is selected when the integration circuit outputs a negative voltage, and the other capacitance is selected when the integration circuit outputs a positive voltage. An integrator configured to select.