JPH1031896A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a noise margin at the time of a normal reabout larger by setting a switching transistor in a nonconductive state at the time of a verification of the reading of data to set a data detecting reference at the time of the verification more strict. SOLUTION: In an EPROM, the detection output S of a high voltage detection circuit 6 is inverted by an inverter circuit 41 and the output of the circuit 41 is applied to the gate of the switching transistor 8b insertingly connected in between the 4a2 of one side of divided load transistors 4a1, 4a2 and a power source node 9. Consequently, since the number of operations of bit line load transistors is made smaller as compares with a normal reading time to lower a potential reading memory cells, the data detecting references made to become more strict.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a nonvolatile semiconductor memory, and more particularly to a circuit for switching a data detection reference between normal reading and verifying.

[0002]

2. Description of the Related Art Non-volatile semiconductor memories such as EPR
An OM (ultraviolet erasable rewritable read-only memory) has a floating gate and a control gate, includes an EPROM cell that stores data according to the amount of charge in the floating gate, and injects charge into the floating gate. When writing (programming) data, it is necessary to detect whether or not the writing has been performed correctly. For this reason, a verify mode for reading from the EPROM cell immediately after writing and comparing the read data with the write data is provided. If the writing has not been correctly performed, the writing is performed again.

As shown in FIG. 9, a differential amplifier 5 is used to detect read data from the EPROM cell. One input side of the differential amplifier 5 has a memory cell 1a connected to a bit line BLa. Potential VBL read to
a is input, and the other input terminal is connected to the dummy memory cell 1b.
Potential V read from the dummy bit line BLb
BLb is input. Here, 2a is a transistor for selecting a column (bit line selection) of the memory cell array, 4a is a bit line load transistor, 2b is a dummy column select transistor, and 4b1, 4b2 are dummy bit line load transistors. The differential amplifier 5 compares the read potential VBLa from the memory cell with the reference potential VBLb,
As shown by 0, data detection is performed according to the magnitude relationship between the two potentials VBLa and VBLb.

[0004]

When the potentials VBLa and VBLb fluctuate due to power supply noise or the like during normal reading, the magnitude relationship may be reversed when the potential difference between the potentials VBLa and VBLb is small. When this inversion occurs, there is a problem that erroneous data detection is performed. In order to prevent this, for example, if the reference potential VBLb is set higher during the verify operation than during the normal read operation and the data detection standard during the verify operation is strict, the difference between the two potentials VBLa and VBLb during the normal read operation can be increased. And the malfunction can be prevented.

SUMMARY OF THE INVENTION The present invention has been made to solve the problem that data detection may be erroneously performed due to power supply noise or the like at the time of normal reading as described above. Is set strictly, and a non-volatile semiconductor memory having a large noise margin at the time of normal reading is provided.

[0006]

SUMMARY OF THE INVENTION A nonvolatile semiconductor memory according to the present invention has a floating gate and a control gate, and is connected to the memory cell for storing data by the amount of charge in the floating gate, and to the memory cell. A load circuit comprising at least two load transistors and a switching transistor connected between at least one of the load transistors and a power supply terminal; and a connection point between the load circuit and the memory cell. A sense amplifier that detects data stored in the memory cell by comparing the potential of the connection point with a reference potential; and when reading data from the memory cell, the switching transistor is turned on during normal data reading. And charge the floating gate to inject charge into the memory cell. By setting the switching transistor to a non-conducting state at the time of verification for reading data from the memory cell in order to check a program state of data to the memory cell when programming the data, the load circuit at the time of normal data reading And a load resistance setting means for setting the resistance value of the load circuit smaller than the resistance value of the load circuit at the time of the verification.

According to the nonvolatile semiconductor memory of the present invention,
The number of load transistors in the load circuit is switched between a verify operation and a normal read operation according to the operation state of the switching transistor. As a result, the data detection criterion at the time of verification can be set more strictly than at the time of normal reading, and after passing the verify check, a large difference between the memory cell read potential and the reference potential can be obtained at the time of normal reading. , The noise margin becomes larger.

[0008]

FIG. 1 shows a part of an EPROM considered in the course of the present invention, wherein 1a has a floating gate and a control gate, and stores data by the amount of charge in the floating gate. A memory cell, 2a is a column selection transistor, BLa is a memory cell side bit line, 4a is a load transistor connected to the bit line BLa, and 5 is a potential VBLa of the bit line BLa as one input (comparison input). A differential amplifier, 1b is a dummy cell, 2b is a transistor for selecting a column for a dummy, BLb is a bit line on a dummy cell side,
4b1, 4b2 and 4b3 are the dummy cell side bit lines B
This is a dummy load transistor connected to Lb, and is divided into three in this example. The memory cell 1a and the dummy cell 1b have the same transistor size, the column selection transistor 2a and the dummy column selection transistor 2b have the same transistor size, and the dummy load transistors 4b1 and 4b2 have a smaller size than the load transistor 4a. Is large.

On the other hand, reference numeral 6 denotes a high program voltage VPP applied to the program voltage input terminal 7 (for example, 12.
5V) is a high voltage detection circuit that generates a detection output of a normal voltage level by detecting a VDD voltage (5V) when the high voltage VPP is not detected, and outputs a ground voltage when the VPP is detected. It is supposed to. 8 is the detection circuit 6
P for a switch controlled by the detection output S of the switch
It is a channel MOS transistor. The switch transistor 8 is connected to the dummy load transistor 4b.
1 to 4b3, for example, is inserted and connected between the source of one transistor 4b3 and the power supply node 9, and the sources of the remaining dummy load transistors 4b1 and 4b2 are connected to the power supply node without passing through the switching transistor. 9 is connected.

FIG. 2 shows a specific example of the high voltage detection circuit 6, wherein a P-type gate and a drain are connected between a program voltage input terminal 7 and a VSS power supply node (ground potential terminal). Channel MOS transistor 21,
22, a P-channel MOS transistor 23 and an N-channel M transistor each having a gate connected to the VDD power supply node.
The OS transistor 24 is connected in series. Then, the potential of the drain interconnection point of the transistors 23 and 24 is connected to the CMOS inverter 25 cascaded in three stages.
26, 27 and the final stage CMOS inverter 27
, The detection output S is obtained from the output terminal. The above CMO
The S inverters 25, 26, and 27 correspond to P-channel MOS transistors P1, P2, P3 and N-channel M
The OS transistors N1, N2 and N3 are connected in series.

In the EPROM, as shown in FIG. 3, during normal reading, the program voltage input terminal 7 is at the ground potential, the output S of the high voltage detection circuit is at 5 V, and the switching transistor 8 is off. 4b3 of the dummy load transistors 4b1 to 4b3 are off, and the dummy bit line potential VBLb (reference potential) at this time is represented by VBLbL. At this time, the memory cell 1a
The potential difference between the read potential (potential of the bit line BLa) VBLa and the reference potential VBLbL is detected and amplified by the differential amplifier 5 to perform data detection. On the other hand, at the time of verification, the program voltage input terminal 7
Is the VPP voltage as in the case of programming, the high voltage detection circuit output S is at the ground potential, the switching transistor 8 is on, and all the dummy load transistors 4b1 to 4b3 are on. Of the dummy bit line (reference potential) VBLb becomes VBLbH higher than VBLbL at the time of the normal reading.

Therefore, at the time of verification, the data detection reference for read potential VBLa from memory cell 1a is set strictly. After passing the verify check based on such a strict standard, the reference potential VBLb is set to a low value VBLbL at the time of normal reading, so that the potential difference from the memory cell reading potential VBLa can be made large, and power noise and the like can be reduced. The noise margin is improved.

A MOS transistor for clamping a bit line potential may be inserted into the bit line BLa and the dummy bit line BLb in the EPROM of FIG. 1 described above. Can be

In the EPROM shown in FIG. 1, the number of operations of the dummy load transistors 4b1 to 4b3 is switched by turning on / off the switch transistor 8. Conversely, the load transistor 4a is divided into a plurality of parts. Even when the number of operations is switched by turning on / off the switching transistor, the same effect as that of FIG. 1 can be obtained. FIG. 4 shows a configuration according to an embodiment of the present invention. In the EPROM according to this embodiment,
The detection output S of the high voltage detection circuit 6 is inverted by the inverter circuit 41, and the divided load transistors 4a1, 4a
The output / S of the inverter circuit 41 is provided to the gate of the switching transistor 8b inserted and connected between the power supply node 9 and the other one 4a2. Therefore, the number of operations of the bit line load transistors during the verify operation is smaller than that during the normal read operation, and the read potential of the memory cell is lowered.

1 and the embodiment of the present invention shown in FIG. 4 are combined so that both the number of operation of the dummy load transistor and the number of operation of the load transistor are different from those in the normal read operation and the verify operation. The data detection criterion at the time of verification may be set strictly by switching with time. An example of the circuit configuration in this case is shown in FIG. 5, and the same parts as those in FIGS. 1 and 4 are denoted by the same reference numerals.

Further, in the above embodiment, the memory cell read potential is compared with the dummy cell side reference potential by the differential amplifier to detect data. However, the present invention is not limited to this. For example, a memory cell read potential may be input to an inverter circuit), an example of which is shown in FIG. That is, 1
a is a memory cell, 2a is a column selection transistor, BLa
Is a bit line load transistor, 4a is a bit line load transistor, 61 is a bit line potential clamping transistor, 62 is an inverter connected between the bit line and the clamping transistor 61, and 63 is data input by the memory cell read potential VBLa. It is a CMOS inverter circuit for detection.
This inverter circuit 63 has a divided P channel M
The OS transistors P4 and P5 and the N-channel MOS transistor N4 are connected in series, and the two P-channel M
A switching P-channel MO is connected between the source of one of the OS transistors P4 and P5, P5, and the power supply node 9.
The S transistor 8a is inserted and connected.

The switching transistor 8a
The detection output S of the high-voltage detection circuit 6 is given to the gate of. Therefore, the circuit threshold of the inverter circuit 63 is switched between normal reading and verifying, and the data detection reference at the time of verifying is set strictly. The above C
Instead of MOS inverter circuit 63, as shown in FIG. 7, a P-channel MOS transistor P4 and a two-divided N
Channel MOS transistors N4 and N5 are connected in series, and these two N-channel MOS transistors N4 and N5 are connected in series.
The switching N-channel MOS transistor 70 may be inserted and connected between the source of one of the transistors N5 and the ground node, and the high voltage detection output S may be applied to the gate of the switching transistor 70.

As shown in FIG. 8, the bit line load transistor is divided into two transistors 4a1 and 4a2, and the power supply node 9 is connected between the source of one of the two transistors 4a1 and 4a2 4a2 and the power supply node 9. P channel M for switch
The OS transistor 8b is inserted and connected, and the inverted signal / S of the output S of the high voltage detection circuit is supplied to the switch transistor 8
You may make it give to the gate of b. In this case, the inverter circuit 63 as the data detection circuit may use the one shown in FIG. 6 or FIG. 7, or may use an inverter circuit having a fixed threshold. Also in the circuit shown in FIG. 8, the data reading conditions at the time of verification can be set more strictly than at the time of reading.

[0019]

As described above, according to the nonvolatile semiconductor memory of the present invention, the data detection criterion at the time of verify can be set more strictly than at the time of normal read. Is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a part of an EPROM considered in the course of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a high voltage detection circuit in the EPROM of FIG. 1;

FIG. 3 is a timing chart shown for explaining the operation of the EPROM of FIG. 1;

FIG. 4 is a circuit diagram showing a partial configuration of an EPROM according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a partial configuration of an EPROM according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a part of an EPROM considered in the course of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a part of an EPROM considered in the course of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a part of an EPROM considered in the course of the present invention.

FIG. 9 is a circuit diagram showing a partial configuration of a conventional EPROM.

FIG. 10 is a timing chart for explaining the operation of the conventional EPROM shown in FIG.

[Explanation of symbols]

1a: memory cell, 1b: dummy cell, 4a1, 4a2, 4b1, 4b2, 4b3: load transistor, 5: differential amplifier, 6: high voltage detection circuit, 7: program voltage input terminal, 8a, 8b: MOS for switch Transistor, 9 ... Power supply node, 41, 62 ... Inverter circuit. 63: CMOS inverter circuit.

Claims (1)

[Claims] 1. A memory cell having a floating gate and a control gate and storing data according to the amount of charge in the floating gate; at least two load transistors connected to the memory cell; and at least one of the load transistors A load circuit comprising a switching transistor connected between the power supply terminal and a power supply terminal, and a connection point between the load circuit and the memory cell,
A sense amplifier that detects data stored in the memory cell by comparing the potential of the connection point with a reference potential; and when reading data from the memory cell, the switching transistor is in a conductive state during normal data reading. In order to check the programmed state of the data in the memory cell when programming data in the memory cell by injecting electric charge into the floating gate, the switching transistor is used at the time of verification for reading data from the memory cell. And a load resistance setting means for setting the resistance value of the load circuit at the time of the normal data reading to be smaller than the resistance value of the load circuit at the time of the verification by setting the non-conducting state to a non-conductive state. Nonvolatile semiconductor memory.