JPH1031618A - Data conversion system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data converting system for improving data converting processing speed in the case of cache hit. SOLUTION: In the case of floating point data, parallelly with the write of data to be written into a data cache to J2, at a data discriminating circuit G, either single precision or double precision and the kind of data in the case of single precision are discriminated and the data discriminated result is written in J3. An aligner A1 inputs the data of a path 4 and the data of a path 5 read from J2, selects any data, outputs the data unnecessitating data conversion in the selected data to a path 7 and outputs data requiring it to a path 6, an aligner A2 inputs the data of a path 16 and the data read from J3, selects any data and outputs them to a path 18, and concerning the data from the path 6, a precision converting circuit C converts single-precision data to double- precision data based on the data discriminated result from a path 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data conversion method for converting data read from a data cache during execution of an instruction.

[0002]

2. Description of the Related Art The prior art of the data conversion method will be described with reference to the configuration diagram of FIG. 4 in the case where data is floating point data and single precision floating point data is converted to double precision floating point data. To do. In the conventional data conversion method shown in the configuration diagram of FIG. 4, the precision of data is converted from single precision to double precision, and a data cache comprising a data address tag J1 and a data cache memory J2 is provided.
A floating point register F1 (hereinafter, FR), a floating point arithmetic unit F2, a data determination circuit G, a precision conversion circuit C as a data conversion circuit, latches L1 and L2, and a selector S
1, S2, S3, aligner A1, and data path 1,
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
13 is provided. FR has a width of 64 bits, single precision data is 32 bits and double precision data is 64 bits. Converting the precision of data from single precision to double precision
This is because, since the floating-point arithmetic unit is a double-precision arithmetic unit, it is necessary to convert single-precision data into double-precision data before performing the arithmetic operation on single-precision data.

FIG. 7 is a view for explaining an example of the format of floating-point data.
It is represented by a bit exponent part and a 23-bit mantissa part, and double-precision data is represented by a 1-bit sign part, an 11-bit exponent part, and a 52-bit mantissa part. The data read width and the data write width of the data cache memory J2 are 64 bits, and the data transfer from the main storage device to the data cache memory J2 is 64 bits * 4cyc =
It is assumed that 64 bits of 256 bits including the data of the target address are transferred in the first cycle.
Instruction execution includes an instruction read stage (IF stage), an instruction decode stage (D stage), an instruction execution stage (E stage), a memory access stage (A stage), a cancel stage (N stage),
The pipeline processing is composed of a writing stage (W stage).

An operation of executing a single-precision floating-point load instruction will be described below as an example. The operation outline of the instruction is as follows.
After reading the bit data and converting it to the appropriate double precision format according to the value of that data, the target F
That is, an operation of writing to R is performed. As a result of decoding the instruction fetched in the IF stage in the D stage, it is found to be a single precision floating point load instruction, and the target address is calculated in the E stage. In the A stage, in order to obtain 32-bit single precision data, the data address tag J1
However, if a cache miss occurs, the data is transferred from the main storage device, so the data passes through path 1 and path 3 and the data cache memory J2
Written in. Further, in this case, the data of the first cycle that simultaneously includes the data of the target address bypasses the data cache memory J2, and the latch L2 and the path 4
Is input to the aligner A1. Aligner A1
Passes 4 depending on cache hit or cache miss
Alternatively, a function of selecting one of the 64-bit data of the pass 5 and outputting the selected data to the pass 7, and selecting the first half or the latter 32 bits of the selected 64-bit data according to the target address and outputting the selected data to the pass 6. There is a function. The aligner A1 outputs 64-bit data to the path 7 regardless of whether the data is single-precision data or double-precision data. Although not shown, a control signal based on the result of the cache hit or the cache miss is input to the aligner A1.
Is selected. Also, when selecting the first half or the latter half 32 bits of 64-bit data, 1 bit for this selection is included in the target address. A selection is made.

[0005] The 32-bit data output to pass 6 is
The data is written in the target FR via the data determination circuit G, the precision conversion circuit C, the path 8, the selector S2, and the path 10. Here, in the data determination circuit G, as shown in FIG.
The value of the input data is judged, and the judgment result for selecting which format to convert from single precision to double precision is output. As shown in FIG. 6, the precision conversion circuit C uses the determination result of the data determination circuit G to format-convert single precision data into double precision data.

Since data conversion is not required in the execution of the double-precision floating-point load instruction, 64-bit double-precision data from the data cache memory J2 or the main memory is selected by the aligner A1, and then the data decision circuit G is selected. , Path 7 bypassing the precision conversion circuit C, selector S2, path 1
Write to the target FR via 0. Although not shown, a control signal based on the decoding result of the D stage is input to the selector S2, and the signal of path 7, 8 or 9 is selected by this control signal. In the case of a store instruction, the selector S3 selects the path 13 from GR for a fixed-point store instruction, the path 11 from FR for a floating-point store instruction, and passes through the paths 2 and 3. Then, data is written to the data cache memory J2. In the execution of the floating-point operation, the data of the FR is sent to the floating-point arithmetic unit F2 via the paths 11 and 12, and the operation result is written to the target FR via the paths 9 and 10.

[0007]

However, in such a conventional data conversion method, if a cache hit occurs as a result of the A-stage cache access, the data is stored in the data cache memory J2, the latch L1, the path 5, and the path 6. , A data determination circuit G, an accuracy conversion circuit C as a data conversion circuit, a path 8 and a path 10 to be written into FR. For this reason, in the execution of the single-precision floating-point load instruction, whenever a cache hit occurs in the target address, the data passes through the data determination circuit G before being converted by the precision conversion circuit C when reading data from the data cache memory J2. Therefore, there is a problem that the processing speed becomes slow. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problem and to provide a method for improving a data conversion processing speed at the time of a cache hit.

[0008]

In order to achieve the above object, the present invention provides a data cache, comprising: a data determination result area for storing, for each data, a data determination result indicating a type of written data; Data determination means for determining the type of the data in parallel with writing the data to the cache and writing the data determination result to the data determination result area is provided, and the data read from the data cache and the data determination result are input. Data conversion means for converting the data based on the data determination result is provided. A first aligner for inputting write data to the data cache and read data from the data cache, selecting and outputting one of the data, and a data aligner. A second aligner for inputting the output data determination result and the data determination result read from the data cache, selecting and outputting one of the data determination results from the two data determination results, Data conversion is performed by using the outputs of the first aligner and the second aligner as inputs of the data conversion means. Further, the first aligner inputs the write data to the data cache and the read data from the data cache, selects either one of the two data, and selects the selected data. And an output terminal for outputting data that does not require data conversion, and an output terminal for outputting data that requires data conversion. The output terminal for outputting data that requires data conversion is provided as an input of the data conversion means. To connect to. The data written to the data cache is floating-point data, and the type of the data is the type of single precision data or double precision data and the type of single precision data.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the data conversion system of the present invention will be described below, taking data as floating point data and converting single precision floating point data into double precision floating point data as an example. A specific description will be given based on the drawings.
FIG. 1 shows a configuration diagram of the embodiment. 2 shows a time chart in the case of a cache miss in the operation example in the embodiment, and FIG. 3 shows a time chart in the case of a cache hit in the operation example in the embodiment. In the processor that performs the data precision conversion shown in the configuration diagram of FIG. 1, the data cache including the data address tag J1 and the data cache memory J2, the data determination result J3, the floating point register F
1 (hereinafter, FR), a floating point arithmetic unit F2, a data determination circuit G, a precision conversion circuit C as a data conversion circuit, and latches L1, L2, L3, L4, and selectors S1, S
2, S3, aligners A1, A2, and data path 1,
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
It is equipped with 13, 14, 15, 16, 17, and 18. F
R is 64 bits wide, single precision is 32 bits, and double precision is 64 bits. The data read width and the data write width of the data cache memory J2 are 64 bits,
The data transfer from the main storage device to the data cache memory J2 is a method in which 64 * 4 = 256 bits and 64 bits including the data of the target address are transferred in the first cycle. In addition, the instruction is executed by the instruction read stage (IF stage) and the instruction decode stage (D
Stage), an instruction execution stage (E stage), a memory access stage (A stage), a cancel stage (N stage), and a write stage (W stage).

First, an operation of executing a single-precision floating-point load instruction will be described as an example. The instruction fetched in the IF stage is decoded in the D stage, and as a result, is determined to be a single-precision floating-point load instruction. The target address is calculated in the E stage. At the A stage, the data address tag J1 is accessed in order to obtain 32-bit single precision data, but in the case of a cache miss, data is transferred from the main storage device, so data is passed through paths 1 and 3. It is written in the data cache memory J2 via
At this time, the data passed through the path 14 is the data judgment circuit G.
Data is input to the data determination circuit G, as shown in FIG.
The precision conversion circuit C outputs a data determination result indicating which format the data is to be precision converted based on. This data determination result is written in the data determination result J3 newly provided in the data cache. The data determination result is 2 bits in this embodiment, and the data determination result J3 stores 2 bits for each 32-bit data. At the same time, the data of the first cycle including the data of the target address bypasses the data cache memory J2 and is input to the aligner A1 via the latch L2 and the path 4. When a cache hit occurs, the data cache memory J2 is input to the aligner A1 via the latch L1 and the path 5. The aligner A1 has a function of selecting one of the 64-bit data of the path 4 or the path 5 and outputting it to the path 7 according to a cache hit or a cache miss, and the first half of the selected 64-bit data according to the target address. Alternatively, there is a function of outputting the latter 32 bits to the path 6. The 32-bit data output to the path 6 is input to the precision conversion circuit C. Although not shown, a control signal based on the result of a cache hit or a cache miss is input to the aligner A1, and the path 4 or the path 5 is selected by this control signal. The selection of the first or second half 32 bits of the 64-bit data includes one bit for this selection in the target address, and the value of this one bit is determined by the aligner A1. A selection is made.

Similarly, in the case of a cache miss, the data determination result of the data determination circuit G also bypasses the data determination result J3, is input to the aligner A2 via the latch L4 and the path 16, and if a cache hit occurs, The output of the data determination result J3 is input to the aligner A2 via the latch L3 and the path 17. The aligner A2 passes the path 16 or 17 depending on the cache hit or the cache miss.
Has a function of selecting any one of the data determination results and outputting the result to the path 18. The data determination result output to the path 18 is input to the precision conversion circuit C. Although not shown, a control signal based on the result of a cache hit or a cache miss is input to the aligner A2, and the control signal selects the path 16 or the path 17.

The precision conversion circuit C receives the 32-bit data from the path 6 and the data determination result from the path 18, and formats the single precision data into double precision data according to the data determination result, as shown in FIG. Convert.

Further, since the data precision conversion is not necessary in the execution of the double precision floating point load instruction, after the 64-bit double precision data from the data cache memory J2 or the main memory is selected by the aligner A1, the pass 7, Write to the target FR via the selector S2 and path 10. Although not shown, a control signal based on the decoding result of the D stage is input to the selector S2, and the signal of path 7, 8 or 9 is selected by this control signal.

In the case of a store instruction, the selector S
3, the path 13 from GR is selected for a fixed-point store instruction, the path 11 from FR is selected for a floating-point store instruction, and data is written to the data cache memory J2 via path 2 and path 3. At this time, the data is written to the data cache memory J2 and the pass 1
4. The output of the data determination circuit G is written to the data determination result J3 via the data determination circuit G and the path 15. As described above, it is necessary to update the value of the data determination result in the store instruction.

In the execution of the floating point operation, pass 1
The FR data is sent to the floating point arithmetic unit F2 via the path 1 and the path 12, and the operation result is written into the target FR via the paths 9 and 10.

In the above embodiment, the data is floating-point data, and a specific example of the data conversion method when single-precision floating-point data is converted to double-precision floating-point data has been described. The data is not limited to the floating point data, and may be any data that needs data conversion after being read from the data cache, and the data conversion method of the present invention is applied to such data. It goes without saying that it is possible.

[0017]

As described above, according to the present invention,
Since the data type is judged in parallel with the writing of the data to the data cache and the data and the data judgment result are written to the data cache, the read data in the case of a cache hit is directly converted by the data conversion circuit. Therefore, the processing speed of the data conversion of the read data in the case of a cache hit can be improved as compared with the related art, and the delay due to the data conversion can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a time chart in the case of a cache miss in the embodiment.

FIG. 3 is a time chart in the case of a cache hit in the embodiment.

FIG. 4 is a diagram showing a configuration of a single-precision data conversion method according to the related art.

FIG. 5 is a diagram illustrating processing contents in a data determination circuit for precision conversion.

FIG. 6 is a diagram showing processing contents in a precision conversion circuit.

FIG. 7 is a diagram showing an example of a data format of floating point data.

[Explanation of symbols]

 J1 Data address tag J2 Data cache memory J3 Data judgment result F1 Floating point register F2 Floating point arithmetic unit G Data judgment circuit C Precision conversion circuit L1 to L4 Latch S1 to S3 Selector A1, A2 Aligner 1 to 18 Pass

Claims (4)

[Claims] 1. A data determination result area for storing, for each data, a data determination result indicating a type of written data in a data cache, wherein the type of the data is determined in parallel with the writing of the data to the data cache. Data determining means for determining and writing the data determination result to the data determination result area, inputting the data read from the data cache and the data determination result, and performing data conversion of the data based on the data determination result A data conversion method comprising a conversion means. 2. The data conversion method according to claim 1, wherein write data to said data cache and read data from said data cache are input, and one of said data is selected. The first to output
, The data determination result output from the data determination unit, and the data determination result read from the data cache are input, and one of the data determination results is selected and output. A data aligner for performing data conversion using outputs of the first aligner and the second aligner as inputs of the data converter. 3. The data conversion method according to claim 2, wherein the first aligner inputs write data to the data cache and read data from the data cache, and selects one of the two data. An output terminal for selecting one of the data and outputting data that does not require data conversion among the selected data, and an output terminal for outputting data that requires data conversion are provided. A data conversion method, wherein an output terminal for outputting data is connected to an input of the data conversion means. 4. The data conversion method according to claim 1, wherein the data written to the data cache is floating-point data, and the type of the data is single-precision data or double-precision data. A data conversion method characterized by the type of data and the type of single precision data.