JPH10308097A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably and stably prevent the occurrence of drain disturb. SOLUTION: In the write mode, the line selective circuit 2 gives voltage VPP to the selective word line and voltage V1 which satisfies a relation: 0<V1<VPP/2 to the non-selective bit line. The row selective circuit 3 gives 0V to the selective bit line and voltage V2 which satisfies VPP/2<V2<VPP to the non-selective word line. In the erase mode, the circuit 2 gives 0V to the selective word line and voltage V2 to the non-selective word line. The circuit 3 gives VPP to the selective bit line and voltage V1 to the non-selective bit line. Thus, the potential difference between the control gate and the drain of the non-selective memory cell transistor is made lower than VPP/2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory device (EEPROM).
It is about.

[0002]

2. Description of the Related Art An EEPROM has a feature that a writing and erasing current is extremely small because a tunnel effect is used for writing and erasing data. FIG. 2 shows a conventional E
It is a block diagram of EPROM. This semiconductor memory is
A memory cell array 11 in which a plurality of memory cell transistors M00 to M11 are arranged in a matrix, word lines W0 and W1 commonly connected to control gates of memory cell transistors in each row, and a drain in common to memory cell transistors in each column. It comprises connected bit lines B0 and B1, a row selection circuit 12 for selecting a predetermined word line, and a column selection circuit 13 for selecting a predetermined bit line.

In a data write mode, a row selection circuit 12 outputs a voltage VPP to a selected word line and outputs a voltage VPP / 2 to an unselected word line. On the other hand, the column selection circuit 13 outputs 0 V to the selected bit line and outputs the voltage VPP / 2 to the non-selected bit lines. As a result, the voltage VPP is applied to the control gate of the memory cell transistor selected by the selected word line and the selected bit line, and 0 V is applied to the drain. As a result, electrons are injected into the floating gate of the selected memory cell transistor by a tunnel phenomenon, and data “1” is written. Also,
In the erase mode, the row selection circuit 12 outputs 0 V to a selected word line and outputs a voltage VPP / 2 to a non-selected word line. On the other hand, the column selection circuit 13 applies the voltage V to the selected bit line.
PP is output, and a voltage VPP / 2 is output to a non-selected bit line. As a result, 0 V is applied to the control gate of the memory cell transistor selected by the selected word line and the selected bit line, and the voltage VPP is applied to the drain. As a result, electrons in the floating gate of the selected memory cell transistor are released to the drain by a tunnel phenomenon, and data “1” is erased.

In such an EEPROM, a drain disturb phenomenon occurs in a non-selected memory cell transistor at the time of writing or erasing. For example, when writing data to the memory cell transistor M00, the voltage VPP / 2 is applied to the control gate of the unselected memory cell transistor M10, and 0 V is applied to the drain. As a result, an electric field is generated between the floating gate and the drain of the transistor M10, electrons are injected into the floating gate, and the threshold voltage of this transistor increases. Therefore, data is erroneously written to the memory cell transistor M10. When erasing the data of the memory cell transistor M00, the voltage VPP / 2 is applied to the control gate of the unselected memory cell transistor M10, and the voltage VPP is applied to the drain. As a result, an electric field is generated between the drain and the floating gate of the transistor M10, electrons in the floating gate are emitted to the drain, and the threshold voltage of the transistor is reduced. Therefore, the data of the memory cell transistor M10 is erroneously erased. The above-described drain disturb phenomenon similarly occurs in the memory cell transistor M01.

In the EEPROM of FIG. 2, by applying a voltage of VPP / 2 to the unselected word lines and unselected bit lines, the tunnel electric field generated in the unselected memory cell transistors is weakened as compared with the case of the selected memory cell transistors, so that the disturbance occurs. Has been prevented. However, in practice, a slight drain disturbance also occurs in the non-selected memory cell transistor, and the level is merely a level that does not cause a problem in the actual operation life. Therefore, when the voltage VPP is reduced, the VPP and VPP / 2 are reduced. There has been a problem that the difference is reduced and disturb resistance becomes insufficient. In view of this, there has been proposed a memory in which the disturb prevention effect is further improved (Japanese Unexamined Patent Publication No.
-272164). FIG.
FIG. 4 is a block diagram of an EEPROM disclosed in Japanese Patent Application Publication No. 4 (JP-A) No. 4;

In this EEPROM, bit lines B0, B
1 is newly connected to a write inhibit line L1 via a capacitor C1, and word lines W0 and W1 are newly connected to a write inhibit line L2 via a capacitor C2. When erasing the data of the memory cell transistor M00,
After applying the voltage VPP / 2 to the word lines W0 and W1, the bit lines B0 and B1, and the write inhibit lines L1 and L2,
0, W1, bit lines B0, B1, write block lines L1,
The potential of L2 is set to VPP, open, 0V, open, VPP, 0V, respectively. Since the potential of the unselected bit line B1 is VPP applied to the write block line L1,
It is raised to VPP / 2 + Δ by the capacitive coupling of the capacitor C1. On the other hand, the potential of the unselected word line W1 is reduced to VPP / 2-.DELTA. By the capacitive coupling of the capacitor C2 because the write block line L2 is grounded. Therefore, by setting Δ to an appropriate voltage value, the potential difference between the drains and the control gates of the unselected memory cell transistors M01, M10, M11 can be made lower than VPP / 2. As a result, no high electric field is generated between the drain and the control gate of the unselected memory cell transistor to induce a tunnel effect, so that the threshold voltage does not change.

When data is written to the memory cell transistor M00, the voltage VPP / 2 is applied to the word lines W0 and W1, the bit lines B0 and B1, and the write inhibit lines L1 and L2.
, Word lines W0 and W1, bit lines B0 and B1
, The potentials of the write inhibit lines L1 and L2 are set to 0, open, VPP, open, 0V and VPP, respectively. Thereby, the unselected memory cell transistors M01, M10, M11
The potential difference between the drain and the control gate is lower than VPP / 2 as in the erase operation, so that the threshold voltage does not change.

[0008]

As described above, Japanese Patent Laid-Open No.
In the EEPROM disclosed in JP-A-272164, an unselected word line and an unselected bit line are connected to a voltage VPP / 2.
, And the potential is level-shifted by capacitive coupling of a capacitor connected to the write block line, thereby preventing the occurrence of drain disturbance. However, in this EEPROM, the non-selected word line and the non-selected bit line are boosted or stepped down by the capacitive coupling of the capacitor, so that the potential of the non-selected word line and the non-selected bit line becomes the disturbance prevention voltage (VPP / 2 + Δ or VPP). / 2-Δ), and there is a problem that drain disturbance occurs during the change to the disturbance prevention voltage. Further, since the voltage changes according to the amount of charge of the capacitor, the disturbance prevention voltage cannot be maintained for a long time, and there is a problem that the capacitance of the capacitor must be increased to maintain the disturbance prevention voltage. Was. SUMMARY An advantage of some aspects of the invention is to provide a nonvolatile semiconductor memory device capable of reliably and stably preventing the occurrence of drain disturb.

[0009]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cell transistors are arranged in a matrix; and a memory in each row of the memory cell array. A word line commonly connected to the control gates of the cell transistors, a bit line commonly connected to the drains of the memory cell transistors in each column of the memory cell array, and row selection means for selecting a predetermined word line; Column selecting means for selecting a predetermined bit line, and the row selecting means comprises:
In the write mode, the high voltage VPP is applied to the selected word line, the first voltage V1 that satisfies the relation of 0 <V1 <VPP / 2 is applied to the unselected word lines, and the ground voltage is applied to the selected word line in the erase mode. And VPP to the unselected word line
/ 2 <V2 <VPP, and the column selecting means applies the ground voltage to the selected bit line and the second voltage V2 to the non-selected bit line in the write mode. In the erase mode, a high voltage VPP is applied to a selected bit line and a first voltage V1 is applied to an unselected bit line. In the write mode, the row selecting means applies a first voltage V1 as an anti-disturb voltage to unselected word lines, and the column selecting means applies a second voltage V2 as an anti-disturb voltage to unselected bit lines. In the erase mode, the row selecting means applies a second voltage V2 to unselected word lines, and the column selecting means applies a first voltage V1 to unselected bit lines. By applying different disturb prevention voltages to the unselected word lines and the unselected bit lines, the potential difference between the control gate and the drain of the unselected memory cell transistor can be made lower than VPP / 2. Since this potential difference is not enough to cause a tunnel phenomenon, the threshold voltage of the unselected memory cell transistor does not change. Further, the first voltage V1 and the second voltage V2 are generated by dividing the high voltage VPP.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an EEPROM showing an embodiment of the present invention. This semiconductor memory includes a memory cell array 1 in which a plurality of memory cell transistors M00 to Mnn are arranged in a matrix, and memory cell transistors M00 to M0n, M10 to M1n,.
Word lines W0 to Wn commonly connected to the control gates of Mn0 to Mnn, and memory cell transistors M00 of each column
.. Mn0, M01 to Mn1,..., Bit lines B0 to Bn commonly connected to the drains of M0n to Mnn, a row selection circuit 2 for selecting a predetermined word line in accordance with an external input address, an external input address , A column selection circuit 3 for selecting a predetermined bit line, and a voltage generation circuit 4 for generating a voltage to be supplied to a word line and a bit line.

Next, write and erase operations for the memory cell array 1 will be described. Table 1 shows operating voltages of the word lines W0 to Wn and the bit lines B0 to Bn in each mode. In Table 1, the left side of “/” indicates the voltage at the time of selection, and the right side indicates the voltage at the time of non-selection.

[0012]

[Table 1]

First, in a data write mode,
The row selection circuit 2 outputs the high voltage VPP from the voltage generation circuit 4 to the selected word line among the word lines W0 to Wn, and outputs the first voltage V1 from the voltage generation circuit 4 to the non-selected word lines. . The high voltage VPP is a voltage having a value sufficient to cause a tunnel phenomenon, for example, 10V. The voltage generating circuit 4 generates the first voltage V1 by dividing the voltage VPP by a level shift circuit including a plurality of transistors or by dividing the voltage VPP by a plurality of resistors. The first voltage V1 is 0 <V1 <VPP / 2,
For example, 2VPP / 5.

On the other hand, the column selection circuit 3 includes bit lines B0 to B0.
Among n, the ground voltage GND (0 V) from the voltage generation circuit 4 is output to the selected bit line, and the second voltage V2 from the voltage generation circuit 4 is output to the non-selected bit lines. Like the voltage V1, the voltage generating circuit 4 generates the second voltage V2 by dividing the voltage VPP by a level shift circuit or by dividing the voltage VPP by a resistor. The second voltage V2 is VPP / 2 <
V2 <VPP, for example, 3VPP / 5.

The voltages V1 and V2 are VPP-V2 <V
The relations of PP / 2, V1-0 <VPP / 2 and V2-V1 <VPP / 2 are satisfied. Then, the sources of all the memory cell transistors are set to the open state.

As a result, of the memory cell transistors M00 to Mnn in the memory cell array 1, the voltage VPP is applied to the control gate of the memory cell transistor selected by the selected word line and the selected bit line, and 0 V is applied to the drain. You. As a result, a high electric field is generated between the floating gate and the drain of the selected memory cell transistor, electrons are injected into the floating gate by a tunnel phenomenon, and the threshold voltage of the transistor increases. Thus, data “1” is written.

At this time, the potential difference between the control gate and the drain of each unselected memory cell transistor is VPP
/ 2, it is possible to reliably prevent the occurrence of the drain disturb phenomenon in the non-selected memory cell transistors. For example, when writing data to the memory cell transistor M00, in the unselected memory cell transistors M01 to MOn connected to the selected word line W0, the voltage VPP is applied to the control gate and the voltage VPP is applied to the drain.
2 is applied.

On the other hand, in the unselected memory cell transistors M10 to Mn0 connected to the selected bit line B0, the voltage V1 is applied to the control gate and 0V is applied to the drain. Then, the selected word line W0 and the selected bit line B
In a non-selected memory cell transistor that is not connected to 0, the voltage V1 is applied to the control gate and the voltage V2 is applied to the drain.

Therefore, the potential difference between the control gate and the drain of each unselected memory cell transistor is
/ 2, and no high electric field is generated between the drain and the control gate of the unselected memory cell transistor so as to induce a tunnel effect, so that the threshold voltage does not change.

Next, in the erase mode, the row selection circuit 2
Outputs the ground voltage GND (0 V) from the voltage generation circuit 4 to the selected word line among the word lines W0 to Wn, and outputs the second voltage V2 from the voltage generation circuit 4 to the non-selected word lines. On the other hand, the column selection circuit 3 applies the high voltage VPP from the voltage generation circuit 4 to the selected bit line among the bit lines B0 to Bn.
And outputs the first signal from the voltage generation circuit 4 to the unselected bit line.
Is output. Then, the sources of all the memory cell transistors are set to the open state.

Thus, the memory cell transistor M00
0 to Mnn, 0 V is applied to the control gate of the memory cell transistor selected by the selected word line and the selected bit line, and voltage VPP is applied to the drain. As a result, a high electric field is generated between the drain and the floating gate of the selected memory cell transistor, electrons in the floating gate are emitted to the drain by a tunnel phenomenon, and the threshold voltage of the transistor decreases. Thus, data “1” is erased.

At this time, the potential difference between the drain and the control gate of each unselected memory cell transistor becomes lower than VPP / 2 as in the case of writing. For example, when erasing data of the memory cell transistor M00, 0V is applied to the control gate and voltage V1 is applied to the drain of the unselected memory cell transistors M01 to MOn connected to the selected word line W0.

On the other hand, in the non-selected memory cell transistors M10 to Mn0 connected to the selected bit line B0, the voltage V2 is applied to the control gate and the voltage VPP is applied to the drain. In a non-selected memory cell transistor not connected to the selected word line W0 and the selected bit line B0, the voltage V2 is applied to the control gate and the voltage V1 is applied to the drain.

Therefore, the potential difference between the control gate and the drain of each unselected memory cell transistor is set to VPP
/ 2, and no high electric field is generated between the drain and the control gate of the unselected memory cell transistor so as to induce a tunnel effect, so that the threshold voltage does not change.

[0025]

According to the present invention, in the writing mode or the erasing mode, the first voltage V1 and the second voltage V2 are applied to the unselected word line and the unselected bit line, respectively. By applying the disturb prevention voltage, the potential difference between the control gate and the drain of the unselected memory cell transistor can be made lower than VPP / 2. Therefore, even if the voltage VPP is lowered to, for example, 13 V or less, a sufficient drain voltage can be obtained. A disturb prevention effect can be obtained. Also, since the first voltage V1 and the second voltage V2, which are constant anti-disturb voltages, are applied to the unselected word line and the unselected bit line from the row selecting means and the column selecting means, a conventional method using a capacitor is used. EEPROM
As described above, it does not take time for the potentials of the unselected word lines and unselected bit lines to reach the disturb prevention voltage, and the potential does not change in accordance with the charge amount of the capacitor. Sure
And it can be prevented stably.

Further, as described in claim 2, by generating the first voltage V1 and the second voltage V2 by dividing the high voltage VPP, it is possible to follow variations and fluctuations in VPP. Drain disturbance can be more reliably prevented from occurring.

[Brief description of the drawings]

FIG. 1 is a block diagram of an EEPROM showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional EEPROM.

FIG. 3 is a block diagram of another conventional EEPROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row selection circuit, 3 ... Column selection circuit, 4 ... Voltage generation circuit, M00-Mnn ... Memory cell transistor, W0-Wn ... Word line, B0-Bn ... Bit line.

Claims (2)

[Claims] 1. A memory cell array in which a plurality of memory cell transistors are arranged in a matrix, a word line commonly connected to control gates of memory cell transistors in each row of the memory cell array, and a memory cell in each column of the memory cell array A bit line commonly connected to the drains of the transistors; a row selecting unit for selecting a predetermined word line; and a column selecting unit for selecting a predetermined bit line. In the write mode, a high voltage VPP is applied to a selected word line and 0 <V1 is applied to an unselected word line.
A first voltage V1 that satisfies the relationship <VPP / 2 is applied, and in the erase mode, a ground voltage is applied to the selected word line and a second voltage V2 that satisfies the relationship VPP / 2 <V2 <VPP to the unselected word line. The column selecting means applies a ground voltage to a selected bit line and a second voltage V2 to an unselected bit line in a writing mode, and applies a high voltage V2 to a selected bit line in an erasing mode.
A nonvolatile semiconductor memory device which applies a first voltage V1 to unselected bit lines while supplying PP. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first voltage V1 and said second voltage V2 are generated by dividing a high voltage VPP. apparatus.