JPH10307704A - Constitution method for circuit for outputting element of two-dimensional linear partial space - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale and delay time of a circuit for successively outputting all two-dimensional vectors to be the elements of a two-dimensional linear partial space parallelly for respective components. SOLUTION: In the case that the base V= a1 , a2 ,..., am } of the two-dimensional linear partial space is supplied, the base V'= a1 ', a2 ',..., am '} for generating the same two-dimensional linear partial space as the two-dimensional linear partial space generated by the base for which the total number of the components to be '1' of the respective two-dimensional vectors is smaller than the total number of the components to be '1' of the respective two-dimensional vectors of the base V is prepared. Then, by calculating the linear combination c1 a1 '+c2 a2 '+...cm am ' of the prepared base V', the circuit for successively outputting all the vectors (v)=(v1 , v2 ,..., Vn ) to be the elements of the two-dimensional linear partial space generated by the supplied base V parallelly for the respective parts is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a circuit for sequentially outputting all binary vectors, which are elements of a binary linear subspace, from a given basis of a given binary linear subspace in parallel. Regarding

[0002]

2. Description of the Related Art First, a binary vector will be described.
A binary vector v of length n is given by v = (v ₁ , v ₂ ,...
, V _n ), and a sequence of length n represented by each component v
_{The value of i} (i = 1, ..., N) is either 1 or 0. Then, two binary vectors of length n v = (v
_{1, v 2, ···, v} n) and _{w = (w 1, w 2} , ···,
The addition v + w of w _n ) is v + w = (v ₁ + w ₁ , v ₁ + w ₂ ,
..., v _n + w _n ). Where 0 + 0
= 0,1 + 0 = 0 + 1 = 1,1 + 1 = 0. For example, v = (1,1,0,0), w = (1,0,0,1)
, V + w = (1 + 1,1 + 0,0 + 0,0 + 1)
= (0,1,0,1). Also, the constant multiple kv of the vector v with respect to the constant k that takes a value of 0 or 1 is kv = (k
· V ₁ , k · v ₂ , ···, k · v _n ). Here, 0.0 = 0, 1.0 = 0 = 0 = 1, 0, 1
= 1. For example, 0 (1,0,1,0) = (0 ·
1,0 · 0,0 · 1,0 · 0) = (0,0,0,0) and 1 (1,0,1,0) = (1 · 1,1 · 0,1 ·
1,1,0) = (1,0,1,0). And 2
In addition and constant multiplication of the original vector, the constant multiplication has a higher priority, and 0 (1, 0, 1, 0) +1 (1, 1, 0, 0)
= (0,1,0,0,0,1,0,0) + (1,1,1
・ 1,1,0,1,0) = (0,0,0,0) + (1,
(1,0,0) = (1,1,0,0).

Next, the linear combination of binary vectors will be described. A finite number of binary vectors a ₁ , a ₂ , ...
·, A _m (a _i respectively binary vector, 1 ≦ i ≦ m) 2-vector of length n produced by the addition and constant multiplication from _{c 1 a 1 + c 2 a} 2 + ··· + c m a m + ... + c _ma
m (c _i = 0, 11 1 ≦ i ≦ m) is defined as a ₁ , a ₂ ,.
It is said to be a linear combination of _m . Also, binary vector a of length n is, when the _{a = c 1 a 1 + c} 2 a 2 + ··· + c m a m, a is a _1, a _2, · · ·, primary a _m It is expressed as a bond. For example, three binary vectors a ₁ =
(1,0,1,1), a ₂ = (1,0,0,1), a ₃ =
A binary vector v = (0,0,1,0) obtained by calculating 1a ₁ + 1a ₂ + 0a ₃ from (0,1,0,0) is a _first- order binary vector a ₁ , a ₂ , a ₃ Is a bond, and v is v = 1
It is said that it is represented by linear combinations of a ₁ , a ₂ and a ₃ like a ₁ + 1a ₂ + 0a ₃ .

Next, the binary linear subspace will be described. m binary vectors a ₁ , a ₂ ,..., a of length n
_{For m} , a ₁ , a ₂ , ..., A _m linear combination c ₁ a ₁ + c
_{2 a 2 + ··· + c m} a m (c i = 0,1 1 ≦ i ≦ m)
Is zero vector 0 = (0, 0,..., 0) only when c ₁ = c ₂ =... = C _m = 0, and a ₁ , a ₂ ,
···, a _m is that it is linearly independent. Then, linearly independent m-number of 2-vector a _1, a _2, · · ·, set of all linear combinations of _{a m W W = {c 1} a 1 + c 2 a 2 + ··· + c m a m | c _i (1 ≦ i
≦ m) ∈ a _{{1,0}} a 1, a} 2, that binary linear subspace generated by · · · a _m. Also, the binary linear subspace W
Set of linearly independent binary vectors {a ₁ , a ₂ ,
..., a _m } is called the basis of W.

For example, three binary vectors a ₁ = (1,
0,1,1), a ₂ = (1,0,0,1), a ₃ = (0,
1,0,0) are linearly independent, the elements a _1, a _2, a ₃ to produce a binary linear subspace W are all linear combination of a _1, a _2, a _3, below eight binary vector _{0a 1 + 0a 2 + 0a 3} 1a 1 + 0a 2 + 0a 3 0a 1 + 0a 2 + 1a 3 1a 1 + 0a 2 + 1a 3 0a 1 + 1a 2 + 0a 3 1a 1 + 1a 2 + 0a 3 0a 1 + 1a 2 + 1a 3 1a 1 + 1a ₂ + 1a ₃ and W = (0,0,0,0), (1,0,1,1) (0,1,0,0), (1,1,1,1) (1,0 , 0,1), (0,0,1,0) (1,1,0,1), (0,1,1,0)}. Also, {a ₁ , a ₂ , a ₃ } is the basis of W.

As described above, from the basis of a given binary linear subspace, all 2 that are elements of that binary linear subspace.
In order to determine the source vector, it is necessary to calculate all linear combinations of the basis.

Conventionally, the length of a binary vector as an element is n
The basis {a ₁ , a ₂ , ..., Of the _binary linear subspace W that is
A circuit as shown in FIG. 2 has been considered as a circuit that sequentially outputs all the elements of W from a _m } and outputs the respective components in parallel.

In FIG. 2, a _i = (a _i-1 , a _i-2 , ...
..., when expressed as a _in), if a _ij is 1, the output from the c _i representing the i-th bit of the m-bit counter 200 is connected to the exclusive OR gate EOR _j, 0 if connected It has not been. Such n EOR gates (EO)
R ₁ , EOR ₂ , ..., EOR _n ), a _binary vector v indicating a linear combination c ₁ a ₁ + c ₂ a ₂ + ... + _cm a _m
= (V ₁ , v ₂ ,..., V _n ) can be output in parallel. Then, the m-bit counter _{200, c 1, c 2,} ···, by sequentially generating all combinations of c _m, all linear combinations of _{{a 1, a 2, ···} , a m} Can be sequentially output. In addition,
If there are 0 input lines to EOR _j , it is always 0 to v _j .
There is output, if only input one from c _i, the input from the c _i are directly connected to v _j. If the output lines to v ₁ , v ₂ , ..., V _n directly connected from the counter 500 are also considered as one input to the EOR gate, the total sum of the components of the base binary vector that are 1 is EOR. Matches the sum of the input lines to the gate.

As described above, the configuration shown in FIG.
Given the basis of the original linear subspace, it is possible to create a circuit that sequentially outputs all elements of the binary linear subspace. However, the circuit of FIG. 2 has an extremely large number of input lines to the EOR gate depending on the base, so that the circuit scale becomes very large and it is difficult to realize. In general, when a multi-input EOR gate is realized by an LSI, the EOR gate having a small number of inputs is realized by multi-stage connection. Therefore, when the number of input lines to the EOR gate increases in the circuit as shown in FIG. 2, the number of connected gate stages increases, and the delay time of the circuit also increases.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to, when a basis of a binary linear subspace is given, sequentially output all elements of the binary linear subspace and output their components in parallel. An object of the present invention is to provide a configuration method that reduces the circuit scale and delay time.

[0011]

SUMMARY OF THE INVENTION A certain binary linear subspace W
The basis of {a ₁ , a ₂ , ... a _m } is given,
In the circuit as shown in FIG. 2, the total number of inputs to the EOR gate coincides with the total number of 1-components of the binary vector of {a ₁ , a ₂ , ..., _Am }, and this number is very large. If it is large, it becomes difficult to actually realize it in an LSI. In the present invention, this is solved as follows.

First, the basic idea of the present invention will be shown. In the basis {a ₁ , a ₂ ,..., A _m }, a set of binary vectors formed by adding an arbitrary binary vector to another arbitrary binary vector is linearly independent. The binary linear subspace generated by the set of element vectors is W
Matches. For example, in {a ₁ , a ₂ ,..., A _m ) which is the basis of the binary linear subspace W, the binary vector a _i
(1 ≦ i ≦ m) and a binary vector a _j (1 ≦ j ≦ m, j ≠)
i), a set of binary vectors ｛a ₁ , a ₂ ,...
_{·, Ai -1, a i +} a j, a i + 1, ···, a j-1, a j, a
_The binary linear subspace generated by _{j + 1} ,..., a _m } matches W. At this time, the number of 1 components of a _i + a _j is a _i
Less than the basis {a ₁ , a ₂ , ..., A
_{i-1, a i + a} j, a i + 1, ···, a j-1, a j, a j + 1, ·
When a circuit is created in the same manner as the circuit of FIG. 2 using..., A _m }, the number of inputs to the EOR gate is reduced by the amount that the number of components of a _i + a _j being 1 is smaller than a _i be able to.

FIG. 1 shows a procedure of a method of creating a basis in which the number of components that become 1 is as small as possible from the basis of a given binary linear subspace according to the present invention. Here, it is assumed that the basis V = {a ₁ , a ₂ ,..., A _m } of the binary linear subspace W is given. The function Min (N) returns the smallest element among the elements of a set N of certain integers, and Group represents a set of matrices. Below, each step S1 in FIG.
~ S7 is shown.

S1. Let N = {1, 2, ..., M}. S2. a ₁ , a ₂ , ..., _Am are the first, second, ...
An m-th row matrix G ₀ that is the m-th row is created, and Group = {G ₀ }. S3. For all matrices of Group, all matrices obtained by adding at least one other row vector of the matrix to the Min (N) th row are obtained, and all the obtained matrices are Group
As an element. S4. Remove Min (N) from N. S5. Steps S3 and S4 are repeated until N becomes an empty set. S6. Among all the matrices included in Group, one matrix having the smallest number of 1's is obtained. S7. A set of m row vectors of the matrix obtained in step S6 is defined as a base V '.

The basis V ′ of W thus obtained is
From {a ₁ ′, a ₂ ′, ..., _Am ′}, as in FIG. 2 (where a _i is a _i ′), an m-bit counter and E
The OR gate creates a circuit that sequentially outputs all elements of W and outputs each component in parallel.

In this circuit, a _i ′ = (a _i−1 ′,
a _i-2 ′, ... a _in ′), a _ij ′
Is 1, c _i representing the i-th bit of the m-bit counter
The output from is connected to the exclusive OR (EOR) gate EOR _j, it is not 0, connected. Such n EOR gates (EOR ₁ , EOR ₂ , ..., E
OR _n ), the linear combination c ₁ a ₁ ′ + c ₂ a ₂ ′ +...
· + C _m a _m 2 illustrates a 'way vector _{v = (v 1, v 2} , ··
, V _n ) can be output in parallel. Then, in the m-bit counter, c ₁ , c ₂ ,..., C
By sequentially generating all combinations of _m ,
All linear combinations of {a ₁ ′, a ₂ ′, ..., _Am ′} can be sequentially output. Incidentally, if the input lines to EOR _j is 0 present, v always 0 is output to _j, in the case of only the input one from c _i, the input from the c _i are directly connected to the v _i.

The sum of the one-component components of the binary vector that is the element of the base V'obtained by the present invention is less than or equal to the sum of the one-component components of the binary vector that is the element of the given base V. The number of inputs to the EOR gate of the circuit of FIG. 2 is less than the number of inputs in the conventional case. As a result, in realizing a circuit in which all elements of the binary linear subspace are sequentially output in parallel with an actual LSI, the circuit can be realized with a smaller circuit scale than before. Further, in general, when implementing a multi-input EOR gate in an LSI, an EOR having a small number of inputs
It is realized by connecting gates in multiple stages. Therefore, by reducing the number of input lines to the EOR gate,
When the circuit is realized by I, the number of gate coupling stages can be reduced, and the delay time can also be reduced as compared with the conventional circuit.

[0018]

3 and 4 show a concrete example of a circuit for sequentially outputting all the elements of a binary linear subspace W according to the prior art and the present invention, and outputting the respective components in parallel.

Suppose that a basis V = {a ₁ , a ₂ } for generating a binary linear subspace W is given, and a ₁ = (1,0,
1,1,0,1,1,1), a ₂ = (1,1,1,1,
0, 0, 1, 1).

Here, when a circuit for sequentially outputting all the elements of W is created in the same manner as in FIG. 2 using the given base V as it is, FIG. 3 is obtained. The circuit of FIG. 3 has a 2-bit counter 3 in which each bit is represented by c ₁ and c _2.
00 and five exclusive OR (EOR) gates 301-
The 305 outputs a linear combination _{c 1 a 1 + c 2 a} 2 a 2-vector _{v = (v 1, v 2} , ... v 8) , and in parallel for each component. Then, by sequentially changing the value of the 2-bit counter 300 from 00 to 11, all elements of W can be output.

According to the present invention, on the other hand, according to the procedure shown in FIG. 1, the sum of the components of the binary vector 1 as the element is equal to or less than the sum of the components of the binary vector 1 as the element of V. V ', the EOR of the circuit of FIG.
One gate can be used. Hereinafter, this will be described.

First, N = according to step S1 of the procedure of FIG.
Let {1, 2}. Next, according to step S2

[0023]

(Equation 1)

Let Group = {G ₀ }.

Next, according to step S3, Group
Min (N) rows for all matrices, ie, all matrices formed by adding one or more outer rows to the first row

[0026]

(Equation 2)

And Group = {G ₀ , G ₁ }. Then, according to step S4, the Min (N) = 1 is removed from N, and N = {2}.

Next, according to step S3 again, for all matrices of Group, the Min (N) th row, that is, all the matrices formed by adding one or more other arbitrary rows to the second row are obtained.

[0029]

[Equation 3]

Then, Group = {G ₀ , G ₁ , G ₂ , G ₃ }
And Then, when Min (n) = 2 is removed from N according to step S4, N becomes an empty set.

Then, according to step S6, Group =
Among the matrices included in {G ₀ , G ₁ , G ₂ , G ₃ }, one of the matrices having the smallest number of 1 components, for example, G ₁ is selected. Next, according to step S ₇ , 1
The sum of all the components becomes 1 of the binary vector that becomes the element of V
A base V ′ = {(0,1,
0,0,0,1,0,0), (1,1,1,1,0,
0,1,1)}.

When a circuit similar to that of FIG. 2 is created using the basis V ', the circuit becomes as shown in FIG. Here, a ₁ ′ = (0,
1,0,0,0,1,0,0), a ₂ ′ (1,1,1,
₁ , 0, 0, ₁ , ₁ ), and the circuit of FIG. 4 includes a 2-bit counter 400 in which each bit is represented by c ₁ and c ₂ and an exclusive OR (EOR) gate 401. From the above, the two-dimensional vector v = (v ₁ , v _{1) of} the linear combination c ₁ a ₁ ′ + c ₁ a ₂ ′
v _2, and outputs a ... v _8), in parallel for each component. Then, by sequentially changing the value of the 2-bit counter 400 from 00 to 11, all the elements of W can be output.

Comparing the circuit of FIG. 4 with the circuit of FIG. 3, the circuit of FIG. 4 is smaller in scale than the circuit of FIG. I have.

While the embodiment of the present invention has been described above, the procedure shown in FIG. 1 is realized using a so-called computer. At that time, the procedure (processing flow) may be prepared in advance in the computer as an application program, or
Alternatively, a recording medium (a floppy disc, an optical disc, etc.) in which a program describing these procedures is recorded may be read (installed) by a computer.

[0035]

As described above, according to the present invention,
Given the basis of a binary linear subspace, this 2
A circuit that sequentially outputs all the elements of the original linear subspace and outputs each component in parallel can be made smaller in scale than before. Further, when the circuit is realized by the LSI, the delay time can be made shorter than that of the conventional circuit. Such a circuit is used, for example, as an internal circuit of a maximum likelihood decoder of a linear block code used in the field of communication, but a maximum likelihood decoder having a delay time smaller than that of the related art can be realized on a small scale.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a procedure of a method of creating a basis having a small number of components that become 1 as much as possible from the basis of a binary linear subspace according to the present invention.

FIG. 2 is a diagram showing a general configuration of a circuit that sequentially outputs all elements of a binary linear subspace and outputs each component in parallel.

FIG. 3 is a diagram illustrating a specific example of a conventional circuit that sequentially outputs all components of a binary linear subspace and outputs each component in parallel.

FIG. 4 is a diagram showing a specific example of a circuit according to the present invention that sequentially outputs all elements of a binary linear subspace W and outputs each component in parallel.

[Explanation of symbols]

 400 2-bit counter 401 Exclusive OR gate

Claims (1)

[Claims] 1. A circuit configuration for sequentially outputting, from a basis of a given binary linear subspace, all binary vectors that are elements of the binary linear subspace generated by the basis, and outputting their components in parallel A two-dimensional linear subspace produced by a given basis, wherein the total number of 1-components of each binary vector is less than the total number of 1-components of each binary vector of a given basis; By creating a basis that generates the same binary linear subspace and calculating a linear combination of the created basis, all binary vectors that are elements of the binary linear subspace generated by a given basis are sequentially determined. And a circuit for outputting the components of the binary subspace, wherein the circuit outputs the components in parallel.