JPH10304197A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a choice between initial error data and initial value data to be used when the image processor performs an error diffusing process for image data of a 1st line. SOLUTION: The image processor has an error diffusing process circuit 22 which performs the error diffusing process for digital image data corresponding to pixels of plural lines and is equipped with a data selecting means consisting of a latch circuit 21, a buffer memory 23, and a NAD circuit 24 that supply specific initial error data which are usable as error data on a last line for the processing of image data of a 1st line by the error diffusing process circuit 22 and predetermined initial value data which are usable as error data on the last line for the processing of the image data of the 1st line by the error diffusing processes circuit 22 and common to all pixels selectively to the error diffusing process circuit 22 according to external selection information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having error diffusion processing means for performing error diffusion processing on digital image data corresponding to pixels of a plurality of lines.

[0002]

2. Description of the Related Art Error diffusion processing is known as a kind of halftone processing in image processing. In such error diffusion processing, when processing image data corresponding to pixels on the first line, processing is performed using predetermined initial value data common to all pixels as error data for the previous line. Also, there is a case where processing is executed using predetermined initial error data determined in advance for each pixel as error data of the previous line.

The conventional image processing apparatus determines which of the above-described processing methods is to be adopted at the design stage in advance, and designs and manufactures circuits in accordance with the decision.

[0004]

However, the conventional image processing apparatus has a problem that the processing method cannot be changed after the circuit is manufactured.

That is, in the case of image data independently generated by a personal computer or the like, image quality can be improved by setting initial error data and processing the first line. When the image is processed, since the image includes a reading error from our office, if the image is further processed using the initial error data, the image quality may be deteriorated. Therefore, it is preferable to be able to select which of the initial error data and the initial value data should be used to process the image data of the first line in accordance with the image data to be processed. Did not make such a choice.

The present invention has been proposed in view of the above points, and when performing the error diffusion process on the image data of the first line, any one of the initial error data and the initial value data is used. It is an object of the present invention to provide an image processing apparatus which can select whether to use.

[0007]

In order to achieve the above object, an image processing apparatus according to the first aspect of the present invention provides an error diffusion process for performing an error diffusion process on digital image data corresponding to a plurality of lines of pixels. A predetermined initial error data predetermined for each pixel, which can be used as error data of a previous line in processing of image data of a first line by an error diffusion processing means. And predetermined initial value data common to all pixels, which can be used as error data of the previous line in processing the image data of the first line by the error diffusion processing means, by using selection information from outside Data selection means for selectively supplying to the error diffusion processing means based on

According to this image processing device, the data selection means is determined in advance for each pixel and can be used as the error data of the previous line in the processing of the image data of the first line by the error diffusion processing means. The predetermined initial error data and predetermined initial value data common to all pixels, which can be used as error data of the previous line in processing the image data of the first line by the error diffusion processing means. Is selectively supplied to the error diffusion processing means based on selection information from the outside, so that when performing the error diffusion processing on the image data of the first line, either the initial error data or the initial value data is used. Can be selected. Therefore, appropriate error diffusion processing according to the type of image data can be performed, and a high-quality image can be obtained when printing or the like is performed.

The error diffusion processing means may output binary image data or output multi-valued image data. Further, the specific content of the error diffusion processing may be any method.

As the selection information, a flag or the like stored in an EEPROM can be used, and the setting can be made before the product is shipped at the manufacturing factory, or the setting can be arbitrarily changed by key operation. You may.

According to a second aspect of the present invention, there is provided the image processing apparatus according to the first aspect, wherein the data selecting means includes an initial error data storage means for storing initial error data, Initial value data storage means for storing value data, and initial error data stored in the initial error data storage means and initial value data stored in the initial value data storage means based on selection information from outside. Selecting means for selectively supplying the error diffusion processing means.

According to this image processing apparatus, in addition to the effects of the image processing apparatus according to the first aspect, initial error data is stored in the initial error data storage means, and initial value data is stored in the initial value data storage means. Therefore, data of arbitrary values can be set as the initial error data and the initial value data.

As the initial error data storage means and the initial value data storage means, a ROM or an EEPROM can be used, but it is not limited thereto.

The selection means includes, for example, initial error data and initial value data storage means stored in the initial error data storage means in accordance with the contents of the selection flag written in the electrically rewritable storage means. The CPU can selectively read out the initial value data stored in the memory and supply it to the error diffusion processing means via a buffer memory or the like, but is not limited to this.

Further, an image processing apparatus according to a third aspect of the present invention is the image processing apparatus according to the first aspect, wherein the data selection means includes an initial error data storage means for storing initial error data; Initial value data generating means for generating value data; and selecting initial error data stored in the initial error data storage means and initial value data generated by the initial value data generating means based on selection information from outside. Selection means for supplying the error diffusion processing means.

According to this image processing apparatus, in addition to the effect of the image processing apparatus according to claim 1, the initial value data generating means generates the initial value data, so that the initial value data is stored. No means is required, and the storage capacity of the storage means can be reduced.

According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the initial value data generating means is configured to negate a clear signal input to a clear terminal. A data holding circuit for supplying error data of the previous line to the error diffusion processing means when the signal is present, and supplying all 0 data to the error diffusion processing means when the clear signal input to the clear terminal is asserted.

According to this image processing apparatus, in addition to the effect of the image processing apparatus according to claim 3, a data holding circuit for supplying error data of the previous line to the error diffusion processing means is used as initial value data generating means. Therefore, it is not necessary to provide the initial value data generating means independently, so that the manufacturing cost can be reduced.

Further, the image processing apparatus according to the invention of claim 5 is the image processing apparatus according to claim 4, wherein the selection means supplies a clear signal to a clear terminal of the data holding circuit, The logic circuit asserts a clear signal when a signal indicating processing of image data of the line and a signal indicating that initial value data should be used are input.

According to this image processing apparatus, in addition to the effect of the image processing apparatus according to the fourth aspect, the selecting means can be realized by a simple circuit composed of one logic circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a circuit block diagram of a facsimile apparatus provided with an image processing apparatus according to the present invention. The facsimile apparatus has a CPU (central processing unit).
) 1, NCU (network control unit) 2, RAM (r
andom access memory) 3, modem 4, ROM (read on)
ly memory) 5, EEPROM (electrically erasable)
and programmable read only memory) 6, gate array 7, codec 8, DMAC (direct memory acce)
ss controller) 9, reading unit 11, recording unit 12, operation unit 1
3 and a display unit 14. CPU1, NCU
2, RAM 3, modem 4, ROM 5, EEPROM 6,
Gate array 7, codec 8, and DMAC 9
They are interconnected by bus lines. The bus lines include an address bus, a data bus, and a control signal line.
A reading unit 11, a recording unit 12, an operation unit 13, and a display unit 14 are connected to the gate array 7. A telephone line 15 is connected to the NCU 2 as an example of a communication line.

The CPU 1 controls the entire facsimile machine. The NCU 2 is connected to the telephone line 15 and performs network control. The RAM 3 stores various data such as image data binarized by error diffusion processing. Modem 4
Performs modulation of transmission data and demodulation of reception data.
The ROM 5 stores various programs, initial setting values, and the like. The EEPROM 6 stores various flags such as an initial value flag, registration data, and the like. Gate array 7
Functions as an input / output interface of the CPU 1 and executes various image processing such as error diffusion processing. The codec 8 encodes transmission facsimile data and decodes reception facsimile data. DMAC9
Performs writing and reading of data to and from the RAM 3.
The reading unit 11 includes a light source, a CCD image sensor, a document feed motor, and the like, reads a document, and outputs an analog image signal. The recording unit 12 includes a printing unit such as an inkjet system or a thermal transfer system, and records a received image or the like on a recording sheet. The operation unit 13 includes a key switch group and the like, and outputs a signal according to a user operation. The display unit 14 is composed of an LCD or the like, and has a CP
Various displays are performed under the control of U1.

FIG. 2 is a circuit block diagram of an error diffusion processing unit of the image processing apparatus constituted by the gate array 7. The error diffusion processing unit includes a latch circuit 21, an error diffusion processing circuit 22, and a buffer memory. 23, and NAND
A circuit 24 is provided.

The latch circuit 21 is composed of, for example, eight D flip-flop circuits, and latches, for example, 8-bit error data read from the buffer memory 23. The error diffusion processing circuit 22 performs an error diffusion process on, for example, 8-bit image data, binarizes the image data based on a control signal from the CPU 1, outputs the binarized image data to the RAM 3, and outputs the binarized image data with the input image data. An error with the image data is calculated, and the calculation result is output to the buffer memory 23 as, for example, 8-bit error data. The buffer memory 23 stores, for example, two lines of error data from the error diffusion processing circuit 22. In processing the image data corresponding to the pixels on the first line, the buffer memory 23 stores the initial error data previously stored in the ROM 5 as the error data of the previous line. N
The AND circuit 24 outputs a NAND output of the first line processing signal and the selection signal from the CPU 1 to a clear terminal of the latch circuit 21. That is, when the reading of the first line of each page of the read document is started by the image sensor of the reading unit 11, the CPU 1 sets the first line processing signal to a high level, and sets the initial value stored in the EEPROM 6 If the flag is on, the selection signal is set to high level. This initial value flag is set to ON when an error data is subjected to error diffusion processing to the image data corresponding to the pixels on the first line, and an initial value common to each pixel is used as the error data. Set to off when using predetermined initial error data determined for each pixel. This setting is performed before shipment from the manufacturing factory.
In this embodiment, when the initial value data is used as the error data, the value is determined to be 0.

FIG. 3 is a circuit block diagram of the error diffusion processing circuit 22. The error diffusion processing circuit 22 includes an arithmetic processing circuit 31, an error calculation circuit 32, a register 33, and a binarization circuit 34. ing.

The arithmetic processing circuit 31 calculates the total data based on the input image data and the error data from the latch circuit 21, and calculates an error calculating circuit 32 and a binarizing circuit 3.
4 is output. For example, of the peripheral pixels of the pixel corresponding to the image data to be processed, error data corresponding to a total of 7 pixels, ie, 5 pixels on the previous line and 2 pixels on the current line, are sequentially read from the buffer memory 23 and are latched.
The sum data is calculated by dividing the error data of each peripheral pixel by 16 and adding weighted values to the image data sequentially. The error calculation circuit 32 calculates an error between the sum data from the arithmetic processing circuit 31 and the image data from the binarization circuit 34, and outputs the calculation result to the buffer memory 23 as error data.
The register 33 holds control data from the CPU 1,
The threshold data and the binarization condition flag constituting the control data are output to the binarization circuit 34. That is, CP
When the reading of the document to be read is started by the image sensor of the reading unit 11, U1 supplies control data including the threshold data and the binarization condition flag to the register 33 and holds the register 33. The binarization circuit 34 binarizes the sum data from the arithmetic processing circuit 31 based on the threshold data from the register 33 and the binarization condition flag,
RAM as binary image data subjected to error diffusion processing
Output to 3.

That is, the error diffusion processing circuit 22 constitutes an error diffusion processing means for performing an error diffusion process on digital image data corresponding to a plurality of lines of pixels. The latch circuit 21, the NAND circuit 24, and the buffer memory 23 are provided with a predetermined pixel-by-pixel predetermined value which can be used as error data of the previous line for processing image data of the first line by the error diffusion processing means. And the predetermined initial value data common to all pixels, which can be used as error data of the previous line in the processing of the image data of the first line by the error diffusion processing means. And data selection means for selectively supplying the error diffusion processing means based on the selection information from.
The ROM 5 constitutes initial error data storage means for storing initial error data. The latch circuit 21 constitutes initial value data generating means for generating initial value data.
The NAND circuit 24, based on selection information from the outside,
A selection unit is configured to selectively supply the initial error data stored in the initial error data storage unit and the initial value data generated by the initial value data generation unit to the error diffusion processing unit. The latch circuit 21 supplies the error data of the previous line to the error diffusion processing means when the clear signal input to the clear terminal is negated, and performs the error diffusion processing when the clear signal input to the clear terminal is asserted. This constitutes a data holding circuit for supplying all 0 data to the means. The NAND circuit 24 supplies a clear signal to the clear terminal of the data holding circuit, and receives a signal indicating processing of image data on the first line and a signal indicating that initial value data is to be used. , And a logic circuit that asserts a clear signal.

Next, the essential points of the operation of the facsimile apparatus thus configured will be described. For example, in the copy mode, when reading of a read document is started by the reading unit 11, an analog image signal corresponding to the image of the read document is serially output from the reading unit 11 and input to the gate array 7. This image signal is converted into 8-bit image data by an A / D converter built in the gate array 7, subjected to various corrections such as shading correction and γ correction by the gate array 7, and then subjected to error diffusion processing. The signal is input to the arithmetic processing circuit 31 of the circuit 22.

On the other hand, when the reading unit 11 starts reading the first line of each page of the read document,
The first line processing signal supplied to the NAND circuit 24 is set to the high level, and the initial value flag stored in the EEPROM 6 is read out. If the initial value flag is “1”, that is, on, the NAND circuit 24 is turned on. To a high level. Of course, actually, the first line processing signal and the selection signal are C
The data is set in a register (not shown) by the PU 1 and output from the register to the NAND circuit 24. Now, assuming that the initial value flag is on, the output of the NAND circuit 24 goes low, and the clear signal inside the latch circuit 21 goes high. The data is output as error data to the arithmetic processing circuit 31 of the error diffusion processing circuit 22. That is,
In this state, initial value data is selected as error data, and the initial value is 0.

As a result, the arithmetic processing circuit 31 calculates the total sum data based on the image data and the error data for seven pixels, and outputs the calculation result to the error calculation circuit 32 and the binarization circuit 34. At this time, the error data are all 0, and the sum data is equal to the original image data. Then, the binarizing circuit 34 calculates the arithmetic processing circuit 31 based on the threshold data from the register 33 and the binarizing condition flag.
Is binarized and output to the RAM 3 and the error calculation circuit 32. Thereby, the error calculation circuit 32
An error between the sum data from the arithmetic processing circuit 31 and the binarized image data from the binarization circuit 34 is calculated, and the calculation result is output to the buffer memory 23 as error data. The writing of the error data to the buffer memory 23 and the reading of the error data from the buffer memory 23 are executed by a memory control circuit (not shown) provided in the error diffusion processing circuit 22.

When the above operation is repeated and the error diffusion processing of the image data corresponding to the pixels for one line is completed,
The CPU 1 sets the first line processing signal supplied to the NAND circuit 24 to low level. This allows NAND
Since the output of the circuit 24 becomes high level, the latch circuit 2
The internal clear signal goes low, and the latch circuit 2
1 outputs the error data read from the buffer memory 23 to the arithmetic processing circuit 31 of the error diffusion processing circuit 22.
That is, since error data for one line has already been stored in the buffer memory 23, they are used as error data for the previous line.

For example, as shown in FIG. 4, seven peripheral pixels B to H of the target pixel A are used for error diffusion processing, and the weights of the peripheral pixels B to H are set to 1, 2, 4, 2, 1, 2,. When set to 4, the arithmetic processing circuit 31 first sets the error data corresponding to the peripheral pixel B latched by the latch circuit 21 to 1
The image data is added to the value, and the result is stored in an output register (not shown) built in the arithmetic processing circuit 31. When the error data corresponding to the peripheral pixel C is latched by the latch circuit 21, the arithmetic processing circuit 31 multiplies the error data by 2/16 and adds the value to the value of the output register to obtain the output register. To be stored. When the error data corresponding to the peripheral pixel D is latched by the latch circuit 21, the arithmetic processing circuit 31 outputs the error data to 4/1.
The value is multiplied by 6, and the value is added to the value of the output register and stored in the output register. When the error data corresponding to the peripheral pixel E is latched by the latch circuit 21, the arithmetic processing circuit 31 multiplies the error data by 2/16 and adds the value to the value of the output register to obtain the output register. To be stored. When the error data corresponding to the peripheral pixel F is latched by the latch circuit 21, the arithmetic processing circuit 31 multiplies the error data by 1/16 and adds the value to the value of the output register to obtain the output register. To be stored. When the error data corresponding to the peripheral pixel G is latched by the latch circuit 21, the arithmetic processing circuit 31 multiplies the error data by 2/16 and adds the value to the value of the output register to obtain the output register. To be stored. If the latch circuit 21 latches the error data corresponding to the peripheral pixel H, the arithmetic processing circuit 3
1 multiplies the error data by 4/16, adds the value to the value of the output register, and stores the result in the output register. When the calculation processing of the sum data using the peripheral pixels B to H is completed in this way, the data stored in the output register is output to the error calculation circuit 32 and the binarization circuit 34 as the sum data.

The processing of the sum data is the same as the processing of the first line described above. In this manner, the image data corresponding to each pixel on the second and subsequent lines is sequentially processed, and the processing for one page is executed. From the second page onwards, 1
The same procedure as the processing for the page is repeated.

By the way, if the initial value flag stored in the EEPROM 6 is set to "0", that is, off, the CPU 1 sets the selection signal supplied to the NAND circuit 24 to low level. Accordingly, even in the processing of the first line, not only the pixels G and H of the current line but also the error data corresponding to the pixels BF of the previous line are sequentially read from the buffer memory 23 from the latch circuit 21. The data is latched by the latch circuit 21 and supplied to the arithmetic processing circuit 31 of the error diffusion processing circuit 22. Pixel B on this previous line
The error data corresponding to F is stored in the ROM 5 in advance as initial error data, and the CPU 1 reads out the data from the ROM 5 and stores it in the buffer memory 23 before the reading unit 11 starts reading a document.

As described above, depending on whether the selection signal supplied to the NAND circuit 24 is asserted or negated,
Whether to use the initial error data or the initial value data for the processing of the first line can be switched. Therefore, an appropriate error diffusion process according to the type of image data can be executed, and a high-quality image can be obtained when printing or the like. For example, when performing error diffusion processing on image data having an error due to reading, such as image data read by the image sensor of the reading unit 11, initial value data is used for processing on the first line. When error diffusion processing is performed on image data having no errors due to reading, such as image data uniquely created by a personal computer, initial error data is used as error data in the processing of the first line. By using this, it is possible to execute an appropriate error diffusion process according to the type of image data.

In the above embodiment, the latch circuit 21
Is cleared to generate the initial value data whose content is 0, and this is used as error data. However, the initial value data may be a value other than 0. For example, both the initial error data and the initial value data are stored in the ROM 5 in advance, and the CPU 1 reads out the ROM
5, one of the initial error data and the initial value data may be read and stored in the buffer memory 23. In this case, the ROM 5 constitutes initial value data storage means for storing initial value data.
Further, the CPU 1 constitutes selection means for selectively supplying the initial error data stored in the initial error data storage means and the initial value data stored in the initial value data storage means to the error diffusion processing means. become.

In the above-described embodiment, an example in which monochrome image data is processed has been described. However, color image data can be similarly processed. That is, in the case of color image data, error diffusion processing may be performed on the image data for each of the colors cyan, magenta, yellow, and black.

Further, in the above-described embodiment, the image processing apparatus according to the present invention is incorporated in a facsimile apparatus. However, the image processing apparatus according to the present invention can be applied to a printer, a copier, or a multifunction machine having various functions including them. The same effect can be exerted even when incorporated. For example, in the case of a multifunction device having a printer function and a copy function, one of the initial error data and the initial value data is selected according to the function to be used, and error diffusion is performed. What is necessary is just to comprise so that a process may be performed.

[0040]

As described above, according to the image processing apparatus of the first aspect of the present invention, the data selection unit performs the processing of the image data of the first line by the error diffusion processing unit. Can be used as predetermined initial error data determined in advance for each pixel, and can be used as error data of a previous line in processing of image data of a first line by error diffusion processing means. The predetermined initial value data common to the pixels is selectively supplied to the error diffusion processing means based on selection information from the outside. Therefore, when performing the error diffusion processing on the image data of the first line, One of the initial error value and the initial value can be selected. Therefore, an appropriate error diffusion process according to the image data can be performed, and a high-quality image can be obtained when printing is performed.

According to the image processing apparatus of the present invention, in addition to the effects of the image processing apparatus of the first aspect, the initial error data is stored in the initial error data storage means, Since the initial value data is stored in the data storage means, any value data can be set as the initial error data and the initial value data.

Further, according to the image processing apparatus of the present invention, in addition to the effect of the image processing apparatus of the first aspect, the initial value data generating means generates the initial value data. The initial value data storage means for storing the value data is unnecessary, and the storage capacity of the storage means can be reduced.

According to the image processing apparatus of the present invention, in addition to the effect of the image processing apparatus of the third aspect, data holding for supplying error data of the previous line to the error diffusion processing means. Since the circuit is used as the initial value data generating means, it is not necessary to provide the initial value data generating means independently, so that the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a facsimile apparatus including an image processing device according to the present invention.

FIG. 2 is a circuit block diagram of an error diffusion processing unit of the image processing device provided in the facsimile apparatus shown in FIG.

FIG. 3 is a circuit block diagram of an error diffusion processing circuit provided in the error diffusion processing unit shown in FIG.

FIG. 4 is an explanatory diagram of a range of peripheral pixels and a weight of each peripheral pixel with respect to a target pixel used for error diffusion processing.

[Explanation of symbols]

 1 CPU 3 RAM 5 ROM 6 EEPROM 11 Reading Unit 21 Latch Circuit 22 Error Diffusion Processing Circuit 23 Buffer Memory 24 NAND Circuit 31 Arithmetic Processing Circuit 32 Error Calculation Circuit 33 Register 34 Binarization Circuit

Claims (5)

[Claims] 1. An image processing apparatus having an error diffusion processing means for performing error diffusion processing on digital image data corresponding to pixels of a plurality of lines, wherein the error diffusion processing means performs Predetermined initial error data that can be used as error data of the previous line for processing and predetermined error data of each pixel in advance, and error data of the previous line are used for the processing of image data of the first line by the error diffusion processing means. And data selection means for selectively supplying predetermined initial value data common to all pixels to the error diffusion processing means based on selection information from the outside. Characteristic image processing device. 2. The data selection means, comprising: an initial error data storage means for storing the initial error data; an initial value data storage means for storing the initial value data; 2. The apparatus according to claim 1, further comprising a selection unit that selectively supplies the initial error data stored in the error data storage unit and the initial value data stored in the initial value data storage unit to the error diffusion processing unit. 3. The image processing apparatus according to any one of the preceding claims. 3. The data selection unit includes: an initial error data storage unit that stores the initial error data; an initial value data generation unit that generates the initial value data; 2. The apparatus according to claim 1, further comprising a selection unit that selectively supplies the initial error data stored in the error data storage unit and the initial value data generated by the initial value data generation unit to the error diffusion processing unit. 3. Image processing device. 4. The initial value data generating means supplies error data of a previous line to the error diffusion processing means when a clear signal input to a clear terminal is negated, and outputs a clear signal input to a clear terminal. 4. The image processing apparatus according to claim 3, further comprising a data holding circuit for supplying all-zero data to said error diffusion processing means when is asserted. 5. The selection means supplies a clear signal to a clear terminal of the data holding circuit, and outputs a signal indicating processing of image data on a first line and a signal indicating that initial value data should be used. The image processing apparatus according to claim 4, comprising a logic circuit that asserts the clear signal when is input.