JPH10303390A - Semiconductor device, semiconductor memory device and method for producing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high reliability by securing a sufficient storage capacity while suppressing the generation of step by suppressing the capacitor of DRAM small and low even when a semiconductor element is further made fine and highly integrated. SOLUTION: A side wall 20 composed of a polycrystalline silicon film is formed and connected with a polycrystalline silicon film 14 on the side face of side wall composed of a silicon oxide film. In this case, a storage node 21 in complicated structure is formed by integrating the polycrystalline silicon films 14 and 17 and the side wall 20. While using a silicon nitride film 12 as a stopper, the silicon oxide film and this side wall are removed by aerolotropic wet etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor memory device having a memory capacitor such as a DRAM.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. Accordingly, in a DRAM which is a typical semiconductor memory device, a lower electrode (storage node electrode) and an upper electrode (cell plate electrode) are made of a dielectric material in order to increase the effective memory cell capacity of the memory capacitor. A so-called stack type memory capacitor which is arranged to face through a film is widely used. In such a memory capacitor, the capacity of the memory cell is determined by the facing area of the storage node electrode and the cell plate electrode.

[0003]

However, as the miniaturization and higher integration of the semiconductor device further progress, the occupied area of the memory capacitor decreases while the storage capacity required for the memory capacitor remains unchanged. In this case, in order to increase the effective facing area between the storage node electrode and the cell plate electrode, the thickness of the storage node electrode must be increased. Then, due to a step between the memory cell portion and its peripheral circuit portion, which is caused mainly by the height of the memory capacitor, a resolution failure is likely to occur in photolithography performed in a later process.

A technique for increasing the surface area of a storage node electrode of a memory capacitor is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-209.
086, a storage node electrode of a memory capacitor is formed in a cylindrical shape, or a storage node electrode is formed in a fin shape, for example, as described in JP-A-7-202028. There is a known technique. These techniques are techniques for increasing the substantial surface area of the storage node electrode by forming the storage node electrode into a structure in which the storage node electrode is entangled upward or laterally.

Another method for increasing the surface area of the storage node electrode is disclosed in Japanese Patent Application Laid-Open No. Hei 7-249693. In this method, a storage contact is buried, a second polycrystalline silicon film is further deposited on a first polycrystalline silicon film having a predetermined shape on an insulating film, and the second polycrystalline silicon film is deposited on the first polycrystalline silicon film.
This is a technique of forming a storage node electrode by anisotropically etching the entire surface of the polycrystalline silicon film and leaving the second polycrystalline silicon film only on the side surfaces of the first polycrystalline silicon film. According to this technique, the surface area of the storage node electrode can be increased by the second sidewall.

However, as described above, even if the storage node electrode has a structure in which the storage node electrode is entangled above or to the side or a sidewall made of polycrystalline silicon is formed on the side surface, miniaturization and high integration of a semiconductor element in the future will occur. It is difficult to say that it can sufficiently cope with such changes, and further measures are needed.

In view of the foregoing, an object of the present invention is to respond to recent demands for further miniaturization and higher integration of semiconductor devices, while suppressing the occurrence of steps by reducing the size and height of capacitors. Another object of the present invention is to provide a semiconductor device, a semiconductor memory device, and a method for manufacturing the same, which can secure a sufficient storage capacity.

[0008]

According to the present invention, there is provided a semiconductor memory device in which an access transistor having a gate and a pair of impurity diffusion layers and a memory in which a lower electrode and an upper electrode face and are capacitively coupled to each other via a dielectric film. And a lower electrode of the memory capacitor,
A first insulating film covering the access transistor is bored to fill an opening exposing a part of the surface of one of the impurity diffusion layers, and further extends above the opening, and a center near an upper end is substantially centered. Has an umbrella-shaped gentle side wall surface and has a shape in which the inside of the umbrella-shaped portion is removed except for a part thereof, and is exposed above the first insulating film from the opening. The dielectric film is formed so as to cover the surface of the lower electrode.

In one embodiment of the semiconductor memory device according to the present invention, the lower electrode and the upper electrode are each made of a polycrystalline silicon film.

[0010] In one embodiment of the semiconductor memory device of the present invention, the upper electrode is formed so as to bury the lower electrode covered with the dielectric film.

In one embodiment of the semiconductor memory device of the present invention, a second insulating film having a low etching rate is formed on the first insulating film, and the opening is formed along with the first insulating film in the second insulating film. 2 is formed on the insulating film.

In one embodiment of the semiconductor memory device according to the present invention, the umbrella-shaped portion of the lower electrode has a first electrode portion which rises substantially upward with the gentle side wall surface, and a lateral portion inside the first electrode portion. A second electrode portion that extends.

[0013] A semiconductor device according to the present invention comprises a semiconductor region, a first insulating film formed on the semiconductor region and having an opening formed to expose a part of the surface of the semiconductor region; Filling and further extending above the aperture,
A first conductive film having a shape in which an umbrella-shaped gentle side wall surface is spread laterally with the vicinity of the upper end substantially as a center, and the inside of the umbrella-shaped portion is removed leaving a part thereof; A second insulating film formed to cover the surface of the first conductive film exposed above the first insulating film;
And a second conductive film formed to face the first conductive film with the insulating film interposed therebetween.

In one embodiment of the semiconductor device of the present invention, the second insulating film functions as a dielectric film, and the first conductive film and the second conductive film are capacitively coupled.

In one embodiment of the semiconductor device of the present invention, the second conductive film is formed so as to bury the first conductive film covered with the second insulating film.

According to the method of manufacturing a semiconductor memory device of the present invention, there is provided an access transistor having a gate and a pair of impurity diffusion layers, and a memory capacitor in which a lower electrode and an upper electrode face each other via a dielectric film and are capacitively coupled. A method of manufacturing a semiconductor memory device comprising: a first step of forming a first insulating film covering the access transistor;
A second insulating film having a low etching rate, a third
A second step of sequentially depositing an insulating film, a first conductive film, and a fourth insulating film, and the fourth insulating film, the first conductive film, the third insulating film, and the second insulating film. An insulating film and the first
A third step of patterning the insulating film to form an opening exposing a part of the surface of the impurity diffusion layer of one of the access transistors; and forming the fourth step so as to fill the opening. A fourth step of depositing a second conductive film on the insulating film and subsequently depositing a fifth insulating film on the second conductive film; and forming the fifth conductive film as a stopper using the first conductive film as a stopper. A fifth step of patterning the insulating film, the second conductive film and the fourth insulating film to leave them in a predetermined shape with the opening substantially at the center; and
Depositing a sixth insulating film on the first conductive film so as to cover the second conductive film and the fifth insulating film, and subsequently anisotropically etching the sixth insulating film; A sixth step of leaving the sixth insulating film on at least a side surface of the second conductive film, and the first step so as to cover the fifth and sixth insulating films.
A third conductive film is deposited on the conductive film, and then the first and third conductive films are anisotropically etched using the sixth insulating film as a mask and the third insulating film as a stopper. ,
A seventh step of leaving the third conductive film from the side surface of the remaining first conductive film to the side surface of the sixth insulating film, and the third step by wet etching using the second insulating film as a stopper. The insulating film, the fourth insulating film, the fifth insulating film, and the sixth insulating film are removed, and the first conductive film, the second conductive film, and the third conductive film are integrated. An eighth step of forming the lower electrode.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the first conductive film in the shape of the lower electrode exposed upward from the opening after the eighth step, the second conductive film,
A ninth step of forming a seventh insulating film functioning as the dielectric film so as to cover the surfaces of the conductive film and the third conductive film.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, after the ninth step, a fourth conductive film is deposited so as to bury the lower electrode covered with the seventh insulating film. And a tenth step of forming the upper electrode.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, the first conductive film, the second conductive film, the third conductive film, and the fourth conductive film are each made of polycrystalline. A silicon film is formed as a material.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, in the second step, a first layer functioning as a planarizing film between the first insulating film and the second insulating film is provided. 8 is formed.

[0021]

In the semiconductor memory device (semiconductor device) of the present invention, the lower electrode has an umbrella-shaped portion which spreads laterally in an umbrella shape. This umbrella-shaped portion has an internal structure (for example, a shape that spreads laterally inside the umbrella-shaped portion), with its side wall rising almost upward with a gentle side wall surface, and the inside thereof being removed except for a part. It has a complicated shape. That is, in this umbrella-shaped portion, the gentle side wall surface of the side wall and the inner surface of the internal structure are all the surfaces,
Even if the height is formed relatively low, it will have a sufficient surface area.

In the method of manufacturing a semiconductor memory device according to the present invention, in the fourth step, a first insulating film, a second insulating film, a third insulating film, and a first insulating film are sequentially deposited on a semiconductor substrate. A second conductive film is formed so as to fill the patterned openings in the conductive film and the fourth insulating film. At this time, the second conductive film is connected to the first conductive film on the inner wall surface of the opening and is deposited on the fourth insulating film. Subsequently, after depositing a fifth insulating film over the second conductive film, in a fifth step, using the first conductive film as a stopper, the fifth insulating film, the second conductive film, The fourth insulating film is patterned. At this time, an upper portion of the second conductive film is formed in a predetermined shape on the fifth insulating film, which spreads laterally around the opening substantially in accordance with the patterning.

Subsequently, in a sixth step, a sixth insulating film is formed in a first sidewall shape on at least the side surface of the second conductive film. Subsequently, in a seventh step, a third conductive film is deposited, and the third conductive film and the first conductive film are
Anisotropic etching is performed using the first insulating film (first sidewall) as a mask to remove the first conductive film other than the portion surrounded by the sixth insulating film (first sidewall) and to remove the remaining portion. A third conductive film is formed in a second sidewall shape from the side surface of the first conductive film to the side surface of the sixth insulating film (first sidewall). At this time, the third conductive film (the second sidewall) is connected to the first conductive film, and the upper part of the second conductive film and the sixth insulating film (the first sidewall) are connected. Face each other. Thereafter, all of the third to sixth insulating films are removed by wet etching. The third to sixth insulating films form the second
Since the first to third conductive films were surrounded above the first insulating film, the third to sixth insulating films were removed, thereby integrating into a complicated shape above the second insulating film. The lower electrode composed of the first to third conductive films thus formed is formed.
The entire surface of the exposed surface of the lower electrode is a portion that is capacitively coupled to the upper electrode through the dielectric film.

Therefore, even if the lower electrode is formed relatively low in order to eliminate a step between the memory cell portion and its peripheral circuit portion, the surface area of the lower electrode that is capacitively coupled to the upper electrode becomes extremely large. , Sufficient storage capacity can be obtained.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. In this embodiment, a so-called COB (Capacitor) in which an access transistor and a memory capacitor are provided as a semiconductor memory device, and the memory capacitor is formed substantially above a bit line.
An example of a DRAM having an Over Bitline structure will be described, and the configuration thereof will be described together with a manufacturing method. 1 to 4 are schematic sectional views showing a method of manufacturing a DRAM of this embodiment in the order of steps.

First, as shown in FIG.
A field oxide film 3 is formed as a device isolation structure on a silicon semiconductor substrate 1 of a mold by a so-called LOCOS method to define a device formation region 2. Instead of the field oxide film 3, a conductive film is buried in the oxide film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed to a predetermined potential by the conductive film to perform element isolation. May be formed.

Next, the surface of the silicon semiconductor substrate 1 in the element forming region 2 which is separated and relatively defined by the field oxide film 3 is subjected to thermal oxidation to form a silicon oxide film. Is deposited to form a polycrystalline silicon film.

Next, the silicon oxide film and the polycrystalline silicon film are patterned by photolithography and subsequent dry etching to leave the silicon oxide film and the polycrystalline silicon film in the element formation region 2 in the form of an electrode. The gate electrode 5 is formed.

Then, after the photoresist used for patterning is removed by ashing, a silicon oxide film is deposited and formed on the entire surface including the gate electrode 5 by CVD, and the entire surface of the silicon oxide film is made anisotropic. Etching is performed to form a sidewall 6 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 4 and the gate electrode 5.

Next, using the gate electrode 5 and the side wall 6 as a mask, an impurity is introduced into the surface region of the silicon semiconductor substrate 1 on both sides of the gate electrode 5 by ion implantation to form a pair of impurity diffusion layers 7 serving as a source / drain. Then, an access transistor having the gate electrode 5 and the pair of impurity diffusion layers 7 is completed.

Next, as shown in FIG. 1B, CV is applied to the entire surface of the silicon semiconductor substrate 1 including the field oxide film 3.
A silicon oxide film is deposited and formed by the D method, and an interlayer insulating film 8 is formed.
To form

Next, a bit line (not shown) electrically connected to one of the impurity diffusion layers 7 (which becomes a drain) in the interlayer insulating film 8.
Is patterned to form an interlayer insulating film 8 (and bit lines).
A flattening layer 11 made of borophosphosilicate glass (BPSG) or the like is formed thereon by CVD to a thickness of about 50 nm. Subsequently, a silicon nitride film 12, a silicon oxide film 13, a polycrystalline silicon film 14 and a silicon oxide film 15 are
About 0 nm, about 50 nm, about 50 nm and 50 nm
It is sequentially formed to the degree.

Next, as shown in FIG. 1C, the silicon oxide film 15, the polycrystalline silicon film 14, the silicon oxide film 13, the silicon nitride film 12, the planarizing layer 11, and the interlayer insulating film 8 are subjected to photolithography and Subsequently, patterning is performed by dry etching to form a storage contact 16 exposing a part of the surface of the other impurity diffusion layer 7 (to be a source) of the access transistor.

Next, as shown in FIG. 2A, a polycrystalline silicon film 17 is further deposited on the silicon oxide film 15 to a thickness of about 50 nm by the CVD method so as to fill the storage contact 16. At this time, the polycrystalline silicon film 17 is connected to the polycrystalline silicon film 14 on the inner wall surface of the storage contact 16 and is deposited on the silicon oxide film 15. Subsequently, the polycrystalline silicon film 1
A silicon oxide film 18 is deposited and formed on the substrate 7 by a CVD method.

Next, as shown in FIG. 2B, the silicon oxide film 1 is formed using the polycrystalline silicon film 14 as a stopper.
8. Photolithography and subsequent dry etching are performed on the polycrystalline silicon film 17 and the silicon oxide film 15 to pattern them into a predetermined shape. At this time, the polycrystalline silicon film 17 is formed on the silicon oxide film 15 to have a shape that spreads laterally around the storage contact 16 substantially in accordance with the patterning.

Next, as shown in FIG. 2C, the polycrystalline silicon film 14 is formed on the polycrystalline silicon film 14 by CVD so as to cover the silicon oxide film 15, the polycrystalline silicon film 17 and the silicon oxide film 18 having the predetermined shapes. Then, a silicon oxide film is deposited and formed. Subsequently, the entire surface of the silicon oxide film is anisotropically etched to form a sidewall 19 while leaving the silicon oxide film on the side surfaces of the silicon oxide film 15, the polycrystalline silicon film 17, and the silicon oxide film 18 having the predetermined shapes. I do.

Next, as shown in FIG. 3A, C is applied so as to cover the silicon oxide film 18 and the side wall 19.
A polycrystalline silicon film is further deposited on the polycrystalline silicon film 14 by the VD method. Subsequently, using the silicon oxide film 13 as a stopper and the sidewalls 19 as a mask,
The entire surface of the polycrystalline silicon film and the polycrystalline silicon film 14 under the polycrystalline silicon film are anisotropically etched to remove the polycrystalline silicon film 14 other than the portion surrounded by the side wall 19 and to remove the remaining polycrystalline silicon film 14. The sidewall 20 is formed while leaving the polycrystalline silicon film from the side to the side surface of the sidewall 19. At this time, the side wall 20 made of the polycrystalline silicon film is
And is opposed to a portion above the polycrystalline silicon film 17 via a side wall 19.

Next, as shown in FIG. 3B, using the silicon nitride film 12 as a stopper,
3. The silicon oxide film 15, the silicon oxide film 18, and the side wall 19 are removed by isotropic wet etching. At this time, a portion 21a extending above the storage contact 16, a portion 21b of the polycrystalline silicon film 14 connected to the portion 21a and spreading laterally, and a substantially T-shaped cross section connected to the portion 21b Storage electrode having a portion 21d of the side wall 19 connected to the portion 21c of the polycrystalline silicon film 17 and an end of the portion 21b, and rising almost upward with an umbrella-shaped gentle side wall surface. 21 are formed.

Next, as shown in FIG. 3C, a silicon oxide film and a silicon nitride film each having a predetermined thickness are formed on the surface of the storage node electrode 21, that is, the surface of the storage node electrode 21 located above the storage contact 18. A film and a silicon oxide film are sequentially formed to cover the surface.
A dielectric film 22 made of a NO film is formed.

Next, as shown in FIG. 4, a polycrystalline silicon film is deposited and formed so as to bury the storage node electrode 21, and the storage node electrode 2 is interposed via the dielectric film 22.
1 and a cell plate electrode 23 facing the surface is formed, and a memory capacitor including the storage node electrode 21, the dielectric film 22, and the cell plate electrode 23 is completed. At this time, in the storage node electrode 21 of the memory capacitor, not only the umbrella-shaped portion extending laterally with the upper end substantially at the center, but also the substantially T-shaped portion 21c inside the portion 21d of the sidewall 19 is also a cell plate electrode. 23. Therefore, a memory capacitor having a sufficient storage capacitance can be obtained even if the storage node electrode 21 is formed relatively low in order to suppress the formation of a step which tends to occur between the memory cell portion and its peripheral circuit portion. be able to.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a contact hole and subsequent formation of a wiring layer, formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion And the like are often formed sequentially.), Etc., to complete the DRAM.

As described above, the D according to the embodiment of the present invention is
According to the RAM, even if further miniaturization and higher integration are performed, the memory capacitor is kept small and the height is kept low to suppress the occurrence of steps, while ensuring sufficient memory cell capacity and high reliability. Can be realized.

In this embodiment, the COB structure D
Although the RAM has been described, the present invention is not limited to this. For example, a so-called CUB (Capacitor Under) in which a memory capacitor is formed substantially below a bit line.
Bitline) structure is also applicable to DRAM.

[0044]

According to the present invention, in response to recent demands for further miniaturization and higher integration of semiconductor devices, the size of the capacitor is reduced and the height is reduced to suppress the occurrence of steps. In addition, it is possible to secure a sufficient storage capacity and realize high reliability.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 2 is a continuation of FIG. 1 showing D in an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 3 is a continuation of FIG. 2 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 4 is a continuation of FIG. 3 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element formation area 3 Field oxide film 4 Gate oxide film 5 Gate electrode 6, 17 Side wall 7 Impurity diffusion layer 8 Interlayer insulating film 11 Flattening film 12 Silicon nitride film 13, 15, 18 Silicon oxide film 14, Reference Signs List 17 Polycrystalline silicon film 16 Storage contact 19 Sidewall (made of silicon oxide film) 20 Sidewall (made of polycrystalline silicon film) 21 Storage node electrodes 21a to 21d Each part (of storage node electrode 21) 22 Dielectric film 23 Cell plate electrode

Claims (13)

[Claims] 1. A semiconductor memory device comprising: an access transistor having a gate and a pair of impurity diffusion layers; and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. The lower electrode of the capacitor fills an opening exposing a part of the surface of one of the impurity diffusion layers by piercing a first insulating film covering the access transistor, and further extends above the opening. At the same time, the umbrella-shaped portion has a shape in which the inside of the umbrella-shaped portion is removed leaving a part thereof removed, and the first umbrella-shaped portion is removed from the first hole through the first hole. Wherein the dielectric film is formed so as to cover a surface of the lower electrode exposed above the insulating film. 2. The semiconductor memory device according to claim 1, wherein said lower electrode and said upper electrode are each made of a polycrystalline silicon film. 3. The semiconductor memory device according to claim 1, wherein the upper electrode is formed so as to bury the lower electrode covered with the dielectric film. 4. The method according to claim 1, wherein a second insulating film having a low etching rate is formed on the first insulating film, and the opening is formed in the second insulating film together with the first insulating film. The semiconductor memory device according to claim 1, wherein: 5. The umbrella-shaped portion of the lower electrode has a first electrode portion standing substantially upward with the gentle side wall surface, and a second electrode portion extending laterally inside the first electrode portion. The semiconductor memory device according to claim 1, wherein: 6. A semiconductor region, a first insulating film deposited on the semiconductor region and having an opening formed to expose a part of the surface of the semiconductor region, filling the opening, and further comprising: A first portion having a shape extending above the opening and having a gently umbrella-shaped side wall surface extending sideways with the vicinity of the upper end substantially as a center, and the inside of the umbrella-shaped portion being removed leaving a part thereof. A conductive film, a second insulating film formed so as to cover a surface of the first conductive film exposed from the opening above the first insulating film, and via the second insulating film A semiconductor device comprising: a second conductive film formed so as to face the first conductive film. 7. The semiconductor device according to claim 6, wherein the second insulating film functions as a dielectric film, and the first conductive film and the second conductive film are capacitively coupled. . 8. The method according to claim 6, wherein the second conductive film is formed so as to bury the first conductive film covered with the second insulating film. Semiconductor device. 9. A method for manufacturing a semiconductor memory device, comprising: an access transistor having a gate and a pair of impurity diffusion layers; and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. A first step of forming a first insulating film covering the access transistor; a second insulating film, a third insulating film, and a first conductive film having a low etching rate on the first insulating film; And a second step of sequentially depositing a fourth insulating film, and the fourth insulating film, the first conductive film, the third insulating film, the second insulating film, and the first insulating film. Forming an opening exposing a part of the surface of the impurity diffusion layer of one of the access transistors.
And a second step on the fourth insulating film so as to fill the opening.
A fourth step of depositing a conductive film, and subsequently depositing a fifth insulating film on the second conductive film; and using the first conductive film as a stopper, the fifth insulating film, Patterning the second conductive film and the fourth insulating film so as to leave them in a predetermined shape with the opening substantially at the center;
And depositing a sixth insulating film on the first conductive film so as to cover the fourth insulating film, the second conductive film, and the fifth insulating film of the predetermined shape, A sixth step of anisotropically etching the sixth insulating film so as to leave the sixth insulating film on at least a side surface of the second conductive film; and covering the fifth and sixth insulating films. A third conductive film is deposited on the first conductive film as described above, and then the first and third conductive films are different using the sixth insulating film as a mask and the third insulating film as a stopper. A seventh step of performing isotropic etching to leave the third conductive film from the side surface of the remaining first conductive film to the side surface of the sixth insulating film, and a wet process using the second insulating film as a stopper. The third insulating film, the fourth insulating film, the fifth insulating film, and the sixth insulating film are etched by etching. An eighth step of forming the lower electrode in which the first conductive film, the second conductive film, and the third conductive film are integrated with each other. Production method. 10. The method according to claim 8, wherein after the eighth step, the first conductive film in the shape of the lower electrode exposed upward from the opening,
10. The method according to claim 9, further comprising a ninth step of forming a seventh insulating film functioning as the dielectric film so as to cover surfaces of the second conductive film and the third conductive film. The manufacturing method of the semiconductor memory device described in the above. 11. A tenth step of forming the upper electrode by depositing a fourth conductive film so as to bury the lower electrode covered with the seventh insulating film after the ninth step. The method according to claim 10, further comprising: 12. The method according to claim 1, wherein each of the first conductive film, the second conductive film, the third conductive film, and the fourth conductive film is formed using a polycrystalline silicon film. 12. The method for manufacturing a semiconductor memory device according to item 11. 13. The method according to claim 9, wherein an eighth insulating film functioning as a planarizing film is formed between the first insulating film and the second insulating film in the second step. ~ 1
3. The method for manufacturing a semiconductor memory device according to any one of 2.