JPH10303363A - Electronic component and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily perform miniaturization. SOLUTION: Plural bare chip components 1 are arranged so as to make a circuit surface 1a form one surface and sealed by an insulation material 3 so as to expose only an electrode part, and plural wiring layers 5 are laminated and formed through an insulation layer 4 on the side of the circuit surface 1a. Also, it is preferable to form the insulation layer 4 by photosensitive resin, form the insulation layer 4 on the circuit surface 1a of the bare chip components 1, laminate and form the plural wiring layers 5 through the insulation layer 4 on it, form a through-hole 7 which is a hole part for which a conductive material is disposed inside of the prescribed position of the insulation layer 4 and electrically connect the electrode part, the wiring layers 5 and the wiring layers 5 with each other. Also, a metal plate 8 in contact with a main surface 1b on the opposite side of the circuit surface 1a of the bare chip components 1 can be disposed as a heat radiation means. Or, a cover member for covering the insulation material 3 is provided, and a part of the cover member can be brought into contact with the main surface 1b on the opposite side of the circuit surface 1a of the bare chip components 1 and turned to the heat radiation means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component and a method of manufacturing the same, and is suitably applied to an electronic component such as a semiconductor device such as a multichip module and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device, a plurality of bare chip components are mounted at high density on a multilayer wiring board and the whole is miniaturized, so that the wiring length between the bare chip components is relatively shortened, and thus, There is a so-called multi-chip module in which the high-speed characteristics and high-frequency characteristics of each bare chip component are improved.

As shown in FIG. 14, usually, in a multi-chip module 101, an insulating layer made of a ceramic substrate or an organic substrate and a wiring layer made of a predetermined conductor pattern are sequentially laminated in the thickness direction. A plurality of bare chip components 103 are placed on one main surface 102a of the multilayer wiring board 102 (however, the illustration of the insulating layer and the wiring layer is omitted in FIG. 14). A plurality of pads (not shown), which are a plurality of electrode portions, formed on the circuit surface 103a on which the pattern is formed, and lands (not shown) corresponding to the respective pads in the wiring layer which is the uppermost layer of the multilayer wiring board 102 are formed of solder. Electrode 104
(Hereinafter, referred to as solder bumps 104.) It is mounted by being electrically and physically connected via a solder bump 104.

[0004] Incidentally, the multi-chip module 101
Since the thermal expansion coefficient of the multilayer wiring board 102 is twice or more the thermal expansion coefficient of the bare chip component 103, when the bare chip component 103 generates heat, the multilayer wiring board 102 and each bare chip component 103
In some cases, thermal stress concentrates on each solder bump 104 between them, and the solder bump 104 may be damaged.

For this reason, the multi-chip module 10
In 1, an insulating material (that is, an underfill material) 105 made of epoxy resin or the like is embedded in each solder bump 104 in a gap between one main surface 102 a of the multilayer wiring board 102 and a circuit surface 103 a of each bare chip component 103. Is filled. Thereby, this multi-chip module 1
In the example No. 01, the concentration of the thermal stress generated in each solder bump 104 is reduced by the insulating material 105, and thus the breakage of the solder bump 104 can be prevented. In addition, the insulating material 105 is used to prevent the solder bumps 104 from being damaged,
By covering a, the circuit surface 103a can be protected from failure due to impurities or moisture contained in the outside air.

[0006]

Incidentally, in the multi-map module 101 having such a configuration, in recent years, each bare chip component 103 is mounted on the one main surface 102a of the multilayer wiring board 102 at a higher density, so that the multi-map module 101 has a higher density. There is a demand for further miniaturization of the chip module 101.

However, in such a multi-chip module 101, when the interval between the bare chip components 103 is reduced to a certain extent or more, one main surface 102a of the multilayer wiring board 102 and the circuit surface 103 of each bare chip component 103
a, it is difficult to fill the gap between the solder bumps 104 with the insulating material 105, and it is difficult to prevent the solder bumps 104 from being damaged by the insulating material 105.
This makes it difficult to protect the circuit surface 103a. Therefore, when it is attempted to further reduce the size of the multi-chip module 101 by mounting each bare chip component 103 at a higher density,
The quality and reliability of the device have been significantly reduced, and miniaturization has been difficult.

The multi-chip module 101
When the number of bare chip components 103 mounted on one main surface 102a of the multilayer wiring board 102 increases, the amount of heat generated by the operation of each bare chip component 103 also increases, and the thermal expansion between the multilayer wiring board 102 and the bare chip component 103 increases. As described above, it is difficult to alleviate the thermal stress generated in each of the solder bumps 104 due to the difference in the coefficient by the insulating material 105 alone. Therefore, in such a case, it is conceivable to reduce the thermal stress concentrated on each solder bump 104 by making the size of each solder bump 104 relatively large in addition to the insulating material 105.

However, in such a case, it is necessary to enlarge the land of the multilayer wiring board 102 in accordance with the size of the solder bump 104, and there is a problem that the multilayer wiring board 102 becomes large. That is, as the multi-layer wiring board 102 becomes larger, the entire multi-chip module 101 also becomes larger, which makes it difficult to cope with downsizing.

Further, the multi-chip module 10
In No. 1, when the number of pads of each bare chip component 103 mounted on one main surface 102a of the multilayer wiring board 102 is relatively large, the number of wirings electrically connected to the lands of the multilayer wiring board 102 is correspondingly increased. This is relatively large, and it is necessary to increase the number of wiring layers of the multilayer wiring board 102.

However, in the multilayer wiring board 102, since the thickness of one insulating layer is usually about 0.1 (mm) and the number of insulating layers increases as the number of wiring layers increases, as described above, When the number of wiring layers is increased, the multilayer wiring board 102 becomes relatively thick in the thickness direction, and it is difficult to cope with miniaturization from this point as well.

Also, the multi-chip module 101
Therefore, when the number of bare chip components 103 mounted on one main surface 102a of the multilayer wiring board 102 increases, there is a problem that it is difficult to efficiently dissipate the heat generated by the operation of each bare chip component 103. It was a factor that hindered the conversion.

Accordingly, the present invention has been proposed in view of the actual situation in the related art, and has as its object to provide an electronic component which can be easily reduced in size and a method for manufacturing the same.

[0014]

In order to achieve the above object, an electronic component according to the present invention comprises a plurality of bare chips having a circuit surface formed with a circuit including an electrode portion having an electrode portion on one principal surface. The components are arranged so that these circuit surfaces form one surface, and these bare chip components are sealed with an insulating material so that only the electrode portions are exposed, and a plurality of wiring layers are insulated on the circuit surface side of the bare chip components. It is characterized by being formed by lamination through layers.

In the above electronic component of the present invention, the insulating layer is formed of a photosensitive resin, the insulating layer is formed on the circuit surface of the bare chip component, and a plurality of wiring layers are laminated on the insulating layer via the insulating layer. Forming, so as to form an insulating layer and a wiring layer in the same manner as a so-called build-up substrate, forming a hole in which a conductive material is disposed in a predetermined position of the insulating layer, by this hole, It is preferable to electrically connect the electrode portion, which is laminated via an insulating layer like a so-called through hole or via hole, to the wiring layers and the wiring layers.

Further, in the electronic component of the present invention, it is preferable that a heat radiating means is provided on a main surface side opposite to a circuit surface of the bare chip component. And, as a heat radiating means, a metal plate in contact with the main surface opposite to the circuit surface of the bare chip component is provided, or a cover member that covers an insulating material that seals a plurality of bare chip components is provided, and a bare chip component is provided. The heat dissipating means may be provided so that a part of the cover member contacts the main surface opposite to the circuit surface.

In the electronic component of the present invention,
Solder bumps may be formed on the electrode parts of the chip parts.When manufacturing the same, a plurality of bare chip parts having the solder bumps formed on the electrode parts of the circuit surface are formed, and these circuit surfaces are formed on one surface. The bare chip component is sealed so as to cover the bare chip component with an insulating material, and the resin on the circuit surface side of the bare chip component is removed to expose the solder bumps. An insulating layer made of conductive resin and having a hole in which a conductive material is disposed at a position corresponding to the electrode portion, and a plurality of wiring layers are formed on the insulating layer via the insulating layer in the same manner as a so-called build-up substrate. It is preferable to form a laminate.

Further, in the electronic component of the present invention, the electrode portion of the chip component may be made more convex than the circuit. In the case of manufacturing this, the surface of the electrode portion which is made to be a convex portion is used as a contact surface. After arranging a plurality of bare chip components on a plate, sealing the bare chip components with an insulating material, removing the plate material, exposing the surface of the electrode portion, the photosensitive resin is placed on the circuit surface side of the bare chip components. An insulating layer having a hole in which a conductive material is disposed is formed at a position corresponding to the electrode portion, and a plurality of wiring layers are stacked on the insulating layer via the insulating layer in the same manner as a so-called build-up substrate. Preferably, it is formed.

In the electronic component of the present invention, a plurality of bare chip components are arranged so that each circuit surface forms one surface, and these bare chip components are sealed with an insulating material so that only the electrode portions are exposed. Therefore, portions other than the electrode portion of the bare chip component are surely covered with the insulating material, and a plurality of wiring layers are laminated and formed on the circuit surface side of the bare chip component via the insulating layer. Even when mounted at a high density, resin is filled between the circuit surface of the bare chip component and the wiring portion, and the circuit surface is protected.

Further, in the electronic component of the present invention,
An insulating layer is formed of a photosensitive resin, an insulating layer is formed on a circuit surface of a bare chip component, and a plurality of wiring layers are formed on the insulating layer via an insulating layer, in the same manner as a so-called build-up board. An insulating layer and a wiring layer are formed, and a hole in which a conductive material is disposed is formed at a predetermined position of the insulating layer. The hole forms an insulating layer such as a so-called through hole or via hole. By electrically connecting the electrode portions and the wiring layers and the wiring layers laminated via the wiring layer, the wiring layers have a relatively high density, the wiring portions can be downsized, and the insulating layers can be relatively thin. Thus, the thickness of the wiring portion is reduced.

In the electronic component of the present invention, if a metal plate is provided as a heat radiating means, which is in contact with the main surface opposite to the circuit surface of the bare chip component, the heat generated by the operation of the electronic component can be efficiently used. Dissipates heat well.

Further, a cover member is provided so as to cover an insulating material for sealing the plurality of bare chip components, and a part of the cover member is in contact with a main surface of the bare chip component opposite to the circuit surface. If the heat radiating means is used, the final shape can be reduced in size.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

The electronic component of this embodiment is an electronic component 10 which is a multi-chip module as shown in FIG. 1, and one main surface 1a is a surface on which a circuit including an electrode portion having an electrode portion (not shown) is formed. A plurality of bare chip components 1 are arranged such that the one main surface 1a (hereinafter, referred to as a circuit surface 1a) forms one surface, and the bare chip components 1 are sealed with an insulating material 3 to form the bare chip components. A wiring section 6 in which a plurality of wiring layers 5 are stacked via an insulating layer 4 is arranged on one circuit surface 1a side.

A solder bump 2 is provided on each of the electrode portions of the circuit (not shown) on the circuit surface 1a of the bare chip component 1, and the insulating material 3 covers the circuit surface 1a of the bare chip component 1, Is sealed so that only the upper end portion (i.e., only the electrode portion) is exposed. The insulating material 3 is made of, for example, a resin such as an epoxy resin. That is, in the electronic component 10 of the present example, portions other than the electrode portions of the bare chip component 1 are surely covered with the insulating material 3.

In the wiring portion 6, the lowermost insulating layer 4 is formed on the circuit surface 1a of the bare chip component 1, and the lowermost wiring layer 5 is formed thereon. In addition, a wiring layer 5 is laminated and formed with an insulating layer 4 interposed therebetween. The uppermost layer is the insulating layer 4, and two wiring layers 5 are conveniently formed. The insulating layer 4 is made of a photosensitive resin, and the insulating layer 4 and the wiring layer 5 are formed in the same manner as a so-called build-up substrate.

In the electronic component 10 of the present embodiment, as described above, the portions other than the electrode portions of the bare chip component 1 are surely covered with the insulating material 3. Even if a plurality of wiring layers 5 are laminated via the insulating layer 4, the circuit surface 1a of the bare chip
And the wiring portion 6 is filled with resin to protect the circuit surface 1a. This is the same even if the bare chip component 1 is mounted at a high density.

In the wiring portion 6, via holes 7 are formed in the lowermost insulating layer 4 so as to correspond to the predetermined solder bumps 2 and to be through holes in which a conductive material is disposed. The solder bumps 2 are electrically connected to the lowermost wiring layer 5. Further, via holes 7 are also formed at predetermined positions of the other insulating layer 4, and electrically connect between different wiring layers 5 or between the solder bumps 7 and the wiring layer 5 which is not the lowermost layer. .

That is, in the electronic component 10 of the present embodiment, the wiring layer 5 has a relatively high density, the wiring portion 6 has a small size, the insulating layer 4 has a relatively small thickness, and the wiring portion 6 has a small thickness. Is made.

In the wiring layer 5 which is the uppermost layer,
On one end 5a side, a plurality of external terminals 5b (only one is shown in FIG. 1) which are end portions of the conductor pattern and serve as connection portions with the outside are formed, and an insulating layer which is an uppermost layer 4
Are formed on the uppermost wiring layer 5 so as to expose each external terminal 5b.

That is, in the electronic component 10 of the present embodiment, each external terminal 5b is electrically connected to the corresponding electrode of the mother board (not shown), so that in each bare chip component 1, the corresponding solder bump 2 , Wiring layer 5, via hole 7, external terminal 5
b, a signal from the motherboard is sequentially input through
Alternatively, a signal can be output.

Further, in the electronic component 10 of the present embodiment, a disconnection of the wiring layer 5 and the via hole 7 corresponding to each external terminal 5b is achieved by bringing a probe (not shown) of an inspection device (not shown) into contact with each external terminal 5b. Or not,
It is possible to easily inspect whether the solder bumps 2 are damaged or not, and whether or not the bare chip components 1 are faulty.

Further, in the electronic component 10 of the present embodiment,
A metal plate 8 is provided via a bonding material 9 so as to be in contact with a main surface 1b opposite to the circuit surface 1a of the bare chip component 1 so that heat generated by the operation of the bare chip component 1 can be efficiently radiated. It has been done.

That is, in the electronic component 10 of this embodiment, since the portions other than the electrode portions of the bare chip component 1 are securely covered with the insulating material 3, even if the bare chip component 1 is mounted at a high density, A resin is filled between the circuit surface 1a and the wiring portion 6, the circuit surface 1a is protected, and the bare chip component 1 can be mounted at high density to reduce the size without deteriorating quality and reliability. In the electronic component 10 of the present embodiment, the solder bumps 2 are also prevented from being damaged because the upper ends of the solder bumps 2 are sealed with the insulating material 3 so as to be exposed.

In the electronic component 10 of this embodiment, since the insulating layer 4 and the wiring layer 5 are formed in the same manner as the build-up substrate, the wiring layer 5 has a relatively high density.
The size of the wiring portion 6 is reduced, the insulating layer 4 is made relatively thin, and the thickness of the wiring portion 6 is reduced, so that the size can be reduced. That is, when the insulating layer 4 is formed as described above, the thickness thereof is about 20 (μm) to 30 (μm), and the thickness of the insulating layer 4 is far more than that of a conventionally used multilayer wiring board. Thinning is possible.

Further, in the electronic component 10 of this embodiment,
Since a photosensitive resin having a relatively low coefficient of thermal expansion is used as the insulating layer 4, even when the number of bare chip components 1 is increased, the difference is caused by a difference in the coefficient of thermal expansion between the wiring portion 6 and the bare chip component 1. Thermal stress is hardly generated, and the thermal stress concentrated on the solder bump 2 can be reduced by the insulating material 3 alone without increasing the size of the solder bump 2.

Furthermore, in the electronic component 10 of the present embodiment, since the metal plate 8 is disposed so as to be in contact with the main surface 1b of the bare chip component 1, the heat generated by the operation of the bare chip component 1 is efficiently radiated. It is made possible, and can be reduced in size.

Next, a method for manufacturing the above-described electronic component will be described. That is, first, as shown in FIG. 2, the solder bumps 2 are respectively formed on a plurality of electrode portions (not shown) formed on each circuit surface 1a of each bare chip component 1. Thereafter, each bare chip component 1 is connected to the circuit surface 1 respectively.
The metal plate 8 is arranged in a predetermined state such that a faces upward and forms one surface, and is adhered by a bonding agent 9.

Next, as shown in FIG. 3, an insulating material such as a resin such as epoxy resin is used to embed each bare chip part 1 and each solder bump 2 by using a predetermined molding apparatus (not shown). 3 and molded as a mold sheet 13 to seal the bare chip components 1. In this way, the bare chip component 1 can be securely fixed by the insulating material 3 and the circuit surface 1a can be reliably covered by the insulating material 3 irrespective of the interval between the bare chip components 1. The circuit surface 1a can be protected from impurities and moisture contained in the outside air. Therefore, the interval between the bare chip components 1 can be significantly narrower than the interval between the bare chip components in an electronic component such as the above-described conventional multi-chip module without deteriorating the characteristics. That is, the bare chip component 1 can be mounted at a high density, and the electronic component manufactured in this manner can be reduced in size without deteriorating quality and reliability.

Next, as shown in FIG. 4, the mold sheet 1 on the circuit surface 1a side of the bare chip component 1 is so arranged that the height of each solder bump 2 is uniformly equal to a predetermined height.
3 is polished and removed by a predetermined polishing machine (not shown) to expose an upper portion of each solder bump 2.
Thus, each bare chip component 1 is integrally sealed with the insulating material 3 so that the circuit surface 1a is covered and the upper part of each solder bump 2 is exposed, and the mold sheet 13 to which the metal plate 8 is attached is formed. Will be done.

Subsequently, the wiring section 6 is formed on the mold sheet 13. That is, a photosensitive resin, for example, polyimide, is dropped or applied to the upper surface 13a of the mold sheet 13 where the solder bumps 2 are exposed. Then, spin coating is performed, and the photosensitive resin is, for example, 30 (μm) to 50 (μm).
m).

Next, the photosensitive resin is cured by placing the mold sheet 13 in a predetermined heating furnace (not shown) in which the inside is maintained at a predetermined temperature and heating for a predetermined time. Thereafter, through holes 7a having a predetermined diameter are formed at predetermined positions corresponding to the predetermined solder bumps 2 of the cured photosensitive resin by a predetermined photo process, as shown in FIG. Sheet 13
An insulating layer 4 made of a photosensitive resin and serving as a lowermost layer is formed on the upper surface 13a of the substrate.

Further, copper is sputtered on the insulating layer 4 and on the inner peripheral surface of each through hole 7a using a predetermined sputtering device (not shown), and a copper thin film having a predetermined thickness is laminated on the insulating layer 4. At the same time, a plurality of via holes 7 are formed. Thereafter, the copper thin film is patterned by a photo process, and as shown in FIG. 6, the lowermost wiring layer 5 made of a conductor pattern electrically connected to the corresponding via hole 7 on the lowermost insulating layer 4 as shown in FIG. To form

Thus, each electrode portion of the bare chip component 1 is electrically connected to the corresponding wiring layer 5 via the corresponding solder bump 2 and via hole 7 sequentially.

Further, similarly, as shown in FIG. 6, the uppermost wiring layer 5 is formed on the lowermost wiring layer 5 via the insulating layer 4.

At this time, needless to say, the uppermost wiring layer 5 has the external terminal 5b at one end 5a, and the via hole 7 is also formed in the insulating layer 4 interposed between the wiring layers 5. Needless to say, the wiring layers 5 are electrically connected.

Further, a photosensitive resin such as polyimide is dropped or applied onto the wiring layer 5 as the uppermost layer, and then spin-coated to cover the wiring layer 5 with the photosensitive resin. Next, the mold sheet 13 is placed in a predetermined heating furnace (not shown) and heated for a predetermined time to cure the photosensitive resin, thereby forming the uppermost insulating layer 4 on the uppermost wiring layer 5. . After that, the wiring layer 5 serving as the uppermost layer
A predetermined one end side of the uppermost insulating layer 4 formed by lamination is separated by a predetermined photo process so as to have a predetermined width. As a result, each external terminal 5b of the wiring layer 5, which is the uppermost layer, is exposed. In this way, the wiring portion 6 in which the insulating layer 4 and the wiring layer 5 are sequentially and alternately laminated is formed on the mold sheet 13 to complete the electronic component.

In this embodiment, since the wiring layer 5 is formed by processing a copper thin film by a predetermined photo process, the pattern of each wiring layer 5 has a line width and a line interval of 2 mm.
The pattern becomes about 0 (μm) to about 30 (μm), and it is possible to form a wiring layer having a higher density than a wiring layer of a conventional electronic component such as a multichip module.
Can be reduced in size, and the electronic components to be manufactured can be reduced in size.

Further, in this embodiment, the thickness of one layer of the insulating layer 4 is about 30 (.mu.m) to 50 (.mu.m), which is much thinner than the insulating layer of a conventional electronic component such as a multichip module. A layer can be formed, the wiring portion 6 can be reduced in thickness, and the manufactured electronic component can be reduced in size and weight.

Further, in this embodiment, a polyimide resin having a relatively low coefficient of thermal expansion as compared with an insulating layer used as a conventional multi-layer wiring board for electronic components such as a multi-chip module or an organic substrate. The insulating layer 4 is formed by the above-described method. Even if the number of bare chip components 1 is significantly increased as compared with the number of bare chip components mounted on electronic components such as a conventional multi-chip module, each solder The thermal stress concentrated on each solder bump 2 can be reduced only by the insulating material 3 without increasing the size of the bump 2, so that the damage of each solder bump 2 can be prevented.

As an electronic component to which the present invention is applied, FIG.
And the like. The electronic component 20 has substantially the same configuration as the electronic component 10 described above.
Therefore, in FIG. 7, portions having the same configuration as in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The electronic component 20 of this embodiment and the electronic component 10 described above
Is that solder bumps are not formed on the electrode portions of the circuit surface 21a of the bare chip component 21. That is, each bare chip component 21 is
Only the upper surface 22a of the electrode portion 1a is sealed with the insulating material 3 so that only the electrode portion is exposed. The electrode section 22 is more convex than a circuit (not shown) formed on the circuit surface 21a.

The via hole 7 is provided at a position corresponding to the predetermined electrode portion 22, and is electrically connected to the wiring layer 5.

Therefore, also in this electronic component 20, the same effect as that of the above-described electronic component 10 can be obtained, the bare chip component 21 can be mounted at a high density, and the wiring section 6 can be made thinner and smaller. Since the heat generated by the operation of the bare chip component 1 can be efficiently dissipated,
Applicable to miniaturization.

Also, in the electronic component 20 of the present embodiment, disconnection of the wiring layer 5 and the via hole 7 corresponding to each external terminal 5b by contacting each external terminal 5b with a probe (not shown) of an inspection device (not shown). Or not,
The failure of the bare chip component 21 can be easily inspected.

Next, a method for manufacturing the electronic component 20 of this embodiment will be described. That is, first, as shown in FIG. 8, a plurality of bare chip components 21 are placed in a predetermined state on a temporary fixing plate 24, which is a plate material, using the upper surface 22a of the electrode portion 22 that is more convex than the circuit on the circuit surface 21a as a contact surface. Place and temporarily fix.

Next, as shown in FIG. 9, a predetermined molding apparatus (not shown) is used to fill the insulating material 3 which is a resin such as an epoxy resin into a shape in which each bare chip component 21 is embedded, thereby forming a mold sheet 23. Molding is performed to seal these bare chip components 21. In this way, the bare chip component 21 can be securely fixed by the resin 23 regardless of the interval between the bare chip components 21, and the insulating material 3 flows between the circuit surface 21 a and the temporary fixing plate 24. 21a can be reliably covered with the insulating material 3, and the circuit surface 21a of the bare chip component 21 can be protected from impurities and moisture contained in the outside air. Accordingly, the interval between the bare chip components 21 can be significantly narrower than the interval between the bare chip components in the electronic component such as the conventional multi-chip module as described above without deteriorating the characteristics. That is, the bare chip component 21 can be mounted at a high density, and the electronic component manufactured in this way can be reduced in size without deteriorating quality and reliability.

Next, the temporary fixing plate 24 is removed, and only the upper surface 22a of the electrode portion 22 on the circuit surface 21a side of the bare chip component 21 is exposed as shown in FIG.
The insulating material 3 on the main surface 21b opposite to the side a is polished and removed using a polishing machine (not shown) until the main surface 21b of the bare chip component 21 appears.

Subsequently, as shown in FIG. 11, the metal plate 8 serving as a heat sink is joined to the main surface 21b side of the bare chip component 21 via a joining material 19. Thus each bare chip part 2
1 is integrally sealed by the insulating material 3 so that the respective electrode portions 22 are exposed, and a mold sheet 23 to which the metal plate 8 is attached is formed.

Subsequently, the wiring portions 6 are formed on the mold sheet 23.
To form That is, the electrode portion 2 of the mold sheet 23
For example, polyimide, which is a photosensitive resin, is dropped or applied to the upper surface 23a where the upper surface 22a of the second substrate 2 is exposed. Then, spin coating is performed, and the photosensitive resin is, for example, 30 (μm) to 5 μm.
Spread to a thickness of 0 (μm).

Next, the mold sheet 23 is placed in a predetermined heating furnace (not shown) in which the inside is maintained at a predetermined temperature and heated for a predetermined time to cure the photosensitive resin. Thereafter, through holes 7a having a predetermined diameter are formed at predetermined positions corresponding to the predetermined electrode portions 22 of the cured photosensitive resin by a predetermined photo process, as shown in FIG. On the upper surface 23a of the sheet 23, an insulating layer 4 made of a photosensitive resin and serving as a lowermost layer is formed.

Further, copper is sputtered on the insulating layer 4 and on the inner peripheral surface of each through hole 7a using a predetermined sputtering device (not shown), and a copper thin film having a predetermined thickness is laminated on the insulating layer 4. At the same time, a plurality of via holes 7 are formed. Thereafter, the copper thin film is patterned by a photo process to form a wiring layer 5 as a lowermost layer made of a conductor pattern electrically connected to the corresponding via hole 7 on the insulating layer 4 as the lowermost layer as shown in FIG. Form.

Thus, each electrode portion 22 of the bare chip component 21 is electrically connected to the corresponding wiring layer 5 via the corresponding via hole 7 sequentially.

Further, similarly, as shown in FIG. 13, the uppermost wiring layer 5 is formed on the lowermost wiring layer 5 with the insulating layer 4 interposed therebetween.

At this time, needless to say, the uppermost wiring layer 5 has an external terminal 5b at one end 5a, and the via hole 7 is also formed in the insulating layer 4 interposed between the wiring layers 5. Needless to say, the wiring layers 5 are electrically connected.

Further, a photosensitive resin such as a polyimide resin is dropped or applied on the uppermost wiring layer 5 and then spin-coated to cover the wiring layer 5 with the photosensitive resin. Next, by placing the mold sheet 23 in a predetermined heating furnace (not shown) and heating it for a predetermined time, the photosensitive resin is cured,
Thus, the insulating layer 4 to be the uppermost layer is formed on the wiring layer 5 to be the uppermost layer. Thereafter, a predetermined one end side of the uppermost insulating layer 4 laminated on the uppermost wiring layer 5 is
Peeling is performed by a predetermined photo process so as to have a predetermined width. Thereby, each external terminal 5 of the wiring layer 5 which is the uppermost layer
Expose b. In this manner, the wiring part 6 in which the insulating layers 4 and the wiring layers 5 are sequentially and alternately laminated is formed on the mold sheet 23 to complete the electronic component.

Also in this embodiment, the same effects as those of the above-described embodiment can be obtained, and the size and thickness of the wiring section 6 can be reduced.

Further, in this embodiment, since no bump electrodes such as solder bumps are formed, the manufacturing process is simplified and the productivity is improved.

In the first example described above, the case where the solder bumps 2 are formed on the respective electrode portions formed on the circuit surface 1a of each bare chip component 1 has been described. However, the present invention is not limited to this. Instead of the solder bumps 2, for example, projecting electrodes made of gold may be provided on each electrode portion formed on the circuit surface 1a of each bare chip component 1.

In the first and second examples described above, the case where the present invention is applied to an electronic component which is a multi-layer module is described. However, the present invention is not limited to this. The multi-chip module may be applied to an electronic component which is laminated by using an adhesive such as epoxy.

Further, in the above-mentioned first and second examples, the case where the insulating material 3 is filled and molded by using a molding machine has been described. However, the present invention is not limited to this, and other methods are used. The bare chip components 1 and 21 may be integrally sealed.

Further, in the first and second examples described above, the insulating layer 4 is formed of polyimide, but the present invention is not limited to this, and the insulating layer 4 may be formed of another photosensitive resin. You may do it.

Further, in the first and second examples described above, the insulating layer 4 is formed by spin coating. However, the present invention is not limited to this, and the insulating layer 4 may be formed by a printing method or the like. It may be formed.

In the first and second examples described above, the conductor pattern of the wiring layer 5 is formed from a copper thin film. However, the present invention is not limited to this. It may be formed from such various kinds of conductive metal thin films. Moreover, you may form from metal foil like copper foil and aluminum foil.

Further, in the first and second examples described above, a resin such as an epoxy resin is used as the insulating material 3, but each of the bare chip components 1, 21 arranged in a predetermined state is used as the insulating material 3. Various insulating materials such as other resin materials may be applied as long as they can be integrally sealed.

Further, in the above-described first and second examples, as the conductive connection means for conductively connecting the wiring layers corresponding to the respective solder bumps and the corresponding wiring layers, the conductive bumps are formed on the inner peripheral surface of the through hole 7a. However, the present invention is not limited to this, and a via hole formed with an aluminum thin film on the inner peripheral surface of the through-hole 7a, and the like. ,
A conductive connection means such as a via hole filled with a conductive material such as silver so as to fill the through hole 7a may be applied.

Further, in the above-described first and second examples, examples in which the present invention is applied to the electronic components 10 and 20 which are multi-chip modules have been described. However, the present invention is not limited to this. Alternatively, the present invention may be applied to a semiconductor device provided with a plurality of electronic components.

In the above-described second example, when the electronic component 20 is manufactured, the insulating layer 4 and the wiring layer 5 are formed after the metal plate 8 is attached. However, the present invention is not limited to this. Alternatively, a metal plate may be attached after forming the wiring layer 5.

Furthermore, in the above-described first and second examples, it has been described that all the bare chip components 1 and 21 are joined to the metal plate 8, but the present invention is not limited to this, and at least one It is sufficient that the above bare chip components 1 and 21 are joined to a metal plate.

Further, in the above second example,
Although the bare chip component 21 having no solder bump is used as a method of manufacturing the electronic component 20, the present invention is not limited to this, and a bare chip component having a bump electrode such as a solder bump may be used in this manufacturing method. .

Further, in the above-described first and second examples, the example in which the metal plate 8 as the heat radiating plate is independently provided as the heat radiating means has been described, but the present invention is not limited to this. A cover member may be provided so as to cover an insulating material for sealing a plurality of bare chip components, and a part of the cover member may be in contact with a main surface opposite to a circuit surface of the bare chip component so as to serve as a heat radiating means. In this way, the final shape can be reduced in size.

[0082]

As is clear from the above description, in the electronic component of the present invention, a plurality of bare chip components are arranged so that each circuit surface forms one surface, and these bare chip components are connected only to the electrode portions. Since it is sealed with an insulating material so as to be exposed, the parts other than the electrode part of the bare chip part are surely covered with the resin, and a plurality of wiring layers are laminated on the circuit surface side of the bare chip part via the insulating layer. Therefore, even if bare chip components are mounted at high density, resin is filled between the circuit surface and the wiring part of the bare chip components, the circuit surface is protected, and quality can be easily reduced without losing quality and reliability. Is made.

Further, in the above electronic component of the present invention,
An insulating layer is formed of a photosensitive resin, an insulating layer is formed on a circuit surface of a bare chip component, and a plurality of wiring layers are formed on the insulating layer via an insulating layer, in the same manner as a so-called build-up board. An insulating layer and a wiring layer are formed, and a hole in which a conductive material is disposed is formed at a predetermined position of the insulating layer. The hole forms an insulating layer such as a so-called through hole or via hole. By electrically connecting the electrode portions and the wiring layers and the wiring layers laminated via the wiring layer, the wiring layers have a relatively high density, the wiring portions can be downsized, and the insulating layers can be relatively thin. Therefore, the thickness of the wiring portion is reduced, and it is possible to sufficiently cope with miniaturization.

Further, in the above electronic component of the present invention,
If a metal plate in contact with the main surface opposite to the circuit surface of the bare chip component is arranged as a heat radiating means, heat generated by the operation of the electronic component is efficiently radiated, and it is possible to sufficiently cope with miniaturization.

Further, a cover member is provided so as to cover an insulating material for sealing a plurality of bare chip components, and heat is dissipated so that a part of the cover member is in contact with a main surface opposite to a circuit surface of the bare chip components. As a means, the final shape can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of an electronic component to which the present invention has been applied.

FIG. 2 is a cross-sectional view illustrating an example of a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of arranging a bare chip component on a metal plate.

FIG. 3 is a cross-sectional view illustrating an example of a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of sealing a bare chip component with an insulating material.

FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing an electronic component to which the present invention is applied in the order of steps, and is a cross-sectional view illustrating a step of polishing an upper surface of a mold sheet.

FIG. 5 is a cross-sectional view illustrating an example of a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and is a cross-sectional view illustrating a step of forming an insulating layer to be a lowermost layer.

FIG. 6 is a cross-sectional view illustrating an example of a method for manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of forming an insulating layer and a wiring layer.

FIG. 7 is a sectional view showing another example of an electronic component to which the present invention is applied.

FIG. 8 is a cross-sectional view illustrating another example of a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of disposing a bare chip component on a temporary fixing plate.

FIG. 9 is a cross-sectional view illustrating another example of a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of sealing a bare chip component with an insulating material.

FIG. 10 is a cross-sectional view showing another example of a method for manufacturing an electronic component to which the present invention is applied in the order of steps, in which a temporary fixing plate is removed;
It is sectional drawing which shows the process of grinding | polishing resin.

FIG. 11 is a cross-sectional view illustrating another example of a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view illustrating a step of disposing a metal plate.

FIG. 12 is a cross-sectional view showing another example of the method of manufacturing an electronic component to which the present invention is applied in the order of steps, and is a cross-sectional view showing a step of forming an insulating layer to be the lowermost layer.

FIG. 13 is a cross-sectional view showing another example of the method for manufacturing an electronic component to which the present invention is applied, in the order of steps, and is a cross-sectional view showing the step of forming an insulating layer and a wiring layer.

FIG. 14 is a sectional view showing a conventional multichip module.

[Explanation of symbols]

1,21 bare chip parts, 1a, 21a circuit surface, 2
Solder bumps, 3 insulating materials, 4 insulating layers, 5 wiring layers,
5b external terminal, 6 wiring section, 7 via hole, 8
Metal plate, 10,20 electronic parts, 22 electrode part

Claims (10)

[Claims] 1. A plurality of bare chip components, each having a main surface serving as a circuit surface on which a circuit including an electrode portion having an electrode portion is formed, are arranged such that these circuit surfaces form one surface,
An electronic component, characterized in that these bare chip components are sealed with an insulating material so that only electrode portions are exposed, and a plurality of wiring layers are formed on the circuit surface side of the bare chip component via an insulating layer. . 2. The insulating layer according to claim 1, wherein the insulating layer is made of a photosensitive resin, has an insulating layer on a circuit surface of the bare chip component, and has a plurality of wiring layers laminated thereon via the insulating layer. A hole in which a conductive material is disposed is formed at a predetermined position, and this hole electrically connects an electrode portion laminated via an insulating layer, a wiring layer, and wiring layers. The electronic component according to claim 1, wherein: 3. The electronic component according to claim 1, wherein a heat radiating means is provided on a main surface side opposite to a circuit surface of the bare chip component. 4. The electronic component according to claim 3, wherein a metal plate in contact with a main surface opposite to a circuit surface of the bare chip component is disposed as a heat radiating means. 5. A cover member for covering an insulating material for sealing a plurality of bare chip components, wherein a part of the cover member is in contact with a main surface opposite to a circuit surface of the bare chip components. 4. The electronic component according to claim 3, wherein said electronic component is a heat radiating means. 6. The electronic component according to claim 1, wherein a terminal portion which is connected to another wiring layer and serves as a connection portion with the outside is formed on the uppermost wiring layer. 7. The electronic component according to claim 1, wherein a solder bump is formed on an electrode portion of an electrode portion of the chip component. 8. The electronic component according to claim 1, wherein the electrode portion of the electrode portion of the chip component is formed to be more convex than the circuit. 9. A plurality of bare chip parts each having a main surface serving as a circuit surface on which a circuit including an electrode portion having an electrode portion on which a solder bump is formed is formed, such that these circuit surfaces form one surface. A first step of disposing, a second step of sealing with an insulating material so as to cover the bare chip components, and a third step of removing the insulating material on the circuit surface side of the bare chip components and exposing the solder bumps. On the circuit surface side of the bare chip component, an insulating layer made of a photosensitive resin and having a hole in which a conductive material is disposed at a position corresponding to the electrode portion is formed, and a plurality of wiring layers are formed on the insulating layer. And a fourth step of laminating via an insulating layer made of a conductive resin and having a hole in which a conductive material is disposed, and electrically connecting the electrode portion with the wiring layer and between the wiring layers. Manufacturing method of electronic parts. 10. A plurality of bare chip parts, each of which has a main surface serving as a circuit surface on which a circuit including an electrode portion having an electrode portion that is a projection is formed, are arranged on a plate material with the electrode portion surface as a contact surface. A first step, a second step of sealing with an insulating material so as to cover these bare chip parts, a third step of removing the plate material and exposing the electrode portion surface, and a circuit surface side of the bare chip parts, An insulating layer made of a photosensitive resin and having a hole in which a conductive material is disposed at a position corresponding to the electrode portion is formed, and a plurality of wiring layers are formed thereon, and the conductive material is formed of a photosensitive resin inside. A fourth step of laminating the insulating layer having the holes arranged therein and electrically connecting the electrode section with the wiring layers and between the wiring layers.