JPH10303212A - Bipolar transistor - Google Patents

Bipolar transistor

Info

Publication number
JPH10303212A
JPH10303212A JP10738097A JP10738097A JPH10303212A JP H10303212 A JPH10303212 A JP H10303212A JP 10738097 A JP10738097 A JP 10738097A JP 10738097 A JP10738097 A JP 10738097A JP H10303212 A JPH10303212 A JP H10303212A
Authority
JP
Japan
Prior art keywords
electrode
emitter
insulating film
base
shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10738097A
Other languages
Japanese (ja)
Other versions
JP3062114B2 (en
Inventor
Masaki Ishii
正樹 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP9107380A priority Critical patent/JP3062114B2/en
Publication of JPH10303212A publication Critical patent/JPH10303212A/en
Application granted granted Critical
Publication of JP3062114B2 publication Critical patent/JP3062114B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve high frequency power gain by providing a shield electrode by setting a parasitic capacitance by a standardized shield at a specified value when a shield electrode is provided between a base pad electrode and a semiconductor board through an insulation film. SOLUTION: Shield electrodes 13AP, 13A cover a first insulation film 4 below base pad electrodes 11P, 11 selectively and are formed of a first conductive film connected to an emitter electrode 7 through emitter pad electrodes 12P, 12. The sum of capacitance between the base pad electrodes 11P, 11 and the shield electrodes 13AP, 13A and a capacitance between an emitter electrode 7 and a semiconductor board 1 is made one or more times to one and half or less times the capacitance between the base pad electrodes 11P, 11 and the semiconductor board 1 when the shield electrodes 13AP, 13A are not provided. The area of the shield electrodes 13AP, 13A and the thickness and permittivity of the first insulation film 4 and a second insulation film 8 are set.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バイポーラトラン
ジスタに関し、特に高周波小信号増幅用のバイポーラト
ランジスタに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly, to a bipolar transistor for amplifying a high-frequency small signal.

【0002】[0002]

【従来の技術】従来のバイポーラトランジスタは、図3
に示すように、n型シリコン半導体基板1の表面部に形
成されたp型ベース領域2と、p型ベース領域2の表面
部に形成されたn型エミッタ領域3と、n型シリコン半
導体基板1を被覆する第1の絶縁膜4(酸化シリコン
膜)と、第1の絶縁膜4を選択的に被覆する第1の導電
膜(アルミニウム系合金膜)でなりp型ベース領域2及
びn型エミッタ領域3にそれぞれ接続するベース電極6
及びエミッタ電極7と、ベース電極6及びエミッタ電極
7の形成された第1の絶縁膜4を被覆する第2の絶縁膜
8(酸化シリコン膜)と、第2の絶縁膜8を選択的に被
覆する第2の導電膜(金膜)でなりベース電極6及びエ
ミッタ電極7にそれぞれ接続されるベースパッド電極1
1P及びエミッタパッド電極12Pとを有している。
2. Description of the Related Art A conventional bipolar transistor is shown in FIG.
As shown in FIG. 1, a p-type base region 2 formed on the surface of the n-type silicon semiconductor substrate 1, an n-type emitter region 3 formed on the surface of the p-type base region 2, and an n-type silicon semiconductor substrate 1 A first insulating film 4 (silicon oxide film) covering the first insulating film 4 and a first conductive film (aluminum-based alloy film) selectively covering the first insulating film 4. Base electrodes 6 connected to regions 3 respectively
And a second insulating film 8 (silicon oxide film) that covers the first insulating film 4 on which the base electrode 6 and the emitter electrode 7 are formed, and selectively covers the second insulating film 8. Base electrode 1 made of a second conductive film (gold film) and connected to base electrode 6 and emitter electrode 7, respectively.
1P and an emitter pad electrode 12P.

【0003】また、図4にしめすように、ベースパッド
電極11P下の第1の絶縁膜を被覆してシールド電極1
3を設けることもある(特開昭60−262462号公
報)。このシールド電極13は、金属膜や抵抗膜を用い
る。
Further, as shown in FIG. 4, a first insulating film under the base pad electrode 11P is coated to form a shield electrode 1P.
3 may be provided (JP-A-60-262462). The shield electrode 13 uses a metal film or a resistance film.

【0004】[0004]

【発明が解決しようとする課題】図3に示すバイポーラ
トランジスタは、ベースパッド電極11P−n型シリコ
ン半導体基板1(コレクタ領域)間容量のため、高周波
電力利得が低いという問題点がある。この問題点は、図
4のシールド電極13を設けることにより一応解決され
る。
The bipolar transistor shown in FIG. 3 has a problem that the high-frequency power gain is low because of the capacitance between the base pad electrode 11P-n type silicon semiconductor substrate 1 (collector region). This problem can be solved by providing the shield electrode 13 shown in FIG.

【0005】シールド電極13によりベース−コレクタ
間寄生容量が低くなって高周波電力利得は向上する。し
かし、ベース−エミッタ間寄生容量とエミッタ−コレク
タ間寄生容量の増大を伴うので、シールド電極の設け方
に影響される。即ち、単にシールド電極を設けるだけで
は不十分である。
The shield electrode 13 reduces the base-collector parasitic capacitance and improves the high-frequency power gain. However, since the parasitic capacitance between the base and the emitter and the parasitic capacitance between the emitter and the collector are increased, it is affected by the method of providing the shield electrode. That is, merely providing the shield electrode is not sufficient.

【0006】本発明の目的は、シールド電極を設けるこ
とによる高周波電力利得の向上を確実に達成できるバイ
ポーラトランジスタを提供することにある。
An object of the present invention is to provide a bipolar transistor which can reliably achieve an improvement in high-frequency power gain by providing a shield electrode.

【0007】[0007]

【課題を解決するための手段】本発明のバイポーラトラ
ンジスタは、第1導電型半導体基板の表面部に形成され
た第2導電型ベース領域と、前記第2導電型ベース領域
の表面部に形成された第1導電型エミッタ領域と、前記
半導体基板を被覆する第1の絶縁膜と、前記第1の絶縁
膜を選択的に被覆する第1の導電膜でなり前記第1導電
型ベース領域及び第1導電型エミッタ領域にそれぞれ接
続するベース電極及びエミッタ電極と、前記ベース電極
及びエミッタ電極の形成された前記第1の絶縁膜を被覆
する第2の絶縁膜と、前記第2の絶縁膜を選択的に被覆
する第2の導電膜でなり前記ベース電極及びエミッタ電
極にそれぞれ接続されるベースパッド電極及びエミッタ
パッド電極と、前記ベースパッド電極下の第1の絶縁膜
を選択的に被覆し前記エミッタパッド電極を介してエミ
ッタ電極に接続される第1の導電膜でなるシールド電極
とを有し、ベースパッド電極−シールド電極間容量とエ
ミッタ電極−半導体基板間容量の和が前記シールド電極
を設けない場合のベースパッド電極−半導体基板間容量
の1以上15倍以下になるように前記シールド電極の面
積並びに第1の絶縁膜及び第2の絶縁膜の厚さと比誘電
率が設定されているというものである。
A bipolar transistor according to the present invention has a second conductivity type base region formed on a surface of a first conductivity type semiconductor substrate and a surface portion of the second conductivity type base region. A first conductive type emitter region, a first insulating film covering the semiconductor substrate, and a first conductive film selectively covering the first insulating film. Select a base electrode and an emitter electrode respectively connected to the one conductivity type emitter region, a second insulating film covering the first insulating film on which the base electrode and the emitter electrode are formed, and the second insulating film. Selectively covering a base pad electrode and an emitter pad electrode which are made of a second conductive film to be covered and connected to the base electrode and the emitter electrode, respectively, and a first insulating film under the base pad electrode. A shield electrode made of a first conductive film connected to the emitter electrode via the emitter pad electrode, wherein a sum of a base pad electrode-shield electrode capacitance and an emitter electrode-semiconductor substrate capacitance forms the shield electrode. The area of the shield electrode, the thicknesses of the first insulating film and the second insulating film, and the relative permittivity are set so as to be 1 to 15 times the capacitance between the base pad electrode and the semiconductor substrate when not provided. That is.

【0008】バイポーラトランジスタの高周波電力利得
は、電極配線の影響を強く受ける。そこで、シールド電
極の大きさを変化させてシールド電極−半導体基板間容
量とベースパッド電極−シールド電極間容量の和(シー
ルドによる寄生容量)の高周波電力利得への影響を、一
般的な小信号増幅用の高周波バイポーラトランジスタの
等価回路(エミッタ接地)を用いて行った。その結果を
図2に示す。縦軸に相対利得(シールド電極を設けない
場合を基準としてデシベルで表示)、横軸にシールドに
よる寄生容量(シールド電極を設けない場合のベースパ
ッド電極−半導体基板間容量で規格化)を示す。但し、
シールド電極を設けない場合のベースパッド電極−半導
体基板間容量はコレクタ接合容量と同程度、周波数は2
GHzとし、また、ベースパッド電極の中心とシールド
電極の中心は一致しているものとする。シールド電極を
大きくしていくと、最初はコレクタ−ベース間容量の減
少により相対利得は向上するが、規格化された寄生容量
が5を越えたあたりから相対利得の向上は少なくなり約
15で0になる。
[0008] The high-frequency power gain of a bipolar transistor is strongly affected by electrode wiring. Therefore, by changing the size of the shield electrode, the influence of the sum of the capacitance between the shield electrode and the semiconductor substrate and the capacitance between the base pad electrode and the shield electrode (parasitic capacitance due to the shield) on the high-frequency power gain can be reduced by general small signal amplification Using a high-frequency bipolar transistor equivalent circuit (common emitter). The result is shown in FIG. The vertical axis shows the relative gain (expressed in decibels based on the case where no shield electrode is provided), and the horizontal axis shows the parasitic capacitance due to the shield (standardized by the capacitance between the base pad electrode and the semiconductor substrate when no shield electrode is provided). However,
When a shield electrode is not provided, the capacitance between the base pad electrode and the semiconductor substrate is almost equal to the collector junction capacitance, and the frequency is 2
GHz, and the center of the base pad electrode coincides with the center of the shield electrode. As the size of the shield electrode is increased, the relative gain initially increases due to a decrease in the collector-base capacitance. However, when the standardized parasitic capacitance exceeds 5, the improvement in the relative gain decreases and becomes approximately 15 to 0. become.

【0009】[0009]

【発明の実施の形態】図1(a)は本発明の第1の実施
のに形態を示す平面図、図1(b)は図1(a)のX−
X線断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a plan view showing a first embodiment of the present invention, and FIG.
It is an X-ray sectional view.

【0010】この実施の形態のバイポーラトランジスタ
は、n型シリコン半導体基板1の表面部に形成されたp
型ベース領域2と、p型ベース領域2の表面部に形成さ
れたn型エミッタ領域3と、n型半導体シリコン基板1
を被覆する厚さ1μmの酸化シリコン膜でなる第1の絶
縁膜4と、第1の絶縁膜4を選択的に被覆する第1の導
電膜(アルミニウム合金膜)でなりp型ベース領域2及
びn型エミッタ領域3にそれぞれ接続するベース電極6
及びエミッタ電極7と、ベース電極6及びエミッタ電極
7の形成された第1の絶縁膜4を被覆する第2の絶縁膜
8(厚さ500nmの酸化シリコン膜)と、第2の絶縁
膜8を選択的に被覆する第2の導電膜(アルミニウム合
金膜)でなりベース電極6及びエミッタ電極7にそれぞ
れ接続されるベースパッド電極11P,11、及びエミ
ッタパッド電極12P,12と、ベースパッド電極11
P(半径40μmの円形),11(幅12μm,長さ2
0μm)下の第1の絶縁膜4を選択的に被覆しエミッタ
パッド電極12P,12を介してエミッタ電極7に接続
される第1の導電膜でなるシールド電極13AP(半径
45μmの円形),13A(幅12μm,長さ20μ
m)とを有している。
The bipolar transistor of this embodiment has a p-type structure formed on the surface of n-type silicon semiconductor substrate 1.
-Type base region 2, n-type emitter region 3 formed on the surface of p-type base region 2, and n-type semiconductor silicon substrate 1.
A first insulating film 4 made of a silicon oxide film having a thickness of 1 μm and a first conductive film (aluminum alloy film) selectively covering the first insulating film 4 to form a p-type base region 2 and Base electrodes 6 connected to n-type emitter regions 3 respectively
And a second insulating film 8 (a silicon oxide film having a thickness of 500 nm) which covers the first insulating film 4 on which the base electrode 6 and the emitter electrode 7 are formed, and a second insulating film 8. A base pad electrode 11P, 11 and an emitter pad electrode 12P, 12 which are made of a second conductive film (aluminum alloy film) to be selectively covered and connected to the base electrode 6 and the emitter electrode 7, respectively;
P (circle with a radius of 40 μm), 11 (width 12 μm, length 2
0 μm) and a first conductive film connected selectively to the emitter electrode 7 via the emitter pad electrodes 12P and 12 by selectively covering the first insulating film 4 below the first insulating film 4 (a circle having a radius of 45 μm), 13A. (Width 12μm, length 20μ
m).

【0011】第1の絶縁膜4と第2の絶縁膜8の比誘電
率を同じとして規格化したシールドによる寄生容量を計
算すると4.9となる。
The calculated parasitic capacitance due to the shield, which is normalized by setting the relative dielectric constant of the first insulating film 4 and the second insulating film 8 to be the same, is 4.9.

【0012】図2から、相対利得は1.1dBとなる。
実際の試作品でも同様の結果が得られた。
From FIG. 2, the relative gain is 1.1 dB.
Similar results were obtained with the actual prototype.

【0013】以上説明したように、シールド電極を設け
る場合、規格化したシールドによる寄生容量は1以上1
5以下で有効であり、好ましくは2.5〜10倍、特に
5前後に設定することが肝要であるといえよう。
As described above, when the shield electrode is provided, the parasitic capacitance due to the standardized shield is one or more and one or more.
It is effective to set the value to 5 or less, preferably 2.5 to 10 times, and especially to about 5.

【0014】なお、実際にパッケージに搭載するとき、
パッケージのベース端子とベースパッド電極11Pとは
ボールボンディングにより接続されるが、ボンディング
線の先端部はベースパッド電極からはみ出されないもの
として説明した。はみだせばそれだけ寄生容量が大きく
なるので図2の曲線からはずれることになる。
When actually mounting on a package,
Although the base terminal of the package and the base pad electrode 11P are connected by ball bonding, it has been described that the tip of the bonding wire does not protrude from the base pad electrode. If it protrudes, the parasitic capacitance will increase accordingly, and will deviate from the curve of FIG.

【0015】又、シールド電極はアルミニウム合金膜で
形成したが、その外に金膜などの金属膜を使用すること
ができる。更に、NPN型のバイポーラトランジスタだ
けではなくPNP型のバイポーラトランジスタにおいて
も同様の効果が得られる。
Although the shield electrode is formed of an aluminum alloy film, a metal film such as a gold film can be used in addition to the shield electrode. Further, similar effects can be obtained not only in NPN-type bipolar transistors but also in PNP-type bipolar transistors.

【0016】[0016]

【発明の効果】第1の効果は、バイポーラトランジスタ
をエミッタ接地で動作させるときの高周波電力利得の向
上を確実に達成できるということである。
The first effect is that an improvement in high-frequency power gain when a bipolar transistor is operated with a common emitter can be reliably achieved.

【0017】その理由は、ベースパッド電極と半導体基
板(コレクタ領域)の間に絶縁膜を介してシールド電極
をいれ、ベースパッド電極とコレクタの間の寄生容量を
小さくするとともに、シールド電極の存在による寄生容
量の大きさを利得向上に有効な条件としたからである。
The reason is that a shield electrode is inserted between the base pad electrode and the semiconductor substrate (collector region) via an insulating film to reduce the parasitic capacitance between the base pad electrode and the collector and to prevent the presence of the shield electrode. This is because the magnitude of the parasitic capacitance is a condition effective for improving the gain.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態を示す平面図(図1
(a))及び図1(a)のX−X線断面図(図1
(b))。
FIG. 1 is a plan view (FIG. 1) showing a first embodiment of the present invention;
(A)) and a cross-sectional view taken along line XX of FIG.
(B)).

【図2】シールド電極による寄生容量と相対利得の関係
を示すグラフ。
FIG. 2 is a graph showing a relationship between a parasitic capacitance due to a shield electrode and a relative gain.

【図3】従来例を示す平面図(図3(a))及び図3
(a)のX−X線断面図(図3(b))。
FIG. 3 is a plan view showing a conventional example (FIG. 3A) and FIG.
FIG. 3A is a sectional view taken along line XX (FIG. 3B).

【図4】別の従来例を示す断面図。FIG. 4 is a sectional view showing another conventional example.

【符号の説明】[Explanation of symbols]

1 n型シリコン半導体基板 2 p型ベース領域 3 n型エミッタ領域 4 第1の絶縁膜(フィールド酸化膜) 5 開孔 6 ベース電極 7 エミッタ電極 8 第2の絶縁膜(層間絶縁膜) 9 開孔 10 開孔 11P,11 シールド電極 12P,12 エミッタパッド電極 13,13AP,13A ベースパッド電極 14 開孔 15 シールド電極−エミッタパッド電極の接続配線 REFERENCE SIGNS LIST 1 n-type silicon semiconductor substrate 2 p-type base region 3 n-type emitter region 4 first insulating film (field oxide film) 5 opening 6 base electrode 7 emitter electrode 8 second insulating film (interlayer insulating film) 9 opening DESCRIPTION OF SYMBOLS 10 Opening 11P, 11 Shield electrode 12P, 12 Emitter pad electrode 13, 13AP, 13A Base pad electrode 14 Opening 15 Shield electrode-emitter pad electrode connection wiring

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型半導体基板の表面部に形成さ
れた第2導電型ベース領域と、前記第2導電型ベース領
域の表面部に形成された第1導電型エミッタ領域と、前
記半導体基板を被覆する第1の絶縁膜と、前記第1の絶
縁膜を選択的に被覆する第1の導電膜でなり前記第1導
電型ベース領域及び第1導電型エミッタ領域にそれぞれ
接続するベース電極及びエミッタ電極と、前記ベース電
極及びエミッタ電極の形成された前記第1の絶縁膜を被
覆する第2の絶縁膜と、前記第2の絶縁膜を選択的に被
覆する第2の導電膜でなり前記ベース電極及びエミッタ
電極にそれぞれ接続されるベースパッド電極及びエミッ
タパッド電極と、前記ベースパッド電極下の第1の絶縁
膜を選択的に被覆し前記エミッタパッド電極を介してエ
ミッタ電極に接続される第1の導電膜でなるシールド電
極とを有し、ベースパッド電極−シールド電極間容量と
エミッタ電極−半導体基板間容量の和が前記シールド電
極を設けない場合のベースパッド電極−半導体基板間容
量の1以上15倍以下になるように前記シールド電極の
面積並びに第1の絶縁膜及び第2の絶縁膜の厚さと比誘
電率が設定されていることを特徴とするバイポーラトラ
ンジスタ。
A first conductive type base region formed on a surface portion of the first conductive type semiconductor substrate; a first conductive type emitter region formed on a surface portion of the second conductive type base region; A first insulating film covering the substrate, and a base electrode comprising a first conductive film selectively covering the first insulating film and connected to the first conductive type base region and the first conductive type emitter region, respectively. And an emitter electrode, a second insulating film covering the first insulating film on which the base electrode and the emitter electrode are formed, and a second conductive film selectively covering the second insulating film. A base pad electrode and an emitter pad electrode connected to the base electrode and the emitter electrode, respectively, and a first insulating film under the base pad electrode which is selectively covered and connected to the emitter electrode via the emitter pad electrode. And a base pad electrode-semiconductor substrate capacitance when the sum of the base pad electrode-shield electrode capacitance and the emitter electrode-semiconductor substrate capacitance is not provided with the shield electrode. A bipolar transistor, wherein the area of the shield electrode, the thicknesses of the first insulating film and the second insulating film, and the relative dielectric constant are set so as to be at least 1 and at most 15 times as large as the above.
【請求項2】 シールド電極を設けない場合のベースパ
ッド電極−半導体基板間容量はコレクタ接合容量と同程
度である請求項1記載のバイポーラトランジスタ。
2. The bipolar transistor according to claim 1, wherein the capacitance between the base pad electrode and the semiconductor substrate when no shield electrode is provided is substantially equal to the collector junction capacitance.
JP9107380A 1997-04-24 1997-04-24 Bipolar transistor Expired - Fee Related JP3062114B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9107380A JP3062114B2 (en) 1997-04-24 1997-04-24 Bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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