JPH10303129A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To markedly increase the degree of freedom in the design of a circuit by greatly reducing the adding area of a catalytic element which promotes the crystallization of silicon by crystallizing an amorphous film through heat treatment after the insulation layer is marked and the catalytic element is added to the amorphous film by ion implantation. SOLUTION: An opening 105 is formed in a slit-like shape elongated in the direction perpendicular to the plane of the figure and the shorter side of the section 105 represents the minimum width of the slit. It is suitable to use an exposure method using an excimer laser, electron beam, etc., for forming a sub-micron pattern and, when the method is used, an extremely fine pattern can be formed and the degree of freedom in the design of the shape of the adding area 106 of a catalytic element also increases. Then the introducing quantity of the catalytic element added to an amorphous film 103 can be controlled precisely. The method for implanting ions of the catalytic element includes a plasma doping method which does not perform mass separation in addition to an ion implanting method accompanied by the mass separation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor device using a semiconductor thin film, and more particularly, to a thin film transistor (Thin Fil) using a crystalline film containing silicon.
m Transistor (TFT).

[0002] In this specification, a semiconductor device generally refers to a device that functions using a semiconductor.
Not only semiconductor elements such as TFTs and IGFETs, but also electro-optical devices (such as liquid crystal display devices) and applied products (such as electronic devices) incorporating them are included in the category of semiconductor devices. In this specification, a semiconductor element, a display device, and the like are described as appropriate in order to make the distinction clear.

[0003]

2. Description of the Related Art In recent years, the technology for forming a semiconductor circuit using thin film transistors (TFTs) formed on a substrate has been remarkably advanced. In particular, an active matrix display device using a crystalline silicon film (polysilicon film or the like) as a thin film semiconductor and mounting a peripheral circuit and a pixel matrix circuit on the same substrate has reached a practical level.

Among them, active matrix type liquid crystal display devices (hereinafter referred to as AM-LCDs) are being actively developed for displays of notebook computers, projectors, portable devices and the like. AM-LCDs are broadly classified into transmissive LCDs and reflective LCDs according to their operation modes.

At present, the development of high-definition and bright liquid crystal display devices has been rushed, and XGA (1024 × 768 pixels) and SXGA
(1280 x 1024 pixels), a structure in which each pixel is extremely fine having a size of 30 m square or less has been developed.

The present inventors have disclosed a technique described in Japanese Patent Application Laid-Open No. 8-78329 as a means for obtaining a crystalline silicon film suitable for a semiconductor device as described above. According to the publication, a mask insulating film is first formed on an amorphous silicon film. Then, a catalyst element which selectively promotes crystallization is introduced by using the mask as a mask to obtain needle-like or columnar crystals grown in a lateral direction, that is, a direction substantially parallel to the substrate and substantially parallel to each other.

Since such a crystal region (hereinafter referred to as a lateral growth region) has relatively uniform crystallinity, it is possible to suppress variations in characteristics of the semiconductor device. In addition, there is an advantage that macroscopic crystal grain boundaries can be controlled at desired positions.

In the technique described in the publication, since a solution containing a catalyst element is applied by spin coating, a short side (hereinafter referred to as a minimum slit width) of an opening (a window to which the catalyst element is added) provided in the mask insulating film is provided. At least 10 μm or more, preferably 20 μm or more. This is because, if the slit width is less than this, poor entry of the solution occurs due to surface tension.

Therefore, in order to obtain a crystalline silicon film consisting of a lateral growth region, it is necessary to form a catalyst element addition region of several hundred μm ² or more in the vicinity thereof. Since this added region contains the catalyst element at a high concentration, it must be removed later. In other words, an area of several hundred μm ² becomes a completely unusable area.

For this reason, the proportion of the region to which the catalyst element is added in the stage of circuit design cannot be ignored, which may cause the size of the entire circuit to be increased more than necessary. This becomes a more remarkable problem in the circuit configuration such as XGA and SXGA as described above.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method for manufacturing a semiconductor device which can cope with miniaturization.

[0012]

According to the invention disclosed in this specification, there is provided a process of forming an insulating layer having an opening on an amorphous film containing silicon, and forming the amorphous layer using the insulating layer as a mask. Adding a catalytic element that promotes crystallization of silicon to the amorphous film by an ion implantation method, crystallizing at least a part of the amorphous film by a heat treatment, and forming a lateral growth region; And the growth distance of the lateral growth region is controlled by the amount of the catalyst element introduced.

In the above configuration, at least one on the same substrate
It is also possible to adopt a configuration in which the catalyst element is added at different locations in an introduction amount different from the other addition regions, and the growth distance of the lateral growth region is controlled by the introduction amount.

In another aspect of the invention, a step of forming an insulating layer having an opening on an amorphous film containing silicon, and a step of forming a silicon crystal on the amorphous film using the insulating layer as a mask. Adding a catalyst element that promotes the formation of the amorphous film by an ion implantation method, crystallizing at least a part of the amorphous film by heat treatment to form a lateral growth region, A step of selectively adding and a step of gettering the catalyst element from a region adjacent to the region to which the element selected from Group 15 is added by heat treatment.

In another aspect of the invention, a step of forming an insulating layer having an opening on an amorphous film containing silicon, and the step of forming a crystal of silicon on the amorphous film using the insulating layer as a mask. Adding a catalyst element that promotes the formation of the amorphous film by an ion implantation method, crystallizing at least a part of the amorphous film by heat treatment to form a lateral growth region, A step of selectively adding, and a step of gettering the catalytic element from a region adjacent to the region to which an element selected from Group 15 is added by a heat treatment, The growth distance of the lateral growth region is controlled by the introduction amount.

The gist of the present invention is to use an ion plantation method (hereinafter referred to as an ion implantation method) as a method for adding a catalyst element when implementing the technique described in Japanese Patent Application Laid-Open No. 8-78329.

In the ion implantation method, even if the short side of the insulating layer serving as a mask becomes 10 μm or less, the penetration failure due to the surface tension as seen in the liquid phase method does not occur. Therefore, the short side (minimum slit width) of the opening formed in the insulating layer serving as a mask may be about 0.01 to 5 μm (preferably 0.25 to 2 μm).

It is also possible to use a plasma doping method without mass separation, a vapor deposition method or the like instead of the ion implantation method.

The amount of the catalyst element to be added is controlled in accordance with the position of the opening and the required growth distance of the lateral growth region on the same substrate, and the growth distance of the lateral growth region is controlled in accordance with the amount of introduction. It is also possible to control.

The introduction amount of the catalytic element indicates the absolute amount of the added catalytic element, and is a concept different from the concentration in a strict sense. Therefore, the definition of the introduction amount in this embodiment will be described with reference to FIG.

When a catalytic element is added by ion implantation, a dose (atoms / cm ² ) is used to quantitatively express the amount of introduction.
Alternatively, the concentration (atoms / cm ³ ) is easy to understand. However, these indicate the introduction amount (absolute amount) of the catalyst element per unit area or unit volume, and the introduction amount changes depending on the area or volume of the addition region. That is, for example, even if they are added at the same concentration, if the area of the addition region is different, the total amount of introduction differs.

FIG. 7 shows a positional relationship between a typical catalytic element addition region (shown by 701) and an active layer (shown by 702 and 703). At this time, 704
Is the minimum slit width (d), 705 is the lateral growth area,
706 is a growth distance (D) of the lateral growth region.

According to the knowledge of the present inventors, when the catalyst element is added at the same concentration, if the minimum slit width (d) of the addition region 701 becomes longer (wider), the growth distance (D) of the lateral growth region is correspondingly increased. Is also longer. That is, it can be seen that there is some correlation between the minimum slit width (d) and the growth distance (D).

When the minimum slit width (d) increases, the amount of the catalyst element added to the addition region 701 necessarily increases. Therefore, there is no doubt that there is a correlation between the introduction amount of the catalyst element and the growth distance (D).

Actually, the length of the addition region 701 in the longitudinal direction should also be related to the amount of introduction. However, from the experiments so far, even if the length in the longitudinal direction changes, the growth distance (D) does not change. It has been found to have little effect. Therefore, it can be said that the minimum slit width (d) is one of the most important parameters in determining the introduction amount of the catalyst element.

From the above, the “introduction amount” in the present specification means that the concentration (atoms / cm ³ ) corresponds to the minimum slit width (d
cm), the unit length in the longitudinal direction (1 cm), and the thickness of the semiconductor film (cm).

In the present invention, a means for controlling the growth distance by changing the addition concentration of the catalyst element and a means for controlling the growth distance by changing the minimum slit width of the opening are particularly described. But,
As can be understood from the above definition, the growth distance can be controlled by changing the thickness of the semiconductor film (for example, an amorphous silicon film).

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, reference numeral 101 denotes a substrate (including a glass substrate or a quartz substrate);
03 is an amorphous film containing silicon, and 104 is an insulating layer serving as a mask. An opening 105 is formed in the insulating layer 104.

At this time, in FIG. 1, the opening 105 is formed in a slit shape having a longitudinal direction in a direction perpendicular to the paper surface, and the short side thereof is the minimum slit width. The minimum slit width may be about 0.01 to 5 μm (preferably 0.25 to 2 μm).

In order to form such a submicron pattern, it is preferable to use an exposure method using an excimer laser, an electron beam, a focused ion beam, or the like. These exposure methods can form an extremely fine pattern, and greatly expand the degree of freedom in designing the shape of the catalyst element addition region 106.

Then, as shown in the left diagram of FIG. 1, a catalytic element is added so that the peak value of the ion profile 107 comes into the amorphous film 103. By doing so, the amount of the catalyst element introduced into the amorphous film 103 can be precisely controlled.

The ion can be added by a plasma doping method (such as ion doping) without mass separation, in addition to the ion implantation method with mass separation. Is more advantageous.

According to the above-mentioned means, as shown in FIG. 2, it is possible to form lateral growth regions having different growth distances on the same substrate. In FIG. 2, 201 is a substrate, 2
Reference numeral 02 denotes a region that forms the first TFT group, and reference numeral 203 denotes a region that forms the second TFT group.
Since the length of the channel formation region is different from that of the TFT group, the required growth distance of the lateral growth region is different.

At this time, if the growth distance of the lateral growth region 204 required for the first TFT group is X ₁ , the introduced amount of the catalyst element addition region 205 is such that the growth distance X ₁ is realized. At (n ₁ ), a catalytic element is added. On the other hand, the second TF
The growth distance of the lateral growth region 206 required in the group T is X ₂
If so, the catalyst element is added to the catalyst element addition region 207 at an introduction amount (n ₂ ) that realizes the growth distance X ₂ .

At this time, the relationship between the growth distance and the amount of introduction may be obtained experimentally in advance. According to the findings of the present inventors, X ₁ >
In the case of X ₂ , the introduction amount of the catalyst element needs to be n ₁ > n ₂ . That is, it has been found that the longer the required growth distance of the lateral growth region, the higher the amount of the added catalytic element must be introduced.

The example described with reference to FIG. 2 is an example in which a catalytic element is added from an opening having the same minimum slit width to an amorphous semiconductor film having a constant film thickness formed on the same substrate. It is. In this case, the growth distance can be controlled by changing the addition concentration of the catalyst element.

When the concentration of the catalyst element is the same, the amount of introduction can be controlled by setting the minimum slit width to a different length. That is, if the catalyst element is added at the same concentration, if the minimum slit width of the opening is long, the introduction amount of the catalyst element added as a whole increases, so that the growth distance of the lateral growth region increases.

[0038]

【Example】

Embodiment 1 An example of manufacturing an active matrix substrate (a substrate on which a semiconductor element is manufactured) of a reflection type liquid crystal display device using the present invention will be described with reference to FIGS.

First, a glass substrate 300 on which a base film such as a silicon oxide film is deposited is prepared as a substrate having an insulating surface. Instead of the glass substrate 300, a quartz substrate, a silicon substrate, a ceramic substrate, or the like may be used.

Next, the amorphous silicon film 301 is plasma-CV
10 to 75 nm (preferably using the D method or the low pressure CVD method)
15 to 45 nm). Note that, in addition to the amorphous silicon film, an amorphous semiconductor film containing silicon, for example, Si _x Ge _1-x
(0 <X <1) can also be used.

Next, the amorphous silicon film 301 is formed by
Crystallization is performed by applying the technology described in JP-A-9. The feature of the publication is that a catalytic element is selectively added to the amorphous silicon film to obtain a region (referred to as a lateral growth region) in which the crystal is grown substantially parallel to the substrate.

In this publication, solution coating is performed as a method for adding nickel. The feature of the present invention resides in that nickel is added by an ion plantation method.

First, a mask insulating film 302 made of a silicon oxide film is formed on the amorphous silicon film 301 to a thickness of 50 to 150 nm. Then, the mask insulating film 302 is patterned to provide an opening 303 in a region to be a peripheral circuit. Although only one opening is shown in the drawings, a plurality of openings are actually formed.

Next, nickel is added by an ion plantation method (also called an ion implantation method). At this time, the dose is adjusted so as to be 1 × 10 ¹² to 1 × 10 ¹⁵ atoms / cm ² (preferably 2 × 10 ¹³ to 2 × 10 ¹⁴ atoms / cm ² ). (FIG. 3 (A))

When nickel is added by the ion implantation method as in this embodiment, the width of the opening provided in the mask insulating film may be about 0.25 to 2 μm. That is, it is possible to add a sufficient amount of nickel to the openings formed in a fine pattern.

In this embodiment, the minimum slit width of the opening is fixed to 1.5 μm. Therefore, in the subsequent ion implantation step, the amount of nickel introduced can be changed in proportion to the dose.

A nickel-added region 304 is formed by this ion implantation step. The amount of nickel introduced in the ion implantation step in FIG.

Next, after removing the mask insulating film 302,
A mask insulating film 305 is provided, and an opening 306 is formed in a region to be a pixel matrix circuit. Then, in this state, nickel is added by an ion implantation method, and the nickel added region 3
07 is formed. The amount of nickel introduced in the ion implantation step in FIG.

When the state shown in FIG. 3 (B) is obtained, at a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) for 4 to 24 hours (typically, in a nitrogen, oxygen or hydrogen atmosphere). Is 8
(About 15 hours), and the amorphous silicon film 301 is crystallized. By this heat treatment, the lateral growth regions 308, 3
09 is obtained. (FIG. 3 (C))

At this time, the growth distance of the lateral growth region 308 is set to A.
And That is, in the ion implantation step of FIG. 3 (A), nickel is added at an introduction amount a which realizes the growth distance A. Further, nickel is added to the lateral growth region 309 at an introduction amount b such that the growth distance B is realized in the ion implantation step of FIG.

The lateral growth regions 308 and 309 have a crystal structure in which needle-like or columnar crystals that have grown substantially parallel to the substrate are assembled. Further, each needle-shaped crystal is characterized by growing substantially parallel to each other and macroscopically in the same direction (arranged with regularity in a specific direction). Further, it has been confirmed by SIMS (Mass Secondary Ion Analysis) that it contains about 5 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ of nickel.

The regions 310 and 3 to which nickel was added were used.
Reference numeral 11 denotes a crystallized region containing nickel at a high concentration.
The regions other than the crystallized regions 308 to 311 remain as uncrystallized regions (amorphous regions) that have not been crystallized.

Next, a resist mask 312 is formed by removing the mask insulating film 305. Then, openings 313 to 315 are formed by patterning. At this time, the openings 313 and 314 are provided on a region adjacent to the element formation portion (the region to be the active layer of the TFT in this embodiment). this is,
This is because a phosphorus element-containing layer (a nickel gettering region) is formed below the openings 313 and 314 in a later step.

The opening 315 is formed on a region which will be a lower electrode of the storage capacitor later. In this embodiment, a part of an active layer which is made conductive by adding phosphorus is used as a lower electrode of an auxiliary capacitor.

Incidentally, without newly forming a resist mask,
The mask insulating film 305 may be patterned to form a necessary opening. In this case, the opening 306 used for nickel addition can be used as it is in the next P ion implantation step.

Next, in this state, P (phosphorus) ions are added by an ion plantation method or a plasma doping method. In the doping step of this embodiment, the accelerating voltage is 5
Up to 25 kV and a dose of 1 × 10 ¹³ to 8 × 10 ¹⁵ atoms / cm
² (preferably 5 × 10 ¹³ to 1 × 10 ¹⁵ atoms / cm ² ).

With such a setting, P ions are added at a concentration of 5 × 10 ¹⁹ to 2 × 10 ²¹ atoms / cm ³ in the P ion added region (hereinafter referred to as phosphorus added region) 316 to 318. Is added. In addition, the phosphorus added region 316 to
318 becomes amorphous once. (FIG. 4 (A))

In the structure of this embodiment, the phosphorus added region 31
P ions added to 6, 317 are added for the purpose of gettering the catalytic element. Further, the phosphorus added region 31
The P ions added to 8 are added for the purpose of providing the silicon film with N-type conductivity and using it as a lower electrode of an auxiliary capacitor.

As described above, according to the present embodiment, the manufacturing process is different in that an area for gettering nickel with the phosphorus element can be formed, and at the same time, an N-type conductive layer serving as a lower electrode of the auxiliary capacitor can be formed. Has been simplified. Of course, the phosphorus added region 318 also has a catalyst element gettering effect.

After the P ion addition step is completed, the resist mask 312 is removed, and the resist mask 312 is removed at 400 to 700 ° C. in a nitrogen atmosphere.
(Typically 600 ° C), 2-24 hours (typically 8-15
(Time), and the nickel remaining in the lateral growth regions 308 and 309 is moved to the phosphorus added regions 319 to 321. At this time, the phosphorus added regions 319 to 32
1 recrystallizes. (FIG. 4 (B))

The nickel remaining in the lateral growth regions 308 and 309 is gettered by the phosphorus-added regions 319 to 321 to reduce the nickel concentration.
22, 323 are obtained. The gettering step using the phosphorus element is disclosed in Japanese Patent Application No. 9-94607 filed on March 27, 1997 by the present inventors.

The inventors confirmed by SIMS (Secondary Mass Ion Analysis) that the nickel concentration in the lateral growth regions 322 and 323 after the step shown in FIG. It was found to be reduced to ¹⁷ atoms / cm ³ or less (below this is the detection lower limit and measurement is impossible).

At this time, the phosphorus added regions 319 to 3
Numeral 21 is a region containing nickel at a high concentration because nickel is gettered and collected. SIMS analysis confirmed the presence of nickel at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ .

However, there is no problem even if nickel is present in the phosphorus-added region 321 functioning as a lower electrode of the auxiliary capacitance, as long as it functions as an electrode. Further, the phosphorus-added regions 319 and 320 are not used at least for a channel formation region (they can be used as source / drain regions).
Therefore, the presence or absence of nickel does not matter since the phosphorus-added regions 319 and 320 are basically removed at the time of forming the active layer.

When the state shown in FIG. 4B is obtained,
The active layers 324 to 326 are formed by patterning the silicon film. The active layers 324 and 325 are mainly composed of an N-type TFT and a P-type TFT of a CMOS circuit constituting a peripheral circuit.
Becomes Further, the active layer 326 becomes a pixel TFT (an N-type TFT in this embodiment) forming a pixel matrix circuit.

At the time of this patterning, it is desirable to remove the portion that has become the nickel added region and the end of the lateral growth region. This is because this region contains nickel at a very high density in a narrow region, so that it is preferentially etched in a later etching step or the like, and may contaminate a chemical solution or the like.

In this patterning, the edges of the nickel-added region and the lateral growth region are preferentially etched, so that a step is formed in the base (base film or quartz substrate surface).
In particular, care must be taken because the step in the nickel added region tends to be large.

Next, an oxide (not shown) formed on the surface of the silicon film is removed. Since such surface oxides take in contaminants and the like in the silicon film, a clean silicon film surface can be obtained by removing them.

Then, a silicon oxide film 327 serving as a gate insulating film is immediately formed to a thickness of 10 to 150 nm by using the plasma CVD method. Of course, a low pressure thermal CVD method, a sputtering method, or the like can also be used. ECR plasma CVD and high-density plasma CVD are also effective. (FIG. 4 (C))

Next, electrode patterns 328 to 331 made of aluminum or a material containing aluminum as a main component are formed. The electrode patterns 328 to 330 are each CM
This is a prototype of the gate electrode that constitutes the OS circuit or the pixel TFT. The electrode pattern 331 is a prototype of the upper electrode of the storage capacitor.

In this embodiment, since a triple gate type TFT is used as the pixel TFT, the electrode pattern 33 is used.
Although 0 is divided into three parts, it is actually the same electrode that is all connected.

When the state shown in FIG. 5A is obtained,
Next, two anodic oxidation steps are performed. The steps from the anodic oxidation step to the ion implantation (phosphorus (P) or boron (B)) described below are described in
This is based on the technology described in JP-A-7-135318. Therefore,
The detailed conditions and the like should be referred to the publication.

After forming the electrode patterns 328 to 331, first, anodic oxidation is performed in a 3% oxalic acid aqueous solution to form porous anodic oxide films 332 to 335. next,
Anodization is performed in an ethylene glycol solution mixed with 3% tartaric acid to form nonporous anodic oxide films 336 to 339. After these two anodic oxidation steps, the gate electrodes 340 to 342 and the upper electrode 343 of the storage capacitor are defined.

When the state shown in FIG. 5B is obtained, dry etching of the gate insulating film 327 is performed using the gate electrode and the porous anodic oxide film as a mask. Through this process, gate insulating films 344 to 347 are formed. Note that the gate insulating film 347 functions as a capacitor insulating film of an auxiliary capacitance. (FIG. 5 (C))

Next, as shown in FIG. 5D, the porous anodic oxide films 332 to 335 are removed, and high-acceleration P ion implantation and low-acceleration P ion implantation are performed. By this step, the source region 348, the drain region 349, and a pair of low-concentration impurity regions (also referred to as LDD regions) 35 of the N-type TFT are formed.
0, a channel formation region 351 is formed.

In this embodiment, the pixel TFT is formed of an N-type TF
T, the source region 352 and the drain region 353 of the pixel TFT, and a pair of low-concentration impurity regions 354 to 3
56, channel formation regions 357 to 359 are formed.

At this time, P ions are also added to the active layer of the P-type TFT, so that the regions 360 and 361 containing the same concentration of P ions as the source / drain regions and the same concentration as the low concentration impurity regions. A region 362 containing P ions is formed. Further, no P ions are added to the region indicated by 363 at all, and the concentration of P ions added in advance is maintained, but the pixel TFT and the drain region 353 are substantially integrated.

Next, a resist mask 364 is provided so that only the P-type TFT is exposed, and high-acceleration B ions and low-acceleration B ions are implanted. By this step, the regions 360 to 362 containing P ions in FIG. 5D are all inverted to P-type, and the source region 365, the drain region 366, the pair of low-concentration impurity regions 367, and the channel formation region 368 of the P-type TFT are formed. Is formed. (FIG. 6 (A))

Using the above ion implantation process,
N-type TFT and P-type TFT with only one patterning process
Source / drain regions can be formed.

Next, with the resist mask 364 removed, activation of the implanted P ions and B ions is performed by any one of furnace annealing, laser annealing, and lamp annealing, or a combination thereof. At the same time, the crystallinity of the active layer broken by the ion implantation is restored.

Next, a laminated film composed of a silicon oxide film and a silicon nitride film is formed as the first interlayer insulating film 369. Then, after forming a contact hole, the source electrode 370 is formed.
To 372 and drain electrodes 373 and 374 are formed.
(FIG. 6 (B))

Next, as the second interlayer insulating film 375, an organic resin film (polyimide, polyamide, polyimide amide, acrylic, or the like) is formed to a thickness of 0.5 to 3 μm (preferably 1.5 to 2.
5 μm). The most significant feature of the organic resin film is its low dielectric constant (about 2.0 to 3.4).
Thereby, the parasitic capacitance between the wirings can be significantly reduced. That is, when configuring a circuit that requires high-frequency driving, such as a logic circuit, a decrease in operation speed can be effectively suppressed.

Next, a contact hole is formed in the second interlayer insulating film 375, and a pixel electrode 376 is formed. In this embodiment, the pixel electrode 376 is made of aluminum or a material containing aluminum as a main component.

Finally, the whole obtained TFT is subjected to a heat treatment in a hydrogen atmosphere to be hydrogenated to reduce dangling bonds in the active layer. Thus, an active matrix substrate in which the CMOS circuit and the pixel TFT are integrally formed on the same substrate as shown in FIG. 6C is completed.

Thereafter, a liquid crystal layer is sandwiched between the active matrix substrate and the opposing substrate by a known cell assembling process to complete a reflection type liquid crystal display device.

The design items such as the type of the liquid crystal material and the cell gap may be appropriately determined by the practitioner. Further, in this embodiment, the black mask is provided on the opposite side, but it may be provided at a necessary portion on the active matrix substrate side.

It is of great significance to make the growth distances of the lateral growth regions different as in the present invention.

For example, the crystallinity may be slightly different depending on the position of the lateral growth region even in the same region. In such a case, a plurality of TFTs are provided in one lateral growth region.
Is formed, the electric characteristics may be different between two separated TFTs.

However, such a delicate characteristic difference causes a problem in a circuit for handling an analog signal or a circuit for high-frequency driving. Therefore, by forming a lateral growth region at a necessary position at a necessary distance, a TFT having a very small characteristic difference can be obtained.
Groups need to be formed.

The present invention is a very effective technique for such a demand. Further, by using the ion implantation method, the area occupied by the catalytic element addition region can be made very small, so that the degree of freedom in circuit design is dramatically improved.

Therefore, in view of the flow of semiconductor circuits in the future, the effects of the present invention are considered to be extremely effective for high-frequency circuits formed by ultrafine processing and having extremely high operation speeds. It is.

[Embodiment 2] In Embodiment 1, aluminum or a material containing aluminum as a main component was used for the gate electrode. However, in the present invention, a crystalline silicon film having one conductivity can be used as the gate electrode. is there.

Further, titanium, tantalum, tungsten,
A metal material such as molybdenum or a metal silicide made of a compound of such a metal material and silicon can be used as the gate electrode.

[Embodiment 3] In this embodiment, an example in which the growth distance of the lateral growth region is controlled by controlling the amount of introduction of the catalytic element (nickel) by means different from that in the embodiment 1 will be described.

In FIG. 8A, reference numeral 800 denotes a glass substrate provided with a base film, and 801 denotes an amorphous silicon film. Then, a mask insulating film 802 is formed, and then an opening 803 is formed.
804 is formed.

At this time, the amount of nickel introduced is controlled by setting the minimum slit width of the opening to a different length. In this embodiment, the minimum slit width of the peripheral circuit is a 'and the minimum slit width of the pixel matrix circuit is b'.

In this state, nickel is implanted by an ion implantation method. The injection conditions may be the same as in the first embodiment.
In this embodiment, nickel ions are implanted at an acceleration voltage of 10 kV and a dose of 2 × 10 ¹⁴ atoms / cm ² . (FIG. 8A)

At this time, since the ion implantation process is performed at a time, the concentration of nickel added to the openings 803 and 804 is the same. However, the nickel-added regions 805 and 806 formed in this ion implantation step have openings 80.
The amount of nickel introduced differs depending on the minimum slit width of 3, 804.

When the state of FIG. 8A is obtained, the first embodiment
The heat treatment is performed under the same conditions as described above, and the amorphous silicon film 802 is crystallized. In this embodiment, the crystallization step is performed by a heat treatment at 570 ° C. for 14 hours. (FIG. 8 (B))

By this crystallization step, the lateral growth region 807,
808 are formed. At this time, the growth distance of the lateral growth region 807 is A ′, and the growth distance of the lateral growth region 808 is B ′. In the present embodiment, the design is made such that the relation of B ′> A ′ is satisfied.

In this embodiment, the lateral growth region 80 is formed after crystallization.
The minimum slit width a ′ is determined so that the growth distance of A 7 becomes A ′, and the minimum slit width b ′ is determined so that the growth distance of the lateral growth region 808 becomes B ′. It is necessary to experimentally determine the relationship between the minimum slit width and the growth distance in advance under the ion implantation conditions (10 kV, 2 × 10 ¹⁴ atoms / cm ² ) of the present embodiment.

In the case where the ion implantation step is performed at one time as in the present embodiment, the addition of nickel is the same over the entire surface of the substrate, so that the control of the minimum slit width is the control of the amount of nickel introduced, and consequently the control of the lateral growth region. It leads to control of the growth distance.
Subsequent steps may follow the first embodiment.

With the structure as in this embodiment, phosphorus can be added using the mask insulating film 802 as a mask when performing a P ion implantation step as shown in FIG. 4A later. This eliminates the need for providing a resist mask, and simplifies the manufacturing process by reducing the number of patterning steps by one.

[Embodiment 4] The present invention is not limited to the ion implantation method described with reference to FIG. 1, but as another embodiment, a catalytic element is directly introduced into an amorphous silicon film without using a resist mask. Can also be added.

As means for this, FIB (Focuss
There is a technique such as the ed Ion Beam method that can irradiate only a fine spot with ions. According to such a technique, a pattern is directly drawn by a focused ion beam containing a catalyst element, and a catalyst element addition region can be formed at a desired position in a desired shape.

According to this embodiment, the steps of forming the resist mask and the patterning step can be simplified, so that the manufacturing cost can be reduced and the manufacturing yield can be improved.

[Embodiment 5] In Embodiments 1 and 2, a planar type TFT is shown as an example of a typical TFT structure. However, a bottom gate type TFT such as an inverted stagger type TFT may be used in the present invention. It is also possible to apply.

As described above, the present invention can be applied regardless of the structure of a semiconductor element (semiconductor device), and is not limited to a semiconductor element having a specific structure.

[Embodiment 6] In this embodiment, an example of a pixel configuration forming a pixel matrix circuit is shown in FIG. However,
Pixel electrodes are omitted to simplify the structure.

In FIG. 9, reference numeral 11 denotes an active layer.
This corresponds to the active layer 326 in FIG. The present embodiment is characterized in that the drain side of the active layer 11 is formed so as to extend all over the pixel, and also serves as the lower electrode 12 of the auxiliary capacitance.

A gate line 13 is disposed above the gate line 13 via a gate insulating film. Gate line 13 corresponds to gate electrode 342 in FIG. In addition, an upper electrode 14 of an auxiliary capacitance is formed separately from the gate line 13. The upper electrode 14 corresponds to the upper electrode 343 in FIG.

In this case, the upper electrode 14 is provided so as to have a shape substantially coinciding with the active layer serving as the lower electrode, and forms an auxiliary capacitance substantially corresponding to the area occupied by the pixel. Also,
The upper electrode 14 is electrically connected between adjacent pixels (connected in parallel with the gate line so as not to cross the gate line). That is, the upper electrodes of the storage capacitors are kept at the same potential in all the pixels.

Next, a source electrode (source line) 15 and a drain electrode 16 are formed on the gate line 13 and the upper electrode 14 of the storage capacitor via a first interlayer insulating film.
These electrodes are respectively the source electrode 37 of FIG.
2 and the drain electrode 374.

Although not shown, FIG.
As shown in FIG. 9C, a reflective liquid crystal display device is completed by forming an interlayer insulating film 375 and a pixel electrode 376 and performing a known cell assembling process. With the structure as in the present embodiment, even if the pixel area is reduced, it is possible to secure the auxiliary capacitance by making the most of the area.

When the configuration as in the present embodiment is adapted to XGA, it is very difficult to form the active layer of the TFT arranged in the pixel matrix circuit in the lateral growth region. This is because, in the XGA, since the pixel size is as small as about 30 μm square, if a large nickel-added region is formed by a conventional method, it becomes impossible to form a lower electrode for forming an auxiliary capacitor by removing the large nickel-added region. It is.

However, in the present invention, the above-described problem does not occur because the nickel-added region can be devised, for example, to be provided below the source electrode 15.

[Embodiment 7] In this embodiment, an example in which the present invention is applied to a reflection type liquid crystal display device having a structure different from that of Embodiment 6 will be described. FIG. 10A is a top view thereof (excluding the counter substrate, the liquid crystal layer, and the pixel electrode).
(B) is a sectional view thereof.

In FIGS. 10A and 10B, reference numeral 20 denotes an active layer, reference numeral 21 denotes a gay electrode (gate line), reference numeral 22 denotes a source electrode (source line), and reference numeral 23 denotes a drain electrode. At this time, the drain electrode 23 is formed large so as to spread over the entire pixel region (region indicated by a dotted line). This drain electrode 23
Functions as a lower electrode of the storage capacitor.

A silicon nitride film 24 (FIG. 10)
(B)), and a titanium film 2 is further formed thereon.
5 are arranged. The titanium film 25 functions as an upper electrode of the storage capacitor, and forms a storage capacitor with the silicon nitride film 24 interposed between the drain electrode 23 and the titanium film 25.

Also, actually, as shown in FIG.
The pixel electrode 26 is formed so as to cover the whole area of the pixel. Then, an alignment film (not shown) is formed thereon. Here, these are collectively called an active matrix substrate.

As shown in FIG. 10B, a transparent substrate 27 on which a transparent conductive film 28 and an alignment film (not shown) are formed is prepared as a counter substrate. The opposite substrate may be provided with a color filter, a black mask, and the like, if necessary.

The liquid crystal layer 30 is sandwiched between the opposing substrate and the active matrix substrate while being sealed in the sealing material 29. The liquid crystal material can be appropriately changed depending on the driving mode of the liquid crystal such as the ECB mode and the guest host mode.

In this embodiment, the liquid crystal layer is not disposed above the peripheral circuit to prevent the formation of a parasitic capacitance between the peripheral circuit and the transparent conductive film 28 on the counter substrate side. Of course, a configuration in which the liquid crystal layer is disposed on the entire surface of the substrate may be used.

[Embodiment 8] In the embodiments 6 and 7, the example of forming the reflection type liquid crystal display device has been described. However, it goes without saying that the present invention can be applied to the transmission type liquid crystal display device.

In the present invention, the effect of increasing the degree of freedom in circuit design can be obtained, which is very effective in improving the aperture ratio of a transmission type display device.

[Embodiment 9] In this embodiment, an example in which an ion implantation step of a catalytic element (nickel) is performed with a configuration different from that of Embodiment 1 will be described.

In FIG. 11, reference numeral 40 denotes a glass substrate;
Is a base film, 42 is an amorphous silicon film, 43 is a buffer layer made of a silicon oxide film or the like, and 44 is a resist mask having an opening. The buffer layer 43 may be formed by a gas phase method such as a plasma CVD method, or may be thermally oxidized,
It may be formed by simple oxidation means such as V oxidation.

The present embodiment is characterized in that the catalyst element is not directly injected into the amorphous silicon
Inject through 3. At this time, it goes without saying that the ion profile at the time of ion implantation is adjusted so that the peak value is located in the amorphous silicon film 42.

Also in the configuration of this embodiment, the nickel-added regions 45 and 46 can be formed in the amorphous silicon film 42 by optimizing the ion implantation conditions.

According to the structure of this embodiment, since the damage at the time of ion implantation does not directly reach the amorphous silicon film 42, it is possible to avoid an adverse effect due to the damage. Further, it is possible to prevent an impurity element other than the catalyst element (such as an element contained in the atmosphere) from being implanted together during the ion implantation.

The amorphous silicon film 42 and the buffer layer 43
Is effective in forming a film continuously by a plasma CVD method. In such a configuration, impurities do not adhere to the surface of the amorphous silicon film 42 and are not implanted together during ion implantation.

It is also possible to perform an ion implantation step combining the structure of this embodiment and the structure of the first embodiment.

[Embodiment 10] In the first embodiment, an example in which an ion implantation method is used as a means for adding P ions is described. In this embodiment, an example in which a gas phase method is used will be described.

In this embodiment, a thin film containing phosphorus is formed by a plasma CVD method in a state where an insulating layer is provided at a necessary position on the amorphous silicon film. For this thin film, a gas such as phosphine (PH ₃ ) may be added to the deposition gas.

By doing so, the region where the thin film is formed at the time of the gettering step (heat treatment) by the phosphorus element functions as a gettering region.

[Embodiment 11] In this embodiment, an example in which a liquid phase method is used as a method for adding P ions will be described. Specifically, a thin film typified by PSG (phosphosilicate glass) is formed by solution coating.

Also in this case, a solution serving as a raw material for PSG is applied in a state where an insulating layer is provided at a necessary portion on the amorphous silicon film, and a thin film containing phosphorus is formed by spin coating. The gettering region can be formed by such a method.

[Embodiment 12] In this embodiment, an example in which a gettering step using a halogen element is performed instead of the gettering step using a phosphorus element in the first embodiment will be described. Note that the same reference numerals as in the first embodiment are used as needed.

First, FIG.
The state shown in FIG. This state is shown in FIG.
This corresponds to the state of (C).

Next, when the state of FIG. 12C is obtained,
Heat treatment is performed in an atmosphere containing a halogen element. In this embodiment, hydrogen chloride (H) is used in an oxygen (O ₂ ) atmosphere.
Cl) at 0.5 to 10% by volume (typically 3%). (FIG. 12 (B))

It should be noted that HF, NF ₃ , HB
One or more compounds selected from compounds containing halogen such as r, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , and Br ₂ can be used. Further, a halide hydride can also be used.

Further, this heat treatment is preferably performed at a temperature exceeding 700 ° C. in order to effectively perform nickel gettering by chlorine. Typically, 800 to 1000 ° C. (950 ° C. in this embodiment) is good. By this treatment, nickel is thoroughly removed or reduced from the entire crystalline silicon film.

Further, as a result of the present inventors confirming by SIMS (mass secondary ion analysis), the nickel concentration contained in the lateral growth regions 51 and 52 after the step shown in FIG.
It was found that it was reduced to at least 5 × 10 ¹⁷ atoms / cm ³ or less (below this is the detection lower limit and cannot be measured).

Further, a halogen element is taken into the lateral growth region by this heat treatment. Therefore, the final active layer (lateral growth region) contains 1 × 10 ¹⁵ to 1 × 10 ²⁰ atom
The halogen element is present at a concentration of s / cm ³ .

Further, as a result of analyzing the lateral growth regions 51 and 52 by TEM (transmission electron microscope), the present inventors have found that a crystal structure in which a plurality of rod-shaped or flat rod-shaped crystals arranged regularly in a specific direction are assembled. confirmed.

The characteristics of this crystal structure are almost the same as the characteristics of the lateral growth region described above. However, according to various analyzes by the present inventors, the boundary (crystal grain boundary) between each rod-shaped crystal (which may be referred to as a needle-shaped crystal) has a very continuous lattice and is extremely consistent, and is electrically inactive. It is speculated that

As evidence, a TFT using an active layer of a crystalline silicon film having such a crystal structure has achieved electrical characteristics that surpass those of a MOSFET formed on single-crystal silicon. Details regarding this crystal structure are described in Japanese Patent Application No. 8-335152 filed on Nov. 29, 1996 by the present inventors.

After the state shown in FIG. 12B is obtained, the silicon film is patterned to form active layers 53 to 55. The active layers 53 and 54 are N-type TFTs and P-type TFTs of a CMOS circuit that mainly forms a peripheral circuit. The active layer 55 becomes a pixel TFT forming a pixel matrix circuit.

Next, a silicon oxide film 56 serving as a gate insulating film is formed.
Is formed to a thickness of 10 to 150 nm using a plasma CVD method, and a heat treatment is performed again at a temperature exceeding 700 ° C. At this time, it is preferable that the processing atmosphere be an atmosphere containing a halogen element as described above. In that case, the conditions may be the same as the conditions described above. (FIG. 12 (C))

It is also effective to improve the quality of the gate insulating film 56 by performing a heat treatment in an inert atmosphere at the end of the heat treatment.

By this heat treatment, further removal of nickel remaining in the active layer can be expected. The active layer 53
A thermal oxide film is formed on the interface between the gate insulating film 56 and the gate insulating film 56, and a good interface between the active layer and the gate insulating film with a small interface level is obtained. Thereafter, a semiconductor device may be manufactured according to the same steps as in the first embodiment.

[Embodiment 13] The present invention can be applied to electro-optical devices other than liquid crystal display devices. Examples of such an electro-optical device include an EL (electroluminescence) display device and an EC (electrochromics) display device.

[Embodiment 14] In this embodiment, an example of an applied product (electronic device) using an electro-optical device using the present invention is shown in FIG. Examples of applied products using the present invention include a video camera, a still camera, a projector, a head-mounted display, a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone, etc.).

FIG. 12A shows a mobile phone, and the main body 20 is provided.
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the display device 2004.

FIG. 12B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102.

FIG. 12C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 is applicable.

FIG. 12D shows a head-mounted display, which comprises a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302.

FIG. 12E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 12F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the application range of the present invention is extremely wide, and it can be applied to display media in all fields. In particular, when a liquid crystal display device is used for a projection display device such as a projector, a very high resolution is required. In such a case, the present invention is a very effective technique.

[0161]

By implementing the present invention, it becomes possible to significantly reduce the region to which the catalyst element is added. Then, by reducing the catalyst element addition region which has conventionally been a dead space, the degree of freedom in circuit design is dramatically improved.

As described above, according to the present invention, a pixel region having a structure as shown in FIG. 9 can be easily formed. The pixel structure shown in FIG. 9 is a very effective configuration when the pixel density is increased to XGA and SXGA and thereafter, and the present invention is an extremely effective technique capable of coping with such miniaturization of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an ion implantation step.

FIG. 2 is a diagram for explaining the introduction amount of a catalytic element and the lateral growth distance.

FIG. 3 illustrates a manufacturing process of a semiconductor device.

FIG. 4 illustrates a manufacturing process of a semiconductor device.

FIG. 5 illustrates a manufacturing process of a semiconductor device.

FIG. 6 illustrates a manufacturing process of a semiconductor device.

FIG. 7 is a diagram for explaining the definition of the amount of catalyst element introduced.

FIG. 8 illustrates a manufacturing process of a semiconductor device.

FIG. 9 is a diagram illustrating a configuration of a pixel region.

FIG. 10 is a diagram illustrating a configuration of a pixel region.

FIG. 11 is a view showing an ion implantation step.

FIG. 12 illustrates a manufacturing process of a semiconductor device.

FIG. 13 is a view showing an applied product to which the present invention can be applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102 Underlayer 103 Amorphous film 104 Insulating layer 105 Opening 106 Catalyst element addition area 107 Ion profile

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 627Z

Claims (14)

[Claims] A step of forming an insulating layer having an opening on an amorphous film containing silicon; and a step of forming a catalyst element for promoting crystallization of silicon on the amorphous film using the insulating layer as a mask. Adding at least a part by an ion implantation method; and crystallizing at least a part of the amorphous film by a heat treatment to form a lateral growth region. A growth distance of the semiconductor device is controlled. A step of forming an insulating layer having an opening on the amorphous film containing silicon; and a step of forming a catalyst element for promoting crystallization of silicon on the amorphous film using the insulating layer as a mask. Adding at least one part by an ion implantation method; and crystallizing at least a part of the amorphous film by heat treatment to form a lateral growth region. A method for manufacturing a semiconductor device, wherein the catalyst element is added in an amount different from that of the region, and the growth distance of the lateral growth region is controlled by the amount of the catalyst element. A step of forming an insulating layer having an opening on the amorphous film containing silicon; and a step of using a catalyst element for promoting crystallization of silicon in the amorphous film using the insulating layer as a mask. A step of adding by an ion implantation method, a step of crystallizing at least a part of the amorphous film by a heat treatment to form a lateral growth region, and a step of selectively adding an element selected from Group 15 A step of gettering the catalyst element from a region adjacent to the region to which an element selected from the group XV is added by heat treatment. 4. A step of forming an insulating layer having an opening on an amorphous film containing silicon, and using a catalyst element for promoting crystallization of silicon in the amorphous film using the insulating layer as a mask. A step of adding by an ion implantation method, a step of crystallizing at least a part of the amorphous film by a heat treatment to form a lateral growth region, and a step of selectively adding an element selected from Group 15 A step of gettering the catalyst element from a region adjacent to the region to which an element selected from the group XV has been added by a heat treatment; and A growth distance of the semiconductor device is controlled. 5. A step of forming an insulating layer having an opening on an amorphous film containing silicon, and using a catalyst element for promoting crystallization of silicon in the amorphous film using the insulating layer as a mask. A step of adding by an ion implantation method, a step of crystallizing at least a part of the amorphous film by a heat treatment to form a lateral growth region, and a step of selectively adding an element selected from Group 15 A step of gettering the catalyst element from a region adjacent to the region to which an element selected from the group XV is added by a heat treatment; and A method for manufacturing a semiconductor device, wherein the catalyst element is added in an amount different from that of the region, and the growth distance of the lateral growth region is controlled by the amount of the catalyst element. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the amount of the catalyst element introduced is controlled by the concentration of the catalyst element added during ion implantation. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the amount of the catalyst element introduced is controlled by a minimum slit width of the opening during ion implantation. 8. The method for manufacturing a semiconductor device according to claim 1, wherein a length of a short side of the opening is 0.25 to 2 μm. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the step of adding the catalyst element is performed at a dose of 1 × 10 ¹² to 1 × 10 ¹⁵ atoms / cm ² . 10. The semiconductor device according to claim 1, wherein one or a plurality of elements selected from Ni, Fe, Co, Pd, Pb, Pt, and Cu are used as the catalyst element. Production method. 11. The lateral growth region according to claim 1, wherein the lateral growth region is a region having a crystal structure in which needle-like or columnar crystals are substantially parallel to the substrate and aligned in directions substantially parallel to each other. Of manufacturing a semiconductor device. 12. A semiconductor device according to claim 3, wherein at least one element selected from the group consisting of P, As, N, Sb and Bi is used as the element selected from the group XV. Method. 13. The method according to claim 3, wherein the step of adding an element selected from the group 15 is performed at 1 × 10 ¹³ to 8 × 10 ¹⁵ at.
A method for manufacturing a semiconductor device, which is performed at a dose of oms / cm ³ . 14. A method for manufacturing a semiconductor device according to claim 3, wherein the element selected from Group 15 is performed by any one of an ion implantation method, a gas phase method, and a liquid phase method. .