JPH10302481A - Ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken the operating speed of a ferroelectric memory. SOLUTION: Electrodes of one sides of ferroelectric capacitive elements 2 are connected to plate lines 131 -134 via transistors 1 and electrodes of other sides of the elements 2 are connected to bit lines 141 -144 . As a result, the bit lines are made to be low resistances and driving speeds of the bit lines are quickened by using tungsten silicide WSi conventionally used as bit lines as plate lines and using platinum Pt conventionally used as plate lines as the bit lines. Moreover, the high resistances of the plate lines do not affect to the speed because the potentials of the plate lines are made to be constant to operate the elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, and more particularly, to a ferroelectric memory in which a memory cell is formed by a ferroelectric capacitive element for holding data stored on a semiconductor substrate and a switching transistor. Regarding memory.

[0002]

FIG. 13 is a circuit diagram of a conventional ferroelectric memory, and FIG. 14 is a sectional view showing a memory cell structure of a conventional ferroelectric memory.

Conventionally, this type of ferroelectric memory has a structure in which one electrode of a ferroelectric capacitor is connected to a bit line via a transistor and the other electrode is connected, as shown in, for example, Japanese Patent Application Laid-Open No. 6-125056. It is configured to connect to a plate line.

[0004] The 1995 Symposium on VSI Technology Digest of
Technical Papers (1995 Symposium on VLSI Dig)
estof Technical Papers) Pages 123 to 124 show a configuration of a memory cell structure using a tungsten silicide (WSi) wiring as a bit line and a platinum (Pt) wiring as a plate line as a method for realizing high integration. ing.

[0005] In strongly circuit diagram of a ferroelectric memory in FIG. 13, one electrode of the ferroelectric capacitive element 22 is connected to one of bit lines 34 ₁ to 34 ₄ via the transistor 21, the other electrode It is connected to one of the plate lines 33 _to 333 _4. Bit lines 34 ₁ and 34 ₂ is connected to the sense amplifier 38 _1, bit line 34 ₃ and 34 ₄ are connected to the sense amplifier 38 _2. Here, the bit line is a wiring for extracting a charge corresponding to a change in the charge stored in the ferroelectric capacitor, and refers to a wire connected to the sense amplifier. Further, the plate line refers to a wiring for defining the potential of one electrode of the ferroelectric capacitor element, which is connected to the electrode to which the bit line is not connected.

FIG. 14 is a cross-sectional view of a memory cell structure used in a conventional ferroelectric memory, in which an upper electrode 35 of a ferroelectric capacitor is formed of tungsten silicide (WSi) via a transistor 31. Connected bit line 34. The lower electrode 33 of the ferroelectric capacitor is formed of a laminated film of Pt and titanium (Ti), and is used as it is as a plate line.

[0007]

However, the above-mentioned prior art has the following problems.

Since a material having a higher resistance than tungsten metal such as tungsten silicide (WSi) is used as a wiring material of the bit line, the time required for driving the bit line becomes longer and the operation speed as a memory becomes slower. I will.

An object of the present invention is to provide a conventional memory cell structure which has been devised to realize high integration without changing the configuration.
An object of the present invention is to provide a ferroelectric memory having a high operation speed.

[0010]

According to a first aspect of the present invention, there is provided a ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film and an upper electrode. A) a unit memory cell is formed by a transistor and a ferroelectric capacitor element, one electrode of which is connected to a plate line via a transistor formed in a substrate shape and the other electrode of which is connected to a bit line; b) Unit memory cells connected to adjacent word lines are not connected to the same plate line or bit line. c) Unit memory cells connected to the same word line are plate lines or bit lines. D) the unit memory cells connected to the same word line are connected to different plate lines and bit lines, respectively, and e) the same plate line Different unit memory cells are connected, all connected to the same bit line, it is characterized in that.

The resistance of the bit line is reduced by using the structure of the conventional memory cell structure. Specifically, one electrode of the ferroelectric capacitor is connected to a plate line via a transistor, and the other electrode of the ferroelectric capacitor is connected to a bit line. Therefore, WSi used for the conventional bit line is used as the plate line, and Pt used for the conventional plate line is used as the bit line.

Since the wiring used as the bit line in the conventional ferroelectric memory is used as the plate line and the wiring used as the plate line is used as the bit line, the configuration of the memory cell structure is not changed. Although the plate line has a high resistance, the operation speed is not affected if the plate line is operated at a constant potential. Since the bit line has a low resistance, the driving time of the bit line is shortened and the operation speed is increased.

In the ferroelectric memories according to the second to sixth aspects of the present invention, the above a) to e) and b ') the unit memory cells connected to adjacent word lines are connected to the same bit line. Are not connected, or b ″) the unit memory cells connected to the adjacent word line and the adjacent bit line, respectively, are connected to the same plate line, and c ′) are connected to the same word line. The connected unit memory cells use every other bit line. D ') Different unit memory cells connected to the same word line are connected to different bit lines and the same plate line, respectively. Or d ") different unit memory cells connected to the same word line are connected to different bit lines,
Claims will describe six types of cases depending on the combination of the above and the like, and will be described in embodiments and examples.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a ferroelectric memory according to the present invention, and FIG. 7 is a plan view showing a memory cell array configuration of the first embodiment.

Referring to FIG. 1, one electrode of a ferroelectric capacitor 2 is connected to a plate line 13 ₁ via a transistor _1.
To 13 are connected to _4. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

FIG. 1 shows each word line 12 _1.
Although 12 ₄ to the connected transistor 1 and a strong set of dielectric capacitance element 2 is illustrated by two word lines 12
The pair of the transistor 1 and the ferroelectric capacitor 2 connected to ₁ or 12 ₃ uses plate lines 13 ₁ and 13 ₃ and bit lines 14 ₁ and 14 ₃ . The set of transistors 1 and the ferroelectric capacitive element 2 connected to the word line 12 ₂ and 12 _4, the plate line 13 _2,
13 ₄ and bit lines 14 ₂ and 14 ₄ are used.
That is, the pair of the transistor 1 and the ferroelectric capacitor 2 connected to the adjacent word line 12 are not connected to the same plate line 13 or bit line 14.

The pair of the transistor 1 and the ferroelectric capacitor 2 connected to the same word line 12 uses every other plate 13 line and every other bit line 14, and
Different sets of transistors 1 and ferroelectric capacitors 2 connected to the same word line 12 are connected to different plate lines 13 and bit lines 14, respectively. Furthermore,
All sets of different transistors 1 and ferroelectric capacitors 2 connected to the same plate line 13 are connected to the same bit line 14.

FIG. 1 shows a sense amplifier 1 having four word lines 12, four plate lines 13 and four bit lines 14, respectively.
Although two 8 are shown, this number can be set arbitrarily. However, the number of bit lines 14 must be even, and the number of sense amplifiers 18 must be half of the number of bit lines 14.

Next, the operation of the first embodiment will be described with reference to FIG.

The case where a set of the transistor 1 and the ferroelectric capacitor 2 connected to the word line 12 ₁ , plate line 13 ₁ and bit line 14 ₁ is used will be described.

When writing, the plate line 13 ₁
Is fixed at a voltage of, for example, Vcc / 2. Then, the potential of the bit line 14 _1, for example, 0 or Vcc after higher than the threshold voltage of the transistor 1 to the voltage of the word line 12 _1, writing data "0" or "1".

When reading is performed, the plate line 13₁ 
For example, Vcc / 2, bit line 14 _Two For example, Vref
It is fixed at the voltage. 14₁ Potential to 0, for example
Float after stipulating. And the word line 12₁ 
Is higher than the threshold voltage of transistor 1,
The written data is "0" or "1"
Depending on the bit line 14₁ Have different potentials
Change. Suppose that value is V₀ , V₁ And V
₀ <Vref <V₁ Set the value of Vref so that
By doing so, the sense amplifier 18₁ Operate
And the bit line 14 ₁ Is V₀ If it is
And V₁ Is changed to, for example, Vcc.

Next, the effect of the first embodiment will be described.

[0025] As described above, when the potential of the plate line 13 ₁ is also read, because during writing also constant at Vcc / 2, the resistance of the plate line does not influence the operation speed. Therefore, if the conventional memory cell structure for realizing high integration shown in FIG. 14 is used as it is, a wiring formed of WSi is used as a plate line, and a low-resistance wiring material is used as a wiring material for forming a bit line. Since Pt is used, the resistance of the plate line becomes higher and the resistance of the bit line becomes lower than in the conventional case, so that the bit line drive time is shortened and the operation speed can be increased.

Next, a second embodiment will be described.

FIG. 2 is a circuit configuration diagram showing a second embodiment, and FIG. 8 is a plan view showing a memory cell array configuration of the second embodiment.

Referring to FIG. 2, one electrode of the ferroelectric capacitor 2 is connected to the plate line 13 ₁ via the transistor _1.
To 13 are connected to _4. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

FIG. 2 shows each word line 12 _1.
Although 12 ₄ and plate lines _{131-134 2} connected transistor 1 and the ferroelectric capacitive element 2 are respectively set is shown by two, the word line 12 ₁ or 12
_{A set of} a transistor 1 and a ferroelectric capacitor 2 connected to ₃ uses bit lines 14 ₁ and 14 ₃ . Then, the transistor 1 and the strong set of dielectric capacitance element 2 is bit line connected to the word line 12 ₂ or 12 ₄ 14
It is used _2, 14 _4. That is, the transistor 1 and the ferroelectric capacitor 2 connected to the adjacent word lines
Are not connected to the same bit line.

The pair of the transistor 1 and the ferroelectric capacitor 2 connected to the same word line 12 uses every other bit line, and is connected to the same word line 12. Different sets of the transistor 1 and the ferroelectric capacitor 2 are connected to different bit lines 14 and the same plate line 13, respectively.

The sense amplifier 18 has the first
This is the same as the case of the embodiment.

The operation and effects are the same as those of the first embodiment, so that the bit line drive time is shortened and the operation speed can be increased.

Next, a third embodiment will be described.

FIG. 3 is a circuit configuration diagram showing a third embodiment, and FIG. 9 is a plan view showing a memory cell array configuration of the third embodiment.

Referring to FIG. 3, one electrode of ferroelectric capacitor 2 is connected to plate line 13 via transistor 1. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

FIG. 3 shows each word line 12 _1.
Although 12 ₄ to the connected transistor 1 and a strong set of dielectric capacitance element 2 is illustrated by two word lines 12
The pair of the transistor 1 and the ferroelectric capacitor 2 connected to ₁ or 12 ₃ uses the bit lines 14 ₁ and 14 ₃ . The set of transistors 1 and the ferroelectric capacitive element 2 connected to the word line 12 ₂ and 12 ₄ are using the bit line 14 _2, 14 _4. That is, the pairs of the transistor 1 and the ferroelectric capacitor 2 connected to the adjacent word lines 12 are not connected to the same bit line 14.

The pair of the transistor 1 and the ferroelectric capacitive element 2 connected to the same word line 12 uses every other bit line and is connected to the same word line 12. Different sets of transistors 1 and ferroelectric capacitors 2 are connected to different bit lines 14, respectively.

The sense amplifier 18 has the first
This is the same as the case of the embodiment.

The operation and effects are the same as in the first embodiment.

Next, a fourth embodiment will be described.

FIG. 4 is a circuit configuration diagram showing a fourth embodiment, and FIG. 10 is a plan view showing a memory cell array configuration of the fourth embodiment.

Referring to FIG. 4, one electrode of the ferroelectric capacitor 2 is connected to the plate line 13 ₁ via the transistor _1.
It is connected to the -13 _3. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

The transistor 1 and the ferroelectric capacitor
For the two sets, the adjacent word lines 12 and
And those connected to adjacent bit lines 14
It is connected to one plate line 13. For example,
Line 12₁ And bit line 14_TwoConnected to the
A pair of a transistor 1 and a ferroelectric capacitor 2 and a word line 12 _Two 
And bit line 14₁ And the transistor 1 connected to
The set of ferroelectric capacitors 2 is a plate line 13₁ Contact
Has been continued.

A pair of the transistor 1 and the ferroelectric capacitor 2 connected to the same word line 12 uses every other plate line and bit line, and is connected to the same word line 12. Different transistors 1
And the ferroelectric capacitor 2 are connected to different plate lines 13 and bit lines 14, respectively. For example, a set of transistor 1 and the ferroelectric capacitive element 2 connected to the word line 12 _1, 2 is but one plate line 1
3 ₁ a is connected to the bit line 14 _2, and the other is connected to a plate line 13 ₃ and the bit line 14 _4.

The sense amplifier 18 has the first
This is the same as the case of the embodiment.

The operation and effects are the same as those of the first embodiment.

Next, a fifth embodiment will be described.

FIG. 5 is a circuit configuration diagram showing a fifth embodiment, and FIG. 11 is a plan view showing a memory cell array configuration of the fifth embodiment.

Referring to FIG. 5, one electrode of ferroelectric capacitive element 2 is connected to plate line 13 ₁ via transistor _1.
It is connected to the -13 _3. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

The transistor 1 and the ferroelectric capacitor
For the two sets, the adjacent word lines 12 and
And those connected to adjacent bit lines 14
It is connected to one plate line 13. For example,
Line 12₁ And bit line 14_TwoConnected to the
A pair of a transistor 1 and a ferroelectric capacitor 2 and a word line 12 _Two 
And bit line 14_Three And the transistor 1 connected to
The set of ferroelectric capacitors 2 is a plate line 13₁ Contact
Has been continued.

The pair of the transistor 1 and the ferroelectric capacitor 2 connected to the same word line 12 uses every other bit line 14 and the same word line 1
2 are connected to different bit lines 14 and the same plate line 13, respectively. For example, there are two pairs of the transistor 1 and the ferroelectric capacitor 2 connected to the word line 12 ₁ , one of which is the plate line 13 ₁
And it is connected to the bit line 14 _2, and the other is connected to a plate line 13 ₁ and the bit line 14 _4.

The sense amplifier 18 has the first
This is the same as the case of the embodiment.

The operation and effects are the same as those of the first embodiment.

Next, a sixth embodiment will be described.

FIG. 6 is a circuit configuration diagram showing the sixth embodiment, and FIG. 12 is a plan view showing a memory cell array configuration of the sixth embodiment.

Referring to FIG. 6, one electrode of ferroelectric capacitor 2 is connected to plate line 13 via transistor 1. The other electrode of the ferroelectric capacitive element 2 is connected to bit line 14 ₁ to 14 _4.

The transistor 1 and the ferroelectric capacitor
For the two sets, the adjacent word lines 12 and
And those connected to adjacent bit lines 14
It is connected to the plate line 13 of the column. For example,
Line 12₁ And bit line 14_ThreeConnected to the
A pair of a transistor 1 and a ferroelectric capacitor 2 and a word line 12 _Two 
And bit line 14_Two And the transistor 1 connected to
The set of ferroelectric capacitors 2 is the plate line 1 in the leftmost column.
3 is connected.

The pair of the transistor 1 and the ferroelectric capacitor 2 connected to the same word line 12 uses every other bit line. For example, a set of transistor 1 and the ferroelectric capacitive element 2 connected to the word line 12 _1, 2 there is, one is connected to the bit line 14 _2, and the other is connected to the bit line 14 ₄ ing.

The sense amplifier 18 has the first
This is the same as the case of the embodiment.

The operation and effects are the same as in the first embodiment.

[0061]

Next, a first embodiment will be described with reference to the circuit configuration shown in FIG. 1 and the memory cell array configuration shown in FIG.

The source of the transistor formed by the element region 11 and the word line 12 also serving as a gate made of polysilicon, a laminated film of polysilicon and WSi, or a laminated film of polysilicon and titanium silicide (TSi). W is connected to one of the drain and
A plate line 13 made of Si is connected, and the other is connected to an upper electrode 15 of the ferroelectric capacitor via a wiring 16 and a contact 17. Pt, iridium (I
r), iridium oxide (IrO), ruthenium (R
u), a lower electrode of a ferroelectric capacitive element made of a ruthenium oxide (RuO) or a laminated film of them and Ti is used as the bit line 14 as it is. FIG.
In FIG. 1, the word lines 12 are sequentially arranged from left to right as shown in FIG.
Corresponding to _{1-12 4,} the plate line 13 and bit line 1
4, shown in FIG. 1 from the top _{131-134 2} and 1
4 correspond to _{1-14 2.} In this structure, the plate line 13 and the bit line 14 are orthogonal to the word line 12.

Next, the operation and effects of the first embodiment will be described.

As an example, it is assumed that 300 nm thick polysilicon is used as a word line, 200 nm thick Pt is used as a bit line, and 200 nm thick WSi is used as a plate line, and the above-mentioned voltage _Vcc is 5 volts. The operation for writing and the operation for reading are as described above.

In this case, when reading, the bit line capacity,
Assuming that the word line resistance and the like are constant, it is proportional to the square root of the bit line resistance. By changing the bit line material from 200 nm thick WSi to 200 nm thick Pt, the resistance changes from 8Ω / □ to 0.6Ω / □, so that the read time is reduced to about 約. Further, since the bit line capacity and the bit line resistance are almost proportional to the number of memory cells connected to one bit line, if the read time is fixed, the number of memory cells per bit line is doubled. be able to.
Further, the material of the plate line is changed from platinum (Pt) to tungsten silicide (WSi), so that the resistance is increased. However, as described above, the potential of the plate line is 2.5.
Since it can be used with a constant V, the change in resistance does not affect the operation speed.

The effect of this embodiment is that, as described above, the read time can be shortened to 1/4 or the number of memory cells connected to one bit line can be doubled. When the number of memory cells connected to one bit line is increased, the number of bit lines is reduced, and the number of sense amplifiers is also reduced. As a result, the chip area is reduced.

Next, a second embodiment will be described with reference to the circuit configuration shown in FIG. 2 and the memory cell array configuration shown in FIG.

The description of the material and the like from the element region 11 to the bit line 14 is the same as that in the first embodiment, and the description is omitted.

In the memory cell array configuration shown in FIG. 8, word lines 12 are sequentially arranged from left to right along word lines 1 shown in FIG.
Corresponds to 2 ₁ to 12 _4, the plate line 13 corresponds to a plate line _{131-134 2} shown in FIG. 2 from left to right. In this structure, the plate line 13 is formed parallel to the word line 12, and the bit line 14 is formed orthogonal to these.

The operation and effects of the second embodiment are the same as those of the first embodiment.

Next, a third embodiment will be described with reference to the circuit configuration shown in FIG. 3 and the memory cell array configuration shown in FIG.

The description of the material and the like from the element region 11 to the bit line 14 is the same as that in the first embodiment, and the description is omitted.

[0073] In Figure 9 the word line 12 corresponding to word lines 12 ₁ to 12 ₄ shown in FIG. 3 from the left, the plate line 13 corresponds to a plate line 13 shown in FIG. 3 . In this structure, all the plate lines 13 are connected to each other.

The operation and effect of the third embodiment are the same as those of the first embodiment.

Next, a fourth embodiment will be described with reference to the circuit configuration shown in FIG. 4 and the memory cell array configuration shown in FIG.

A transistor is formed by the element region 11 and the word line 12 serving also as a gate made of polysilicon, a stacked film of polysilicon and tungsten silicide (WSi), or a stacked film of polysilicon and titanium silicide (TSi). However, two transistors are formed using one of the source and the drain in common. A plate line 13 made of WSi is connected to a commonly used source / drain via a contact 17, and an upper electrode 15 of a ferroelectric capacitor is connected to the other via a wiring 16 and a contact 17. I have. Pt,
Iridium (Ir), iridium oxide (IrO),
The lower electrode of the ferroelectric capacitor composed of ruthenium (Ru), ruthenium oxide (RuO) or a laminated film of them and Ti is used as the bit line 14 as it is.

In FIG. 10, word lines 12 are arranged in order from the left.
The word line 12 shown in FIG.₁ ~ 12_Four Corresponding to
Plate lines 13 are shown in FIG.
Line 13 ₁ ~ 13_Two It corresponds to. In this structure,
The port line 13 and the bit line 14 are orthogonal to the word line 12.
ing.

The operation and effects of the fourth embodiment are similar to those of the first embodiment. In addition, as compared with the first embodiment, the width between the element regions adjacent to the bit line in the direction parallel to the bit line can be made wider, so that there is an effect that the resistance to a short circuit between the adjacent elements is increased.

Next, a fifth embodiment will be described with reference to the circuit configuration shown in FIG. 5 and the memory cell array configuration shown in FIG.

The description of the material and the like from the element region 11 to the bit line 14 is the same as that in the fourth embodiment, and the description is omitted.

[0081] In FIG. 11, the word line 12 corresponds to the word line 12 ₁ to 12 ₄ shown in FIG. 5 from left to right, the plate lines 13 ₁ to the plate line 13 is shown in FIG. 5 from the top which corresponds to 13 _2. In this structure, the plate line 13 is formed parallel to the word line 12 and orthogonal to the bit line 14.

The operation and effects of the fifth embodiment are the same as those of the fourth embodiment.

Next, a sixth embodiment will be described with reference to the circuit configuration shown in FIG. 6 and the memory cell array configuration shown in FIG.

The description of the material and the like from the element region 11 to the bit line 14 is the same as that in the fourth embodiment, and the description is omitted.

[0085] In FIG. 12 corresponds to the word line 12 ₁ to 12 ₄ shown word line 12 in FIG. 6 from left to right, the plate line 13 corresponds to a plate line 13 shown in FIG. 6 . In this structure, all the plate lines 13 are connected to each other.

The operation and effects of the sixth embodiment are the same as those of the fourth embodiment.

[0087]

As described above, the ferroelectric memory of the present invention has the following effects.

The first effect is that the operation speed can be increased without changing the configuration of the memory cell structure.

The reason is that the wiring used as the bit line in the conventional ferroelectric memory is used as the plate line, and the wiring used as the plate line is used as the bit line. It has not changed, and the plate line has a high resistance.However, if the operation is performed with the plate line potential kept constant, the operation speed is not affected, and the bit line has a low resistance. Drive time is shortened, and the operating speed is increased.

The second effect is that the chip area can be reduced unless the operation speed is changed.

The reason is that the resistance of the bit line is lower than that of the prior art, so that the number of memory cells connected per bit line can be increased to achieve the same operation speed. The number of bit lines is reduced, and the number of sense amplifiers can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a ferroelectric memory according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment.

FIG. 3 is a circuit configuration diagram showing a third embodiment.

FIG. 4 is a circuit configuration diagram showing a fourth embodiment.

FIG. 5 is a circuit configuration diagram showing a fifth embodiment.

FIG. 6 is a circuit diagram showing a sixth embodiment.

FIG. 7 is a plan view showing a memory cell array configuration of the first embodiment.

FIG. 8 is a plan view illustrating a configuration of a memory cell array according to a second embodiment;

FIG. 9 is a plan view illustrating a configuration of a memory cell array according to a third embodiment;

FIG. 10 is a plan view showing a memory cell array configuration of a fourth embodiment.

FIG. 11 is a plan view showing a configuration of a memory cell array according to a fifth embodiment;

FIG. 12 is a plan view illustrating a configuration of a memory cell array according to a sixth embodiment;

FIG. 13 is a circuit configuration diagram of a conventional ferroelectric memory.

FIG. 14 is a sectional view showing a memory cell structure of a conventional ferroelectric memory.

[Explanation of symbols]

1, 21 Transistor 2, 22 Ferroelectric Capacitance Element 11 Element Area 12, 12 _{1 to} 12 ₄ , 32 _{1 to} 32 ₄ Word Line 13, 13 _{1 to} 13 ₄ , 33 _{1 to} 33 ₄ Plate Line 14, 14 ₁ to 14 14 _4, 34, 34 ₁ to 34 ₄ bit lines 15, 35 ferroelectric capacitive element upper electrode 16 wiring 17 contacts 18 _1, 18 _2, 38 _1, 38 ₂ sense amplifiers 33 ferroelectric capacitive element the lower electrode

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (7)

[Claims] 1. A ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film and an upper electrode, wherein: a) one of the electrodes is plated via a transistor formed in a substrate shape; A unit memory cell is formed by the transistor and the ferroelectric capacitor element connected to the bit line and the other electrode is connected to the bit line. B) The unit memory cells connected to adjacent word lines are: C) Unit memory cells connected to the same word line, not connected to the same plate line or bit line, use every other plate line or bit line, and d) connected to the same word line. Are connected to different plate lines and bit lines, respectively, and e) the different unit memory cells connected to the same plate line are all the same. Tsu is connected to preparative line, a ferroelectric memory, characterized in that. 2. A ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film and an upper electrode, wherein: a) one of the electrodes is plated via a transistor formed in a substrate shape; A unit memory cell is composed of the transistor and the ferroelectric capacitor element connected to the bit line and the other electrode connected to the bit line, and b ′) the unit memory cells connected to adjacent word lines are C ') The unit memory cells connected to the same word line use every other bit line, and d') are connected to the same word line. The different unit memory cells are connected to different bit lines and the same plate line, respectively. 3. A ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film, and an upper electrode, wherein: a) one of the electrodes is plated via a transistor formed in a substrate shape; A unit memory cell is composed of the transistor and the ferroelectric capacitor element connected to the bit line and the other electrode connected to the bit line, and b ′) the unit memory cells connected to adjacent word lines are C ') The unit memory cells connected to the same word line use every other bit line, and d ") are connected to the same word line. The different unit memory cells are respectively connected to different bit lines, and f) All the unit memory cells are connected to a common plate line. 4. A ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film, and an upper electrode, wherein: A unit memory cell is composed of the transistor and the ferroelectric capacitor element, the other electrode being connected to the bit line and the other electrode being connected to the bit line, and b ″) being connected to the adjacent word line and the adjacent bit line, respectively. C) the unit memory cells connected to the same word line, c) the unit memory cells connected to the same word line use every other plate line and bit line, and d) Different unit memory cells connected to the same word line are connected to different plate lines and bit lines, respectively. . 5. A ferroelectric memory having a ferroelectric capacitor composed of a laminated film of a lower electrode, a ferroelectric film, and an upper electrode, wherein: a) one of the electrodes is plated via a transistor formed in a substrate shape; A unit memory cell is composed of the transistor and the ferroelectric capacitor element, the other electrode being connected to the bit line and the other electrode being connected to the bit line, and b ″) being connected to the adjacent word line and the adjacent bit line, respectively. C ′) The unit memory cells connected to the same word line use every other bit line, and d ′. A) different unit memory cells connected to the same word line are connected to different bit lines and the same plate line, respectively; 6. A ferroelectric memory having a ferroelectric capacitor comprising a laminated film of a lower electrode, a ferroelectric film and an upper electrode, wherein: a) one of the electrodes is plate-connected via a transistor formed in a substrate shape; A unit memory cell is composed of the transistor and the ferroelectric capacitor element, the other electrode being connected to the bit line and the other electrode being connected to the bit line, and b ″) being connected to the adjacent word line and the adjacent bit line, respectively. C ′) that the unit memory cells connected to the same word line use every other bit line, and that the unit memory cells connected to the same word line use every other bit line. Characteristic ferroelectric memory. 7. The ferroelectric memory according to claim 1, wherein platinum or a laminated film of platinum and titanium is used as a bit line material, and tungsten silicide is used as a plate line material.