JPH10302477A - Boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a boosting circuit capable of performing a control so that an internal voltage does not excessively rise at the time of testing the accelerated-deterioration of a semiconductor memory or the like. SOLUTION: When a clock signal CLK is applied to this circuit, a boosted pulse OUT2 higher than a power source voltage VCC is outputted from a boosted pulse generation control part 10 and it is held at the capacitor 22 connected to the output side of an inverter 21 to be applied to memory cells or the like as a boosted internal voltage VBO. When the VBO is not higher than a fixed value, a control signal BI to be outputted from a control signal generating part becomes 'L' and the capacitor 25 at the output side of a NOR 24 is connected to the capacitor 24 in parallel and the internal voltage VBO which is boosted more high is obtained. When the VBO exceeds the fixed value, the control signal BI becomes 'H' and a boosting action by the capacitor 25 is extinguished and the excessive rising of the internal voltage VBO is limited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosting circuit for generating an internal voltage higher than a power supply voltage in an electronic device such as a semiconductor memory, and more particularly, to an acceleration circuit which applies a power supply voltage higher than that in a normal operation. The present invention relates to a booster circuit capable of controlling the value of the internal voltage during a deterioration test.

[0002]

2. Description of the Related Art In an electronic device such as a semiconductor memory, a booster circuit for generating an internal voltage higher than a power supply voltage for a part of circuits requiring a higher voltage than an externally applied power supply voltage. May be incorporated. FIG. 2 is a circuit diagram showing an example of a booster circuit incorporated in a conventional semiconductor memory. This booster circuit includes a booster pulse generation controller 10. The boost pulse generation control unit 10 includes inverters 11 to 14 cascaded in four stages, and an input signal (for example, a 1 MHz clock signal) CLK is supplied to the input side of the first stage inverter 11. It has become. One end of a capacitor 15 is connected to the output side of the second-stage inverter 12, and the other end of the capacitor 15 is connected to the node N1. An N-channel MOS transistor (hereinafter, referred to as a node N1)
The drain of “NMOS” 16 and the NMOS 17
Is connected to the gate. The gate and source of the NMOS 16 are connected to the power supply voltage VCC. Also, N
The source of the MOS 17 is connected to the node N2, and the drain is connected to the power supply voltage VCC.

The node N2 and the output side of the inverter 13 are connected via a capacitor 18. The node N2 is further connected to the drain of an NMOS 19. The gate and source of the NMOS 19 are connected to the power supply voltage V
Connected to CC. The output signal OUT1 is output from the output side of the inverter 14 of the boost pulse generation control unit 10, and the output signal OUT2 is output from the node N2. The output signal OUT1 of the boost pulse generation control unit 10 is provided to the input side of the inverter 21. The output signal OUT2 of the boost pulse generation control unit 10 is the capacitance C22
Is provided to one end of a capacitor 22 having The other end of the capacitor 22 is connected to the output side of the inverter 21. Furthermore, one end of the capacitor 22 and the power supply voltage VC
C, cascade-connected NMOSs 23a to 23c
Is connected. Then, the boosted internal voltage VBO is output to one end of the capacitor 22, that is, the output side of the output signal OUT2 of the boost pulse generation control unit 10, and is applied to, for example, a word line in a memory cell of a semiconductor memory. I have.

[0004] The operation of such a booster circuit is as follows. The voltage of the node N1 is set to V
CC-Vt (where Vt is a threshold voltage of the NMOS 16;
(Vt = 0.8 to 1.0 V). Here, when the clock signal CLK becomes level “H”, the inverter 1
2 also becomes “H”, and the coupling of the capacitor 15 causes the node N1 to be boosted by VCC + Vt + α. Due to this boosting action, the voltage of the node N2 becomes NMO
It is charged to VCC through S17. Thereafter, when the clock signal CLK goes to level “L”, the level on the output side of the inverter 12 also goes to “L”, and the NMOS 17 is turned off. Further, after a certain delay time, the inverter 13
Becomes high, the voltage of the node N2 is boosted to VCC + α. Note that the NMOSs 23a to
The overvoltage limiter 23 composed of the internal voltage VB
O is a circuit for preventing abnormally high,
The overvoltage limiting section 23 limits the voltage so that the voltage does not exceed VCC + 3Vt. The voltage of the node N2 boosted in this way, that is, the internal voltage VBO is applied to the word line in the memory cell of the semiconductor memory, and the operation of the semiconductor memory is performed.

[0005]

However, the conventional booster circuit has the following problems. The defect occurrence rate of an electronic device such as a semiconductor memory is large immediately after the start of use, and has a characteristic of decreasing in inverse proportion to the number of years of use.
The accelerated aging test (burn-in test) is a method of selecting electronic devices with initial failures using this characteristic. By applying a high voltage at a high temperature to operate the electronic devices, the device is simulated for a long time. It is a test that creates a state.
For example, while the normal operating conditions are an ambient temperature of 0 to 70 ° C. and a power supply voltage VCC = 3 V, an ambient temperature of 125 ° C. and a power supply voltage VCC = 7 V are applied as test conditions during an accelerated deterioration test. After operating under such test conditions for a predetermined period of time, those that do not cause abnormalities are selected as non-defective products.

However, when an externally applied power supply voltage VCC increases as a test condition during an accelerated deterioration test, an internal voltage VBO generated by a booster circuit incorporated in the electronic device also increases. That is, the internal voltage VBO is boosted by + α with respect to the power supply voltage VCC. The magnitude α of the boosted voltage is
It is determined by the capacitance C22 of No. 2 and the current consumption on the load side, and has a substantially constant value. Therefore, the power supply voltage V
When CC rises, internal voltage VBO also rises accordingly. Therefore, there is a problem that an unnecessarily high internal voltage VBO is generated at the time of the accelerated deterioration test, which causes internal destruction of a gate oxide film or the like. SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, and provides a booster circuit that can control an increase in the internal voltage VBO during, for example, an accelerated deterioration test.

[0007]

In order to solve the above-mentioned problems, a first aspect of the present invention is to periodically set the level to "H".
And a constant power supply voltage, which is alternately switched to "L", and holds the voltage of the input signal at "H",
A boosting pulse generation control unit that superimposes the held voltage on the power supply voltage when the input signal becomes “L” to generate a boosting pulse higher than the power supply voltage; A first capacitor that supplies an internal voltage higher than the power supply voltage regardless of the level of the input signal, and an overvoltage limiting unit that limits the internal voltage from rising to a predetermined value or more with respect to the power supply voltage The following internal voltage control section is provided in the booster circuit having the following. That is, the internal voltage control unit is controlled by a control signal having different first and second levels. When the control signal is at the first level, a second capacitor is connected in parallel with the first capacitor. When the control signal is at the second level, the value of the internal voltage is controlled by disconnecting the second capacitor.

According to a second aspect of the present invention, in a booster circuit having the same boost pulse generation control unit as the first invention, a first capacitor, and an overvoltage limiting unit, the overvoltage control unit is configured as follows. ing. That is, the overvoltage limiter is controlled by a control signal having different first and second levels, and when the control signal is at the first level, the internal voltage is a first voltage based on the power supply voltage. When the control signal is at the second level, the internal voltage is prevented from rising above a second voltage lower than the first voltage with respect to the power supply voltage. It has the function to do. According to a third aspect, in the booster circuit according to the first or second aspect, the level of the power supply voltage or the internal voltage is detected, and the first level is detected when the power supply voltage or the internal voltage is equal to or lower than a specific level. And a control signal generator for outputting the second level control signal when the power supply voltage or the internal voltage exceeds the specific level.

According to a fourth aspect of the present invention, the control signal generation unit according to the third aspect of the invention determines whether or not an external control voltage supplied from outside is higher than a reference voltage. A high-voltage detection unit that outputs a voltage signal, and when the high-voltage signal is given, compares the internal voltage with the external control voltage, and when the internal voltage is equal to or less than the external control voltage, the first voltage. A second level control signal when the internal voltage exceeds the external control voltage, and when the high voltage signal is not supplied, the first level control signal is output. And a voltage comparison unit for outputting a control signal. According to the first aspect, since the booster circuit is configured as described above, the following operation is performed. When the control signal is at the first level, the second capacitor of the internal voltage control unit is connected in parallel to the first capacitor, and these capacitors hold the boosted pulse generated from the boosted pulse generation control unit. You. As a result, an internal voltage higher than the power supply voltage is supplied from these first and second capacitors. On the other hand, when the control signal is at the second level, the second capacitor is not connected, the boost pulse is held only by the first capacitor, and an internal voltage somewhat higher than the power supply voltage is supplied.

According to the second invention, the following operation is performed. The boosting pulse generated from the boosting pulse generator control unit is held by a capacitor, and an internal voltage higher than the power supply voltage is supplied. When the first level control signal is supplied to the overvoltage limiter, the overvoltage limiter limits the internal voltage from rising above the first voltage with respect to the power supply voltage. Further, when the control signal of the second level is applied to the overvoltage limiter, the internal voltage is limited from rising to a second voltage or higher that is lower than the first voltage based on the power supply voltage. According to the third invention, the level of the power supply voltage or the internal voltage is detected in the control signal generation unit, and the control signal of the first or second level is output, and the internal voltage control unit in the first invention, or It is provided to the overvoltage limiter in the second invention. According to the fourth aspect, when the external control voltage supplied from the outside is higher than the reference voltage, the high voltage detection unit outputs a high voltage signal. The high-voltage signal activates the voltage comparison unit, compares the internal voltage with the external control voltage, and outputs a first-level control signal when the internal voltage is equal to or lower than the external control voltage. Is exceeded, a second level control signal is output.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a booster circuit showing a first embodiment of the present invention. Elements in common with the elements in the conventional booster circuit of FIG. Common symbols are assigned. This booster circuit has a booster pulse generation control unit 10 similar to the conventional one, and a NAND gate of a logical OR of two inputs constituting an internal voltage control unit (hereinafter, referred to as an output gate) is provided on the output side of the output signals OUT1 and OUT2. "N
OR) 24 and a capacitor 25, and a control signal generator 3 for generating a control signal BI for controlling the internal voltage.
0 is added. That is, the output signal OU
T1 is provided to the first input side of the NOR 24 together with the inverter 21. One end of a capacitor 25 having a capacitance C25 is connected to the output side of the NOR 24, and the other end of the capacitor 25 is connected to the output side of the output signal OUT2 of the boost pulse generation control unit 10.

The control signal generator 30 has a resistor 31, and one end of the resistor 31 is supplied with the internal voltage VBO. The other end of the resistor 31 is connected to one end of a constant current source 32 and the gate of the NMOS 33. Constant current source 3
The other end of 2 and the source of NMOS 33 are connected to ground potential GND. The power supply voltage VCC is applied to the drain of the NMOS 33 via the constant current source 34.
The inverter 35 is connected to the drain of the NMOS 33.
The control signal BI is output to the output side of the inverter 35 and supplied to the second input side of the NOR 24. Other configurations are the same as those of the booster circuit of FIG. In the booster circuit having such a configuration, the boosting pulse generation controller 10 operates in the same manner as the operation of the conventional booster circuit in FIG. The following operation is performed in the control signal generation unit 30.

The power supply voltage VCC is supplied to the drain of the NMOS 33 via the constant current source 34. Since the internal voltage VBO output from the boost pulse generation control unit 10 is connected to the ground potential GND via the resistor 31 and the constant current source 32, the gate of the NMOS 33 has a voltage proportional to the internal voltage VBO. Is applied. For this reason,
When the internal voltage VBO is lower than a certain value, the NMOS 33
Is turned off, and the level on the input side of the inverter 35 becomes "H". On the other hand, when the internal voltage VBO exceeds a certain value, the NMOS 33 is turned on and the inverter 3
5 becomes "L". Therefore, inverter 3
5 is "L" when the internal voltage VBO is lower than a predetermined value, and "H" when the internal voltage VBO exceeds the predetermined value.
Becomes The circuit constant of the booster circuit changes as follows according to the control signal BI. During a normal operation, the power supply voltage VCC has a normal value, so that the internal voltage VBO is equal to or lower than a fixed value, and the control signal BI is “L”. Thus, the output signal OUT1 of the boost pulse generation control unit 10
Is inverted through an inverter 21 and a NOR 24 and supplied to capacitors 22 and 25, respectively. As a result, a boosting operation according to the combined capacitance C22 + C25 of the capacitors 22 and 25 is performed.

On the other hand, during the accelerated deterioration test, the power supply voltage VC
Since C is set high, the internal voltage VBO rises above a certain value with the operation of the booster circuit, and the control signal BI becomes “H”.
become. As a result, the output signal of the NOR 24 is fixed at “L”, and the output signal OUT of the boost pulse generation control unit 10 is output.
1 is inverted by only the inverter 21 and supplied to the capacitor 22. Thus, a boosting operation according to the capacitance C22 of the capacitor 22 is performed. That is, the increase in the internal voltage VBO during the accelerated deterioration test is smaller than that during the normal operation. As described above, the booster circuit according to the first embodiment includes the control voltage generator 30 that generates the control signal BI according to the value of the internal voltage VBO, and the internal voltage VBO supply whose operation is controlled by the control signal BI. And a capacitor 25. Thereby, the capacitor 22,
By setting the capacitances C22 and C25 to appropriate values, and performing a boosting operation with a small capacitance (C22) during the accelerated deterioration test, the internal voltage V such that internal breakdown does not occur.
BO is generated and a large capacitance (C22 +
By performing the step-up operation at C25), a necessary internal voltage VBO can be obtained.

Second Embodiment FIG. 3 is a circuit diagram of a booster circuit according to a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. This booster circuit uses a P-channel M instead of NOR 24 and capacitor 25 in the booster circuit of FIG.
In this configuration, a series circuit including an OS transistor (hereinafter referred to as “PMOS”) 26 and a capacitor 27 having a capacitance C27 is connected in parallel with the capacitor 22. The control signal BI similar to that of FIG. 1 is supplied to the gate of the PMOS 26. Other configurations are the same as those of the booster circuit of FIG. The operation of the booster circuit having such a configuration is substantially the same as the operation of the booster circuit of FIG. However, the circuit constant changes as follows according to the control signal BI.

In a normal operation, since the control signal BI is "L", the PMOS 26 is turned on and the capacitor 27 is connected in parallel with the capacitor 22. Thereby, the combined capacitance C22 + C2 of the capacitors 22 and 27
The boosting operation according to 7 is performed. On the other hand, at the time of the accelerated deterioration test, since the control signal BI becomes “H”, the PMOS 26
Is turned off, and the capacitor 27 is disconnected. Thus, a boosting operation according to the capacitance C22 of the capacitor 22 is performed. Thus, the booster circuit of the second embodiment has the same advantages as the booster circuit of the first embodiment.

Third Embodiment FIG. 4 is a circuit diagram of a booster circuit according to a third embodiment of the present invention. In FIG. 4, components common to those in FIG. 1 are denoted by common reference numerals. This booster circuit includes a NOR 24a having the same configuration and a capacitor 25a having a capacitance C25a in parallel with the NOR 24 and the capacitor 25 in the booster circuit of FIG.
And the capacitor 25 of the NOR 24b and the capacitance C25b
b is connected. And these NO
An output signal OUT1 from the boost pulse generation control unit 10 is provided to a first input side of R24a, 24b. On the other hand, the control voltage BI is applied to the second input sides of the NORs 24a and 24b via the short-circuit fuses 28a and 28b. Further, cutting fuses 29a and 29b are connected between the second input sides of the NORs 24a and 24b and the ground potential GND, respectively. Other configurations are the same as those in FIG.

The operation of the booster circuit having such a configuration is described with reference to FIG.
Is substantially the same as the operation of the booster circuit of FIG. However, the control signal B
During normal operation in which I is “L”, capacitors 25, 25 a and 25 b are connected in parallel to capacitor 22,
Combined capacitance C2 of capacitors 22, 25, 25a, 25b
The only difference is that the boosting operation according to 2 + C25 + C25a + C25b is performed. As described above, the booster circuit according to the third embodiment includes the NOR 24a, the capacitor 25a, and the NO, which can be connected or disconnected by the short-circuit fuses 28a and 28b and the disconnection fuses 29a and 29b.
R24b and capacitor 25b are provided. Thus, in the process of manufacturing the semiconductor device, a proper value capacitor (for example, the capacitor 25a) is connected to the short-circuit fuse 28a and the cut fuse 29a during a probing test in which the integrated circuit on the semiconductor wafer is checked using a probe.
Can be left by short-circuiting and cutting with a laser beam or the like, and unnecessary capacitors (for example, the capacitor 25b) can be separated. Therefore, the capacitors 25, 25a and the like can be selected and connected in parallel so as to have an optimum capacitance, and an appropriate internal voltage VBO can be generated.

Fourth Embodiment FIG. 5 is a circuit diagram of a booster circuit showing a fourth embodiment of the present invention. Elements common to the conventional elements in FIG. 2 are denoted by the same reference numerals. I have. This booster circuit is different from the overvoltage control section 23 of FIG.
3A is provided. That is, in the overvoltage control unit 23A, a PMOS 23d is provided instead of the NMOS 23c in the overvoltage control unit 23 in FIG. And the control voltage BI
Is applied to the gate of the PMOS 23d. The operation of the boost pulse generation control section 10 in the booster circuit having such a configuration is the same as the operation of the conventional booster circuit of FIG. However, in the overvoltage control unit 23A, during the normal operation in which the control signal BI is “L”, the PMOS 2
3d is turned on, and the internal voltage VBO becomes VCC + 3V
The voltage is limited so as not to exceed t. On the other hand, during the accelerated deterioration test in which the control signal BI becomes “H”, the PMOS
23d is in a through state, and the limit voltage of the internal voltage VBO is VCC + 2Vt. Therefore, the rise of the internal voltage VBO at the time of the accelerated deterioration test is limited by the overvoltage control unit 23A, and the internal voltage VBO that does not cause internal breakdown is generated.
Can be generated.

Fifth Embodiment FIG. 6 is a circuit diagram of a control signal generator according to a fifth embodiment of the present invention. The control signal generator 30A is used, for example, in place of the control signal generator 30 of FIG. 1 and includes a high voltage detector 40 and a voltage comparator 50. The high voltage detection unit 40 detects the level of the external control voltage REF supplied from outside, and outputs a high voltage signal HV when the level is higher than a reference voltage. The external control voltage REF is connected to the three cascaded NMOSs 41a,
It is given to the drain of the NMOS 41a at the head of 41b and 41c. The gates and sources of the NMOSs 41a to 41c are connected, and the source of the last NMOS 41c is commonly connected to the drain of the NMOS 42 and the gates of the PMOS 43 and the NMOS 44 which are connected complementarily. The source of the NMOS 42 is connected to the ground potential GN.
D, the gate is connected to the source of the PMOS 43 and the drain of the NMOS 44, respectively. Also, PMOS
The drain of 43 is connected to the power supply potential VCC, and the source of the NMOS 44 is connected to the ground potential GND. The input side of the inverter 45 is connected to the drain of the NMOS 44, and a high voltage signal HV is output from the output side of the inverter 45.

The voltage comparing section 50 compares the external control voltage REF with the internal voltage VBO when the high voltage signal HV is applied, and has an NMOS 51 to which the high voltage signal HV is applied. . The source of the NMOS 51 is connected to the ground potential GND, and the drain is
Commonly connected to 53 sources. The drain of the NMOS 52 is connected to the source of the PMOS 54 and the gate of the PMOS 55. On the other hand, the drain of the NMOS 53 is connected to the source of the PMOS 55 and the gate of the PMOS 54. The drains of the PMOSs 54 and 55 are each connected to the power supply voltage VCC. NMOS 52
The external control voltage REF is connected to the resistors 56a, 5
The internal voltage VBO is applied to the gate of the NMOS 53 by being divided by the resistors 57a and 57b. The input side of the inverter 58 is connected to the drain of the NMOS 53, and the control signal BI is output to the output side of the inverter 58.

In such a control signal generation unit 30A, the level of the external control voltage REF is shifted by a fixed voltage by the NMOSs 41a to 41c of the high voltage detection unit 40, and the level of the external control voltage REF is shifted to the gates of the PMOS 43 and NMOS 44 which are connected complementarily. Given. Therefore, if the external control voltage REF is high, the NMOS 44 is turned on, and the high voltage signal HV on the output side of the inverter 45 becomes “H”. Also,
If the external control voltage REF is low, the PMOS 43 is turned on, and the high voltage signal HV becomes “L”. When the high voltage signal HV becomes “H”, the NMOS 51 of the voltage comparison unit 50
Is turned on, and the comparison circuit composed of the NMOSs 52 and 53 operates. Thereby, the external control voltage REF
Is compared with the internal voltage VBO, and if the external control voltage RBO
If EF is higher, the control signal BI on the output side of the inverter 58 becomes "L". If the internal voltage VBO is higher, the control signal BI becomes "H". On the other hand, when the high voltage signal HV is “L”, the NMOS 5 of the voltage comparison unit 50
1 is turned off, and the comparison circuit constituted by the NMOSs 52 and 53 does not operate. Therefore, the control signal BI on the output side of the inverter 58 becomes “L” regardless of the value of the internal voltage VBO.

As described above, the control signal generator 30A of the fifth embodiment includes a high voltage detector 40 for detecting whether the value of the external control voltage REF is higher than the reference voltage, Only when the value of REF is large, there is provided a voltage comparison unit 50 that compares the external control voltage REF with the internal voltage VBO and outputs the comparison result as a control signal BI. For this reason, since the internal voltage VBO can be controlled by the external control voltage REF provided by the analog voltage, there is an advantage that the rise of the internal voltage VBO can be accurately limited. Note that the present invention is not limited to the above embodiment, and various modifications are possible. As a variation of this,
For example, there are the following (a) to (g).

(A) The booster circuit shown in FIG. 1 and the like has been described as generating an internal voltage of a semiconductor memory. However, the present invention is not limited to the semiconductor memory, and is applicable to booster circuits in various semiconductor devices where an accelerated deterioration test is performed. can do. (B) The booster circuit of FIG. 1 has the control signal generator 30 that detects the increase in the internal voltage VBO during the accelerated deterioration test and generates the control signal BI. BI may be given. (C) In the control signal generator 30 of FIG. 1, the power supply voltage VC
Although the control signal BI is generated by C and the internal voltage VBO, the control signal BI may be generated by applying the power supply voltage VCC to the resistor 31 and detecting only the value of the power supply voltage VCC. (D) In addition to the NOR 24 and the capacitor 25, the NOR circuit 24a and the capacitor 25a
Although it has the OR 24b and the capacitor 25b, a plurality of NORs 24i (i = c, d,...) And the capacitor 25i may be further provided. This makes it possible to obtain a more appropriately adjusted internal voltage VBO.

(E) Capacitors 15, 18, 22, 2
5 has been described as a normal capacitor, for example,
The drain and source of the NMOS can be commonly connected, and the gate capacitance between the gate and the gate can be used as the capacitance. Thereby, for example, the capacitor 15 and the like can be easily formed on the silicon substrate. (F) The overvoltage control unit 23A in FIG. 5 may be used in place of the overvoltage control unit 23 in the booster circuits in FIGS. This makes it possible to reliably prevent the internal voltage VBO from unnecessarily increasing. (G) The control signal generation unit 30A in FIG. 6 can be used as a control signal BI generation circuit in the booster circuits in FIGS. 3 to 5 as well as in FIG.

[0026]

As described above in detail, according to the first aspect, the internal voltage control unit for controlling the value of the internal voltage according to the level of the control signal is provided. Thus, the required internal voltage can be obtained by setting the control signal to the first level at the time of the normal power supply voltage. On the other hand, for example, when the control signal is set to the second level during the accelerated deterioration test, even if a power supply voltage higher than normal is applied,
Since the rise in the internal voltage is suppressed, it is possible to prevent the occurrence of internal dielectric breakdown and the like. According to the second invention,
The limit voltage in the overvoltage control unit can be controlled by the level of the control signal. For this reason, at the time of a normal power supply voltage, the control signal is set to the first level to increase to a required internal voltage, and at the time of an accelerated deterioration test, the control signal is set to the second level, By limiting the rise of the internal voltage to a lower level, it is possible to prevent the occurrence of internal dielectric breakdown and the like.

According to the third aspect of the present invention, since the control signal generator for detecting the level of the power supply voltage or the internal voltage and outputting the control signal is provided, the first signal can be obtained without requiring an external signal.
Alternatively, the same effect as the second invention can be obtained. According to the fourth aspect, the high voltage detection unit that determines the external control voltage supplied from the outside and outputs a high voltage signal, and compares the internal voltage and the external control voltage when the high voltage signal is supplied. And a voltage comparator for controlling the level of the control signal.
As a result, the internal voltage limit value can be given by the external control voltage based on the actual analog voltage, and the rise of the internal voltage can be accurately limited.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional booster circuit.

FIG. 3 is a circuit diagram of a booster circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a booster circuit showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a booster circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a control signal generator according to a fifth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Boost pulse generation control part 22, 25, 25a Capacitor 24 NOR 26 PMOS 23 Overvoltage control part 30 Control signal generation part 40 High voltage detection part 50 Voltage comparison part

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H02M 3/07 G11C 11/34 371A (72) Inventor Kenji Sato 9-2 Yamato-cho, Miyazaki-shi, Miyazaki Miyazaki Oki Microdesign Miyazaki (72) Inventor Yasushi Kai, 9-2 Yamatocho, Miyazaki City, Miyazaki Prefecture Oki Micro Design Miyazakinai

Claims (4)

[Claims] An input signal and a constant power supply voltage which are alternately switched to a high level and a low level periodically are provided,
Step-up pulse generation for holding a high-level voltage of the input signal, superimposing the held voltage on the power supply voltage when the input signal goes low, and generating a booster pulse higher than the power supply voltage A control unit; a first capacitor that holds the boost pulse and supplies an internal voltage higher than the power supply voltage regardless of the level of the input signal; A booster circuit having an overvoltage limiter that limits the rise of the voltage, is controlled by control signals having different first and second levels, and when the control signal is at the first level, the first Connecting a second capacitor in parallel with the capacitor,
A booster circuit provided with an internal voltage controller for controlling the value of the internal voltage by disconnecting the second capacitor when the control signal is at the second level; 2. An input signal and a constant power supply voltage which are alternately switched to a high level and a low level periodically are provided,
Step-up pulse generation for holding a high-level voltage of the input signal, superimposing the held voltage on the power supply voltage when the input signal goes low, and generating a booster pulse higher than the power supply voltage A control unit that holds the boost pulse and supplies an internal voltage higher than the power supply voltage regardless of the level of the input signal; and that the internal voltage rises to a predetermined value or more with respect to the power supply voltage. An overvoltage limiting section for limiting the operation of the boosting circuit, wherein the overvoltage limiting section is controlled by a control signal having different first and second levels, and when the control signal is at the first level, Limiting that the internal voltage rises above a first voltage with respect to the power supply voltage, wherein when the control signal is at the second level, the internal voltage is based on the power supply voltage; Booster circuit and limits that rises above a second voltage lower than the first voltage Te. 3. The booster circuit according to claim 1, wherein the level of the power supply voltage or the internal voltage is detected, and the control of the first level is performed when the power supply voltage or the internal voltage is lower than a specific level. A control signal generating unit that outputs a control signal of the second level when the power supply voltage or the internal voltage exceeds the specific level.
A booster circuit characterized by being provided. 4. A high-voltage detection unit that determines whether an external control voltage supplied from outside is higher than a reference voltage and outputs a high-voltage signal when the external control voltage is higher than the reference voltage. And when the high voltage signal is supplied, compares the internal voltage with the external control voltage, and outputs the first level control signal when the internal voltage is equal to or less than the external control voltage, A voltage comparing unit that outputs the second level control signal when the internal voltage exceeds the external control voltage, and outputs the first level control signal when the high voltage signal is not applied; 4. The method according to claim 3, wherein
The booster circuit as described.