JPH10301658A - Computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower power by monitoring the change of address data on an address bus, detecting an idle state where an instruction is not executed and stopping the generation of the clock signals of a signal generation means. SOLUTION: A PLL 3 stops the generation of the clock signals CKB when control signals are '0' for instance and an interruption control part 4 outputs detection signals K1 to an AND circuit 10 by the value of '0' when interruption signals STOPCLK# for requesting the stoppage of the generation of the clock signals CKB of the PLL 3 are inputted. An idle detector 8 detects the case that the change of the address data of the address bus AB is turned to a certain fixed pattern timewise as the idle state of a CPU 1 and outputs the detection signals K2 to the AND circuit 10 by the value of '0'. The AND circuit 10 outputs '0' to the PLL 3 in the case that '0' is inputted from one of the interruption control circuit 4 and an address detection circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CPU (Central Processing) capable of driving with low power consumption.
Unit: central processing unit).

[0002]

2. Description of the Related Art A configuration for reducing power consumption of a conventional CPU will be described with reference to FIG. , FIG. 3 shows “Pentium, published by Intel Japan Co., Ltd., 1994.
^TM Family User's Manual (first volume), 305P
-311P "is a block diagram of clock control of the CPU shown in FIG.

In FIG. 1, reference numeral 1 denotes a CPU. Reference numeral 2 denotes a CPU core unit, which is a basic unit for interpreting and executing instructions in the CPU 1. 3 is a PLL (phase
And converts the frequency of the clock signal CKA input from outside of the CPU 1 into a clock signal CKB having a frequency of, for example, 1.5 times or 2 times the frequency of the clock signal CKB.
Output to the core unit 2. Reference numeral 4 denotes an interrupt control unit that controls an input interrupt signal.

Next, the operation of the above-described conventional example will be described with reference to FIG. FIG. 1 shows an example of a block diagram of clock control of a conventional CPU. The CPU core unit 2 operates at a frequency 1.5 times or twice the frequency of the data bus DB, which is a collection of external data signals, and the address bus AB, which is a collection of address signals. The frequency of the 1.5 times or 2 times clock signal CKB is generated by the PLL 3 based on an external clock signal CKA.

When the interrupt signal STOPCLK # is input, the interrupt control unit 4 controls the PLL 3
The internal clock 5B for the CPU core unit 2 is stopped. Thereby, the CPU 1 can control the power consumption in the CPU core unit 2. That is, CPUl
Indicates that the interrupt control unit 4 outputs the interrupt signal STOPCLK #
Is detected, execution of the instruction is stopped at the next instruction boundary, and P
The output of the clock signal CKB from LL3 is stopped.

When the interrupt control unit 4 detects the release of the interrupt signal STOPCLK #, the CPU 1 executes the instruction following the interrupted instruction.
The output of the clock signal CKB of LL3 is restarted, and the process returns to the normal processing operation. As described above, in the conventional CPU 1 system, the interrupt signal STOPCLK # is externally generated by an external circuit for controlling power consumption.

Usually, a computer system is designed to perform a series of operations for some input. When there is no input for a work request, the computer system is set to an idle state and "do nothing". It is in a state.

[0008]

However, even in the idle state as described above, the CPU cannot be controlled by an external circuit.
The clock signal CKB is always output from the PLL 3 to the CPU core unit 2 unless the interrupt signal STOPCLK # is input to the CPU core unit 1. For this reason, since the same power is consumed as when the CPU 1 itself performs some processing operation, it is difficult to realize sufficiently low power consumption.

The present invention has been made under such a background, and provides a computer capable of realizing low power consumption by detecting an idle state of a CPU, stopping a clock signal to a CPU core unit. Is to do.

[0010]

According to the first aspect of the present invention,
In the computer, monitoring means for monitoring a change in address data on an address bus for transferring address data in a central processing unit of the computer, and outputting a monitoring signal based on the monitoring result; Idle detection means for detecting the state, and outputting a detection signal based on the detection result;
Signal generating means for generating a clock signal for operating the central processing unit; and stopping means for stopping the generation of the clock signal by the signal generating means. From the generation of the clock signal.

According to a second aspect of the present invention, in the computer according to the first aspect, the computer further comprises interrupt control means for controlling an interrupt signal, wherein the interrupt control means requests the central processing unit to stop a clock signal. When a signal is input, a control signal is output to the stopping means, and the generation of the clock signal from the signal generating means is stopped.

According to a third aspect of the present invention, in the computer according to the first or second aspect, an AND circuit is provided. The AND circuit receives the detection signal and the control signal, and outputs the detection signal and the control signal. An AND operation with the control signal is performed, and as a result of the AND operation, a stop signal is output to the stop unit.

According to a fourth aspect of the present invention, in the computer according to the first or second aspect, an OR circuit is provided. The OR circuit receives the detection signal and the control signal, and outputs the detection signal and the control signal. An OR operation with the control signal is performed, and a stop signal is output to the stop unit as an OR result. .

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a computer according to an embodiment of the present invention. In this figure, 1 is a CPU. Reference numeral 2 denotes a CPU core unit, which is a basic unit for interpreting and executing instructions in the CPU 1. Reference numeral 3 denotes a PLL, which changes the frequency of the clock signal CKA input from outside the CPU 1 to, for example, 1.5.
The clock signal CKB is converted into a double or double frequency clock signal and output to the CPU core unit 2.

When the control signal S is, for example, "0", the PLL 3 stops generating the clock signal CKB.
Reference numeral 4 denotes an interrupt control unit that controls an input interrupt signal. Further, when an interrupt signal STOPCLK # requesting stop of generation of the clock signal CKB of the PLL 3 is input, the interrupt control unit 4 outputs the detection signal K1 to the AND circuit 10 with a value of “0”. Reference numeral 8 denotes an idle detection device that monitors a change in data on the address bus AD of the CPU 1.

That is, the idle detecting device 8 has a CPU
Since only the instruction loop is executed when 1 is in the idle state, the idle state is detected using the characteristic that the temporal change of the same address data is repeated on the address bus AB in a certain cycle. That is, the idle detection device 8 detects, as an idle state, a case where a change in address data on the address bus AB has a certain pattern with respect to time, and outputs the detection signal K2 to the AND circuit 10 with a value of “0”. Output.

When “0” is input from either the interrupt control circuit 4 or the address detection circuit 8, the AND circuit 10 outputs “0” to the PLL 3.

Next, the operation of the above-described embodiment will be described with reference to FIGS. FIG. 2 is a stop clock state transition diagram regarding generation of the clock signal CKB in the CPU 1.

In state S1 (normal state), CP
U1 performs a normal instruction processing operation. Here, if the interrupt signal STOPCLK # is input to the interrupt control unit 4, or if the address detection device 8 detects the idle state of the CPU 1 from the change pattern of the address data of the address bus AD, the CPU 1 proceeds to the state S2. Transition state.

Next, in the state 2 (clock stop permission state), the CPU 1 performs write-back of the internal cache memory in order to maintain consistency of the internal cache memory of the high-speed memory mounted inside the CPU with the external memory. , An external address strobe signal EADS # signal is detected.

That is, the CPU 1 does not access the memory in the idle state, but another device sharing the address bus AB and the data bus DB may access the external memory. . And
When detecting the external address strobe signal EADS # signal, the CPU 1 shifts the processing to the state S3.

When the CPU 1 does not detect the external address strobe signal EADS # signal, the CPU 1 sets the processing to the state S.
Move to 4. Here, assuming that CPU 1 detects external address strobe signal EADS # signal, CPU 1 shifts the processing to state S3.

Next, in the state S3 (clock stop snoop state), the CPU 1 executes a cache snoop cycle in which the contents of the internal cache memory whose address matches the external memory are rewritten according to the contents of the external memory. Then, when the cache snoop cycle ends, the CPU 1 shifts the processing to the state S2.

Next, in the state S2, the CPU 1 shifts the processing to the state S4 because the consistency of the internal cache memory with the external memory is ensured.

Next, state S4 (clock stop state)
When the CPU 1 receives an interrupt signal, the interrupt controller 4 sets the detection signal K1 to "0", and the address detection device 8 changes the idle state of the CPU 1 from the change pattern of the address data on the address bus AD. Upon detection, the detection signal K2 is set to “0”.

As a result, the AND circuit 10 outputs the control signal S to the PLL 3 as "0". As a result, PL
L3 stops generating the clock signal CKB. As a result, the CPU core unit 2 receives the clock signal C of the driving clock.
The operation stops when KB is not input.

The return to the normal processing is performed when the stopped condition is released. That is, when the PLL 3 is stopped by the request of the interrupt signal STOPCLK #, the return to the normal processing is performed by the interrupt signal STOPCL #.
The condition is that K # is released.

The idle state is detected by the idle detecting device 8.
And the PLL 3 is stopped, the condition is that the idle detecting device 8 detects the non-idle state from the change pattern of the address bus AB.

When these conditions are satisfied,
The CPU 1 sets the detection signal K1 of the interrupt control unit 4 and the detection signal K2 of the idle detection device 8 to "1",
The generation of the third clock signal CKB is restarted. Thereby, the CPU 1 shifts the processing to the state S5.

Next, in a state S5 (WAIT state), the CPU 1 controls the clock signal C generated by the PLL3.
Until the KB transmission frequency is stabilized, a predetermined period of time is set to a wait state (WAIT state), and actual processing is not resumed. Then, after a predetermined time has elapsed, the CPU 1
The process proceeds to a state S1 in which a normal operation is performed.

As mentioned above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change and the like within a range not departing from the gist of the present invention. The present invention is also included in the present invention. For example, when the interrupt signal STOPCLK # is input, the interrupt control circuit 4 outputs the output signal K1 as “1”. Also,
When the idle detection device 8 detects the idle state,
The detection signal K2 is output as "1". And PLL3 is
When the control signal S becomes “1”, the clock signal CKB
Stop output of In the case of each signal state described above, an OR circuit can be used instead of the AND circuit 10.

[0032]

According to the first aspect of the present invention, a computer monitors a change in address data on an address bus for transferring address data in a central processing unit of the computer, and outputs a monitoring signal based on the monitoring result. Monitoring means, idle detection means for detecting an idle state in which no instruction is executed from the monitoring signal, and outputting a detection signal based on the detection result; and a signal for generating a clock signal for operating the central processing unit. Generating means; and stopping means for stopping the generation of the clock signal by the signal generating means. The stopping means stops the generation of the clock signal from the signal generating means by the detection signal. If you are idle, the computer can detect your idle state By stopping the clock signal for driving at body no longer perform unnecessary operation the central processing unit, there is an effect that it is possible to achieve low power consumption.

According to the second aspect of the present invention, there is provided an interrupt control means for controlling an interrupt signal, wherein the interrupt control means receives an interrupt signal for requesting the central processing unit to stop a clock signal. If
Since the generation of the clock signal from the signal generation unit is stopped, the clock signal for driving the central processing unit can be stopped by an external interrupt signal as in the related art.

Further, according to the third aspect of the present invention, an AND circuit is provided, and the AND circuit receives the detection signal and the control signal, and performs an AND operation on the detection signal and the control signal. Since a stop signal is output to the stop means as an AND result, the clock signal for driving the central processing unit can be stopped when either the detection signal or the control signal is input.

According to a fourth aspect of the present invention, there is provided an OR circuit. The OR circuit receives the detection signal and the control signal, and ORs the detection signal and the control signal. Since a stop signal is output to the stop means as an OR result, when one of the detection signal and the control signal is input, the clock signal for driving the central processing unit can be stopped.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a stop clock state transition of a computer according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a computer according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 CPU core part 3 PLL 4 Interrupt control part 8 Idle detection device 10 AND circuit

Claims (4)

[Claims] 1. A monitoring means for monitoring a change in address data on an address bus for transferring address data in a central processing unit of a computer and outputting a monitoring signal according to the monitoring result, and an instruction is executed from the monitoring signal. Idle detection means for detecting that there is no idle state, and outputting a detection signal based on the detection result; signal generation means for generating a clock signal for operating the central processing unit; and And a stop means for stopping generation of the clock signal, wherein the stop means stops generation of the clock signal from the signal generation means in response to the detection signal. 2. An interrupt control means for controlling an interrupt signal, wherein the interrupt control means sends a control signal to the stop means when an interrupt signal for requesting the central processing unit to stop a clock signal is input. Output,
2. The computer according to claim 1, wherein generation of said clock signal from said signal generation means is stopped. 3. An AND circuit, to which the detection signal and the control signal are inputted, which ANDs the detection signal and the control signal, and outputs a stop signal as an AND result to the stop means. The computer according to claim 1, wherein the output is performed to a computer. 4. An OR circuit, to which the detection signal and the control signal are inputted, which ORs the detection signal and the control signal, and outputs a stop signal as an OR result to the stop means. 2. An output to a computer.
Or the computer according to claim 2.