JPH10300825A - Defect inspection device for circuit pattern of substrate - Google Patents

Defect inspection device for circuit pattern of substrate

Info

Publication number
JPH10300825A
JPH10300825A JP9105701A JP10570197A JPH10300825A JP H10300825 A JPH10300825 A JP H10300825A JP 9105701 A JP9105701 A JP 9105701A JP 10570197 A JP10570197 A JP 10570197A JP H10300825 A JPH10300825 A JP H10300825A
Authority
JP
Japan
Prior art keywords
sample stage
wafer
substrate
image
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9105701A
Other languages
Japanese (ja)
Inventor
Kazuhito Shigihara
和仁 鴫原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9105701A priority Critical patent/JPH10300825A/en
Publication of JPH10300825A publication Critical patent/JPH10300825A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To perform a defect inspection with high precision and high throughput by use of a sample stage less changed in attitude precision, inclination, height or the like with the lapse of time by holding and moving a substrate within vacuum, forming an image by secondary electrons, and automatically inspecting the defect of a circuit pattern by comparison. SOLUTION: When a wafer 14 is placed on a sample stage 5, electron beams are emitted from an electron gun 1 to the wafer 14. The electron beams scan only one dimension, and the sample stage 5 is continuously moved in the direction orthogonal to the scanning direction. In order to obtain the image of the wafer 14, the generated secondary electrons are detected synchronously with the scanning of the electron beam and the movement of the sample stage 5. This signal is transmitted to the image memory 10 of an image processing part 104, and compared with the taken image of the adjacent part one before. The part where a difference is recognized as the comparison result is judged as a defect, and the information such as coordinate is transmitted to a system computer 105.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置特に基板
の検査装置に係わり、基板の回路パターンの欠陥検査装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device for inspecting a substrate, and more particularly to a device for inspecting a circuit pattern on a substrate.

【0002】[0002]

【従来の技術】従来の走査型電子顕微鏡(SEM)は、
非常に限られた視野を高倍率で、たとえば数十μm角の
領域を時間をかけて観察する装置である。また、半導体
検査装置の一つである測長用走査型電子顕微鏡は、ウェ
ハなどの基板上の定められた複数点のみを高倍率で測定
するため、試料ステージはステップアンドリピート方式
を採用し、「静的」な位置決め精度・位置検出精度・姿
勢精度が重要視されていた。
2. Description of the Related Art Conventional scanning electron microscopes (SEMs)
This is an apparatus for observing a very limited visual field at high magnification, for example, an area of several tens of μm square over time. In addition, the scanning electron microscope for length measurement, which is one of the semiconductor inspection devices, measures only a predetermined plurality of points on a substrate such as a wafer at a high magnification, so the sample stage adopts a step-and-repeat method, The importance of "static" positioning accuracy, position detection accuracy, and attitude accuracy was emphasized.

【0003】[0003]

【発明が解決しようとしている課題】上記従来機構で
は、ウェハなどの基板の限られた部分を高倍率で観察す
ることを目的としていたため、試料ステージはステップ
アンドリピート方式を採用していた。一方、本装置はウ
ェハなどの基板のどこに欠陥があるかを探す装置である
から、非常に広い範囲をくまなく検査する必要がある。
この広い範囲の検査を従来のステップアンドリピート方
式で行った場合、試料ステージが目標位置に移動し、振
動が整定するまで検査を中段しなければならず、この中
段時間は本装置のスループットを著しく低下させる。こ
の中段時間を0にし、かつ電子線を二次元走査するのと
同様の画像を形成するために、本装置では電子線は一方
向のみの一次元走査とし、走査方向と直交する方向に試
料ステージを連続移動する方式を採用している。
In the above-mentioned conventional mechanism, the objective is to observe a limited portion of a substrate such as a wafer at a high magnification, so that the sample stage employs a step-and-repeat method. On the other hand, since the present apparatus is an apparatus for searching for a defect on a substrate such as a wafer, it is necessary to inspect a very wide range.
When performing this wide-range inspection by the conventional step-and-repeat method, the sample stage must be moved to the target position and the inspection must be performed in the middle stage until the vibration is settled. Lower. In order to set this middle stage time to 0 and to form an image similar to two-dimensional scanning of the electron beam, the electron beam is one-dimensionally scanned in one direction in this apparatus, and the sample stage is moved in a direction orthogonal to the scanning direction. Is adopted.

【0004】しかしこの方式では試料ステージの連続移
動に速度変動が生じた場合、形成される画像が誤ったも
のとなりこれを前の画像と比較してしまうと正しいパタ
ーンであっても欠陥として認識されてしまうという問題
が発生する。又、摺動材の磨耗が大きい場合、試料ステ
ージの姿勢精度・傾き・高さ(フォーカス)等の経時変
化を招き、修理等のダウンタイムによる装置稼働率の低
下を引き起こすという問題がある。
However, in this method, if the speed of the continuous movement of the sample stage fluctuates, the formed image becomes erroneous, and if this is compared with the previous image, the correct pattern is recognized as a defect. The problem that occurs. In addition, when the sliding material is significantly worn, there is a problem that the posture accuracy, inclination, height (focus), etc. of the sample stage are changed with time, and the operation rate of the apparatus is reduced due to downtime such as repair.

【0005】本発明の目的は、真空中で安定した速度で
連続移動可能であり、かつ姿勢精度・傾き・高さ(フォ
ーカス)等の経時変化の少ない試料ステージにより、高
精度,高スループットである基板の回路パターンの欠陥
検査装置を提供することにある。
An object of the present invention is to achieve high accuracy and high throughput by using a sample stage which can be continuously moved at a stable speed in a vacuum and has little change with time such as posture accuracy, inclination and height (focus). An object of the present invention is to provide a defect inspection device for a circuit pattern on a substrate.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
には、本発明は試料ステージの摩擦抵抗を減らす事が必
要となり、その手段としては、試料ステージそのものの
軽量化と、積極的に外力を加え結果的に摺動面にかかる
荷重を小さくする方法とがある。試料ステージの軽量化
には、形状・材質の変更などが上げられるがこれには剛
性の低下、つまり試料ステージ精度の低下を招くという
弊害があり、大きな効果は期待できない。そこで、本発
明では外力を加える手段を採用し、試料テーブルの中に
重量低減機構を設ける構造とした。
In order to achieve the above object, the present invention requires that the frictional resistance of the sample stage be reduced. To reduce the load applied to the sliding surface as a result. To reduce the weight of the sample stage, a change in shape, material, and the like can be raised. However, this has the adverse effect of lowering the rigidity, that is, lowering the accuracy of the sample stage, and a great effect cannot be expected. Therefore, the present invention adopts a structure in which a means for applying an external force is employed and a weight reduction mechanism is provided in the sample table.

【0007】[0007]

【発明の実施の形態】以下、本発明の一実施例を図面に
従って説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

【0008】(実施例1)図1は本発明の基板の回路パ
ターンの欠陥検査装置の全体構成図である。本装置は大
別して電子光学系101,試料室102,制御部10
3,画像処理部104,システムコンピュータ105より
構成されている。電子光学系101は電子銃1,コンデ
ンサレンズ2,走査偏向器3,対物レンズ4により構成
されている。試料室102は,試料ステージ5,レーザ
測長系6,ウェハ高さ測定器7より構成されている。ま
た二次電子検出器8が対物レンズ4の下方にあり、二次
電子検出器8の出力信号はAD変換器9によりデジタル
データとなり画像処理部104へ送られる。画像処理部
104は画像メモリ10,画像メモリ11と演算部12
より構成されている。検査装置各部の動作命令および動
作条件は、制御部103から入出力される。また、レー
ザ測長系6,ウェハ高さ測定器7の信号から補正信号を
生成し、電子線201が常に正しい位置に照射されるよ
う対物レンズ4や、走査信号発生器13に補正信号を送
る。画像処理部104,制御部103はさらに上位のシ
ステムコンピュータ105により制御されている。
(Embodiment 1) FIG. 1 is an overall configuration diagram of a defect inspection apparatus for a circuit pattern on a substrate according to the present invention. This apparatus is roughly divided into an electron optical system 101, a sample chamber 102, a control unit 10
3, an image processing unit 104 and a system computer 105. The electron optical system 101 includes an electron gun 1, a condenser lens 2, a scanning deflector 3, and an objective lens 4. The sample chamber 102 includes a sample stage 5, a laser measuring system 6, and a wafer height measuring device 7. The secondary electron detector 8 is below the objective lens 4, and the output signal of the secondary electron detector 8 is converted into digital data by the AD converter 9 and sent to the image processing unit 104. The image processing unit 104 includes an image memory 10, an image memory 11, and an arithmetic unit 12.
It is composed of Operation commands and operation conditions of each part of the inspection apparatus are input and output from the control unit 103. Further, a correction signal is generated from the signals of the laser length measuring system 6 and the wafer height measuring device 7 and the correction signal is sent to the objective lens 4 and the scanning signal generator 13 so that the electron beam 201 is always irradiated to a correct position. . The image processing unit 104 and the control unit 103 are controlled by a higher-order system computer 105.

【0009】電子線201の加速は電子銃1に高圧の負
の電位を印加することでなされる。これにより、電子線
201はその電位に相当するエネルギでウェハ14方向
に進み、コンデンサレンズ2で収束され、さらに対物レ
ンズ4により細く絞られ試料ステージ5の上に搭載され
たウェハ14に照射される。ウェハ14を観察するのに
最適な照射電子エネルギは数百eVである。ところが本
装置では電子線電流が大きいため数百eVの低いエネル
ギでは電子同士が反発しあう空間電荷効果により電子線
201を細く絞れない。そこで、電子銃1からウェハ1
4直前までは電子線201を10keVの高いエネルギ
に加速している。このエネルギをウェハ14直前で数百
eVの最適な値に減速するために、ウェハ14には高圧
の負の電圧を印加できるようになっている。
The acceleration of the electron beam 201 is performed by applying a high negative potential to the electron gun 1. As a result, the electron beam 201 advances toward the wafer 14 with energy corresponding to the potential, is converged by the condenser lens 2, is further narrowed down by the objective lens 4, and irradiates the wafer 14 mounted on the sample stage 5. . The optimum irradiation electron energy for observing the wafer 14 is several hundred eV. However, in this apparatus, since the electron beam current is large, the electron beam 201 cannot be narrowed down due to the space charge effect in which electrons repel each other at an energy as low as several hundred eV due to the large electron beam current. Then, from the electron gun 1 to the wafer 1
Until just before 4, the electron beam 201 is accelerated to a high energy of 10 keV. In order to reduce this energy to an optimum value of several hundred eV immediately before the wafer 14, a high negative voltage can be applied to the wafer 14.

【0010】ウェハ14が試料ステージ5に載せられる
と電子銃1からの電子線201がウェハ14に照射され
る。電子線201は一次元のみ走査し、その走査方向と
直行する方向に試料ステージ5を連続的に移動させる方
法を採用している。ウェハ14の画像を取得するために
は、発生した二次電子を検出し、これらを電子線201
の走査および試料ステージ5の移動と同期して検出す
る。この信号を画像処理部104の画像メモリ10に送
り、すでに取り込んである一つ前に取り込んだ隣接部の
画像と比較する。比較した結果差が認められた部分は欠
陥と判断し座標等の情報をシステムコンピュータ105
に送る。比較が終わったら画像メモリ10の画像により
画像メモリ11を更新し、同様のことを繰り返す。
When the wafer 14 is placed on the sample stage 5, an electron beam 201 from the electron gun 1 is irradiated on the wafer 14. The electron beam 201 scans only one dimension, and employs a method of continuously moving the sample stage 5 in a direction perpendicular to the scanning direction. In order to acquire an image of the wafer 14, generated secondary electrons are detected, and these are
In synchronization with the scanning of the sample and the movement of the sample stage 5. This signal is sent to the image memory 10 of the image processing unit 104, and is compared with the image of the adjacent part that has been captured immediately before and has already been captured. The part where a difference is found as a result of the comparison is judged as a defect, and information such as coordinates is transmitted to the system computer 105.
Send to When the comparison is completed, the image memory 11 is updated with the image in the image memory 10, and the same is repeated.

【0011】所定の範囲の検査が終了したら、ウェハ1
4は大気中に送られる。
When the inspection of a predetermined range is completed, the wafer 1
4 is sent to the atmosphere.

【0012】以上に説明した一連の動作によりプロセス
途中の半導体ウェハ14の欠陥を高速に検査することが
できる。
By the above-described series of operations, a defect of the semiconductor wafer 14 during the process can be inspected at high speed.

【0013】図2は重量低減機構21を用いた試料ステ
ージ5の正面図、図3は重量低減機構21を用いた試料
ステージ5の側面図である。試料ステージ5は、テーブ
ル22,テーブル23,テーブル24,ステージ駆動系
25,重量低減機構21,摺動材26によって構成され
ている。テーブル23はステージ駆動系25により連続
的に移動する。この時、テーブル23は摺動材26を介
してテーブル22と接触しており、テーブル23,テー
ブル24,ウェハ14の重量は全て摺動材26での摩擦
抵抗となる。ここで、テーブル22とテーブル23の間
に重量低減機構21を設けることにより、摺動材26で
の重量負担分を軽減できる。摺動抵抗及び摺動材26の
磨耗量は重量に比例しているため、重量低減機構21の
働きによりそれぞれ軽減することができる。重量低減機
構21は、板ばね27とテーブル22上をころがるベア
リング28で構成され、板ばね27はテーブル23が浮
き上がらない適正な重量低減力を発生させる。
FIG. 2 is a front view of the sample stage 5 using the weight reducing mechanism 21, and FIG. 3 is a side view of the sample stage 5 using the weight reducing mechanism 21. The sample stage 5 includes a table 22, a table 23, a table 24, a stage drive system 25, a weight reducing mechanism 21, and a sliding member 26. The table 23 is continuously moved by the stage drive system 25. At this time, the table 23 is in contact with the table 22 via the sliding member 26, and the weights of the table 23, the table 24, and the wafer 14 are all frictional resistance of the sliding member 26. Here, by providing the weight reduction mechanism 21 between the table 22 and the table 23, the weight burden on the sliding member 26 can be reduced. Since the sliding resistance and the amount of wear of the sliding member 26 are proportional to the weight, they can be reduced by the operation of the weight reducing mechanism 21, respectively. The weight reduction mechanism 21 includes a leaf spring 27 and a bearing 28 that rolls on the table 22. The leaf spring 27 generates an appropriate weight reduction force that prevents the table 23 from floating.

【0014】[0014]

【発明の効果】これにより、製造過程で発生した欠陥を
短時間で安定的に発見可能にし、半導体プロセスにフィ
ードバックすることにより半導体装置の不良率を低減
し、信頼性を向上した。
As a result, defects generated in the manufacturing process can be stably found in a short time, and the defect rate of the semiconductor device is reduced by feeding back to the semiconductor process, thereby improving the reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置のブロック図。FIG. 1 is a block diagram of a semiconductor device of the present invention.

【図2】重量低減機構を用いた試料ステージの正面図。FIG. 2 is a front view of a sample stage using a weight reduction mechanism.

【図3】重量低減機構を用いた試料ステージの側面図。FIG. 3 is a side view of a sample stage using a weight reduction mechanism.

【符号の説明】[Explanation of symbols]

1…電子銃、2…コンデンサレンズ、3…走査偏向器、
4…対物レンズ、5…試料ステージ、6…レーザ測長
系、7…ウェハ高さ測定器、8…二次電子検出器、9…
AD変換器、10,11…画像メモリ、12…演算部、
13…走査信号発生器、14…ウェハ、101…電子光
学系、102…試料室、103…制御部、104…画像
処理部、105…システムコンピュータ、201…電子
線。
1. Electron gun, 2. Condenser lens, 3. Scanning deflector,
4 Objective lens 5 Sample stage 6 Laser length measuring system 7 Wafer height measuring device 8 Secondary electron detector 9
AD converters, 10, 11: image memory, 12: operation unit,
13: scanning signal generator, 14: wafer, 101: electron optical system, 102: sample chamber, 103: control unit, 104: image processing unit, 105: system computer, 201: electron beam.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】電子線を基板に照射するための照射手段
と、前記基板から前記電子線照射により励起された二次
電子を検出する検出手段と、前記基板を大気から真空内
に自動的に搬送させる搬送手段と、真空内で前記基板を
保持移動させるとともに重量低減機構が付加された移動
手段と、前記移動手段の座標を検出する座標検出手段
と、前記二次電子により像を形成、比較する像形成手段
と、前記像形成手段における比較から前記基板上に形成
されている回路パターンの欠陥を自動的に検出する欠陥
検出手段からなることを特徴とする基板の回路パターン
の欠陥検査装置。
An irradiating means for irradiating the substrate with an electron beam; a detecting means for detecting secondary electrons excited by the electron beam irradiation from the substrate; and automatically moving the substrate from the atmosphere into a vacuum. Transport means for transporting, a moving means having a weight reduction mechanism while holding and moving the substrate in a vacuum, a coordinate detecting means for detecting the coordinates of the moving means, and forming and comparing an image with the secondary electrons A defect detecting means for automatically detecting a defect of a circuit pattern formed on the substrate based on a comparison between the image forming means and a defect of the circuit pattern formed on the substrate.
JP9105701A 1997-04-23 1997-04-23 Defect inspection device for circuit pattern of substrate Pending JPH10300825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9105701A JPH10300825A (en) 1997-04-23 1997-04-23 Defect inspection device for circuit pattern of substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9105701A JPH10300825A (en) 1997-04-23 1997-04-23 Defect inspection device for circuit pattern of substrate

Publications (1)

Publication Number Publication Date
JPH10300825A true JPH10300825A (en) 1998-11-13

Family

ID=14414679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9105701A Pending JPH10300825A (en) 1997-04-23 1997-04-23 Defect inspection device for circuit pattern of substrate

Country Status (1)

Country Link
JP (1) JPH10300825A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100494146B1 (en) * 2002-07-16 2005-06-13 주식회사 하이닉스반도체 Multi- Utilizing Holder Of Particle Inspection Device And Inspection Method Thereof
JP2007123916A (en) * 2006-11-28 2007-05-17 Hitachi Ltd Inspection method of semiconductor device, inspection device, and method of manufacturing semiconductor device using same
KR100780759B1 (en) 2005-01-24 2007-11-30 삼성전자주식회사 TFT Array Inspecting Apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100494146B1 (en) * 2002-07-16 2005-06-13 주식회사 하이닉스반도체 Multi- Utilizing Holder Of Particle Inspection Device And Inspection Method Thereof
KR100780759B1 (en) 2005-01-24 2007-11-30 삼성전자주식회사 TFT Array Inspecting Apparatus
JP2007123916A (en) * 2006-11-28 2007-05-17 Hitachi Ltd Inspection method of semiconductor device, inspection device, and method of manufacturing semiconductor device using same

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