JPH10294653A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent level fluctuation caused by noises from being transmitted to an internal circuit by removing the noise even when this noise is superimposed on an input signal. SOLUTION: This circuit is provided with a bias voltage generating circuit 3 for generating a bias voltage Vb different from the threshold voltage of an input circuit 1 just by a prescribed level. This bias voltage generating circuit 3 is composed of an inverter IV2 having a threshold voltage at level different from the threshold voltage of an inverter IV1 in the input circuit 1 and a feedback resistor Rf1 connected between the input terminal and output terminal of this inverter IV2. The synthetic signal of the input signal IN transmitted to a signal input terminal TM and a bias voltage Vb is supplied to the input circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a structure in which the level of a sine wave type input signal is identified by a predetermined reference voltage, and a signal having a level corresponding to the identified result is supplied to an internal circuit. A semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a typical example of a conventional semiconductor integrated circuit of this type.

This semiconductor integrated circuit includes an inverter IV3 connecting an input terminal to a signal input terminal TM, and a feedback resistor Rf2 connected between the input terminal and the output terminal of the inverter IV3. An amplifier circuit 4 for amplifying and transmitting the transmitted sine wave type input signal IN, and an inverter IV1 having a threshold voltage of a predetermined voltage level and receiving an output signal Vo of the amplifier circuit 4 at an input terminal thereof. The voltage level of the output signal Vo of the circuit 4 is changed to the inverter IV.
An input circuit 1 for identifying a signal Va with a threshold voltage of 1 and supplying a signal Va of a level corresponding to the identification result to the internal circuit 2
And a configuration having:

Next, the operation of this semiconductor integrated circuit will be described.
The description will be made with reference to the signal waveform diagrams of the respective parts shown in FIG.

The sine wave type input signal IN (FIG. 5A) transmitted to the signal input terminal TM is amplified by the amplifier circuit 4 (FIG. 5B) and input to the input circuit 1.

[0006] In the input circuit 1, the signal (V) from the amplifier circuit 4 is applied by the threshold voltage Vt of the inverter IV 1.
The voltage level of (o) is identified, and a signal Va of “0” level is supplied to the internal circuit 2 if the voltage level of this signal (Vo) is higher than the threshold voltage Vt, and a “1” level if it is lower than the threshold voltage Vt.

At this time, if noise or the like is not superimposed on the input signal IN (part (A) of FIG. 5B), FIG.
As shown in FIG. 5, the signal Va supplied to the internal circuit 2 has a simple step-like waveform that simply changes from the “0” level to the “1” level.
(Part (B) of (b)) Even if the noise level is low, the signal is amplified by the amplifier circuit 4, and the output signal Vo crosses the threshold voltage Vt several times as shown in FIG. 5 (d). That is, the signal Va does not form a simple step from the “0” level to the “1” level, but supplies an erroneous signal to the internal circuit 2.

As an example of a case where noise or the like is superimposed on the input signal IN, for example, when digital signal processing is performed in a preceding circuit, that is, a circuit that outputs the input signal IN, a level change of the signal is performed. Near the point, noise often occurs due to fluctuations in the ground potential and power supply potential due to the level change. In such a case, noise or the like is generated near the zero crossing point of the output signal of this circuit, that is, the input signal IN of the present application. Will be superimposed.

[0009]

In the conventional semiconductor integrated circuit described above, after the input signal IN is amplified by the amplifier circuit 4, the input circuit 1 converts the output signal (Va) with reference to the threshold voltage Vt. Since the level is determined, if low-level noise or the like is superimposed particularly near the zero cross point of the input signal IN, this noise is also amplified, and the output signal (Va) has a simple step shape. However, there is a problem that an erroneous signal is supplied to the internal circuit 2.

It is an object of the present invention to provide a semiconductor integrated circuit in which even if noise is superimposed on an input signal, the noise is removed and a level fluctuation due to the noise is not transmitted to an internal circuit.

[0011]

A semiconductor integrated circuit according to the present invention has a threshold voltage of a predetermined level, and has an input terminal receiving a composite signal of a sine wave type input signal from a signal input terminal and a bias voltage. An input circuit for receiving a voltage level of the composite signal with respect to the threshold voltage and supplying a signal having a level corresponding to the result of the identification to an internal circuit; And a bias voltage generating circuit for generating the different bias voltages and supplying the same to the input terminal of the input circuit.

The bias voltage generating circuit includes an inverter having a threshold voltage substantially equal to the bias voltage, and a feedback resistor provided between an output terminal and an input terminal of the inverter. A circuit for outputting the bias voltage from an output terminal of the inverter, or a first resistor receiving a power supply voltage at one end, one end connected to the other end of the first resistor, and the other end connected to a ground potential point A second resistor, and is configured as a circuit that outputs the bias voltage at a voltage level determined by the resistance values of the first and second resistors from a connection point of the first and second resistors.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The first embodiment includes an inverter IV1 having a predetermined threshold voltage Vt1, and receives a composite signal of a sine wave type input signal IN and a bias voltage Vb transmitted to a signal input terminal TM. An input circuit 1 that receives a signal Va received at its terminal (input terminal of the inverter IV1) and identifies the voltage level of the synthesized signal with respect to the threshold voltage Vt1, and supplies a signal Va having a level corresponding to the identified result to the internal circuit 2.
And an inverter IV2 having a threshold voltage Vt2 at a level different from that of the inverter IV1, and the inverter I2
A feedback resistor Rf1 connected between the output terminal and the input terminal of the inverter V2;
2 and a bias voltage generating circuit 3 for generating a bias voltage Vb of the same level and supplying the same to the input terminal of the input circuit 1.

Next, the operation of the first embodiment will be described with reference to the waveform diagrams of the respective parts shown in FIG.

As shown in FIG. 2A, the composite signal supplied to the input terminal of the input circuit 1 includes an input signal IN from a signal input terminal TM, a bias voltage Vb from a bias voltage generation circuit 3, and , And has a waveform in which the input signal IN changes vertically with reference to the bias voltage Vb.

Here, assuming that the threshold voltage Vt2 of the inverter IV2 of the bias voltage generating circuit 3 is 2.5V,
Bias voltage Vb generated by bias voltage generation circuit 3
Becomes 2.5V which is the same level as the threshold voltage Vt2 of the inverter IV2.

On the other hand, the threshold voltage Vt1 (also the threshold voltage of the input circuit 1) of the inverter IV1 of the input circuit 1 is set to 2.3V which is slightly different from the bias voltage Vb (2.5V). ing.

The level of the composite signal input to the input circuit 1 is identified by a threshold voltage (Vt1 = 2.3 V), and when noise is not superimposed on the input signal IN (FIG. 2).
As shown in FIG. 2B, at the point crossing the threshold voltage of the input circuit 1 (2.3 V, which is the same as the threshold voltage Vt1 of the inverter IV1), as shown in FIG.
A signal Va that changes from “0” level to “1” level in a simple step is supplied to the internal circuit 2.

When noise is superimposed (see FIG. 2)
(Part (B) of (a)) As shown in FIG. 2 (c), even if there is a level fluctuation due to noise near the bias voltage Vb (= 2.5V), avoid this level fluctuation part. Since it crosses the threshold voltage Vt1 (2.3 V),
As in the case where no noise is superimposed, the signal V that simply changes from “0” level to “1” level in a step-like manner
The signal a is supplied to the internal circuit 2. That is, noise near the zero cross point superimposed on the input signal IN can be removed.

As can be seen from FIG. 2C, the input circuit 1
The voltage level difference between the threshold voltage (Vt1) and the bias voltage Vb may be set according to the level of noise to be removed.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In the second embodiment, the bias voltage generating circuit 3a includes a first resistor R1 having one end receiving the power supply voltage Vcc, one end connected to the other end of the first resistor R1, and the other end connected. A second resistor R2 connected to a ground potential point, and a connection point between these resistors R1 and R2 is
Bias voltage V at a voltage level determined by the resistance value
This is a circuit for outputting b, and the other parts are the same as in the first embodiment.

In the second embodiment, since the bias voltage generating circuit 3a can be constituted by only two resistors, the first
The number of circuit elements is reduced and simplified compared to the embodiment of
There is an advantage. Other operations and effects are the same as those of the first embodiment.

[0026]

As described above, according to the present invention, a bias voltage generating circuit for generating a bias voltage different from a threshold voltage of an input circuit by a predetermined voltage level is provided, and an input signal transmitted to a signal input terminal is provided. And the bias voltage are combined and supplied to the input circuit, so that even if noise is superimposed on the input signal, this noise is removed and the level fluctuation due to the noise is not transmitted to the internal circuit. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 5 is a waveform chart of signals at various parts for explaining the operation of the semiconductor integrated circuit shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input circuit 2 Internal circuit 3, 3a Bias voltage generation circuit 4 Amplification circuit IV1-IV3 Inverter R1, R2 Resistance Rf1, Rf2 Feedback resistance

Claims (3)

[Claims] An input terminal receives a composite signal of a sine wave type input signal and a bias voltage from a signal input terminal at a predetermined level, and sets a voltage level of the composite signal to the threshold. An input circuit for identifying a value voltage and supplying a signal having a level corresponding to the identified result to an internal circuit; and generating the bias voltage different from the threshold voltage by a predetermined level to provide an input to the input circuit. And a bias voltage generating circuit for supplying the bias voltage to an end. 2. The method according to claim 1, wherein the bias voltage generation circuit includes an inverter having a threshold voltage substantially equal to the bias voltage.
2. The semiconductor integrated circuit according to claim 1, further comprising a feedback resistor provided between an output terminal and an input terminal of the inverter, wherein the circuit outputs the bias voltage from an output terminal of the inverter. 3. The bias voltage generating circuit includes a first resistor receiving a power supply voltage at one end, and a second resistor having one end connected to the other end of the first resistor and the other end connected to a ground potential point. 2. The semiconductor integrated circuit according to claim 1, further comprising: a circuit for outputting, from a connection point of the first and second resistors, the bias voltage at a voltage level determined by the resistance values of the first and second resistors. .