JPH10293730A - Data writing method, data reading method and data storage memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect whether or not the read and write of data whose data length is determined is abnormal to an FIFO(first-in first out) memory circuit. SOLUTION: Each data whose data length is determined is separately written/ read to buffer memory 31 according to the addresses of write and read pointers 32 and 33 whose count up values are set by a loop setting circuit 34. When it is normally written, writing is completed at any of plural specific addresses that exist. A 1st detecting circuit 37 decides a write as abnormal when the address of the pointer 32 is not a specific address. When it is normally read, reading is completed at any of plural specific addresses. The pointer 37 decides the reading as abnormal when the address of the pointer 33 is not a specific address. When they are decided abnormal, an address changing circuit 41 rewrites the address of the write or read pointer to a specific address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (First
(1st Out) format data storage memory circuit.

In recent years, it has been demanded that a large number of peripheral devices such as audio / video equipment and digital cameras can be connected to a personal computer, for example, in response to multimedia. There is a demand for highly accurate transfer data in data transfer between a personal computer and each peripheral device or between each peripheral device. The error correction function of the continuous data itself can be dealt with by taking measures such as inserting a code (CRC). Therefore, in the process of receiving continuous data before the code is generated, the data must be correctly transferred to the processing circuit.

[0003]

2. Description of the Related Art Conventionally, for example, one standard of digital data transfer is IEEE 1394 standard. This I
EEE1394 includes isochronous transfer in which transfer data (packets) of a predetermined data amount (byte length) is continuously transferred at a predetermined interval time.

In this isochronous transfer method, transfer data (packets) of a predetermined data amount is transmitted and received between apparatuses at a predetermined interval. At this time, the device for inputting the transfer data or the device for outputting the transfer data does not transfer the transfer data according to the input / output interface, but the MPU provided in the device uses the IEEE 139.
4 in accordance with the bus protocol. Therefore, it is necessary to temporarily hold the transfer data (packet) for the time required for the execution process, and the apparatus is provided with a data storage memory circuit for this purpose.

[0005] This data storage memory circuit has a FIFO
(First In First Out) data buffer memory circuit. This FIFO type memory circuit includes a write pointer and a read pointer. The value of the write pointer is used for the write address of the buffer memory. The value of the read pointer is used for the read address of the buffer memory. The values of both pointers are used to determine the state (FULL / EMPTY) in which the buffer memory holds data.

In this FIFO type memory circuit, for example, transfer data that has been isochronously transferred from another device is written via a protocol controller. Transfer data (packet) input to the memory circuit
Is data (isochronous data) from which a header portion is removed, and the data length of the isochronous data is always constant. For example, if the data length of the isochronous data is 250 bytes, the data having the length of 250 bytes is written one byte at a time in response to the write enable signal. Therefore, when 250 write enable signals are output, isochronous data having a length of 250 bytes is written to the memory circuit. More specifically, each time the write enable signal is output, the write pointer is incremented by "1", and one-byte data is written to the address indicated by the incremented write pointer. 250
When byte-length isochronous data is written,
The write pointer waits for writing of isochronous data of the next packet.

[0007] The same operation is performed when reading out one packet of isochronous data from the memory circuit. 2
The 50-byte data is read out one byte at a time in response to the read enable signal. Therefore, when 250 read enable signals are output, isochronous data having a length of 250 bytes is read out by the memory circuit. More specifically, each time the read enable signal is output, the read pointer is incremented by "1", and one byte of data is read from the address indicated by the incremented read pointer. When isochronous data having a length of 250 bytes is read, the read pointer waits for reading of isochronous data of the next packet.

[0008]

By the way, while writing isochronous data of a packet having a length of 250 bytes, noise may occur in the write enable signal. Due to this noise, the write pointer is incremented, and 1-byte data of the same content is written to the buffer memory. As a result, 250 bytes of isochronous data should be written,
Isochronous data including extra data exceeding the length of 0 bytes is written. And the isochronous
When data is read out one byte at a time, data exceeding 250 bytes in length is processed as isochronous data of a subsequent packet and is read as isochronous data of a subsequent packet.

On the other hand, if the write enable signal disappears due to noise for some reason, isochronous data having a length of 250 bytes should be written.
A byte length of less than 250 bytes, that is, isochronous data with insufficient data is written. When the isochronous data is read out one byte at a time, since the isochronous data is insufficient data of less than 250 bytes, a part of the isochronous data of the subsequent packet is replaced with the isochronous data of the previous packet. Abnormal data transfer such as being read out as a part of data.

Similarly, while reading isochronous data, noise is added to the read enable signal, and the read pointer is incremented by this noise, and 1-byte data is read from the buffer memory from a new address. As a result, the isochronous data having a length of 250 bytes should be read.
A problem arises in that isochronous data having a byte length exceeding the byte length is read. That is, abnormal data transfer occurs in which a part of the isochronous data of the subsequent packet is read out as a part of the isochronous data of the previous packet.

On the other hand, if the read enable signal is lost due to noise for some reason, the 250-byte long isochronous data should be read.
Insufficient isochronous byte length less than 50 bytes
A problem arises in that the data is read and a part of the isochronous data is not read. Then, the isochronous
An abnormal data transfer occurs in which a part of the data is processed as isochronous data of the subsequent packet and read out as a part of the isochronous data of the subsequent packet.

A first object of the present invention is to transfer data having a fixed data length into a memory in a plurality of times and write the transferred data to the memory if the transfer data is not correctly written. Is to provide a data writing method and a data storage memory circuit capable of writing data at a correct position.

[0013] A second object of the present invention is to provide a method in which, when transfer data having a determined data length is read out from a memory in a plurality of times and sequentially, if the transfer data is not read normally, the subsequent transfer data is transferred. An object of the present invention is to provide a data reading method and a data storage memory circuit that can read data from a correct position.

A third object of the present invention is to provide a data storage capable of detecting whether or not the transfer data has been normally written when the transfer data having the determined data length is divided into a plurality of times and sequentially written into the memory. It is to provide a memory circuit.

A fourth object of the present invention is to provide a data transfer method capable of detecting whether or not transfer data having a fixed data length is normally read when the transfer data is read out from a memory in a plurality of times. It is to provide a storage memory circuit.

A fifth object of the present invention is to provide a data storage memory circuit in which transfer data having a determined data length is written and read sequentially in a plurality of times, so that the transfer data is normally written and read. It is an object of the present invention to provide a data storage memory circuit which can detect whether or not transfer data has been correctly written, and in which transfer data to be written later can be written to a correct position, or transfer data to be read next can be read from a correct position. .

[0017]

According to the first aspect of the present invention, the data having a predetermined data length is divided into a plurality of predetermined write times in response to a write enable signal, and the write enable signal is divided into a plurality of predetermined times. A write pointer which is shifted in response to the write pointer and writes the write pointer to a write address of a buffer memory designated by the write pointer, wherein the count-up value of the write pointer is an integral multiple of the data length and the storage capacity of the buffer memory is When the write pointer is reset as the count-up value of the maximum value among a plurality of pieces that does not exceed the above, when the last write of the data having the determined data length to be sequentially written by the number of writes is completed, The write address of the write pointer at that time is the count-up value, the data length, If the write address of the write pointer does not correspond to any of the plurality of specific addresses obtained based on the specific address, the write address of the write pointer is rewritten from the plurality of specific addresses to a specific address closest to the write address indicated at that time. I made it.

According to a second aspect of the present invention, the data having the determined data length is divided into a plurality of predetermined write times in response to the write enable signal and shifted in response to the write enable signal. A data write method for writing data to a write address of a buffer memory specified by a write pointer, wherein the count-up value of the write pointer is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory. The write pointer is reset with the largest value among the count values as a count-up value, and the number of writes is counted by a write counter that counts the write enable signal. The last write of fixed length data has been completed When the write counter does not indicate the number of times of writing, the write address of the write pointer is indicated at that time from among a plurality of specific addresses obtained based on the count-up value and the data length. Rewrite to the specific address closest to the write address.

According to a third aspect of the present invention, the data having the determined data length is divided into a plurality of predetermined times of reading in response to the read enable signal and shifted in response to the read enable signal. A data read method for reading data from a read address of a buffer memory specified by a read pointer, wherein a count-up value of the read pointer is an integral multiple of the data length and does not exceed a storage capacity of the buffer memory. The read pointer is reset when the maximum value of the data is counted up, and when the last read of the data having the determined data length, which is sequentially read out by dividing the read count, is completed, the read pointer at that time is completed. Is determined based on the count-up value and the data length. It was plural when none of the particular address, and the read address of the read pointer to rewrite to the plurality nearest the specific address to the read address shown at that time out of the specified address.

According to a fourth aspect of the present invention, data having a determined data length is divided into a plurality of predetermined read times in response to a read enable signal and shifted in response to the read enable signal. A data read method for reading data from a read address of a buffer memory specified by a read pointer, wherein a count-up value of the read pointer is an integral multiple of the data length and does not exceed a storage capacity of the buffer memory. The read value is counted by a read counter that counts the read enable signal, and the read number is counted, and the read number is sequentially read out by dividing the read number. The last read of data with a fixed data length is completed. When the read counter does not indicate the number of times of reading, the read address of the read pointer is indicated from the plurality of specific addresses obtained based on the count-up value and the data length. Rewritten to the specific address closest to the read address.

According to a fifth aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined times of writing and sequentially read out of a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the maximum value of a plurality of values that are integer multiples of the data length and do not exceed the storage capacity of the buffer memory is designated as the count-up value. Pointer loop setting circuit, and When the last write of the data having the determined data length is completed, the write address of the write pointer at that time is set to any one of the plurality of specific addresses obtained based on the count-up value and the data length. A write detection circuit for judging a write error when not applicable is provided.

According to a sixth aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined times of writing and is sequentially read out of a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the maximum value of a plurality of values which is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory is designated as the count-up value. Pointer loop setting circuit, and When the last read of the data having the determined data length is completed, the read address of the read pointer at that time is set to any one of the plurality of specific addresses obtained based on the count-up value and the data length. A read detection circuit for judging a read error when not applicable.

According to a seventh aspect of the present invention, data having a determined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the count-up value of the write pointer and the read pointer is counted up to the maximum value among a plurality of values that are integral multiples of the data length and do not exceed the storage capacity of the buffer memory. A pointer loop setting circuit specified as a value, When the last write data to the data length is determined to be written sequentially divided is completed,
When the write address of the write pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length, a write detection circuit that determines a write error, When the last read of the data having the determined data length, which is sequentially read separately, is completed, the read address of the read pointer at that time may be any one of a plurality of specific addresses obtained based on the count-up value and the data length. If not, the detection circuit for reading to determine a read error, and when the detection circuit for writing determines a write error, the write address of the write pointer is indicated from the plurality of specific addresses at that time. Write address change to rewrite to the specific address closest to the write address A read address for rewriting a read address of the read pointer from the plurality of specific addresses to a specific address closest to the write address indicated at that time when the read detection circuit determines that the read is abnormal. And a change circuit.

According to an eighth aspect of the present invention, in the data storage memory circuit according to the fifth aspect, when the write detection circuit determines that the write is abnormal, the write address of the write pointer is changed to the plurality of specific addresses. And a write address change circuit for rewriting to a specific address closest to the write address indicated at that time.

According to a ninth aspect of the present invention, in the data storage memory circuit according to the sixth aspect, when the read detection circuit determines that a read error has occurred, the read address of the read pointer is changed to the plurality of specific addresses. And a read address change circuit for rewriting to a specific address closest to the read address indicated at that time.

According to a tenth aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined write times and sequentially read out from a plurality of predetermined read times. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, a write counter that counts the number of times of writing in response to the write enable signal, and the last write of the data having the determined data length that is sequentially written into the number of times of write has been completed When the write counter is When not indicate the write times, and a second light detection circuit for determining the writing error of the data.

According to an eleventh aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined times of writing, and is sequentially read out of a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the read counter that counts the number of times of reading in response to the enable signal for reading and the last reading of the data whose data length is sequentially read out divided into the number of times of reading have been completed. The read counter is When not indicate the number of times out, and a second lead for the detection circuit to determine that the reading error of the data.

According to the twelfth aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined times of writing and sequentially read out of a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the count-up value of the write pointer and the read pointer is counted up to the maximum value among a plurality of values that are integral multiples of the data length and do not exceed the storage capacity of the buffer memory. A pointer loop setting circuit designated as a value, A write counter for counting the number of writes in response to a read enable signal; a read counter for counting the number of reads in response to the read enable signal; When the last write of the determined data is completed, when the write counter that counts the number of writes does not indicate the number of writes, a second write detection circuit that determines that the data write is abnormal, When the last read of the data having the determined data length that is sequentially read in the read count is completed, when the read counter that counts the read count does not indicate the read count,
A second read detection circuit that determines that the data is read abnormally, and a write address of the write pointer based on the count-up value and the data length when the second write detection circuit determines that the data is abnormal. A write address change circuit for rewriting a specific address closest to the write address indicated at that time from among the plurality of specific addresses obtained in the above manner, and when the second read detection circuit determines that a read error has occurred, A read address changing circuit for rewriting the read address of the read pointer from a plurality of specific addresses obtained based on the count-up value and the data length to a specific address closest to the read address indicated at that time; With. According to a thirteenth aspect of the present invention, in the data storage memory circuit according to the tenth aspect, when the second write detection circuit determines that writing is abnormal, the write address of the write pointer is changed to the count-up value and the data. A write address change circuit is provided for rewriting a specific address closest to the write address indicated at that time from among a plurality of specific addresses obtained based on the length.

According to a fourteenth aspect of the present invention, in the data storage memory circuit according to the eleventh aspect, the read address of the read pointer is counted up when the second read detection circuit determines that a read error has occurred. A read address changing circuit is provided for rewriting a plurality of specific addresses obtained based on the value and the data length to a specific address closest to the indicated read address at that time.

According to a fifteenth aspect of the present invention, data having a determined data length is sequentially written into a plurality of predetermined times of writing and is sequentially read out of a plurality of predetermined times of reading. A buffer memory, a write pointer that specifies while shifting the write address of the buffer memory in response to the write enable signal, and a read pointer that specifies while shifting the read address of the buffer memory in response to the read enable signal In the data storage memory circuit, the count-up value of the write pointer and the read pointer is counted up to the maximum value among a plurality of values that are integral multiples of the data length and do not exceed the storage capacity of the buffer memory. A pointer loop setting circuit designated as a value; When the last write data to the data length is determined to be written in the order is completed is divided into,
When the write address of the write pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length, a write detection circuit that determines a write error, When the last read of the data having the determined data length, which is sequentially read separately, is completed, the read address of the read pointer at that time may be any one of a plurality of specific addresses obtained based on the count-up value and the data length. If the above does not apply, the read detection circuit that determines that the read is abnormal, a write counter that counts the number of times of writing in response to the enable signal for write, and the number of reads in response to the enable signal for read. A read counter for counting, A second write detection circuit that determines that the data write is abnormal when the last write of the data having the determined data length is completed, the write counter does not indicate the number of writes, and When the last read of the data having the determined data length and sequentially read out by dividing the number of read times is completed, when the read counter for counting the number of read times does not indicate the number of read times, it is determined that the data read is abnormal. When the second detection circuit for reading and the detection circuit for writing or the second detection circuit for writing determines that the reading is abnormal, the write address of the write pointer is obtained based on the count-up value and the data length. The specific address closest to the read address indicated at that time from among the specified specific addresses When the write address changing circuit rewritten to the scan, the read detection circuit or the second read detection circuit judges that the reading error,
A read address changing circuit for rewriting the read address of the read pointer from a plurality of specific addresses obtained based on the count-up value and the data length to a specific address closest to the read address indicated at that time; With.

(Operation) According to the first aspect of the present invention, the storage capacity of the buffer memory is determined by the count-up value. At this time, the count-up value of the write pointer is set to the maximum value among a plurality of values that is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory, so that the data length is determined. When the data is written to the buffer memory according to the write address of the write pointer, when it is written normally, the data is written at any one of a plurality of specific addresses that are an integral multiple of the data length and equal to or less than the count-up value. Writing is completed. As a result, when the writing is abnormal, the writing is completed at an address outside the specific address.
When a write error occurs, the write address of the write pointer is rewritten from a plurality of specific addresses to a specific address closest to the write address indicated at that time. Is written from a normal position, and the subsequent data is completely written at a specific write address.

According to the second aspect of the invention, when the data having the determined data length is normally written, the writing is completed with a predetermined number of times of writing in response to the write enable signal. Therefore, when the last writing of the data having the determined data length is completed, and when the write counter does not indicate the number of times of writing, abnormal writing occurs. When a write error occurs, the write address of the write pointer is rewritten from a plurality of specific addresses to a specific address closest to the write address indicated at that time. Is written from a normal position, and the subsequent data is completely written at a specific write address.

According to the third aspect of the present invention, the count-up value of the read pointer is set to the maximum value among a plurality of values which are integral multiples of the data length and do not exceed the storage capacity of the buffer memory. Therefore, when each data whose data length is determined is read from the buffer memory according to the read address of the read pointer, when the data is read normally, there are a plurality of data that are an integral multiple of the data length and equal to or less than the count-up value. The reading is completed at any of the specific addresses. As a result, when the reading is abnormal, the reading is completed at an address outside the specific address. When a read error occurs, the read address of the read pointer is rewritten from a plurality of specific addresses to the specific address closest to the read address indicated at that time, so that the subsequent data to be read next is read out. Are read from a normal position, and the subsequent data is completely read at a specific read address.

According to the fourth aspect of the present invention, when the data having the determined data length is normally read, the reading is completed at a predetermined number of times of reading in response to the read enable signal. Therefore, when the last reading of the data having the determined data length is completed, and when the read counter does not indicate the number of times of reading, abnormal reading is performed. Then, when a read error occurs, the read address of the read pointer is rewritten from a plurality of specific addresses to a specific address closest to the read address indicated at that time, so that the subsequent data to be read next is read out. Is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

According to the invention of claim 5, the count-up value of the write pointer is calculated by the pointer loop setting circuit.
Since the maximum value among a plurality of data lengths that are integral multiples of the data length and does not exceed the storage capacity of the buffer memory is used as the count-up value, each data whose data length is determined is stored in the buffer memory according to the write address of the write pointer. When the data is normally written, the writing is completed at one of a plurality of specific addresses that are an integral multiple of the data length and equal to or less than the count-up value. Therefore, the write detection circuit can check the write address at that time of the write pointer when the data writing is completed, and can determine that the writing is abnormal if the specific address is not indicated.

According to the present invention, the count-up value of the read pointer is calculated by the pointer loop setting circuit.
Since the maximum value among a plurality of data lengths that are integral multiples of the data length and does not exceed the storage capacity of the buffer memory is used as the count-up value, each data whose data length is determined is stored in the buffer memory according to the read address of the read pointer. When the data is normally read, the reading is completed at one of a plurality of specific addresses that are an integral multiple of the data length and equal to or less than the count-up value. Therefore, the read detection circuit looks at the read address at that time of the read pointer when the data read is completed, and can determine that the read is abnormal if the specific address is not indicated.

According to the invention of claim 7, claims 5 and 6 are provided.
In addition to the operation of the invention described in the above, when the write detection circuit determines that the write is abnormal, the write address change circuit changes the write address of the write pointer from the plurality of specific addresses to the write address indicated at that time. Rewrite to the closest specific address. As a result, subsequent data to be written next is written from a normal position, and the writing of the subsequent data is completed at a specific write address. When the read detection circuit determines that the read is abnormal, the read address change circuit rewrites the read address of the read pointer from a plurality of specific addresses to a specific address closest to the read address indicated at that time. I made it.
As a result, subsequent data to be read next is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

According to the eighth aspect of the present invention, in addition to the operation of the fifth aspect, when the write detection circuit determines that a write error has occurred, the write address change circuit sets a plurality of write addresses of the write pointer. The specific address is rewritten from the specific addresses to the specific address closest to the write address indicated at that time. As a result, subsequent data to be written next is written from a normal position, and the writing of the subsequent data is completed at a specific write address.

According to the ninth aspect of the present invention, in addition to the operation of the sixth aspect, when the read detecting circuit determines that the reading is abnormal, the read address changing circuit sets a plurality of read addresses of the read pointer. The specific address closest to the read address indicated at that time is rewritten from the specific addresses. As a result, subsequent data to be read next is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

According to the tenth aspect of the present invention, when the last write of the data having the determined data length is completed, or when the data is normally written, the write counter indicates the number of times of writing. A second write detection circuit, when the last write of the data having the determined data length is completed, when the write counter does not indicate the number of times of writing,
It can be determined that a writing error has occurred.

According to the eleventh aspect of the present invention, when the last read of the data having the determined data length is completed, or when the data is normally read, the read counter indicates the number of times of reading. A second read detection circuit, when the last read of the data having the determined data length is completed, when the read counter does not indicate the read count,
It can be determined that a reading error has occurred.

According to the twelfth aspect of the present invention, in addition to the functions of the tenth and eleventh aspects, when the second write detection circuit determines that a write error has occurred, the write address change circuit sets the write pointer. Is rewritten from a plurality of specific addresses to a specific address closest to the write address indicated at that time. As a result, subsequent data to be written next is written from a normal position, and the writing of the subsequent data is completed at a specific write address. Also, when the second read detection circuit determines that the read is abnormal,
The read address change circuit rewrites the read address of the read pointer from a plurality of specific addresses to a specific address closest to the read address indicated at that time. As a result, subsequent data to be read next is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

According to the thirteenth aspect of the present invention, in addition to the operation of the tenth aspect, when the second write detection circuit determines that the write is abnormal, the write address change circuit writes the write pointer. The address is rewritten from a plurality of specific addresses to a specific address closest to the write address indicated at that time. As a result, subsequent data to be written next is written from a normal position, and the writing of the subsequent data is completed at a specific write address.

According to the fourteenth aspect of the present invention, in addition to the operation of the eleventh aspect, when the second read detecting circuit determines that the read is abnormal, the read address changing circuit reads the read pointer. The address is rewritten from a plurality of specific addresses to a specific address closest to the read address indicated at that time. As a result, subsequent data to be read next is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

According to the invention of claim 15, claim 5,
In addition to the effects of the inventions described in 6, 10, and 11, when the write detection circuit or the second write detection circuit determines that the writing is abnormal, the write address change circuit sets the write addresses of the write pointer to a plurality of addresses. The specific address is rewritten to the specific address closest to the write address indicated at that time. As a result, subsequent data to be written next is written from a normal position, and the writing of the subsequent data is completed at a specific write address.

When the read detection circuit or the second read detection circuit determines that the read is abnormal, the read address change circuit indicates the read address of the read pointer from the plurality of specific addresses at that time. Rewrite to the specific address closest to the read address. As a result, subsequent data to be read next is read from a normal position, and the writing of the subsequent data is completed at a specific read address.

[0047]

FIG. 3 shows a system configuration based on IEEE1394. Personal computer (hereinafter referred to as personal computer) 1, digital V as a peripheral device
The TR 2 and the color page printer 3, which is also a peripheral device, are connected to each other via a bus 4 compliant with IEEE1394.

FIG. 2 shows the IEEE 13 provided in the personal computer 1.
1 shows a block circuit for explaining a system configuration conforming to H.94. The personal computer 1 includes an IEEE1394 protocol controller (hereinafter, referred to as IPC) 11, a microprocessor unit (hereinafter, referred to as MPU) 12, and a DMA (Direct Memory Access) controller (hereinafter, referred to as IPC).
DMAC 13). IPC11, MP
The U12 and the DMAC 13 are each formed by a one-chip semiconductor integrated circuit device (LSI).

The IPC 11 includes the MPU 12 and the DMAC 1
3 to exchange data. IPC 11 is connected to bus 4
And a digital VTR 2 and an IEEE 1394 protocol controller (IPC) provided in the color page printer 3.

The IPC 11 is a protocol control circuit 2
1. Transmission packet data storage memory circuit 22, reception packet data storage memory circuit 23, first input / output interface 24, and second input / output interface 2.
5 is provided.

The first input / output interface 24 is connected to the digital VTR 2 via the bus 4 and exchanges packets 27 in the isochronous transfer between the protocol control circuit unit 21 and the IPC of the digital VTR 2. The second input / output interface 25 is connected to the color page printer 3 via the bus 4, and exchanges packets 27 in isochronous transfer between the protocol control circuit unit 21 and the IPC of the page printer 3.
The packet 27 includes a header 28 and isochronous data 29 as shown in FIG.

Transmission packet data storage memory circuit 22
Are connected to the DMAC 13. The transmission packet data storage memory circuit 22 inputs and temporarily stores transfer data (packet 27) for transmission output from the DMAC 13. The transmission packet data storage memory circuit 22 is connected to the protocol control circuit unit 21.
Then, the transmission packet data storage memory circuit 22
The temporarily stored transfer data (packet 27) is output to the protocol control circuit unit 21.

Receiving packet data storage memory circuit 23
Are connected to the protocol control circuit section 21.
The receiving packet data storage memory circuit 23 receives and temporarily stores transfer data (packet 27) for reception output from the control circuit unit 21. The receiving packet storage memory circuit 23 is connected to the DMAC 13. Then, the reception packet data storage memory circuit 23 transfers the temporarily held transfer data (packet 27) to the DMAC 1
Output to 3.

The protocol control circuit section 21 is connected to the first and second input / output interfaces 24 and 25. The protocol control circuit unit 21 communicates with the digital VTR 2 via the first input / output interface 24 and the bus 4.
The transfer data (packet 27) in the isochronous transfer is exchanged with the protocol control circuit unit, and the input transfer data is output to the color page printer 3 via the second input / output interface 25. The protocol control circuit 21 exchanges transfer data (packet 27) in isochronous transfer with the protocol control circuit of the color page printer 3 via the second input / output interface 25 and the bus 4. , And outputs the input transfer data to the digital VTR 2 via the first input / output interface 24.

The protocol control circuit unit 21
Exchanges control data with the
It is analyzed whether or not the transfer data input from 4, 25 is the transfer data transferred for its own device (personal computer 1). When analyzing the transfer data for the own device, the protocol control circuit unit 21 transfers the data to the DMAC 13 via the reception packet data storage memory circuit 23 based on the control data from the MPU 12.

Further, the protocol control circuit section 21
Transfer data for transmission output from the DMAC 13 stored in the transmission credit packet data storage memory circuit 22 based on the control data from the transmission 12 (packet 27)
Enter Then, the protocol control circuit unit 21 adds the header to the first and second input / output interfaces 2.
4 and 25.

Next, the transmission packet data storage memory circuit 22 will be described. For convenience of description, a circuit configuration of a portion of the transfer data (packet 27) for temporarily holding the isochronous data 29 without the header 28 will be described. In the present embodiment, the isochronous data 29 has a fixed byte length of 250 bytes for convenience of explanation.

FIG. 1 shows the block circuit. In FIG. 1, the transmission packet data storage memory circuit 22 includes:
A buffer memory 31, a write pointer 32, a read pointer 33, a pointer loop setting circuit 34, a write counter 35, a read counter 36, a first detection circuit 37 as a write and read detection circuit, a second write and read A second detection circuit 38 as a read detection circuit,
A break counter 39, an interrupt signal generation circuit 40, an address change circuit 41 as a write and read address change circuit, and a control register 42 are provided.

The buffer memory 31 is a two-port readable and rewritable memory (RAM). In this embodiment, the buffer memory 31 has a memory capacity of 1024 bytes for convenience of explanation. In the buffer memory 31, predetermined 250-byte length isochronous data 29 sequentially output from the DMAC 13 is written in units of 1 byte,
The written 250-byte long isochronous data 29 is read in units of 1 byte. Therefore, the read and write addresses are respectively “0” to “1”.
023 ”in total.
Further, the number of times of writing for writing all of the isochronous data 29 having a length of 250 bytes is 250 times. Similarly, the number of times of reading for reading all of the isochronous data 29 having a length of 250 bytes is 250.

The write pointer 32 is an address counter for writing, and the value indicated by the pointer 32 becomes a write address. The write pointer 32 is "0"
Is a pointer from which the value of “1023” can be counted. The write pointer 32 adds the number of write enable signals WE output from the MPU 12 each time 1-byte data is written. Accordingly, the value (write address) of the write pointer 32 is incremented by "1" each time the write enable signal WE is input, and the address of the buffer memory 31 is shifted by one to the upper address. Each time the write enable signal WE is output from the MPU 12, the DMA
250 bytes long isochronous data 2 from C13
One byte of the isochronous data 29 is output to the buffer memory 31, and the one byte of the isochronous data 29 is written to the address indicated by the incremented write pointer 32.

When the value of the write pointer 32 is a count-up value, that is, in this case, “1023”, when the next new write enable signal WE is inputted, the write pointer 32 becomes the value of “0”. Is reset to The write pointer 32 can appropriately change the value before being reset to "0", that is, the count-up value.

The read pointer 33 is an address counter for reading, and the value indicated by the pointer 33 becomes the read address. Read pointer 33 is "0"
Is a counter that can count the value of “1023” from The read pointer 33 adds the number of read enable signals RE output from the protocol control circuit unit 21 each time one byte of data is read. Accordingly, the value (read address) of the read pointer 33 is incremented by "1" every time the read enable signal RE is input, and the address of the buffer memory 31 is shifted by one to the upper address. Then, from the address of the buffer memory 31 indicated by the value of the read pointer 33, 1
The bytes of isochronous data 29 are output to the protocol control circuit unit 21.

When the value of the read pointer 33 is a count-up value, that is, in this case, “1023”, when the next new read enable signal RE is inputted, the read pointer 33 becomes the value of “0”. Is reset to The read pointer 33 can appropriately change the value before being reset to “0”, that is, the count-up value.

The contents of the write pointer 32 and the read pointer 33 are output to the MPU 12. The writing and reading of the data 29 are controlled via the protocol control circuit section 21.

As described above, the write address and the read address are shifted by one address on the basis of the values of the write pointer 32 and the read pointer 33, so that the buffer memory 31 stores the FIFO (First In F).
irst Out) type data buffer memory.

The pointer loop setting circuit 34 is connected to the write pointer 32 and the read pointer 33. The pointer loop setting circuit 34 outputs data for changing the count-up value of the write pointer 32 and the read pointer 33. The count-up value is an integer multiple of the byte length of the isochronous data 29, and is set to a maximum value that does not exceed the memory capacity of the buffer memory 31. The setting of the count-up value is performed based on the data length change data set in the control register 42.

In this embodiment, the one packet 27
Data 29 for convenience of explanation.
The length was set to 50 bytes. The memory capacity of the buffer memory 31 in which writing and reading are performed in units of 1 byte is 1024 bytes. Since the count-up value is an integer of 250 bytes and does not exceed 1024 bytes, the count-up value is “1000 (= 250 × 4 <1024)”.

More specifically, since the write pointer 32 and the read pointer 33 include “0”, “0” to “9”
99 "and the count-up value is" 9 ".
99 ". Therefore, when a new write enable signal WE is output when the value is “999”, the write pointer 32 is reset to “0”. Similarly, when the value of the read pointer 33 is “999” and a new read enable signal RE is output, the read pointer 33 is reset to “0”. Then, the counting operation is performed again from “0”.

Therefore, the buffer memory 31 has a maximum of 4
The isochronous data 29 of the packets 27 can be written. If the address “0” is the first address to be written, one packet 2
The address (specific address) at which the 250-byte isochronous data 29 of No. 7 completes writing is “24”.
9 "," 499 "," 749 ", or" 999 ". Therefore, 1
When the writing of the 250-byte length isochronous data 29 in one packet 27 is completed, it means that the writing was not performed normally for some reason.

The specific addresses at which the 250-byte isochronous data 29 of one packet 27 completes reading at the end are always "249", "499",
The address is either “749” or “999”. Therefore, one packet 27 with other addresses is used.
Data of 250 bytes length isochronous data 29
Is completed, it means that the reading was not performed normally for some reason.

The first detection circuit 37 is provided with the write pointer 3
2 and the read pointer 33, and each pointer 32,
Enter the current value (address) of 33. The first detection circuit 37 receives the input data break signal EN1 and the output data break signal EN2 from the MPU 12. The input data break signal EN1 is one packet 2
7 byte 250-byte isochronous data 29
That the output to the buffer memory 31 has been completed
12 is a signal to be determined and output. The output data break signal EN2 is a signal that the MPU 12 determines that reading of the 250-byte isochronous data 29 in one packet 27 has been completed and outputs it.

The first detection circuit 37 responds to the input data break signal EN1 and determines whether the value (address) of the write pointer 32 at that time is one of "249", "499", "749" or "999". Determine whether the address is a specific address. And if there is a matching address,
It is determined that the 250-byte isochronous data 29 in the packet 27 in which the writing has been completed has been normally written.

Conversely, if they do not match, it is determined that the 250-byte isochronous data 29 in the packet 27 for which writing has been completed has not been normally written, that is, that abnormal writing has been performed. When it is determined that the writing is abnormal, the first detection circuit 37 outputs a first writing abnormality signal S1.

The first detection circuit 37 responds to the output data break signal EN2 to read the read pointer 33 at that time.
Are "249", "499", "74"
It is determined whether the address is a specific address of “9” or “999”. If there is a matching specific address, it is determined that the isochronous data 29 having a length of 250 bytes in the packet 27 whose reading has been completed has been normally read.

On the other hand, if they do not match, the 250-byte isochronous data 29 in the packet 27 whose reading has been completed has not been read normally.
That is, it is determined that abnormal reading has been performed. When it is determined that the reading is abnormal, the first detection circuit 37 outputs a first reading abnormal signal S2.

The input data break signal EN 1 and the output data break signal EN 2 are output to a break counter 39. The break counter 39 has a count-up value set based on the divided block data of the control register 42. For example, when the divided block data is “1”, the count-up value becomes “1”, and the break counter 39 outputs the first detection signal N1 every time one input data break signal EN1 is output. Similarly, the break counter 39 outputs the second detection signal N2 every time one output data break signal EN2 is output.

The write counter 35 receives the write enable signal WE and counts the number of times of writing. In the present embodiment, when the 250th write enable signal WE is input corresponding to the 250-byte length of the isochronous data 29 in one packet 27, the first period signal P1 is output, reset and reset from the beginning. Write enable signals WE
Count. Therefore, the write counter 35 indicates that the isochronous data 29 has been correctly stored in the buffer memory 31.
, The first period signal P1 is output every time all of the isochronous data 29 having a length of 250 bytes in one packet 27 is written.

The read counter 36 receives the read enable signal RE and counts the number of times of reading. In the present embodiment, when the 250th read enable signal RE is input corresponding to the 250-byte length of the isochronous data 29 in one packet 27, the second period signal P2 is output, reset and reset again from the beginning. Read enable signals RE
Count. Therefore, the read counter 36 indicates that the isochronous data 29 has been correctly read from the buffer memory 31.
, The second period signal P2 is output every time all of the 250-byte length isochronous data 29 in one packet 27 is read.

The second detection circuit 38 is connected to the write and read counters 35 and 36,
The first and second period signals P1 and P2 from 5 and 36 are input. The second detection circuit 38 is provided with the break counter 3
9 to receive the first and second detection signals N1 and N2.

The second detection circuit 38 determines whether the first detection signal N1 of the break counter 39 has been output simultaneously with the output of the first period signal P1. And, at the same time, the packet 2 whose writing has been completed
Byte 250 isochronous data 2
No. 9 determines that data has been written normally. Conversely, if they are not at the same time, it is determined that the 250-byte length isochronous data 29 in the packet 27 for which writing has been completed has not been normally written, that is, abnormal writing has been performed. When it is determined that the writing is abnormal, the second detection circuit 38 outputs a second writing abnormal signal S3.

The second detection circuit 38 determines whether the second detection signal N2 of the break counter 39 has been output simultaneously with the output of the second period signal P2. And, at the same time, the packet 2 whose read has been completed
7 byte 250-byte isochronous data 29
Is determined to be normally read. Conversely, if they are not at the same time, it is determined that the 250-byte isochronous data 29 in the packet 27 for which writing has been completed has not been normally read, that is, that abnormal reading has been performed. When it is determined that the reading is abnormal, the second detection circuit 38 outputs a second reading abnormal signal S4.

The interrupt signal generation circuit 40 is connected to the first detection circuit 37 and receives the first write error signal S1 and the first read error signal S2 from the first detection circuit 37. The interrupt signal generation circuit 40 outputs the first interrupt signal T1 in response to the first write error signal S1, and sends the second interrupt signal T2 to the address change circuit 41 and the MPU 12 in response to the first read error signal S2. Output.

The interrupt signal generation circuit 40 is connected to the second detection circuit 38, and the second detection circuit 38
The write error signal S3 and the second read error signal S4 are input. The interrupt signal generation circuit 40 outputs the first interrupt signal T1 in response to the second write abnormality signal S3 and the second interrupt signal T3.
The second interrupt signal T2 is output to the address change circuit 41 and the MPU 12 in response to the read abnormality signal S4.

The address change circuit 41 responds to the first interrupt signal T1 and outputs the packet 27 whose write has been completed.
Assuming that a state in which the 250-byte isochronous data 29 has not been properly written has occurred in the buffer memory 31, the value of the write pointer 32 at that time is read. Then, the address change circuit 41 executes a process of forcibly changing the value of the write pointer 32. The values (addresses) to be changed are “249”, “499”, “7”.
The specific address is either “49” or “999”. More specifically, a specific address closest to the value (address) of the write pointer 32 at that time is selected from the four specific addresses, and the value of the write pointer 32 is changed to the selected specific address.

For example, when the value (address) of the write pointer 32 is “512”, for example, noise enters the write enable signal WE for some reason, and the isochronous data 29 in one packet 27 has a length of 250 bytes or more. Is written extra to the addresses "250" to "512" of the buffer memory 31. That is, it is determined that extra 13 bytes of data have been written in the addresses “500” to “512”. Therefore, the 250-byte isochronous data 29 of the subsequent packet 27 is written from the address “513”.

Therefore, this is prevented and "500" to "7"
The address change circuit 41 writes the write pointer 32 so that the 250-byte isochronous data 29 of the subsequent packet 27 can be written to the address "49".
Is changed to “499”.

In response to the second interrupt signal T 2, the address change circuit 41 determines that the 250-byte isochronous data 29 in the packet 27 whose reading has been completed has not been normally read out. , The read pointer 33 at that time is read. Then, the address change circuit 41 executes a process of forcibly changing the value of the read pointer 33. Values (addresses) to be changed are “249”, “499”,
A specific address of either “749” or “999” is set. More specifically, a specific address closest to the value (address) of the read pointer 33 at that time is selected from the four specific addresses, and the value of the read pointer 33 is changed to the selected specific address.

For example, when the value (address) of the read pointer 33 is “730”, for example, noise enters the read enable signal RE for some reason and the isochronous data 29 in one packet 27 is data of less than 250 bytes. Therefore, it is determined that only the data at the addresses “500” to “730” in the buffer memory 31 has been read. That is, it is determined that the 19-byte data at the addresses “731” to “749” has not been read. Therefore, 250 of the subsequent packet 27
The byte-length isochronous data 29 is read from the address "731" assuming that it starts from the address "731".

Therefore, this is prevented, and “750” to “9”
The address change circuit 41 changes the value of the read pointer 32 to "749" so that the 250-byte isochronous data 29 of the subsequent packet 27 at the address "99" can be read.

The control register 42 is a register in which various mode setting data are recorded by the MPU 12. The mode setting data includes first valid data and second valid data.
Valid data, byte length change data, divided data, etc.

The first valid data is supplied to the first detection circuit 37.
Is the data for setting whether or not to use the first detection circuit 37 when the content to be used is set.
Are in a state where comparison operation is possible based on the contents. Second
Is valid data for setting whether or not to use the second detection circuit 38. When the content to be used is set, the second detection circuit 38 can perform a comparison operation based on the content. State.

The byte length change data is one packet 2
7, the byte length of the isochronous data 29 is, for example, 2
There is data for various changes from 50-byte length to 100-byte length. Then, the pointer loop setting circuit 34 sets the count-up value of the write pointer 32 and the read pointer 33 to a value that is an integral multiple of the byte length of the byte length change data and does not exceed the memory capacity of the buffer memory 31. ing.

Therefore, for example, if the byte length change data is “150 byte length”, the count-up value is 1 in which writing and reading are performed in units of 1 byte.
“900 (= 150 × 6 <1024)” for the buffer memory 31 having a memory capacity of 024 bytes. That is, the write pointer 32 and the read pointer 33
It is a counter from "0" to a count-up value of "899".

Therefore, the buffer memory 31 has a maximum of 4
Isochronous packets of 150 packets each having a length of 150 bytes.
The data 29 can be written. When the address “0” is the first address to be written, the specific address at which the 150-byte isochronous data 29 of one packet 27 completes writing is always
"149", "299", "449", "599",
The address is either “749” or “899”. Therefore, one packet 27 with other addresses is used.
Data of 150 bytes long isochronous data 29
When the writing is completed, it means that writing was not performed normally for some reason. In addition, always 250 bytes of isochronous data 2 of one packet 27
The specific address for which 9 completes reading last is “14
9 "," 299 "," 449 "," 599 "," 74 "
Either “9” or “899”. Therefore, when reading of the 150-byte length isochronous data 29 in one packet 27 at another address is completed, it means that reading was not performed normally for some reason.

Further, in this case, the write and read counters 35 and 36 respectively output the first and second period signals P1 and P2 when the 150 write and read enable signals WE and RE are input, respectively. It is supposed to.

The divided data is a packet 2 for isochronous transfer by combining a plurality of data blocks.
Used to make 7 In this case, the byte length change data is also changed.

For example, when five 50-byte data blocks are combined into 250-byte isochronous data 29 of one packet 27, and the 250-byte isochronous data 29 of one packet 27 is When the data is read after being divided into 50-byte data blocks, the divided data is “5”. This divided data is set as the count-up value “5” of the break counter 39. The MPU 12 outputs an input data break signal EN1 each time the last one byte of data in each data block is completely written. Therefore, the input data break signal EN
Each time five 1s are counted, the break counter 39 outputs the first detection signal value N1.

Then, the write counter 35 is set to 250
When the write enable signal WE is input, that is, when writing of five data blocks (writing of data having a length of 50 × 5 bytes) is completed, the first period signal P1 is output to the second detection circuit 38. Output to When the fifth input data break signal EN1 is input, the break counter 39 outputs the first detection signal N1 to the second detection circuit 38. When the first period signal P1 and the first detection signal N1 are simultaneously input, the second detection circuit 38 generates five data blocks for generating 250-byte length isochronous data 29 of one packet 27. Is determined to have been written normally. Conversely, if they are not at the same time, the second detection circuit 38 determines that five data blocks have not been written normally, that is, that abnormal writing has been performed. When it is determined that the writing is abnormal, the second detection circuit 38 outputs a second writing abnormal signal S3.

The same applies to the case where the 250-byte isochronous data 29 of one packet 27 is divided into five 50-byte data blocks and read. The MPU 12 outputs an output data break signal EN2 every time the reading of the last one byte of data of each data block is completed. Then, every time the number of the break signals EN2 is counted by 5, the break counter 39 outputs the second detection signal value N2.

The read counter 36 calculates 250
When the read enable signal RE is input, that is, when reading of five data blocks (writing of data of 50 × 5 byte length) is completed, the second period signal P2 is output to the second detection circuit 38. I do. When the fifth output data break signal EN2 is input, the break counter 39 outputs the second detection signal N2 to the second detection circuit 38. The second detection circuit 38 outputs the second period signal P
When the second detection signal N2 and the second detection signal N2 are input simultaneously, it is determined that five data blocks have been normally read. Conversely, if they are not at the same time, the second detection circuit 38 determines that five data blocks have not been read normally, that is, an abnormal read has occurred. When it is determined that the reading is abnormal, the second detection circuit 38 outputs a second reading abnormal signal S4.

The reception packet data storage memory circuit 23 is also the transmission packet data storage memory circuit 2 described above.
Since the circuit configuration is the same as that of FIG. 2 and is easily understood, the description thereof is omitted.

Next, the operation of the transmission packet data storage memory circuit 22 configured as described above will be described. (A) Writing of 250 bytes of isochronous data 29.

The first and second valid data of the control register 42 are set so that the first detection circuit 37 and the second detection circuit 38 operate together. The byte length change data of the control register 42 is set to 250 bytes. Further, the division data of the control register 42 is "1". For convenience of explanation, the value (address) of the write pointer 32 indicates “249”.

When the first 1-byte data of the 250-byte isochronous data 29 is output from the DMAC 13 and the first write enable signal WE is output from the MPU 12, the write pointer 3
2 responds to the first write enable signal WE with “2
From “49” to “250”. The first one-byte data is written to the address “250” of the buffer memory 31. Thereafter, each time a new write enable signal WE is input from the MPU 12, the value of the write pointer 32 is incremented, the address is shifted to one address, and the shifted new address contains one byte of isochronous data 29. It is written one by one. Along with this writing, the write counter 35 counts the write enable signal WE.

Eventually, the first write enable signal W
250th write enable signal WE counting from E
Is output, the value of the write pointer 32 becomes “499”
Becomes 250 bytes of isochronous data 29
Of the last one byte in the buffer memory 31
Is written to the address “499”.

The 250th write enable signal WE
Is output from the MPU 12, the input data break signal EN1 is output to the first detection circuit 37. The first detection circuit 37 responds to the break signal EN1 to change the value of the write pointer 32 at that time to “249”, “499”,
It is determined whether the address corresponds to a specific address of “749” or “999”. Then, when the isochronous data 29 having a length of 250 bytes is normally written based on the normal write enable signal WE, the value of the write pointer 32 becomes “499” and matches one of the four specific addresses. Therefore, the first detection circuit 37 determines that the data has been written normally.

On the other hand, if they do not match, the first detection circuit 37 determines that abnormal writing has been performed, and outputs a first write abnormal signal S1 to the interrupt signal generating circuit 40. The interrupt signal generation circuit 40 outputs the first write abnormality signal S
1 to output the first interrupt signal T1 to the address change circuit 4
1 and the MPU 12. The address change circuit 41 responds to the first interrupt signal T1 by 25
Assuming that a state in which the isochronous data 29 having a length of 0 bytes has not been normally written has occurred in the buffer memory 31, the value of the write pointer 32 at that time is read. At this time, for example, noise enters the write enable signal WE for some reason, the value of the write pointer 32 is, for example, “512”, and extra 13-byte data is written to addresses from “500” to “512”. If the address is changed, the address change circuit 41
Is changed to “499”.

Therefore, the 250-byte length isochronous data 29 of the subsequent packet 27 can be written in order from the “500” address of the buffer memory 31. As a result, the isochronous data 29 written from the “500” address of the buffer memory 31 is sequentially read from the head when read.

When the 250th write enable signal WE is output, the write counter 35 outputs the first period signal P 1 to the second detection circuit 38.
Also, the first input data break signal E from the MPU 12 is used.
The first detection signal N from the break counter 39 in response to N1
1 is output to the second detection circuit 38. At this time, the second detection circuit 38 outputs the first period signal P1 and the first detection signal N
When 1s are output at the same time, it is determined that the data has been normally written.

On the other hand, when noise affecting writing is generated in the write enable signal WE and the count operation of the write counter 35 malfunctions, if not simultaneous, the second detection circuit 38 It is determined that writing has been performed. When it is judged as abnormal writing,
The second detection circuit 38 outputs a second write abnormality signal S3 to the interrupt signal generation circuit 40. Interrupt signal generation circuit 4
0 outputs the first interrupt signal T1 to the address change circuit 41 and the MPU 12 in response to the second write error signal S3.

The address change circuit 41 outputs the first interrupt signal T
In response to 1, the same operation as described above is executed, and the value of the write pointer 32 is changed so that the 250-byte isochronous data 29 of the subsequent packet 27 is sequentially written and read from a predetermined head address. . In this case, the abnormal writing is detected by using the first detection circuit 37 and the second detection circuit 38, but may be performed by using one of them.

(B) 250 bytes long isochronous
Read data 29. Each content of the control register 42 is set to the same content as described above. For convenience of explanation, the value (address) of the read pointer 33 indicates “749”.

When the first read enable signal RE is output from the protocol control circuit 21, the read pointer 33 changes from "749" to "750" in response to the first read enable signal RE. The first 1-byte data is read from the address “750” of the buffer memory 31. Thereafter, each time a new read enable signal RE is input from the protocol control circuit unit 21, the value of the read pointer 33 is incremented, the address is shifted for each upper address, and Data 29 is read one byte at a time. Along with this reading, the read counter 36 counts the read enable signal RE.

Eventually, the first read enable signal R
250th read enable signal RE counting from E
Is output, the value of the read pointer 33 becomes “999”.
Becomes 250 bytes of isochronous data 29
Of the last one byte in the buffer memory 31
Is read from the address “999”.

The 250th read enable signal RE
Is output from the MPU 12, the output data break signal EN2 is output to the first detection circuit 37. In response to the break signal EN2, the first detection circuit 37 sets the value of the read pointer 33 at that time to “249”, “499”, “7”.
It is determined whether the address corresponds to a specific address of “49” or “999”. When the isochronous data 29 having a length of 250 bytes is normally read based on the normal read enable signal RE, the value of the read pointer 33 becomes “999” and one of the four comparison targets is compared. Since the address matches the address, the first detection circuit 37
Is determined to be normally read.

On the other hand, if they do not match, the first detection circuit 37 determines that abnormal reading has been performed, and outputs a first reading abnormal signal S2 to the interrupt signal generating circuit 40. The interrupt signal generation circuit 40 outputs the first read abnormality signal S
2 in response to the second interrupt signal T2 and the address change circuit 4
1 and the MPU 12. The address change circuit 41 responds to the second interrupt signal T2 by 25
Assuming that a state in which the 0-byte isochronous data 29 has not been normally read has occurred in the buffer memory 31, the value of the read pointer 33 at that time is read. At this time, for example, noise enters the read enable signal RE for some reason, and the value of the read pointer 33 becomes “1”.
0 "and the isochronous packet of the subsequent packet 27 written at the address from" 0 "to" 10 ".
Assuming that the data 29 has been read, the address change circuit 41 changes the value of the read pointer 33 to “999”.

Therefore, the 250-byte length isochronous data 29 of the succeeding packet 27 is sequentially read from the “0” address of the buffer memory 31. As a result, the isochronous data 29 written from the “0” address of the buffer memory 31 is sequentially read from the head.

When the 250th read enable signal RE is output, the read counter 36 outputs the second period signal P2 to the second detection circuit 38.
Also, the first output data break signal E from the MPU 12 is output.
The second detection signal N from the break counter 39 in response to N2
2 is output to the second detection circuit 38. When the second period signal P2 and the second detection signal N2 are output at the same time, the second detection circuit 38 determines that the reading has been performed normally.

On the other hand, when noise affecting reading is generated in the read enable signal RE and the count operation of the read counter 36 malfunctions, if not simultaneous, the second detection circuit 38 It is determined that reading has been performed. When it is determined that the reading is abnormal,
The second detection circuit 38 outputs the second read abnormality signal S4 to the interrupt signal generation circuit 40. Interrupt signal generation circuit 4
0 outputs the second interrupt signal T2 to the address change circuit 41 and the MPU 12 in response to the second read abnormal signal S4.

The address change circuit 41 outputs the second interrupt signal T
In response to step 2, the same operation as described above is executed, and the value of the read pointer 33 is changed so that the 250-byte length isochronous data 29 of the next new packet 27 is sequentially read from a predetermined start address. . In this case, the abnormal writing is detected by using the first detection circuit 37 and the second detection circuit 38, but may be performed by using one of them.

(C) Data block writing. The first and second valid data of the control register 42 are the first
Are set so that both the detection circuit 37 and the second detection circuit 38 operate. The byte length change data of the control register 42 is set to 50 bytes. Further, the division data of the control register 42 is "5". In other words, this is a case where five data blocks each having a length of 50 bytes are collectively written as isochronous data 29 having a length of 250 bytes of one packet 27.

Therefore, the pointer loop setting circuit 34 sets the count-up value of the write pointer 32 and the read pointer 33 to "1000 (= 50 × 20 <1024)". That is, the write pointer 32 and the read pointer 3
3 is a counter from “0” to a count-up value of “999”. The specific addresses of the buffer memory 31 in which the plurality of 50-byte data blocks have been completely written are “49”, “99”, and “14”.
9 "," 199 "," 149 "," 199 "..." 89 "
9 "," 949 ", or" 999 ". For convenience of explanation, the value (address) of the write pointer 32 indicates “249”.

When the first 1-byte data of the first 50-byte data block is output from the DMAC 13 and the first write enable signal WE is output from the MPU 12, the first 1-byte data is output in the same manner as described above. The byte data is stored in the buffer memory 31 at address “25”.
0 ". Thereafter, each time a new write enable signal WE is input from the MPU 12, the value of the write pointer 32 is incremented, the address is shifted upward by one address, and the data block is written one byte at a time to the shifted new address. Go. Along with this writing, the write counter 35 counts the write enable signal WE.

When the 50th write enable signal WE counted from the first write enable signal WE is output, the last 1-byte data in the first 50-byte length data block is processed as described above. Is written into the buffer memory 31 at the address “299”.

When the 50th write enable signal WE is output, the MPU 12 outputs the input data break signal E.
N1 is output, and the first detection circuit 37 determines whether the value of the write pointer 32 at that time corresponds to any of the 20 types of addresses in response to the break signal EN1. When a 50-byte data block is normally written based on the normal write enable signal WE, the value of the write pointer 32 becomes “299”, which matches one of the 20 types of specific addresses. , The first detection circuit 37 determines that the data has been written normally.

On the other hand, if they do not match, the first detection circuit 37 determines that an abnormal write has been performed, and outputs a first write abnormal signal S1 to the interrupt signal generating circuit 40 in the same manner as described above. The interrupt signal generation circuit 40 outputs the first interrupt signal T1 to the address change circuit 41 and the MPU 12 in response to the first write error signal S1. The address change circuit 41 responds to the first interrupt signal T1 by 50
Assuming that a state in which the byte-length data block has not been normally written has occurred in the buffer memory 31, the write pointer 32 at that time is read. At this time, for example, noise enters the write enable signal WE for some reason, and the value of the write pointer 32 is “312”.
Extra 13 in addresses from "300" to "312"
Assuming that byte data has been written, the address change circuit 41 changes the value of the write pointer 32 to “299”.

Accordingly, the next second data block having a length of 50 bytes can be written in order from the "300" address of the buffer memory 31. As a result, the second data block written from the “300” address of the buffer memory 31 is sequentially read from the head when read.

Thereafter, the determination is similarly performed for the second to fifth data blocks, and if an abnormal write is performed, the value of the write pointer 32 is similarly changed. Further, when the 250th write enable signal WE is output, that is, when the write enable signal WE for writing the last byte of the fifth data block is output,
The first period signal P1 is output from the write counter 35 to the second detection circuit 38. Further, in response to the fifth input data break signal EN1 from the MPU 12, the first detection signal N1 is output from the break counter 39 to the second detection circuit 3.
8 is output. When the first period signal P1 and the first detection signal N1 are simultaneously output, the second detection circuit 38 determines that the data has been correctly written.

On the other hand, when noise affecting writing is generated in the write enable signal WE and the count operation of the write counter 35 malfunctions, if not simultaneous, the second detection circuit 38 It is determined that writing has been performed. When it is judged as abnormal writing,
The second detection circuit 38 outputs a second write abnormality signal S3 to the interrupt signal generation circuit 40. Interrupt signal generation circuit 4
0 outputs the first interrupt signal T1 to the address change circuit 41 and the MPU 12 in response to the second write error signal S3.

The address change circuit 41 outputs the first interrupt signal T
1 in response to the value of the write pointer 32 so that when the data of the next new set of the first data block is read out, the data is sequentially read from a predetermined start address. To change. In this case, the abnormal writing is detected by using the first detection circuit 37 and the second detection circuit 38, but may be performed by using one of them.

(D) Reading a data block. Each content of the control register 42 is assumed to be the same as that of the data block. For convenience of explanation, the value (address) of the read pointer 33 indicates “499”.

When the first read enable signal RE is output from the protocol control circuit 21, the read pointer 33 changes from "499" to "500" in response to the first read enable signal RE. The first one-byte data is read from the address “500” in the buffer memory 31. Thereafter, every time a new read enable signal RE is input from the protocol control circuit unit 21, data to be a data block at a new address of the buffer memory 31 is read out one byte at a time in the same manner as described above. Along with this reading, the read counter 36
The read enable signal RE is counted.

Eventually, the first read enable signal R
When the fiftyth read enable signal RE counted from E is output, the value of the read pointer 33 becomes “549”, and the last one byte of data that is a 50-byte data block is stored in the address of the buffer memory 31. "54
9 ".

When the 50th read enable signal RE is output, the MPU 12 outputs the output data break signal E.
N2 is output to the first detection circuit 37. The first detection circuit 37 determines whether or not the value of the read pointer 33 at that time is a corresponding address among the 20 types of specific addresses in response to the break signal EN2. Then, when data forming a 50-byte data block is normally read based on the normal read enable signal RE, the value of the read pointer 33 becomes “549” and 2
Because it matches one of the 0 specific addresses, the first
The detection circuit 37 determines that the data has been read out normally.

On the other hand, if they do not match, the first detection circuit 37 determines that abnormal reading has been performed, and outputs a first reading abnormal signal S2 as described above. The interrupt signal generation circuit 40 responds to the first read abnormality signal S2 and outputs the second interrupt signal T2 to the address change circuit 41 and the MP.
Output to U12. In response to the second interrupt signal T2, the address change circuit 41 reads the read pointer 33 at that time, assuming that a state in which data forming a 50-byte data block has not been normally read has occurred in the buffer memory 31. At this time, for example, noise enters the read enable signal RE for some reason, and the value of the read pointer 33 is “510”, and “500” to “5”
Assuming that data for a subsequent data block written to addresses up to 10 has been read, the address change circuit 41 sets the value of the read pointer 33 to “51”.
"0" to "499".

Therefore, the data for the succeeding 50-byte data block is stored in the buffer memory 31 at “50”.
The addresses are sequentially read from the "0" address. As a result, 2 written from the “500” address of the buffer memory 31
The data for the data block is sequentially read from the head.

Thereafter, the determination for reading data for the second to fifth data blocks is similarly performed, and if an abnormal read is performed, the value of the read pointer 33 is similarly changed.

Then, when the 250th read enable signal RE is output, that is, when the read enable signal RE for reading the last 1-byte data in the fifth data block is output. Then, the second period signal P2 is output from the read counter 36 to the second detection circuit 38. In addition, a second detection signal N2 is output from the break counter 39 to the second detection circuit 38 in response to the fifth output data break signal EN2 from the MPU 12. The second detection circuit 38 determines that the data has been normally written when the second period signal P2 and the second detection signal N2 are simultaneously output.

On the other hand, when noise affecting reading is generated in the read enable signal RE and the count operation of the read counter 36 malfunctions, if not simultaneous, the second detection circuit 38 It is determined that writing has been performed. When it is judged as abnormal writing,
The second detection circuit 38 outputs the second read abnormality signal S4 to the interrupt signal generation circuit 40. Interrupt signal generation circuit 4
0 outputs the second interrupt signal T2 to the address change circuit 41 and the MPU 12 in response to the second read abnormal signal S4.

The address change circuit 41 outputs the second interrupt signal T
2, the same operation as described above is performed, and the value of the read pointer 33 is read so that when the data of the first data block of the next new set is read, the data is sequentially read from a predetermined start address. To change. In this case, the abnormal writing is detected by using the first detection circuit 37 and the second detection circuit 38, but may be performed by using one of them.

Next, the features of the embodiment configured as described above will be described below. (1) According to the above embodiment, the count-up value of the write pointer 32 is set by the pointer loop setting circuit 34.
The maximum value among a plurality of data which is an integral multiple of the data length of 250 bytes and does not exceed the storage capacity of 1024 bytes of the buffer memory 31 is used as a count-up value. Data 29
Is written to the buffer memory 31 in accordance with the write address of the write pointer 32, and when the data is normally written, the writing is completed at one of a plurality of specific addresses. When the writing of the isochronous data 29 is completed, the first detection circuit 37 determines whether the current write address of the write pointer 32 is a specific address. it can.

(2) According to the above-described embodiment, the write counter 35 counts the number of times of writing the 250-byte isochronous data 29, and the first time the normal number of times of writing has been performed, the first The period signal P1 is output. And
In response to a break signal EN1 indicating completion of the last writing of the 250-byte isochronous data 29, the second detection circuit 38 outputs the first signal from the write counter 35 to the first detection circuit 38.
Since the presence / absence of the period P1 is determined, it is possible to determine whether or not a writing error has occurred, similarly to the above (1). By using the first detection circuit 37 and the second detection circuit 38 at the same time, it is possible to detect a writing abnormality with higher accuracy.

(3) According to the above embodiment, the count-up value of the read pointer 33 by the pointer loop setting circuit 34 is an integral multiple of the data length of 250 bytes and exceeds the storage capacity of 1024 bytes of the buffer memory 31. When the maximum value of a plurality of pieces of data not to be read is used as a count-up value, and the isochronous data 29 having a data length of 250 bytes is determined from the buffer memory 31 in accordance with the read address of the read pointer 33, the data is read normally. At that time, the reading is completed at one of a plurality of specific addresses. When the reading of the isochronous data 29 is completed, the first detection circuit 37 determines whether or not the current read address of the read pointer 33 is a specific address. it can.

(4) According to the above embodiment, the read counter 36 counts the number of times of reading of the 250-byte isochronous data 29, and the second time when the predetermined normal number of times of reading has been performed. The period signal P2 is output. And
In response to a break signal EN2 indicating the completion of the last read of the 250-byte isochronous data 29, the second detection circuit 38 outputs a second signal from the read counter 36 to the second detection circuit 38.
Since the presence or absence of the period P2 is determined, it is possible to determine whether or not a reading error has occurred, similarly to the above (3). By using the first detection circuit 37 and the second detection circuit 38 at the same time, it is possible to detect a reading error with higher accuracy.

(5) In the above embodiment, when it is determined that a write error has occurred, the address change circuit 41 sets the write address of the write pointer 32 to the closest write address from the plurality of specific addresses. Rewritten to a specific address. Therefore, the subsequent isochronous data 29 to be written next can be written from a normal address, and the writing can be completed at a specific write address. As a result, the subsequent data 29 is correctly read.

(6) In the above embodiment, when it is determined that a read error has occurred, the address change circuit 41 sets the read address of the read pointer 33 to the closest read address from the plurality of specific addresses. Rewritten to a specific address. Therefore, the subsequent isochronous data 29 to be read next is read from a normal address, and the reading can be completed at a specific read address.

(7) In the above embodiment, the break counter 3
9 is provided so that the break signals EN1 and EN2 are counted and the first and second detection signals N1 and N2 are output based on the divided data, so that the second detection circuit 38 outputs a plurality of data blocks. It is also possible to cope with writing and reading when one packet 27 is created collectively.

(8) In the above embodiment, since the address change circuit 41 can appropriately change the byte length change data of the control register 42, the isochronous data 29 having a byte length other than the 250 byte length is determined in advance. Etc. can also be transferred. Further, it is possible to cope with writing and reading when one packet 27 is created by combining a plurality of data blocks. In this case, unlike the above (7), the first detection circuit 37 can determine whether or not there is an error in writing and reading in units of each data block, and when it is abnormal, change to a specific address. Can be.

The embodiments of the present invention are not limited to the above embodiments, but may be implemented as follows. In the above embodiment, the first detection circuit 37 is the MPU 12
However, the first and second detection signals N1 and N2 from the break counter 39 may be input. In this case, the first detection circuit 37 cannot determine the presence or absence of writing and reading errors in units of each data block.

In the above embodiment, the packet data storage memory circuit 22 has the two detection circuits of the first detection circuit 37 and the second detection circuit 38, but only one of them. It may be embodied in a packet data storage memory circuit not provided. In this case, the circuit scale can be reduced accordingly.

In the above embodiment, two abnormalities, abnormal writing and abnormal reading, are detected, but it is also possible to detect only one of them. In this case, the circuit scale can be reduced accordingly.

In the above embodiment, the control register 42
The packet data storage memory circuit 22 is provided with various functions, but may be embodied in a packet data storage memory circuit without the control register 42. In this case, although only one fixed condition can be detected, the circuit configuration can be simplified accordingly.

In the above embodiment, the protocol controller 11 in the system conforming to IEEE 1394 is used.
Packet data storage memory circuits 22, 23 built in
However, the present invention may be applied to any memory circuit as long as it is a FIFO buffer memory circuit. in this case,
Only the FIFO type buffer memory circuit may be implemented as a one-chip semiconductor integrated circuit device. Of course, FIF
A device including a plurality of O-type buffer memory circuits may be implemented as a one-chip semiconductor integrated circuit device.

[0154]

According to the first and second aspects of the present invention, when a write error occurs, the next data to be written next is written from a normal position and the subsequent data is completed at a specific write address. Can be done.

According to the third and fourth aspects of the present invention, when a read error occurs, the next data to be read next is read from a normal position, and the subsequent data is completed at a specific read address. Can be.

According to the fifth aspect of the present invention, it is possible to detect whether data has been written normally. According to the invention of claim 6, it is possible to detect whether or not the data has been read normally.

According to the invention of claim 7, according to claims 5 and 6,
In addition to the effects of the invention described in the above, when a write error occurs, the subsequent data to be written next can be written from a normal position and the subsequent data can be completed at a specific write address, and When a read error occurs, the subsequent data to be read next can be read from a normal position, and the subsequent data can be completed at a specific read address.

According to the invention of claim 8, in addition to the effect of the invention of claim 5, when a write error occurs,
The subsequent data to be written next can be written from a normal position, and the writing of the subsequent data can be completed at a specific write address.

According to the ninth aspect of the present invention, in addition to the effect of the sixth aspect, when a read error occurs,
The subsequent data to be read next is read from a normal position, and the reading of the subsequent data can be completed at a specific read address.

According to the tenth aspect of the present invention, it is possible to detect whether data has been written normally. According to the eleventh aspect of the present invention, it is possible to detect whether data has been read out normally.

According to the twelfth aspect, in addition to the effects of the tenth and eleventh aspects, when a write error occurs, the next data to be written next is written from a normal position and the subsequent data is written. The data can be completed at a specific write address, and when a read error occurs, the next data to be read next is read from a normal position and the subsequent data is read at a specific read address. Can be completed.

According to the thirteenth aspect, in addition to the effect of the tenth aspect, when a write error occurs, the next data to be written next is written from a normal position and the subsequent data is written. The write can be completed at a specific write address.

According to the fourteenth aspect, in addition to the effect of the eleventh aspect, when a read error occurs, the next data to be read next is read from a normal position and the subsequent data is read. The read can be completed at a specific read address.

According to the invention of claim 15, claim 5, claim 5
In addition to the effects of the inventions described in 6, 10 and 11, when a write error occurs, the subsequent data to be written next is written from a normal position, and the subsequent data is completed at a specific write address. In addition, when a read error occurs, subsequent data to be read next can be read from a normal position, and the subsequent data can be completed at a specific read address.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a transmission packet data storage memory circuit.

FIG. 2 is a block diagram for explaining a configuration in a personal computer.

FIG. 3 is a system configuration diagram using a bus compliant with IEEE1394.

FIG. 4 is an explanatory diagram for explaining a packet.

[Explanation of symbols]

 22 Transmission Packet Data Storage Memory Circuit 31 Buffer Memory 32 Write Pointer 33 Read Pointer 34 Pointer Loop Setting Circuit 35 Write Counter 36 Read Counter 37 First Detector 38 Second Detector 39 Break Counter 40 Interrupt Signal Generator 41 Address change circuit

Claims (15)

[Claims] 1. A buffer designated by a write pointer, which divides data having a determined data length into a plurality of predetermined write times in response to a write enable signal and shifts the data in response to the write enable signal. In a data writing method for writing to a write address of a memory, the count-up value of the write pointer is an integer multiple of the data length, and a maximum value among a plurality of pieces not exceeding the storage capacity of the buffer memory is determined. The write pointer is reset as a count-up value, and when the last write of the data having the determined data length, which is sequentially written according to the write count, is completed, the write address of the write pointer at that time is the count-up value. Multiple specific addresses obtained based on the When none of the the data writing method as rewritten closest specific address to the write address shown at that time from among the plurality of the specific address a write address of the write pointer. 2. A buffer designated by a write pointer, which divides data having a determined data length into a plurality of predetermined times of writing in response to a write enable signal and shifts the data in response to the write enable signal. In a data writing method for writing to a write address of a memory, the count-up value of the write pointer is an integer multiple of the data length, and a maximum value among a plurality of pieces not exceeding the storage capacity of the buffer memory is determined. The write pointer is reset as a count-up value, and the number of writes is counted by a write counter that counts the write enable signal. When the last write is completed, the write When the counter does not indicate the number of times of writing, the write address of the write pointer is set to the write address that is indicated at that time among the plurality of specific addresses obtained based on the count-up value and the data length. A data writing method that rewrites to a specific address that is close. 3. A buffer designated by a read pointer which divides data having a determined data length into a plurality of predetermined read times in response to a read enable signal and shifts the data in response to the read enable signal. In a data reading method for reading data from a read address of a memory, a count-up value of the read pointer is an integer multiple of the data length, and a maximum value among a plurality of pieces not exceeding the storage capacity of the buffer memory is determined. When the read pointer is reset as a count-up value, and when the last read of the data having the determined data length, which is sequentially read in accordance with the read count, is completed,
If the read address of the read pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length, the read address of the read pointer is changed to the read address of the plurality of specific addresses. A data reading method for rewriting from the inside to a specific address closest to the indicated read address at that time. 4. A buffer designated by a read pointer which is shifted in response to the read enable signal by dividing data having a determined data length into a plurality of predetermined read times in response to a read enable signal. In a data reading method for reading data from a read address of a memory, a count-up value of the read pointer is an integer multiple of the data length, and a maximum value among a plurality of pieces not exceeding the storage capacity of the buffer memory is determined. The read pointer is reset as a count-up value, and the number of reads is counted by a read counter that counts the read enable signal. When the last read is completed, When the counter does not indicate the number of times of reading, the read address of the read pointer is the closest to the read address indicated at that time from among a plurality of specific addresses obtained based on the count-up value and the data length. A data reading method that rewrites to a specific address. 5. A buffer memory in which data having a predetermined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. A pointer loop setting circuit that designates a count-up value of the write pointer as an integer multiple of the data length and designates a maximum value among a plurality of values that does not exceed the storage capacity of the buffer memory as a count-up value; The data to be written sequentially in the number of times of writing When the last write of the data having the determined length is completed, when the write address of the write pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length, the write is performed. A data storage memory circuit comprising: a write detection circuit for determining an abnormality. 6. A buffer memory in which data having a determined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. A pointer loop setting circuit that designates a count-up value of the read pointer as an integer multiple of the data length and designates a maximum value among a plurality of values that does not exceed the storage capacity of the buffer memory as a count-up value; The data read out sequentially in accordance with the read number When the last read of the data having the determined length is completed, when the read address of the read pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length, the read is performed. A data storage memory circuit comprising: a read detection circuit for determining an abnormality. 7. A buffer memory in which data having a determined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. Pointer loop setting for designating the maximum value of a plurality of values, which is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory, as the count-up value of the count-up value of the write pointer and the read pointer. A circuit, and writing sequentially in the plurality of times When the last write of the data having the determined data length is completed, the write address of the write pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length. At this time, a write detection circuit for judging a write error, and when the last read of the data having the determined data length, which is sequentially read in accordance with the read count, is completed, the read address of the read pointer at that time is the count-up value. A read detection circuit that determines an abnormal read when none of the plurality of specific addresses determined based on the data length and the write address; and a write pointer when the write detect circuit determines an abnormal write. The write address of the specified address from among the plurality of specific addresses. A write address changing circuit for rewriting to a specific address closest to the address; and a read address of the read pointer from the plurality of specific addresses when the read detection circuit determines that the read is abnormal. A data storage memory circuit comprising: a read address change circuit for rewriting a specific address closest to a read address. 8. The data storage memory circuit according to claim 5, wherein the write address of the write pointer is indicated from the plurality of specific addresses when the write detection circuit determines that the write is abnormal. A data storage memory circuit comprising a write address change circuit for rewriting to a specific address closest to a write address. 9. The data storage memory circuit according to claim 6, wherein when the read detection circuit determines that the read is abnormal, the read address of the read pointer is indicated from the plurality of specific addresses at that time. A data storage memory circuit including a read address change circuit for rewriting to a specific address closest to the read address being read. 10. A buffer memory in which data having a predetermined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. A write counter for counting the number of times of writing in response to the write enable signal; and when the last writing of the data having the determined data length to be sequentially written by dividing the number of times of writing is completed, the write counter is Indicates the number of times of writing There upon, the data storage memory circuit and a second light detection circuit for determining the writing error of the data. 11. A buffer memory in which data having a predetermined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. A read counter that counts the number of reads in response to the read enable signal; and when the last read of the data having the determined data length that is sequentially read in the read count is completed, the read counter is Indicates the number of times of reading. There upon, the data storage memory circuit and a second lead for the detection circuit to determine that the reading error of the data. 12. A buffer memory in which data having a determined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable signal. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a read enable signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. Pointer loop setting circuit for designating, as a count-up value, a count-up value of a write pointer and a read pointer, which is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory, among a plurality of values. And responding to the write enable signal. A write counter for counting the number of times of writing, a read counter for counting the number of times of reading in response to the enable signal for reading, When the writing is completed, when the write counter that counts the number of times of writing does not indicate the number of times of writing, a second write detection circuit that determines that there is an abnormality in the writing of the data, When the last read of the data having the determined data length is completed, when the read counter for counting the number of times of reading does not indicate the number of times of reading, it is determined that the reading of the data is abnormal. A detection circuit, and the second write detection circuit determines that a write error has occurred. Then, a write address for rewriting a write address of the write pointer from a plurality of specific addresses obtained based on the count-up value and the data length to a specific address closest to the write address indicated at that time. A change circuit, and when the second read detection circuit determines that the read is abnormal, the read address of the read pointer is selected from a plurality of specific addresses obtained based on the count-up value and the data length. And a read address change circuit for rewriting to a specific address closest to the read address shown in FIG. 13. The data storage memory circuit according to claim 10, wherein the write address of the write pointer is based on the count-up value and the data length when the second write detection circuit determines that the write is abnormal. A data storage memory circuit comprising a write address change circuit for rewriting a specific address closest to the write address indicated at that time from among the plurality of specific addresses obtained in the above manner. 14. The data storage memory circuit according to claim 11, wherein the read address of the read pointer is based on the count-up value and the data length when the second read detection circuit determines that the read is abnormal. A data storage memory circuit comprising a read address change circuit for rewriting a specific address closest to the read address indicated at that time from among the plurality of specific addresses obtained in the above manner. 15. A buffer memory in which data having a determined data length is sequentially written in a plurality of predetermined times of writing and sequentially read out in a plurality of predetermined times of reading, and a write enable signal. A data storage memory circuit comprising: a write pointer that shifts and specifies a write address of a buffer memory in response to a read enable signal; and a read pointer that shifts and specifies a read address of a buffer memory in response to a read enable signal. Pointer loop setting circuit for designating, as a count-up value, a count-up value of a write pointer and a read pointer, which is an integral multiple of the data length and does not exceed the storage capacity of the buffer memory, among a plurality of values. And written sequentially in the plurality of times When the last writing of the data having the determined data length is completed, and the write address of the write pointer at that time does not correspond to any of the plurality of specific addresses obtained based on the count-up value and the data length. A write detection circuit for judging a write error, and when the last read of the data having the determined data length, which is sequentially read out by dividing the read count, is completed, the read address of the read pointer at that time is the count-up value. A read detection circuit for judging a read error when the address does not correspond to any of the plurality of specific addresses obtained based on the data length; and a write circuit for counting the number of writes in response to the write enable signal. A counter that counts the number of reads in response to the read enable signal; A counter for reading the data, when the last writing of the data having the determined data length, which is sequentially read out by dividing the number of times of writing, is completed, when the counter for writing does not indicate the number of times of writing, A second write detection circuit that determines an abnormality; and a read counter that counts the number of reads when the last read of the data whose data length has been determined and that is sequentially read by dividing the number of reads is completed. When the number of times is not indicated, a second read detection circuit that determines that the data is read abnormally, and when the write detection circuit or the second write detection circuit determines that there is a read error, writing of the write pointer The address is changed from the plurality of specific addresses to the read address indicated at that time. A write address change circuit for rewriting to a specific address that is close to the read address, and when the read detection circuit or the second read detection circuit determines that a read error has occurred, the read address of the read pointer is selected from the plurality of specific addresses. A data storage memory circuit comprising: a read address change circuit for rewriting a specific address closest to the indicated read address at that time.